A method, device and electronic device for processing false sharing

Abstract

The present invention discloses a pseudo-sharing processing method, device and electronic device, wherein the method comprises: when multiple threads modify any independent variable between different memories, determining the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; when the byte size occupied by the independent variable in the memory is different from the byte size of the cache line used by the CPU, determining the byte size to be filled according to the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; performing byte filling at the tail of the byte size of the independent variable according to the byte size to be filled, so that the sum of the byte size occupied by the independent variable in the memory and the byte size to be filled is equal to an integer multiple of the byte size of the cache line used by the CPU.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a pseudo-sharing processing method, device and electronic equipment. Background Art

[0002] CPU cache is a temporary storage located between the CPU and the memory. Its capacity is much smaller than that of the memory, but its exchange speed is much faster than that of the memory block. The smallest unit of data exchanged between the CPU and the memory using the cache is not a byte, but a cache line of a fixed size area. The cache line is generally a continuous byte of an integer power of 2. The cache line size of different CPU models is different. The current mainstream cache line is usually 64 bytes.

[0003] In the case of high system concurrency, in order to avoid using locks and prevent the system overhead caused by locking, independent memory is usually used to open different memory spaces according to different threads, so that threads do not conflict with each other. However, when multiple threads modify independent variables, if these variables share a cache line, when the value of one of the independent variables changes, it will cause the entire cache line to be polluted, which will inadvertently affect the performance of each other and cause false sharing. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defect of the false sharing problem when the existing multi-threads modify independent variables between different memories, thereby providing a false sharing processing method, device and electronic device.

[0005] According to the first aspect, an embodiment of the present invention discloses a pseudo-sharing processing method, which, when multiple threads modify any independent variables that are independent of each other between different memories, determines the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; when the byte size occupied by the independent variable in the memory is different from the byte size of the cache line used by the CPU, determines the byte size to be filled according to the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; and performs byte filling at the tail of the byte size of the independent variable according to the byte size to be filled, so that the sum of the byte size occupied by the independent variable in the memory and the byte size to be filled is equal to an integer multiple of the byte size of the cache line used by the CPU.

[0006] Optionally, the size of bytes to be filled is determined based on the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory, including: when the byte size of the cache line used by the CPU is smaller than the byte size occupied by the independent variable in the memory, performing a modulo calculation on the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; determining the size of bytes to be filled based on the byte size corresponding to the modulo calculation result and the byte size of the cache line used by the CPU, so that the sum of the byte size to be filled and the byte size corresponding to the modulo calculation result is equal to the byte size of the cache line used by the CPU.

[0007] Optionally, the size of bytes to be filled is determined based on the size of bytes of the cache line used by the CPU and the size of bytes occupied by the independent variable in the memory, and also includes: when the size of bytes of the cache line used by the CPU is larger than the size of bytes occupied by the independent variable in the memory, performing a modulo calculation on the size of bytes of the cache line used by the CPU and the size of bytes occupied by the independent variable in the memory; and using the size of bytes corresponding to the result of the modulo calculation as the size of bytes to be filled, so that the sum of the size of bytes to be filled and the size of bytes occupied by the independent variable in the memory is equal to the size of bytes of the cache line used by the CPU.

[0008] Optionally, the size of the number of bytes of the cache line used by the CPU is determined according to the acquired CPU model.

[0009] According to the second aspect, an embodiment of the present invention further discloses a pseudo-shared processing device, comprising: a first determination module, used to determine the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory when multiple threads modify any independent variables between different memories; a second determination module, used to determine the byte size to be filled according to the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory when the byte size occupied by the independent variable in the memory is different from the byte size of the cache line used by the CPU; a filling module, used to perform byte filling at the end of the byte size of the independent variable according to the byte size to be filled, so that the sum of the byte size occupied by the independent variable in the memory and the byte size to be filled is equal to an integer multiple of the byte size of the cache line used by the CPU.

[0010] Optionally, the second determination module includes: a first calculation submodule, used to perform a modulo calculation on the byte size of the cache line used by the CPU and the byte size of the independent variable in the memory when the byte size of the cache line used by the CPU is smaller than the byte size occupied by the independent variable in the memory; a first determination submodule, used to determine the byte size to be filled based on the byte size corresponding to the modulo calculation result and the byte size of the cache line used by the CPU, so that the sum of the byte size to be filled and the byte size corresponding to the modulo calculation result is equal to the byte size of the cache line used by the CPU.

[0011] Optionally, the second determination module also includes: a second calculation submodule, used to perform a remainder calculation on the number of bytes of the cache line used by the CPU and the number of bytes occupied by the independent variable in the memory when the number of bytes of the cache line used by the CPU is greater than the number of bytes occupied by the independent variable in the memory; a second determination submodule, used to use the number of bytes corresponding to the remainder calculation result as the number of bytes to be filled, so that the sum of the number of bytes to be filled and the number of bytes occupied by the independent variable in the memory is equal to the number of bytes of the cache line used by the CPU.

[0012] Optionally, the size of the number of bytes of the cache line used by the CPU is determined according to the acquired CPU model.

[0013] According to the third aspect, an embodiment of the present invention also discloses an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the pseudo-sharing processing method as described in the first aspect or any optional embodiment of the first aspect.

[0014] According to a fourth aspect, an embodiment of the present invention further discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the pseudo-sharing processing method as described in the first aspect or any optional embodiment of the first aspect.

[0015] The technical solution of the present invention has the following advantages:

[0016] The pseudo-sharing processing method / device provided by the present invention determines the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory when multiple threads modify any independent independent variable between different memories. When the byte size occupied by the independent variable in the memory is different from the byte size of the cache line used by the CPU, the byte size to be filled is determined according to the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory. According to the byte size to be filled, byte filling is performed at the tail of the byte size of the independent variable, so that the sum of the byte size occupied by the independent variable in the memory and the byte size to be filled is equal to an integer multiple of the byte size of the cache line used by the CPU. Through this solution, the position of the independent variable in the CPU cache can be ensured to be in different CPU cache lines by dynamically filling the array size, thereby avoiding the problem of pseudo-sharing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a flowchart of a specific example of a method for processing false sharing in an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of a specific example of a method for processing false sharing in an embodiment of the present invention;

[0020] Figure 3 is a schematic diagram of a specific example of a method for processing false sharing in an embodiment of the present invention;

[0021] Figure 4 is a principle block diagram of a specific example of a pseudo-sharing processing device in an embodiment of the present invention;

[0022] Figure 5 FIG. 4 is a specific example diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0025] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] The reason for false sharing is that when multiple threads modify their own independent variables, if different independent variables are in the same cache line in the CPU cache, when the value of one of the independent variables changes, it will cause the entire cache line to be polluted. To this end, the embodiment of the present application provides a method for solving false sharing, as follows:

[0028] The embodiment of the present invention discloses a pseudo-sharing processing method, which can be applied to different high-concurrency scenarios, such as Figure 1 As shown, the method comprises the following steps:

[0029] Step 101, when multiple threads modify any independent variable between different memories, determine the size of the bytes of the cache line used by the CPU and the size of the bytes occupied by the independent variable in the memory;

[0030] Exemplarily, since different CPU models have different definitions of cache lines, when multiple threads modify independent variables, the CPU model can be determined by calling CPU parameters and then the size of the bytes of the cache line used by the corresponding CPU can be determined.

[0031] Step 102, when the number of bytes occupied by the independent variable in the memory is different from the number of bytes of the cache line used by the CPU, determine the number of bytes to be filled according to the number of bytes of the cache line used by the CPU and the number of bytes occupied by the independent variable in the memory;

[0032] For example, since different programming languages ​​may be used during system development, the number of bytes occupied by different independent variables in different programming languages ​​in the memory may be different, so the size of the cache line used by the corresponding independent variable in the memory can be determined by communicating with the memory. The number of bytes of the independent variable is modulo the number of bytes of the determined cache line used by the CPU to accurately calculate the relationship between the number of bytes of the independent variable and the number of bytes of the cache line used by the CPU, and then determine the set padding data memory size.

[0033] Step 103, byte padding is performed at the end of the byte size of the independent variable according to the size of the bytes to be filled, so that the sum of the byte size occupied by the independent variable in the memory and the size of the bytes to be filled is equal to an integer multiple of the byte size of the cache line used by the CPU.

[0034] As an optional implementation of the present invention, step 102 includes: when the byte size of the cache line used by the CPU is smaller than the byte size occupied by the independent variable in the memory, performing a modulo calculation on the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; determining the byte size to be filled according to the byte size corresponding to the modulo calculation result and the byte size of the cache line used by the CPU, so that the sum of the byte size to be filled and the byte size corresponding to the modulo calculation result is equal to the byte size of the cache line used by the CPU.

[0035] For example, assuming that the number of bytes occupied by the independent variable in the memory is 70 bytes, and the number of bytes of the cache line used by the CPU is 64 bytes, since it is necessary to accurately ensure that different independent variables are in different cache lines, the size of the byte array to be filled can be calculated by taking the modulo of the number of bytes occupied by the independent variable in the memory and the number of bytes of the determined CPU cache line. Figure 2 As shown, the calculated modulo result is 6 bytes, which means that only 58 bytes of memory padding block are needed to ensure that the independent variable just fills two CPU cache lines.

[0036] As an optional implementation of the present invention, step 102 also includes: when the byte size of the cache line used by the CPU is larger than the byte size occupied by the independent variable in the memory, performing a modulo calculation on the byte size of the cache line used by the CPU and the byte size occupied by the independent variable in the memory; using the byte size corresponding to the modulo calculation result as the byte size to be filled, so that the sum of the byte size to be filled and the byte size occupied by the independent variable in the memory is equal to the byte size of the cache line used by the CPU.

[0037] For example, assuming that the number of bytes of the independent variable is 58 bytes and the CPU cache is 64 bytes, the size of the field to be filled can also be calculated by the modulo operation. Figure 3 As shown, the calculated modulus result is 6 bytes, which means that only 6 bytes of memory padding block are needed to ensure that the independent variable just fills a CPU cache line, and the set byte array is appended to the end of the corresponding independent variable to form a continuous memory, so that the memory occupied by the independent variable can be accurately determined to be an integer multiple of the CPU cache line. The solution recorded in this embodiment can ensure that the position of the independent variable in the CPU cache is in different CPU cache lines by dynamically filling the array size.

[0038] Specifically, for the convenience of explanation, assume that the size of the CPU cache line obtained is CPU_CACHE_SIZE. Since the CPU cache in the local test is 64 bytes, the value of the cache line is CPU_CACHE_SIZE=64; assume that the size of the number of bytes of the independent variable in the memory obtained is VAR_SIZE. The size of the number of bytes of the independent variable in the memory obtained in different languages ​​is not the same. VAR_SIZE=SIZE(PARAMETERS)=20 obtained in the local test; assume that the size after taking the remainder is COMPLEMENT_SIZE, and the corresponding formula is COMPLEMENT _SIZE=VAR_SIZE%CPU_CACHE_SIZE; Through the values ​​of the above local test parameters, we can calculate that the size of COMPLEMENT_SIZE after taking the remainder is COMPLEMENT_SIZE=20%64=44; for the sake of convenience, assume that the filling array is pad[], the size of the byte array is (CPU_CACHE_SIZE-COMPLEMENT_SIZE), that is, 64-20=44, then the filling array is pad

[44] ; append the filled byte array pad

[44] to the end of the corresponding independent variable to complete the entire dynamic filling process.

[0039] Most of the existing technologies achieve the corresponding effect of avoiding false sharing by setting a fixed cache size before and after the independent variables that need to be isolated. However, adopting this solution in a large system will greatly waste memory and cause unnecessary costs. The solution recorded in this embodiment dynamically fills the memory by calculating the size of the byte array by taking the modulus of the size, which can accurately make the independent variables occupy the cache line without causing memory waste, and can save the additional cost caused by memory occupation; and the false sharing processing method provided in the embodiment of the present invention can improve system performance by avoiding false sharing, and can greatly shorten the response time of the system in high concurrency scenarios.

[0040] The embodiment of the present invention also discloses a pseudo-sharing processing device, such as Figure 4 As shown, the device comprises:

[0041] The first determination module 201 is used to determine the size of the bytes of the cache line used by the CPU and the size of the bytes occupied by the independent variable in the memory when multiple threads modify any independent variable between different memories;

[0042] A second determining module 202 is used to determine the size of bytes to be filled according to the size of bytes of the cache line used by the CPU and the size of bytes occupied by the independent variable in the memory when the size of bytes occupied by the independent variable in the memory is different from the size of bytes of the cache line used by the CPU;

[0043] The filling module 203 is used to perform byte filling at the end of the byte size of the independent variable according to the size of the bytes to be filled, so that the sum of the byte size occupied by the independent variable in the memory and the size of the bytes to be filled is equal to an integer multiple of the byte size of the cache line used by the CPU.

[0044] The false sharing processing device provided by the present invention can ensure that the positions of independent variables in the CPU cache are in different CPU cache lines by dynamically filling the array size through this solution, thereby avoiding the problem of false sharing.

[0045] As an optional embodiment of the present invention, the second determination module includes: a first calculation submodule, which is used to perform a modulo calculation on the byte size of the cache line used by the CPU and the byte size of the independent variable in the memory when the byte size of the cache line used by the CPU is smaller than the byte size occupied by the independent variable in the memory; a first determination submodule, which is used to determine the byte size to be filled based on the byte size corresponding to the modulo calculation result and the byte size of the cache line used by the CPU, so that the sum of the byte size to be filled and the byte size corresponding to the modulo calculation result is equal to the byte size of the cache line used by the CPU.

[0046] As an optional embodiment of the present invention, the second determination module also includes: a second calculation submodule, which is used to perform a remainder calculation on the number of bytes of the cache line used by the CPU and the number of bytes occupied by the independent variable in the memory when the number of bytes of the cache line used by the CPU is greater than the number of bytes occupied by the independent variable in the memory; and a second determination submodule, which is used to use the number of bytes corresponding to the remainder calculation result as the number of bytes to be filled, so that the sum of the number of bytes to be filled and the number of bytes occupied by the independent variable in the memory is equal to the number of bytes of the cache line used by the CPU.

[0047] As an optional implementation manner of the present invention, the size of the number of bytes of the cache line used by the CPU is determined according to the acquired CPU model.

[0048] The embodiment of the present invention further provides an electronic device, such as Figure 5 As shown, the electronic device may include a processor 401 and a memory 402, wherein the processor 401 and the memory 402 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0049] The processor 401 may be a central processing unit (CPU). The processor 401 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0050] The memory 402 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the pseudo-sharing processing method in the embodiment of the present invention. The processor 401 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory 402, that is, the pseudo-sharing processing method in the above method embodiment is implemented.

[0051] The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created by the processor 401, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 402 may optionally include a memory remotely arranged relative to the processor 401, and these remote memories may be connected to the processor 401 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0052] The one or more modules are stored in the memory 402, and when executed by the processor 401, the following is performed: Figure 1 The false sharing processing method in the illustrated embodiment.

[0053] For details of the above electronic equipment, please refer to Figure 1 The corresponding related descriptions and effects in the illustrated embodiments can be understood and will not be repeated here.

[0054] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0055] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for processing false sharing, characterized in that: include: When multiple threads modify any independent variable between different memories, determine the size of the cache line used by the CPU and the size of the bytes occupied by the independent variable in the memory; When the number of bytes occupied by the independent variable in the memory is different from the number of bytes of the cache line used by the CPU, the number of bytes to be filled is determined according to the number of bytes of the cache line used by the CPU and the number of bytes occupied by the independent variable in the memory; Performing byte padding at the tail of the byte number of the independent variable according to the byte number to be filled, so that the sum of the byte number size occupied by the independent variable in the memory and the byte number size to be filled is equal to an integer multiple of the byte number size of the cache line used by the CPU; The number of bytes to be filled is determined according to the number of bytes of the cache line used by the CPU and the number of bytes occupied by the independent variable in the memory, including: When the size of the bytes of the cache line used by the CPU is smaller than the size of the bytes occupied by the independent variable in the memory, the size of the bytes of the cache line used by the CPU and the size of the bytes occupied by the independent variable in the memory are modulo calculation; Determine the size of bytes to be filled according to the size of bytes corresponding to the modulo calculation result and the size of bytes of the cache line used by the CPU, so that the sum of the size of bytes to be filled and the size of bytes corresponding to the modulo calculation result is equal to the size of bytes of the cache line used by the CPU; When the size of the bytes of the cache line used by the CPU is larger than the size of the bytes occupied by the independent variable in the memory, the modulus of the size of the bytes of the cache line used by the CPU and the size of the bytes occupied by the independent variable in the memory is calculated; The byte size corresponding to the modulo calculation result is used as the byte size to be filled, so that the sum of the byte size to be filled and the byte size occupied by the independent variable in the memory is equal to the byte size of the cache line used by the CPU.

2. The method according to claim 1, characterized in that The size of the number of bytes of the cache line used by the CPU is determined according to the acquired CPU model.

3. A pseudo-sharing processing device, characterized in that: include: The first determination module is used to determine the size of the bytes of the cache line used by the CPU and the size of the bytes occupied by the independent variable in the memory when multiple threads modify any independent variable between different memories; A second determining module is used to determine the size of bytes to be filled according to the size of bytes of the cache line used by the CPU and the size of bytes occupied by the independent variable in the memory when the size of bytes occupied by the independent variable in the memory is different from the size of bytes of the cache line used by the CPU; A filling module, used for performing byte filling at the tail of the byte number of the independent variable according to the byte number size to be filled, so that the sum of the byte number size occupied by the independent variable in the memory and the byte number size to be filled is equal to an integer multiple of the byte number size of the cache line used by the CPU; Wherein, the second determining module includes: A first calculation submodule is used for performing a modulo calculation on the size of the bytes of the cache line used by the CPU and the size of the bytes of the independent variable in the memory when the size of the bytes of the cache line used by the CPU is smaller than the size of the bytes of the independent variable in the memory; A first determination submodule is used to determine the size of bytes to be filled according to the size of bytes corresponding to the modulo calculation result and the size of bytes of the cache line used by the CPU, so that the sum of the size of bytes to be filled and the size of bytes corresponding to the modulo calculation result is equal to the size of bytes of the cache line used by the CPU; A second calculation submodule is used for performing a modulo calculation on the size of the bytes of the cache line used by the CPU and the size of the bytes of the independent variable in the memory when the size of the bytes of the cache line used by the CPU is greater than the size of the bytes occupied by the independent variable in the memory; The second determination submodule is used to use the byte size corresponding to the modulo calculation result as the byte size to be filled, so that the sum of the byte size to be filled and the byte size occupied by the independent variable in the memory is equal to the byte size of the cache line used by the CPU.

4. The device according to claim 3, characterized in that The size of the number of bytes of the cache line used by the CPU is determined according to the acquired CPU model.

5. An electronic device, characterized in that: include: at least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the pseudo-sharing processing method as described in claim 1 or 2.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the false sharing processing method according to claim 1 or 2 are implemented.

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