Method for fabricating gate, source and drain of HEMT by one-time photolithography

Abstract

The present invention discloses a method for fabricating the gate, source, and drain of a HEMT by single lithography. In this application, source slots, gate slots, and drain slots are formed by single lithography. Then, photoresist is disposed at the gate slots, and then a first metal layer is deposited to form the contact layer between the source and the drain. At the same time, due to the setting of the photoresist, the metal deposition at the gate slot position is deposited on the photoresist and will not be deposited at the gate slot position. Then, the photoresist is removed by wet etching. Finally, a gate contact layer is formed at the gate slot. In this way, the slots of the source, drain, and gate are formed simultaneously through the lithography step. For the critical dimension of the gate and the critical distance from the gate to the source and drain, etc., they are completed by lithography, avoiding the alignment error caused by multiple lithographies in the traditional integration process, thereby enabling the high electron mobility transistor to be more miniaturized and improving its radio frequency performance effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of transistor manufacturing, and particularly relates to a method for fabricating the gate, source, and drain of a HEMT by single lithography, a transistor, and an electronic device. Background Art

[0002] A transistor is a semiconductor device, commonly used as an amplifier or an electrically controlled switch. Transistors are the basic building blocks that regulate the operation of computers, mobile phones, and all other modern electronic circuits. Due to their fast response speed and high accuracy, transistors can be used for a wide variety of digital and analog functions, including amplification, switching, voltage regulation, signal modulation, and oscillators. Transistors can be packaged independently or as part of an integrated circuit in a very small area that can hold one hundred million or more transistors.

[0003] During the manufacturing process of high electron mobility transistor (HEMT) devices, multiple lithography steps are often required. Using multiple lithographies in traditional integrated processes will introduce alignment errors. That is, alignment is required for each lithography. Naturally, some alignment errors need to be reserved between the various structural components during the alignment process. If multiple alignments are performed, the reserved alignment errors will gradually accumulate, making it difficult to further miniaturize the final cost volume. Summary of the Invention

[0004] In order to overcome the above-mentioned drawbacks of the prior art, the purpose of the present invention is to provide a method for fabricating the gate, source, and drain of a HEMT by single lithography, a transistor, and an electronic device, aiming to solve the technical problem of alignment errors caused by the need for multiple lithographies during the manufacturing process of existing high electron mobility transistor (HEMT) devices and the difficulty in miniaturization.

[0005] The technical solution adopted by the present invention to achieve its purpose is as follows:

[0006] A method for fabricating the gate, source, and drain of a HEMT by single lithography, characterized by comprising the following steps:

[0007] Deposit a first dielectric layer, a second dielectric layer, and a third dielectric layer on the substrate in sequence;

[0008] Perform lithography on the first dielectric layer, the second dielectric layer, and the third dielectric layer to form a source slot, a gate slot, and a drain slot;

[0009] Perform wet etching on the second dielectric layer after lithography to form a groove structure;

[0010] Form an inverted photoresist at the gate slot;

[0011] Deposit a first metal layer;

[0012] Remove the photoresist and the first metal layer on the photoresist by wet method;

[0013] Wet-etch the second dielectric layer and the third dielectric layer;

[0014] Form a gate contact layer at the gate trench.

[0015] Further, in the step of forming an inverted photoresist at the gate trench, wherein the photoresist extends upward from the bottom of the gate trench by a preset height, the thickness of the photoresist is greater than the depth of the gate trench, and the width of the photoresist is greater than the width of the gate trench.

[0016] Further, in the step of forming a gate contact layer at the gate trench, the following steps are included:

[0017] Deposit a fourth dielectric layer and a fifth dielectric layer in sequence;

[0018] Open a window in the fifth dielectric layer at the gate trench position;

[0019] Deposit a second metal layer at the gate trench position, and the second metal layer is the gate contact layer.

[0020] Further, after the step of forming a gate contact layer at the gate trench, the following steps are further included:

[0021] Open a window in the fourth dielectric layer and the fifth dielectric layer at the source trench position to expose the first metal layer to form a source contact layer;

[0022] Open a window in the fourth dielectric layer and the fifth dielectric layer at the drain trench position to expose the first metal layer to form a drain contact layer.

[0023] Further, the first dielectric layer and the third dielectric layer are silicon nitride SiNx, and the second dielectric layer is silicon dioxide SiO2.

[0024] Further, the material of the fourth dielectric layer is silicon nitride SiNx or aluminum oxide Al2O3, and the thickness of the fourth dielectric layer is 100 Å, the material of the fifth dielectric layer is silicon dioxide SiO2, and the thickness of the fifth dielectric layer is 3000 Å.

[0025] Further, in the step of wet-etching the second dielectric layer after photolithography to form a groove structure, the wet-etching solution used is a hydrogen fluoride solution.

[0026] Further, the substrate includes a high-resistance silicon layer, a buffer layer, a gallium nitride layer, and an aluminum gallium nitride layer from bottom to top in sequence.

[0027] Correspondingly, fabricate the gate, source, and drain of the HEMT by the method of one-time photolithography as described above.

[0028] Correspondingly, the present invention also provides an electronic device, including the transistor as described above.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] In the method for fabricating the gate, source, and drain of a HEMT by single lithography proposed by the present invention, since in the prior art, multiple lithographies are mostly used because the contact layer of the gate is different from that of the source and drain, and the contact layer of the gate needs to be separately set. In order to prevent the metal layer deposited on the source and drain from covering the gate slot, multiple lithographies are required to separate the metal layer of the gate from the source and drain; while in this application, source slots, gate slots, and drain slots are formed by single lithography, then photoresist is set at the gate slots, and then the first metal layer is deposited to form the contact layer of the source and drain. At the same time, due to the setting of the photoresist, the metal deposition at the gate slot position is deposited on the photoresist and will not be deposited at the gate slot position. Then the photoresist is removed by wet process, and finally the gate contact layer is formed at the gate slot. In this way, the slots of the source, drain, and gate are formed simultaneously through a single lithography step. For the critical dimensions of the gate and the critical distances from the gate to the source and drain, etc., they are completed through a single lithography, avoiding the alignment errors caused by multiple lithographies in the traditional integration process, thereby enabling the high electron mobility transistor to be more miniaturized and improving its radio frequency performance. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 It is a flowchart of the method in an embodiment of the present invention;

[0033] Figure 2 It is a schematic structural diagram after step S100 in an embodiment of the present invention;

[0034] Figure 3 It is a schematic structural diagram after step S200 in an embodiment of the present invention;

[0035] Figure 4 It is a schematic structural diagram after step S300 in an embodiment of the present invention;

[0036] Figure 5 It is a schematic structural diagram after step S400 in an embodiment of the present invention;

[0037] Figure 6Schematic diagram after step S500 in an embodiment of the present invention;

[0038] Figure 7 Schematic diagram after step S600 in an embodiment of the present invention;

[0039] Figure 8 Schematic diagram after step S700 in an embodiment of the present invention;

[0040] Figure 9 Schematic diagram after step S810 in an embodiment of the present invention;

[0041] Figure 10 Schematic diagram after step S820 in an embodiment of the present invention;

[0042] Figure 11 Schematic diagram after step S830 in an embodiment of the present invention;

[0043] Figure 12 Schematic diagram after the final completion in an embodiment of the present invention.

[0044] Explanation of the reference numerals in the drawings:

[0045] Label Name Label Name 1 Substrate 7 Drain Slot 2 First Dielectric Layer 8 Photoresist 3 Second Dielectric Layer 9 First Metal Layer 31 Groove Structure 10 Fourth Dielectric Layer 4 Third Dielectric Layer 11 Fifth Dielectric Layer 5 Source Slot 12 Second Metal Layer 6 Gate Slot

[0046] The realization of the object, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0047] In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific implementation manners. It should be noted that, without conflict, the implementation manners of the present invention and the features in the implementation manners can be combined with each other. In the following description, many specific details are set forth in order to fully understand the present invention. The described implementation manners are only a part of the implementation manners of the present invention, rather than all of the implementation manners. All other implementation manners obtained by those of ordinary skill in the art based on the implementation manners in the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific implementation manners, and are not intended to limit the present invention.

[0049] HEMT, fully known as High Electron Mobility Transistor in Chinese and High Electron Mobility Transistor in English;

[0050] Referring to Figures 1 - 12 , an embodiment of the present invention provides a method for fabricating the gate, source, and drain of a HEMT by single lithography, which is characterized by including the following steps:

[0051] Step S100, referring to Figure 2 , sequentially deposit a first dielectric layer 2, a second dielectric layer 3, and a third dielectric layer 4 on the substrate 1;

[0052] Specifically, the substrate 11 in this embodiment contains an epitaxial layer heterojunction, and several dielectric layers are deposited above the substrate 1. After lithography, the dielectric layers can form source slots, gate slots, and drain slots. The material selection of the dielectric layers will also adaptively select materials that are beneficial to the implementation of subsequent steps. In this embodiment, the first dielectric layer 2 and the third dielectric layer 4 are silicon nitride SiNx, and the second dielectric layer 3 is silicon dioxide SiO2. Therefore, the first dielectric layer 2, the second dielectric layer 3, and the third dielectric layer 4 form a sandwich structure, and other suitable dielectric materials can also be selected for the silicon nitride SiNx according to requirements.

[0053] Step S200, referring to Figure 3 , perform single lithography on the first dielectric layer 2, the second dielectric layer 3, and the third dielectric layer 4 to form source slots, gate slots, and drain slots;

[0054] Specifically, one of the reasons why it is difficult to further miniaturize the volume of HEMT products in the prior art is that multiple lithographies are required in the process of fabricating HEMT in the prior art. Each lithography requires alignment, and a certain distance must be reserved as the alignment error each time. Therefore, multiple lithographies cause the alignment errors to accumulate continuously, ultimately making it difficult to further miniaturize the volume of HEMT products. In this embodiment, the slots of the source (Source), drain (Drain), and gate (Gate) are formed simultaneously through a single lithography step. For the critical dimensions of the gate and the critical distances from the gate to the source and drain, they are completed through a single lithography, that is, only one alignment is required, avoiding the problem of the accumulation of multiple alignment errors caused by multiple lithographies in the traditional integrated process, thereby achieving the effect of better realizing device miniaturization.

[0055] Step S300, referring to Figure 4 , perform wet etching on the second dielectric layer 3 after lithography to form a groove structure 31;

[0056] Specifically, in this embodiment, the second dielectric layer 3 is wet-etched to form a groove structure 31, that is, an undercut of the second dielectric layer 3 is formed. The wet etching is carried out using a wet etching solution, and the groove structure 31 that meets the requirements is etched according to the actual situation. Specifically, the groove structure 31 is a notch formed by the second dielectric layer 3 being recessed inward relative to the first dielectric layer 2 and the third dielectric layer 4. The main function of the groove structure 31 is to prevent the metal from depositing on the second dielectric layer 3 during the subsequent deposition of the first metal layer 9. Since the deposition process is mostly metal evaporation and will deposit from top to bottom, due to the existence of the groove structure 31, the metal will deposit on the upper layer of the third dielectric layer 4 and the sidewalls of the first dielectric layer 2 and the third dielectric layer, and will not deposit on the sidewalls of the second dielectric layer. If the groove structure 31 is not provided for the second dielectric layer 3, then a small amount of metal may also deposit on the sidewalls of the second dielectric layer 3. In the subsequent steps, the second dielectric layer 3 needs to be wet-stripped. Because the sidewalls of the second dielectric layer 3 are deposited with metal, the second dielectric layer 3 cannot be wet-stripped. However, the groove structure 31 in this embodiment makes it difficult for the metal to deposit on the sidewalls of the second dielectric layer 3, and finally realizes the effect that the solution can contact and dissolve and strip the second dielectric layer 3 through the groove structure 31 during wet stripping.

[0057] Step S400, refer to Figure 5 , an inverted photoresist 8 is formed at the gate opening 6;

[0058] Specifically, in this embodiment, the setting of the inverted photoresist 8 mainly plays the role of sealing and protecting the gate opening 6, so as to prevent the metal from depositing at the first gate opening 6 during the subsequent step of depositing the first metal layer 9. One of the reasons for using multiple photolithographies in the prior art is that the contact layer of the gate is different from the source and drain, so the contact layer of the gate needs to be set separately. In order to prevent the metal from covering the gate opening 6 when depositing the metal layers of the source and drain, multiple photolithographies are required to separate the metal layer of the gate from the source and drain.

[0059] The reverse-type photoresist 8 is provided to prevent the deposition of the first metal layer 9 at the gate trench 6; therefore, the setting of the photoresist 8 needs to have certain limitations. The overall shape of the lithography machine in this embodiment is an inverted trapezoid. The photoresist 8 extends upward from the bottom of the gate trench 6 by a preset height. The thickness of the photoresist 8 is greater than the depth of the gate trench 6, and the width of the photoresist is greater than the width of the gate trench 6, so as to completely block the deposition of the first metal onto the gate trench 6. Moreover, the width of the top of the photoresist 8 is less than the length of the first dielectric layer 2 after lithography, so that the photoresist 8 will not extend to the positions of the drain trench 7 and the source trench 5, thereby ensuring that the first metal layer 9 can be completely deposited at the positions of the drain trench 7 and the source trench 5. Finally, the positions where the first metal layer 9 is deposited are the positions of the photoresist 8, the third dielectric layer 4, the sidewalls of the first dielectric layer 2, the drain trench 7, and the source trench 5. The first metal layer 9 serves as the contact layer for the source and the drain.

[0060] Step S500, refer to Figure 6 , deposit the first metal layer 9;

[0061] Specifically, in this embodiment, the first metal layer 9 is formed by metal evaporation deposition. The deposition in this step is a top layer deposition, that is, it will be deposited on the upper surfaces of the source trench, the drain trench, the photoresist, and the third dielectric layer. The first metal layer 9 at the positions of the source trench 5 and the drain trench 7 serves as the metal contact layer for the source and the drain to connect with external devices. The metal material can be a conductive material such as titanium, aluminum, gold, etc., and multiple layers are stacked to form a complete first metal layer 9. For example, in this embodiment, a combined layer of Ti / AI / Ni / Au is used to form the first metal layer 9.

[0062] Step S600, refer to Figure 7 , remove the photoresist 8 and the first metal layer 9 on the photoresist 8 by wet etching;

[0063] Specifically, in this embodiment, the photoresist 8 and the first metal layer 9 on the photoresist 8 are removed by wet etching. Mainly, the photoresist 8 is removed by wet etching, and after the photoresist 8 is removed, the first metal layer 9 on the photoresist 8 will naturally fall off.

[0064] Step S700, refer to Figure 8 , strip the second dielectric layer 3 and the third dielectric layer 4 by wet etching;

[0065] Specifically, in this embodiment, since both the second dielectric layer 3 and the third dielectric layer 4 are layers that are not required for the finished product, because the second dielectric layer 3 and the third dielectric layer 4 are used to prevent the deposition of the first metal layer 9 at the gate trench 6 position, the second dielectric layer 3 and the third dielectric layer 4 can be removed after the deposition of the first metal layer 9 is completed; among them, the specific steps of wet stripping are as follows: wet etching is used for wet stripping, and the wet etching solution contacts the second dielectric layer 3 through the groove structure 31 of the second dielectric layer 3, and the wet etching solution gradually dissolves the second dielectric layer 3. When the second dielectric layer 3 is dissolved and stripped, the third dielectric layer 4 will be naturally stripped; the wet etching solution used is hydrogen fluoride solution and HF solution, such as BOE buffered etchant. BOE is a mixture of HF and NH4F in different proportions. HF is the main etchant, and NH4F is used as a buffer. The concentration of [H+] is fixed by NH4F to maintain a certain etching rate. HF will etch glass and any substance containing silica.

[0066] Step S800, refer to Figures 9 - 12 , a gate contact layer is formed at the gate trench 6.

[0067] Specifically, the metal contact layers of the source and drain are completed through the previous steps, and only the structure at the gate trench 6 position remains unfinished. Therefore, this step is to form a gate contact layer at the gate trench 6 position, and thus the core device structure is completed, including the three metal contact layers of the source, gate, and drain.

[0068] Specifically, the following technical effects are brought: Since in the prior art, multiple photolithographies are mostly used because the gate contact layer is different from the source and drain, and the gate contact layer needs to be set separately. In order to prevent the metal layer of the source and drain from covering the gate trench 6 during deposition, multiple photolithographies are required to separate the gate metal layer from the source and drain; while in this application, source trenches, gate trenches, and drain trenches are formed through one photolithography, then a photoresist 8 is set at the gate trench 6, and then the first metal layer 9 is deposited to form the contact layers of the source and drain. At the same time, due to the setting of the photoresist 8, the metal deposition at the gate trench 6 position is deposited on the photoresist 8 and will not be deposited at the gate trench 6 position. Then the photoresist 8 is removed by wet etching, and finally a gate contact layer is formed at the gate trench 6. In this way, the trenches of the source, drain, and gate are formed through one photolithography step at the same time. For the critical dimensions of the gate and the critical distances from the gate to the source and drain, etc., they are completed through one photolithography, avoiding the alignment errors caused by multiple photolithographies in the traditional integration process, and thus achieving the effect that the HEMT can be made more miniaturized.

[0069] Further, in the step of forming a gate contact layer at the gate trench 6, the following steps are included:

[0070] Step S810, refer to Figure 9 , deposit the fourth dielectric layer 10 and the fifth dielectric layer 11 in sequence;

[0071] Step S820, refer to Figure 10 , open a window in the fifth dielectric layer 11 at the position of the gate slot 6;

[0072] Step S830, refer to Figure 11 , deposit the second metal layer 12 at the position of the gate slot 6, and the second metal layer 12 is a gate contact layer.

[0073] Specifically, this embodiment is the specific step process of forming a gate contact layer at the gate slot 6. First, deposit the fourth dielectric layer 10 and the fifth dielectric layer 11 in sequence. The material of the fourth dielectric layer 10 is silicon nitride SiNx or aluminum oxide Al2O3, and the thickness of the fourth dielectric layer 10 is 100 angstroms. The material of the fifth dielectric layer 11 is silicon dioxide SiO2, and the thickness of the fifth dielectric layer 11 is 3000 angstroms. Then, open a window in the fifth dielectric layer 11 at the position of the gate slot 6, specifically by photolithography and etching the fifth dielectric layer 11, that is, SiO2, to open the window of the gate. Again, deposit the second metal layer 12 at the position of the gate slot 6, and the second metal layer 12 is a gate contact layer. Specifically, the second metal layer 12 is formed by deposition and photolithography etching, that is, the required gate metal contact layer is formed. The material of the second metal layer 12 is the same as that of the first metal layer 9. The metal material in the second metal layer 12 can be a conductive material such as titanium, aluminum, gold, etc. for multi-layer stacking to form a complete second metal layer 12. For example, in this embodiment, a combined layer of Ti / AI / Ni / Au is used to form the second metal layer 12. Thus, the core device structure, including three metal contact layers of the source electrode, gate electrode, and drain electrode, is completed.

[0074] Further, after the step of forming a gate contact layer at the gate slot 6, the following steps are further included:

[0075] Step S840, refer to Figure 12 , open a window in the fourth dielectric layer 10 and the fifth dielectric layer 11 at the position of the source slot 5 to expose the first metal layer 9 to form a source contact layer;

[0076] Step S850, refer to Figure 12 , open a window in the fourth dielectric layer 10 and the fifth dielectric layer 11 at the position of the drain slot 7 to expose the first metal layer 9 to form a drain contact layer.

[0077] Specifically, in this embodiment, both the fourth dielectric layer 10 and the fifth dielectric layer 11 are deposited, so they will be deposited at the positions of the source electrode and the drain electrode simultaneously. Therefore, it is necessary to open windows in the fourth dielectric layer 10 and the fifth dielectric layer 11 at the position of the source electrode slot 5 to expose the first metal layer 9 to form a source electrode contact layer; and open windows in the fourth dielectric layer 10 and the fifth dielectric layer 11 at the position of the drain electrode slot 7 to expose the first metal layer 9 to form a drain electrode contact layer. Finally, the first metal layer 9 and the second metal layer 12 on the source electrode, the drain electrode, and the gate are exposed, so as to form metal contact layers corresponding to the end electrodes to connect with other electrical components.

[0078] Further, the material of the fourth dielectric layer 10 is silicon nitride SiNx or aluminum oxide Al2O3, and the thickness of the fourth dielectric layer 10 is 100 angstroms. The material of the fifth dielectric layer 11 is silicon dioxide SiO2, and the thickness of the fifth dielectric layer 11 is 3000 angstroms.

[0079] Further, the substrate 1 sequentially includes a high-resistance silicon layer, a buffer layer, a gallium nitride layer, and a gallium aluminum nitride layer from bottom to top.

[0080] Correspondingly, it is fabricated by the method of fabricating the gate, source electrode, and drain electrode of the HEMT through one-time photolithography as described in the above embodiment.

[0081] Correspondingly, the present invention also provides an electronic device including a transistor as described in the above embodiment.

[0082] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order from here, or they can be fabricated into individual integrated circuit modules respectively, or multiple modules or steps among them can be fabricated into a single integrated circuit module to be implemented. In this way, the present invention is not limited to any specific combination of hardware and software.

[0083] It should be noted that other contents of the method, transistor, and electronic device for fabricating the gate, source electrode, and drain electrode of the HEMT by one-time photolithography disclosed in the present invention can be referred to the prior art and will not be elaborated here.

[0084] The above are only optional embodiments of the present invention and do not impose any form of limitation on the present invention. Therefore, any modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. Method for fabricating the gate, source and drain of a HEMT by one-time photolithography, Characterized in that, Comprising the following steps: Deposit a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate in sequence; Perform photolithography on the first dielectric layer, the second dielectric layer and the third dielectric layer to form a source slot, a gate slot and a drain slot; Perform wet etching on the second dielectric layer after photolithography to form a groove structure; Form an inverted photoresist at the gate slot; Deposit a first metal layer; Remove the photoresist and the first metal layer on the photoresist by wet method; Strip the second dielectric layer and the third dielectric layer by wet method; Form a gate contact layer at the gate slot; Wherein, in the step of forming an inverted photoresist at the gate slot, the photoresist extends upward from the bottom of the gate slot by a preset height, the thickness of the photoresist is greater than the depth of the gate slot, and the width of the photoresist is greater than the width of the gate slot; and the width of the top of the photoresist is less than the length of the first dielectric layer after photolithography, so that the photoresist does not extend to the positions of the drain slot and the source slot; Wherein, in the step of forming a gate contact layer at the gate slot, it includes the following steps: Deposit a fourth dielectric layer and a fifth dielectric layer in sequence; Open a window in the fifth dielectric layer at the gate slot position; Deposit a second metal layer at the gate slot position, and the second metal layer is the gate contact layer.

2. The method for fabricating the gate, source and drain of a HEMT by one-time photolithography according to claim 1, Characterized in that, After the step of forming a gate contact layer at the gate slot, the following steps are further included: Open a window in the fourth dielectric layer and the fifth dielectric layer at the source slot position to expose the first metal layer to form a source contact layer; Open a window in the fourth dielectric layer and the fifth dielectric layer at the drain slot position to expose the first metal layer to form a drain contact layer.

3. The method for fabricating the gate, source and drain of a HEMT by one-time photolithography according to claim 1, Characterized in that, The first dielectric layer and the third dielectric layer are silicon nitride SiNx, and the second dielectric layer is silicon dioxide SiO2.

4. The method for fabricating the gate, source and drain of a HEMT by one-time photolithography according to claim 1, Characterized in that, The material of the fourth dielectric layer is silicon nitride SiNx or aluminum oxide Al2O3, and the thickness of the fourth dielectric layer is 100 Å, the material of the fifth dielectric layer is silicon dioxide SiO2, and the thickness of the fifth dielectric layer is 3000 Å.

5. The method for fabricating the gate, source and drain of a HEMT by one-time photolithography according to claim 1, Characterized in that, In the step of performing wet etching on the second dielectric layer after photolithography to form a groove structure, the wet etching solution used is a hydrogen fluoride solution.

6. The method for fabricating the gate, source and drain of a HEMT by one-time photolithography according to claim 1, Characterized in that, The substrate sequentially includes a high-resistance silicon layer, a buffer layer, a gallium nitride layer, and a gallium aluminum nitride layer from bottom to top.

7. A transistor, characterized in that, it is fabricated by the method for fabricating the gate, source, and drain of the HEMT through single lithography as described in any one of claims 1-6.

8. An electronic device, characterized in that, it includes the transistor as described in claim 7.

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