Methods for improving STI flatness

Abstract

The present invention provides a method for improving STI flatness, comprising providing a substrate having a well and an STI formed thereon to define an active area; forming a photoresist layer on the substrate to cover the STI and the active area, and performing photolithography to expose the active area and a portion of the STI; performing ion implantation on the exposed active area and the portion of the STI to form a lightly doped drain; and implanting ions into the exposed active area and the portion of the STI using inactive ions, wherein the depth of the STI implanted with ions is a first depth, and the depth of the STI not implanted with ions is a second depth, and the difference between the first depth and the second depth is less than 10 angstroms. The present invention improves the height difference between the STI region implanted with ions and the STI region not implanted with ions, facilitates the removal of dummy gates, and prevents the performance of the metal gate from being affected after formation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving STI flatness. Background Art

[0002] The STI (shallow trench isolation) effect refers to the fact that carriers generate different carrier densities as their distance from the STI edge changes. The farther away from the STI edge, the sparser the carrier distribution. To prevent the STI effect, the mask opening is usually opened on the STI. At this time, both the STI part area and the active area are ion implanted. Ion implantation affects the etching rate of the subsequent oxide layer removal, causing the ion-implanted part of the STI area to be lower than the non-ion-implanted part, with a gap of about 100 angstroms. This gap will cause some residue when the dummy gate is removed, affecting the performance of the metal gate.

[0003] Therefore, a method for improving STI flatness is needed to improve the height difference between the STI ion-implanted portion and the non-ion-implanted portion, so as to facilitate the removal of the dummy gate on the metal gate without affecting the performance of the metal gate. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for improving STI flatness, which is used to solve the problem in the prior art that ion implantation affects the etching rate of the subsequent oxide layer removal, resulting in the ion-implanted portion of the STI region being lower than the non-ion-implanted portion. This height difference will cause some residue to remain when the dummy gate is removed, affecting the performance of the metal gate.

[0005] To achieve the above objectives and other related objectives, the present invention provides a method for improving STI flatness, comprising:

[0006] Step 1: providing a substrate, wherein a well is formed on the substrate, and an STI is also formed on the substrate to define an active area;

[0007] Step 2: forming a photoresist layer covering the STI and the active area on the substrate, and performing photolithography to expose the active area and the STI portion;

[0008] Step 3: performing ion implantation on the exposed active area and part of the STI to form a lightly doped drain;

[0009] Step 4: Use non-activated ions to perform ion implantation on the exposed active area and part of the STI, wherein the depth of the STI implanted with ions is a first depth, and the depth of the STI not implanted with ions is a second depth, so that the difference between the first depth and the second depth is less than 10 angstroms.

[0010] Preferably, the substrate in step 1 is a silicon substrate.

[0011] Preferably, the exposed portion of the STI in step 2 is a rectangle with a length and a width of 0.1 micrometer to 0.2 micrometer.

[0012] Preferably, the element type of the non-activated ions in step 4 is the fourth group or the zero group in the periodic table.

[0013] Preferably, the inactive ions in step 4 are any one of silicon ions, argon ions, xenon ions and germanium ions.

[0014] Preferably, the implantation energy of the ion implantation in step 4 is 1 to 60 keV.

[0015] Preferably, the ion implantation in step 4 has an implantation dose of 1E14 to 5E16 atom / cm2.

[0016] Preferably, the ion implantation in step 4 is performed with a tilt and rotation angle, wherein the tilt angle and the rotation angle are both 0 degrees.

[0017] Preferably, the method further comprises step five of removing the photoresist layer, and then forming a metal gate between the lightly doped drains on the same well using a gate-last process.

[0018] Preferably, the gate-last process includes:

[0019] (1) forming a dummy gate in the active region;

[0020] (2) forming a sidewall spacer on the sidewall of the dummy gate;

[0021] (3) heavily doping the active region;

[0022] (4) forming an interlayer dielectric layer covering the dummy gate and the sidewalls;

[0023] (5) polishing the interlayer dielectric layer by chemical mechanical planarization to expose the dummy gate;

[0024] (6) removing the dummy gate so that a trench is formed between the sidewalls;

[0025] (7) Forming a metal gate in the trench.

[0026] Preferably, the material of the interlayer dielectric layer in step (4) is silicon dioxide.

[0027] As described above, the method for improving STI flatness of the present invention has the following beneficial effects:

[0028] The present invention improves the height difference between the ion-implanted STI region and the non-ion-implanted STI region, facilitates the subsequent removal of the dummy gate, and avoids the performance of the metal gate being affected after formation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0030] Figure 2 Shown is a schematic diagram of the active region defined by STI in the substrate of the present invention;

[0031] Figure 3 It is a schematic diagram showing the method of defining a lightly doped region by photolithography according to the present invention;

[0032] Figure 4 Shown is a schematic diagram of the lightly doped embodiment of the present invention;

[0033] Figure 5 Shown is a schematic diagram of the present invention after forming a dummy gate;

[0034] Figure 6 Schematic diagram showing heavy doping after forming sidewall spacers according to the present invention;

[0035] Figure 7 It is a schematic diagram showing the interlayer dielectric layer formed and then polished according to the present invention;

[0036] Figure 8 Shown is a schematic diagram of the present invention after heavy doping and removal of the dummy gate;

[0037] Figure 9 Shown is a schematic diagram of forming a metal gate according to the present invention;

[0038] Figure 10 Shown is a schematic diagram of the implantation position of STI non-activated ions according to the present invention. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] See also Figure 1 The present invention provides a method for improving the flatness of STI12, comprising:

[0041] Step 1, see Figure 2, providing a substrate 10, on which a well 11 is formed, wherein the well 11 is a P well 11 and an N well 11, and an STI 12 is further formed on the substrate 10 to define an active region;

[0042] In a possible embodiment, the substrate 10 in step 1 is a silicon substrate 10. The well 11 can be formed directly on the substrate 10 by ion implantation, or after an epitaxial layer is formed on the substrate 10, the well 11 can be formed on the epitaxial layer by ion implantation.

[0043] Step 2, please refer to Figure 3 , forming a photoresist 13 layer covering the STI 12 and the active area on the substrate 10, and exposing the active area and part of the STI 12 by photolithography, and the exposed part of the well 11 is the area to be lightly doped later;

[0044] In one possible implementation, see Figure 10 The exposed portion of the STI 12 in step 2 is a rectangle with a length and a width of 0.1 micron to 0.2 micron.

[0045] Step 3: Ion implantation is performed on the exposed active area and part of the STI 12 to form a lightly doped drain, as shown below. Figure 4 The structure shown;

[0046] Specifically, for example, when ion implantation is performed on the P-well 11 , the N-well 11 may be masked by the photoresist 13 layer, so that the P-well 11 and the surrounding STI 12 are partially exposed, and then lightly doped drain implantation is performed with N ions.

[0047] In step 4, non-activated ions are used to perform ion implantation on the exposed active area and part of the STI 12, i.e., ion implantation is performed on the rectangular area 121 as shown in FIG10 , wherein the depth of the STI 12 implanted with ions is a first depth, and the depth of the STI 12 not implanted with ions is a second depth. In the prior art, there is a difference of about 100 angstroms between the first depth and the second depth of ion implantation. After adopting this step, the difference between the first depth and the second depth can be made less than 10 angstroms.

[0048] In a possible embodiment, the element type of the non-activated ions in step 4 is the fourth group or the zero group in the periodic table.

[0049] In one possible embodiment, the non-activated ions in step four are any one of silicon ions, argon ions, xenon ions and germanium ions, and the preferred embodiment is silicon ions. It should be understood that other types of non-activated ions can also be used here to compensate for the height difference between the ion-implanted STI12 area and the non-ion-implanted STI12 area, and there is no specific limitation on their ion type.

[0050] In a possible implementation manner, the implantation energy of the ion implantation in step 4 is 1 to 60 keV, preferably 3 keV. The implantation energy is determined by the actual process and is not specifically limited here.

[0051] In one possible implementation, the ion implantation dosage in step 4 is 1E14 to 5E16 atom / cm 2 , and preferably 1E15 atom / cm 2 .

[0052] In a possible embodiment, the preferred implantation angle of the ion implantation in step 4 is that both the tilt angle and the rotation angle of the ion implantation are 0 degrees.

[0053] In a possible embodiment, the method further includes step five of removing the photoresist layer 13 , and then forming a metal gate 17 between the lightly doped drains on the same well 11 by using a gate-last process.

[0054] In one possible implementation, the gate-last process includes:

[0055] (1) A pseudo gate 14 is formed in the active region to obtain Figure 5 In the structure shown, the dummy gate 14 is located between the lightly doped drains formed previously;

[0056] (2) forming a sidewall spacer 15 on the sidewall of the dummy gate 14;

[0057] (3) Heavy doping of the active region yields the following Figure 6 The structure shown;

[0058] (4) forming an interlayer dielectric layer 16 covering the dummy gate 14 and the sidewall 15;

[0059] (5) Grinding the interlayer dielectric layer 16 by chemical mechanical planarization to expose the dummy gate 14, and obtaining the following Figure 7 The structure shown;

[0060] (6) Remove the pseudo gate 14 so that a groove is formed between the sidewalls 15, forming a Figure 8 In the structure shown, the STI 12 in the prior art has a difference of approximately 100 angstroms between the first and second ion implantation depths, which can cause some residue when the dummy gate 14 is removed, affecting the performance of the metal gate 17. After ion implantation of inactive ions into the exposed active area and part of the STI 12, the difference between the implanted and unimplanted depths of the STI 12 is less than 10 angstroms, thereby improving the residue of the dummy gate 14.

[0061] (7) Form a metal gate 17 in the trench, forming Figure 9 The structure shown.

[0062] In one possible embodiment, the material of the interlayer dielectric layer 16 in step (4) is silicon dioxide.

[0063] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0064] In summary, the present invention improves the height difference between the ion-implanted STI region and the non-ion-implanted STI region, facilitating subsequent removal of the dummy gate and preventing degradation of metal gate performance after fabrication. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses significant industrial value.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving STI flatness, characterized in that: At least: Step 1: providing a substrate, on which a well is formed, and forming an STI to define an active area; Step 2: forming a photoresist layer covering the STI and the active area on the substrate, and performing photolithography to expose the active area and a portion of the STI; Step 3: performing ion implantation on the exposed active area and part of the STI to form a lightly doped drain; Step 4: Performing ion implantation on the exposed active area and a portion of the STI using inactive ions, where the inactive ions are from Group IV or Group 0 of the periodic table and are any one of silicon ions, argon ions, xenon ions, and germanium ions. The depth of the STI implanted with ions is a first depth, and the depth of the STI not implanted with ions is a second depth, and the difference between the first depth and the second depth is less than 10 angstroms.

2. The method for improving STI flatness according to claim 1, wherein: The substrate in step 1 is a silicon substrate.

3. The method for improving STI flatness according to claim 1, wherein: The exposed portion of the STI in step 2 is a rectangle with a length and a width of 0.1 micrometer to 0.2 micrometer.

4. The method for improving STI flatness according to claim 1, wherein: The implantation energy of the ion implantation in step 4 is 1 to 60 keV.

5. The method for improving STI flatness according to claim 1, wherein: The ion implantation in step 4 has an implantation dose of 1E14 to 5E16 atom / cm 2 .

6. The method for improving STI flatness according to claim 1, wherein: The ion implantation in step 4 is performed with a tilt and rotation angle, wherein the tilt angle and the rotation angle are both 0 degrees.

7. The method for improving STI flatness according to claim 1, wherein: The method further includes step five of removing the photoresist layer, and then forming a metal gate between the lightly doped drains on the same well using a gate-last process.

8. The method for improving STI flatness according to claim 7, wherein: The gate-last process includes: (1) forming a dummy gate in the active area; (2) forming a sidewall on the sidewall of the dummy gate; (3) heavily doping the active area; (4) forming an interlayer dielectric layer covering the dummy gate and the sidewall; (5) grinding the interlayer dielectric layer by chemical mechanical planarization to expose the dummy gate; (6) removing the dummy gate to form a trench between the sidewalls; and (7) forming a metal gate in the trench.

9. The method for improving STI flatness according to claim 8, wherein: The material of the interlayer dielectric layer in step (4) is silicon dioxide.

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