Anti-latch-up circuit and chip for tri-state output stage

Abstract

The application provides a latch prevention circuit and a chip for a tri-state output stage, comprising a tri-state output circuit, an N-Well potential selection circuit and a P-Well potential selection circuit; an input end is arranged on the tri-state output circuit, and output ends of the tri-state output circuit are connected with the N-Well potential selection circuit and the P-Well potential selection circuit respectively. Only several MOS transistors are adopted, so that the circuit power consumption and manufacturing cost are greatly reduced, the tri-state gate output stage circuit and the inverter output driving stage circuit are commonly used, the base potential selection of a parasitic bipolar device can be automatically performed, the formation of a parasitic loop is prevented, and thus the latch effect is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to an anti-latch circuit and chip for a three-state output stage. Background Art

[0002] In many interface chips, the three-state output stage typically operates in high-speed mode. Due to internal chip parasitics and parasitic inductance from package bonding, the three-state output stage experiences an upward overcharge (greater than the power supply Vdd) and a downward overshoot (less than ground potential), causing the chip to latch up and malfunction.

[0003] Traditional three-state output circuits are usually directly connected to the chip pins. Due to the presence of package parasitic inductance, when the chip is operating normally, an upward overcharge voltage higher than the power supply and a downward overcharge voltage lower than the ground potential will usually occur. If the overcharge is too large or lasts too long, it is likely that the chip will latch up. The specific process is as follows:

[0004] like Figure 1 As shown in Figure 1, (a) is a parasitic bipolar transistor in a tri-state gate circuit, and (b) is the equivalent circuit of this parasitic transistor. When a large upward overcharge occurs at the output, the emitter junction of the PNP transistor turns on, and current is injected into Rp, turning on the emitter junction of the NPN transistor. This current flows through Rn, creating a voltage drop across Rn relative to Vdd, turning on the PNP transistor. At this point, a positive feedback loop is formed by Rn, Rp, NPN, and PNP. If the loop gain is greater than 1, the loop becomes active until both transistors are fully turned on, drawing a large current from Vdd, and the circuit latches.

[0005] In most interface circuits, to prevent latch-up, chip area is often sacrificed in exchange for stronger anti-latch-up capabilities, or complex circuits are used to implement the chip's anti-latch-up function. This increases chip manufacturing costs and circuit power consumption to a certain extent.

[0006] In the Chinese patent document with publication number CN101916760A, a thyristor ESD protection structure that effectively avoids the latch-up effect is disclosed. The thyristor device is used to avoid the latch-up effect of the chip while achieving ESD protection. However, this implementation uses BJT and resistor-capacitor devices, which increases the manufacturing cost of the chip to a certain extent.

[0007] In the Chinese patent document with publication number CN113410232A, a CMOS integrated circuit chip and a preparation process for suppressing the latch-up effect are disclosed, which avoids the occurrence of latch-up from the aspects of process and equipment manufacturing. The present invention directly solves the problem of latch-up from the perspective of circuit design. SUMMARY

[0008] In view of the defects in the prior art, the present application aims to provide an anti-latch-up circuit and chip for a tri-state output stage.

[0009] The anti-latch-up circuit for a tri-state output stage according to the present application comprises a tri-state output circuit, an N-Well potential selection circuit and a P-Well potential selection circuit; an input end is arranged on the tri-state output circuit, and the output end of the tri-state output circuit is connected with the N-Well potential selection circuit and the P-Well potential selection circuit respectively.

[0010] Preferably, the tri-state output circuit comprises a mos transistor M1 and a mos transistor M2; the gate of the mos transistor M1 constitutes an Input1 end, and the source of the mos transistor M1 is connected with Vdd; the gate of the mos transistor M2 constitutes an Input2 end, and the source of the mos transistor M2 is connected with GND; the drain of the mos transistor M1 is connected with the drain of the mos transistor M2 and constitutes an Output end.

[0011] Preferably, the N-Well potential selection circuit comprises a mos transistor M3 and a mos transistor M4, and the P-Well potential selection circuit comprises a mos transistor M5 and a mos transistor M6.

[0012] The source of the mos transistor M1 is connected with the source of the mos transistor M4 and the gate of the mos transistor M3 respectively, and the substrate of the mos transistor M1 is connected with the substrate and the drain of the mos transistor M3 and the substrate and the drain of the mos transistor M4 respectively.

[0013] The source of the mos transistor M2 is connected with the gate of the mos transistor M5 and the source of the mos transistor M6 respectively, and the substrate of the mos transistor M2 is connected with the substrate and the drain of the mos transistor M5 and the substrate and the drain of the mos transistor M6 respectively.

[0014] The Output end is connected with the source of the mos transistor M3, the gate of the mos transistor M4, the source of the mos transistor M5 and the gate of the mos transistor M6.

[0015] Preferably, the substrate and the drain of the mos transistor M3 constitute a voltage output end of the N-Well potential selection circuit.

[0016] Preferably, the substrate and the drain of the mos transistor M5 constitute a voltage output end of the P-Well potential selection circuit.

[0017] Preferably, the tri-state output circuit comprises a parasitic PNP transistor, a parasitic NPN transistor, a parasitic resistor Rp and a parasitic resistor Rn, one emitter of the PNP transistor is connected with Vdd, the other emitter of the PNP transistor constitutes the connection of the Output terminal, the collector of the PNP transistor is connected with one end of the resistor Rp and the base of the NPN transistor respectively, the other end of the resistor Rp is connected with the P-Well potential selection circuit, the base of the PNP transistor is connected with one end of the resistor Rn and the collector of the NPN transistor respectively, the other end of the resistor Rn is connected with the N-Well potential selection circuit, one emitter of the NPN transistor constitutes the Output terminal, the other emitter of the NPN transistor is connected with the GND terminal.

[0018] Preferably, the other end of the resistor Rp is connected with the substrate and the drain of the mos transistor M5 and the substrate and the drain of the mos transistor M6 respectively; one emitter of the PNP transistor is connected with the source of the mos transistor M5 and the gate of the mos transistor M6 respectively, the source of the mos transistor M6 is connected with the GND terminal, the source of the mos transistor M4 and the gate of the mos transistor M3 is connected with Vdd, the other end of the resistor Rn is connected with the substrate and the drain of the mos transistor M4 and the substrate and the drain of the mos transistor M3 respectively, one emitter of the NPN transistor is connected with the source of the mos transistor M3 and the gate of the mos transistor M4 respectively.

[0019] According to the chip provided by the application, the tri-state output stage anti-latch circuit is provided.

[0020] Compared with the prior art, the application has the following beneficial effects:

[0021] 1. Only a few MOS transistors are used, which greatly reduces the circuit power consumption and manufacturing cost;

[0022] 2. The circuit provided by the application is applicable to tri-state gate output stage circuits and inverter output drive stage circuits, can automatically select the base potential of the parasitic bipolar device, prevents the formation of a parasitic loop, and thus avoids the latch effect.

[0023] 3. The technical circuit has simple structure, is convenient to apply, does not consume static power consumption, and is easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0025] Figure 1 The parasitic effect of the tri-state gate output stage circuit in the prior art and the equivalent circuit;

[0026] Figure 2 The figure is a schematic diagram of the anti-latching circuit in the embodiment of the present application.

[0027] Figure 3 The figure is a parasitic equivalent circuit of the tri-state gate output stage circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0028] The present application will be described in detail below with specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present application. These are within the scope of protection of the present application.

[0029] The present application introduces an anti-latching circuit for a tri-state output stage, which comprises a tri-state output circuit, an N-Well potential selection circuit and a P-Well potential selection circuit; an input end is arranged on the tri-state output circuit, and the output end of the tri-state output circuit is connected with the N-Well potential selection circuit and the P-Well potential selection circuit respectively.

[0030] Reference Figure 2 The tri-state output circuit comprises a mos transistor M1 and a mos transistor M2, the gate of the mos transistor M1 constitutes an Input1 end, and the source of the mos transistor M1 is connected with Vdd; the gate of the mos transistor M2 constitutes an Input2 end, the source of the mos transistor M2 is connected with GND, and the drain of the mos transistor M1 is connected with the drain of the mos transistor M2 and constitutes an Output end.

[0031] The N-Well potential selection circuit comprises a mos transistor M3 and a mos transistor M4, and the P-Well potential selection circuit comprises a mos transistor M5 and a mos transistor M6.

[0032] The source of the mos transistor M1 is connected with the source of the mos transistor M4 and the gate of the mos transistor M3 respectively, and the substrate of the mos transistor M1 is connected with the substrate and the drain of the mos transistor M3 and the substrate and the drain of the mos transistor M4 respectively.

[0033] The source of the mos transistor M2 is connected with the gate of the mos transistor M5 and the source of the mos transistor M6 respectively, and the substrate of the mos transistor M2 is connected with the substrate and the drain of the mos transistor M5 and the substrate and the drain of the mos transistor M6 respectively.

[0034] The Output end is connected with the source of the mos transistor M3, the gate of the mos transistor M4, the source of the mos transistor M5 and the gate of the mos transistor M6.

[0035] The substrate and drain of the mos transistor M3 constitute the voltage output end of the N-Well potential selection circuit; the substrate and drain of the mos transistor M5 constitute the voltage output end of the P-Well potential selection circuit.

[0036] When the output (Output) voltage of the tri-state output circuit 101 appears upward overshoot, and the overshoot is greater than V dd +V th,p , M4 in the N-Well potential selection circuit 102 is closed, and M3 is opened, at this time, the output voltage V-NW of 102 is equal to the output voltage of 101, so that the substrate potential of M1 is selected as a potential higher than Vdd. When the output (Output) voltage of the tri-state output circuit 101 appears downward overshoot, and the overshoot is less than Gnd-V th,n , M6 in the P-Well potential selection circuit 103 is closed, and M5 is opened, at this time, the output voltage V-PW of 103 is equal to the output voltage of 101, so that the substrate potential of M2 is selected as a potential lower than Gnd.

[0037] Referring Figure 3 , the suppression of the parasitic circuit loop of the tri-state output circuit can be explained as follows: the parasitic circuit of the tri-state output circuit includes a PNP transistor, an NPN transistor, a resistor Rp and a resistor Rn, one emitter of the PNP transistor is connected to Vdd, the other emitter of the PNP transistor constitutes the Outout end, the collector of the PNP transistor is connected to one end of the resistor Rp and the base of the NPN transistor, the other end of the resistor Rp is connected to the P-Well potential selection circuit, the base of the PNP transistor is connected to one end of the resistor Rn and the collector of the NPN transistor, the other end of the resistor Rn is connected to the N-Well potential selection circuit, one emitter of the NPN transistor constitutes the Output end, and the other emitter of the NPN transistor is connected to the GND end.

[0038] The other end of the resistor Rp is connected to the substrate and drain of the mos transistor M5 and the substrate and drain of the mos transistor M6; one emitter of the PNP transistor is connected to the source of the mos transistor M5 and the gate of the mos transistor M6, the source of the mos transistor M6 is connected to the GND end, the source of the mos transistor M4 and the gate of the mos transistor M3 are connected to Vdd, the other end of the resistor Rn is connected to the substrate and drain of the mos transistor M4 and the substrate and drain of the mos transistor M3, and one emitter of the NPN transistor is connected to the source of the mos transistor M3 and the gate of the mos transistor M4.

[0039] As Figure 3 shown, when the output (Output) voltage of the tri-state output circuit 101 appears upward overshoot, and the overshoot is greater than V dd +Vth,p When the output voltage of the tri-state output circuit 101 is equal to Vdd, the output voltage of the N-Well selection circuit is equal to the output voltage of the tri-state output circuit, and the output voltage of the P-Well selection circuit is equal to Gnd. At this time, the base voltage of the PNP is equal to Vdd and greater than Gnd, and the base voltage of the NPN is equal to Gnd, so the PNP and the NPN are both in the off state, the parasitic loop is closed, and the Latch-Up phenomenon is avoided.

[0040] When the output (Output) voltage of the tri-state output circuit 101 appears to be down overshoot, and the overshoot size is less than Gnd+V th,n When the output voltage of the tri-state output circuit 101 is equal to Vdd, the output voltage of the N-Well selection circuit is equal to the output voltage of the tri-state output circuit, and the output voltage of the P-Well selection circuit is equal to Gnd. At this time, the base voltage of the PNP is equal to Vdd and greater than Gnd, and the base voltage of the NPN is equal to Gnd, so the PNP and the NPN are both in the off state, the parasitic loop is closed, and the Latch-Up phenomenon is avoided.

[0041] The application also introduces a chip comprising the anti-latch-up circuit of the tri-state output stage.

[0042] Those skilled in the art know that, in addition to implementing the system provided by the application and each device, module and unit thereof in the form of pure computer readable program code, the same functions can also be achieved by logically programming the method steps in the form of logic gates, switches, special integrated circuits, programmable logic controllers and embedded microcontrollers. Therefore, the system provided by the application and each device, module and unit thereof can be considered as a hardware component, and the devices, modules and units included therein for achieving various functions can also be considered as structures within the hardware component. The devices, modules and units for achieving various functions can also be considered as both software modules for implementing methods and structures within hardware components.

[0043] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0044] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be combined with each other at will without conflict.

Claims

1. An anti-latch-up circuit for a tri-state output stage, characterized by The tri-state output circuit, the N-Well potential selection circuit and the P-Well potential selection circuit are included; an input end is arranged on the tri-state output circuit, and the output end of the tri-state output circuit is connected with the N-Well potential selection circuit and the P-Well potential selection circuit respectively; The tri-state output circuit includes a mos tube M1 and a mos tube M2, the gate of the mos tube M1 constitutes an Input1 end, and the source of the mos tube M1 is connected with Vdd; the gate of the mos tube M2 constitutes an Input2 end, the source of the mos tube M2 is connected with GND, and the drain of the mos tube M1 is connected with the drain of the mos tube M2 and constitutes an Output end; The N-Well potential selection circuit includes a mos tube M3 and a mos tube M4, and the P-Well potential selection circuit includes a mos tube M5 and a mos tube M6; The source of the mos tube M1 is connected with the source of the mos tube M4 and the gate of the mos tube M3 respectively, and the substrate of the mos tube M1 is connected with the substrate and the drain of the mos tube M3 and the substrate and the drain of the mos tube M4 respectively; The source of the mos tube M2 is connected with the gate of the mos tube M5 and the source of the mos tube M6 respectively, and the substrate of the mos tube M2 is connected with the substrate and the drain of the mos tube M5 and the substrate and the drain of the mos tube M6 respectively; The Output end is connected with the source of the mos tube M3, the gate of the mos tube M4, the source of the mos tube M5 and the gate of the mos tube M6; The tri-state output circuit includes a parasitic PNP transistor, a parasitic NPN transistor, a parasitic resistor Rp and a parasitic resistor Rn, one emitter of the PNP transistor is connected with Vdd, the other emitter of the PNP transistor constitutes a connection Output end, the collector of the PNP transistor is connected with one end of the resistor Rp and the base of the NPN transistor respectively, the other end of the resistor Rp is connected with the P-Well potential selection circuit, the base of the PNP transistor is connected with one end of the resistor Rn and the collector of the NPN transistor respectively, the other end of the resistor Rn is connected with the N-Well potential selection circuit, one emitter of the NPN transistor constitutes the Output end, and the other emitter of the NPN transistor is connected with the GND end.

2. The anti-latch circuit for a tri-state output stage of claim 1, wherein: The substrate and the drain of the mos tube M3 constitute a voltage output end of the N-Well potential selection circuit.

3. The anti-latch circuit for a tri-state output stage of claim 1, wherein: The substrate and the drain of the mos tube M5 constitute a voltage output end of the P-Well potential selection circuit.

4. The anti-latch-up circuit for a tri-state output stage of claim 1, wherein: The other end of the parasitic resistor Rp is connected with the substrate and the drain of the mos tube M5 and the substrate and the drain of the mos tube M6 respectively. One emitter of the PNP triode is connected to the source of the mos M5 and the gate of the mos M6, the source of the mos M6 is connected to the GND terminal, the source of the mos M4 and the gate of the mos M3 are connected to the Vdd terminal, the other end of the resistor Rn is connected to the substrate and the drain of the mos M4 and the substrate and the drain of the mos M3, respectively, one emitter of the NPN triode is connected to the source of the mos M3 and the gate of the mos M4, respectively.

5. A chip, characterized by: An anti-latch-up circuit comprising a tri-state output stage according to any one of claims 1 to 4.

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