Mask package for preventing degradation during the fabrication of high aspect ratio features

Abstract

A tool and method for fabricating high aspect ratio features with very tight critical dimension control by processing the substrate in a manner that encapsulates the mask to prevent degradation during etch back, thereby preventing feature liner material from pinching off during the deposition-etch cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 62 / 909,073, filed October 1, 2019, which is incorporated herein by reference for all purposes. Technical Field

[0003] The present application relates to processing substrates, and more particularly, to encapsulating masks to prevent degradation during deposition-etch cycles used to fabricate high aspect ratio features with very tight critical dimension control. Background Art

[0004] The fabrication of certain semiconductor devices often involves vertically etching features in layers or stacks of layers of various materials, including but not limited to silicon nitride, silicon oxide, polysilicon, boron-doped oxides, other oxides, ashable hard masks (AHMs), carbon masks, and the like.

[0005] Features typically etched vertically into a single layer or stack of layers can vary widely in shape. Common features typically include, but are not limited to, columns, holes, trenches, slits, and other geometric or non-geometric shapes.

[0006] The aspect ratio of a given vertical etched feature is defined by its depth divided by its width. For example, a high aspect ratio column is characterized by a relatively small diameter (i.e., width) relative to its relatively deep depth. A high aspect ratio trench is defined as having a relatively deep depth and a relatively narrow sidewall-to-sidewall width.

[0007] The fabrication of high-aspect-ratio features is crucial for certain types of semiconductor devices. For example, in 3D NAND memory devices, it is desirable to fabricate pillars, trenches, and other features with very high aspect ratios that span the depth of multiple stacked layers within the device. However, fabricating extremely high-aspect-ratio features is difficult using current manufacturing processes.

[0008] During deep vertical etch processes, the sidewalls of features inevitably etch. This lateral etching undesirably increases the width of the feature, reduces the aspect ratio, and can cause sidewall distortion and / or bowing. The extent of lateral etching, distortion, and / or bowing is characterized by the critical dimension, or "CD," measurement, of the feature. Generally, the smaller the CD of a feature, the better.

[0009] To improve CD measurements, it is known to use lateral etch barriers or "liners" on the sidewalls of features. These sidewall liners are typically metal-based materials (such as tungsten carbide or "WC") or carbon-based polymers that act as a barrier to mitigate the effects of lateral etching during vertical etching. While these liners work to some extent, they have some disadvantages. If the liner material is highly resistant to fluorine-, chlorine-, and / or bromine-based etching chemistries, the liner material may interact with the vertical etching process, causing streaks and kinks, typically resulting in undesirable uneven and rough vertical grooves in the sidewalls, uneven concave profiles, and irregularities in the holes on the flat surface of the layer or layer stack in which the feature is vertically etched. If the liner material is not highly resistant to the etching chemistry, the protection against bowing may be insufficient or inadequate.

[0010] This problem is problematic for several reasons. First, because the insulation between features can be insufficient due to bending phenomena, electrical shorts between features can occur. Second, to avoid the possibility of electrical shorts, features are carefully spaced farther apart than would normally be desirable. Consequently, the density of some semiconductor devices is lower than achievable with a given processing technology. Third, surface irregularities on the sidewalls and recesses at the bottom of the features result in poor contact surfaces and make it difficult to deposit other films and / or materials into the features.

[0011] Therefore, when pushing the boundaries when vertically etching high aspect ratio features, conventional metal-based or carbon-based polymer liners are insufficient. For the next generation of process technologies, new processes for fabricating deep features with extremely high aspect ratios and tight critical dimension control in semiconductor structures are therefore needed. Summary of the Invention

[0012] The present invention relates to semiconductor processing for fabricating deep features with very high aspect ratios and tight critical dimension (CD) control.

[0013] In one non-exclusive embodiment, the present invention is directed to a method of fabricating a semiconductor substrate comprising: (a) vertically etching a feature in one or more layers formed on the semiconductor substrate, the feature having sidewalls and a depth; and (b) depositing an amorphous carbon liner on the sidewalls of the feature.

[0014] In certain non-exclusive embodiments, the present invention further relates to iterating (a) and optionally iterating (b) until the feature reaches a desired depth. In each iteration of step (a), the feature is etched vertically deeper to the one or more layers, while the amorphous carbon liner resists lateral vertical etching of the sidewalls of the feature. In each optional iteration of (b), the amorphous carbon liner deposited on the sidewalls of the feature is replenished.

[0015] In other non-exclusive embodiments, the present invention is directed to fabricating features into a semiconductor substrate by:

[0016] (a) encapsulating the top surface, openings, and sidewalls (i.e., the "neck") of the mask, which define the features nominally etched into the semiconductor substrate, with an etch-resistant material;

[0017] (b) depositing an amorphous carbon liner on the sidewalls of the mask and the sidewalls of the etched features;

[0018] (c) performing an amorphous carbon liner etch to remove excess amorphous carbon that may have been deposited around the opening, sidewalls, and / or neck of the mask during deposition of the amorphous carbon liner;

[0019] (d) performing feature etching to increase the depth of the feature in the semiconductor substrate.

[0020] For variations of the above embodiments, each of steps (a) to (d) can be repeated individually or collectively as needed or desired. By selectively performing steps (a)-(d), a number of advantages can be achieved. First, by encapsulating the mask with an etch-resistant material, amorphous carbon liner etching can occur for a longer period of time before the mask degrades. Therefore, excess amorphous carbon deposits in the mask opening can be removed, thereby providing an ideal entry profile for the feature to be etched. Second, with a better mask entry profile, the amorphous carbon liner can be deposited deeper into the feature and more uniformly on the sidewalls of the feature. Third, due to the better profile of the amorphous carbon liner, feature etching can be performed for a longer period of time before the amorphous carbon liner needs to be replenished. Therefore, features can be etched deeper, CD control is tighter, and the number of iterations may be fewer.

[0021] The use of an amorphous carbon liner is advantageous for a number of reasons. Amorphous carbon is highly resistant to fluorine, chlorine, and / or bromine chemistries commonly used for vertical etching of features. By having an amorphous carbon liner on the sidewalls, the effects of lateral etching are significantly reduced or eliminated. Furthermore, the deposition process can be easily controlled, which means that the amorphous carbon liner can be customized to meet specific desired specifications such as material thickness, uniformity, composition, conformality, etc. Therefore:

[0022] (a) minimizing lateral etching effects during vertical etching processes, thereby avoiding sidewall bowing and / or surface irregularities of holes on the top surface of one or more layers defining the features;

[0023] (b) reducing or eliminating streaks, kinks, unevenness, roughness, vertical surfaces, grooves, and other surface irregularities in the sidewall; and

[0024] (c) Highly dense deep features with extremely high aspect ratios and tight CD control can be achieved, which is suitable for next-generation process technologies and semiconductor devices.

[0025] In other embodiments, the deposition and etching processes are performed in a single substrate processing tool having a structure for performing both deposition and etching processes. In alternative embodiments, the deposition and etching processes can be performed in a single tool having separate deposition and etching process chambers, or in two separate deposition and etching tools. In the latter two embodiments, the substrate needs to be transferred between the different process chambers.

[0026] In yet another embodiment, features fabricated as described herein can take on a variety of shapes and sizes, including but not limited to cylinders, holes, grooves, slots, and other geometric or non-geometric shapes. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present application and its advantages may best be understood by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a flow chart illustrating processing steps for fabricating one or more features on a semiconductor substrate in accordance with a non-exclusive embodiment of the present invention.

[0029] Figure 2 Several iterations of (a) vertical etching followed by (b) amorphous carbon deposition liner are shown during fabrication of one or more features on a semiconductor substrate, according to a non-exclusive embodiment of the present invention.

[0030] Figure 3 is a flow chart showing processing steps for fabricating one or more features on a semiconductor substrate according to another non-exclusive embodiment of the present invention.

[0031] Figures 4A-4D is a series of diagrams showing the Figure 3 Flowchart for encapsulating masks to prevent degradation during the fabrication of high aspect ratio features.

[0032] Figure 5 Schematic diagram showing iterative processing of (a) vertical etching and (b) amorphous carbon liner deposition using separate etching and plasma enhanced chemical vapor deposition (PECVD) tools according to a non-exclusive embodiment of the present invention.

[0033] Figure 6 Schematic diagram showing the iterative processing of (a) etching and (b) amorphous carbon liner deposition performed in situ in a single tool according to a non-exclusive embodiment of the present invention.

[0034] Figure 7is a diagram of an exemplary PECVD tool according to a non-exclusive embodiment of the present invention, which can be used for (b) deposition of an amorphous carbon liner.

[0035] Figure 8 is a block diagram of a system controller for controlling an ALD tool according to a non-exclusive embodiment of the present invention.

[0036] In the accompanying drawings, similar reference numerals are sometimes used to denote similar structural elements. It should also be understood that the drawings in the accompanying drawings are schematic and not necessarily drawn to scale. DETAILED DESCRIPTION

[0037] The present application will now be described in detail with reference to several non-exclusive embodiments as shown in the accompanying drawings. In order to provide a thorough understanding of the present disclosure, a large number of specific details are set forth in the following description. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without some or all of these specific details. In other examples, conventional processing steps and / or structures are not described in detail in order to avoid obscuring the present disclosure.

[0038] In a first non-exclusive embodiment, the present application relates to semiconductor processing for fabricating deep features with very high aspect ratios and tight critical dimension (CD) control. In a non-exclusive embodiment, the present invention relates to a method of fabricating a semiconductor substrate comprising: (a) vertically etching a feature in one or more layers formed on the semiconductor substrate, wherein the feature has sidewalls and a depth; and (b) depositing an amorphous carbon liner on the sidewalls of the feature.

[0039] In certain non-exclusive embodiments, the present invention further relates to iteratively performing (a) and optionally (b) until the vertically etched feature reaches a desired depth. In each iteration of (a), the feature is vertically etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. In each optional iteration of (b), the amorphous carbon liner deposited on the sidewalls of the feature is replenished.

[0040] Processing flow chart

[0041] Reference Figure 1 , a flowchart 100 is shown illustrating iterations of processing steps (a) and (b) as defined above for fabricating one or more vertically etched features in one or more layers formed on a semiconductor substrate.

[0042] In an initial step 102 , a nominal or “starting” vertical etch is performed to create one or more features on a semiconductor substrate.

[0043] In step 104, the nominal vertical etch is stopped. In a non-exclusive embodiment, the depth of the nominal vertical etch is in the range of 3 to 4 microns. It should be understood that this range is merely exemplary. A deeper or shallower nominal vertical etch may be performed.

[0044] In optional step 106, a conformal etch is performed. The purpose of the conformal etch is to open and / or control the CD of one or more holes defining one or more vertical features etched into the semiconductor substrate. By opening and / or controlling the CD of the hole(s), the upper sidewall region of the feature is prevented from being blocked, which avoids so-called "capping" or "pinch-off" conditions. If a given hole is blocked or too small, it may become blocked, causing the polymer material to "cap" or "pinch-off" the top of the feature during the subsequent vertical etch. Furthermore, by opening and / or controlling the CD of the hole of the feature, the subsequent deposition of amorphous carbon tends to be more conformal. Conformal etching can be performed using a number of different chemistries, including but not limited to oxygen (O2), nitrous oxide (N2O), carbon dioxide (CO2), hydrogen (H2), and / or any other inert gas, or any mixture or combination thereof.

[0045] In step 108, an amorphous carbon liner is deposited on the sidewalls of the one or more features, generally extending from the top of the opening down to the depth of the bottom of the one or more features. In many embodiments, the thickness of the amorphous carbon liner is in the range of 5 to 500 angstroms. It should be understood that this range is exemplary only. The amorphous carbon liner can be made thinner or thicker.

[0046] In optional step 110, the deposited amorphous carbon liner is densified. By making the amorphous carbon liner more dense, its useful life before requiring replenishment is extended. Densification of the amorphous carbon liner can be achieved by densifying the amorphous carbon liner, removing hydrogen from the amorphous carbon liner, or a combination of the two. For example, by exposing the semiconductor substrate to a radio frequency (RF) plasma or hydrogen plasma with an inert plasma chemistry (e.g., argon, nitrogen, helium, etc.), the amorphous carbon liner can be densified and hydrogen removed, both of which result in densification.

[0047] In another optional step 112, an etch back is performed to remove excess amorphous carbon that may have deposited on: (i) the planar surfaces of one or more layers surrounding or near the holes defining one or more features; and (ii) the sidewalls of one or more features. By removing these excess deposits, a "pinch-off" condition, which could partially or completely block or close the width of a given feature, is avoided. If pinch-off occurs, it can prevent the chemistry of the subsequent vertical etch process from reaching the depth of the feature, thereby inhibiting the vertical etch process. Furthermore, the ability to remove any excess deposited material from the sidewalls generally results in a final feature with improved CD tightness. The etch back can be performed using a number of different chemistries, including but not limited to those containing oxygen (O2), nitrous oxide (N2O), carbon dioxide (CO2), hydrogen (H2), nitrogen (N2), or any mixture or combination thereof.

[0048] In step 114, it is determined whether the feature has been vertically etched to its desired depth. If so, the process is complete. If not, the above steps 102-112 are repeated, including the vertical etch start and stop steps 102, 104, and any of the optional steps 106-112.

[0049] For each iteration of the vertical etching step 102, several factors may be considered before stopping the vertical etching in step 104. One important factor is the state of the amorphous carbon liner. While amorphous carbon is generally highly resistant to fluorine, chlorine, and / or bromine, it is not completely unaffected by these etching chemistries. Factors such as the thickness of the amorphous carbon liner, the relationship between the lateral etch rate of the amorphous carbon liner and the rate at which the feature is vertically etched, and other criteria may be used to determine when to stop the vertical etching and replenish the amorphous carbon liner. For very deep features (e.g., depths of 4 microns or greater), multiple iterations of (a) vertical etching and (b) deposition may be required.

[0050] It should be noted that step 108 is listed as "optional." Generally speaking, an amorphous carbon liner is almost always deposited after the nominal first vertical etch process. In this way, the sidewalls of one or more features experience minimal lateral etching during the subsequent vertical etch step (a). At some point, after one or more iterative vertical etches (a), the feature reaches its desired vertical depth. When this occurs, supplementing the amorphous carbon liner may be unnecessary or undesirable. In this case, deposition step 108 can be optionally skipped.

[0051] Semiconductor substrate with vertically etched features

[0052] Reference Figure 2, shows several iterations of (a) a vertical etching process of step 102 followed by (b) an amorphous carbon deposition process of step 108 during the fabrication of one or more features 14 on an exemplary semiconductor substrate 10. The fabrication of features 14 on a semiconductor device generally follows the above-described process for Figure 1 In this particular example, three (3) iterations of (a) the vertical etching process of step 102 and (b) the amorphous carbon deposition process of step 108 are performed to bring the feature 14 to its desired depth.

[0053] Semiconductor substrate 10 includes one or more layers 12. For simplicity, only one layer 12 is shown. It should be understood that layer 12 may include multiple stacked layers. The single layer or layers 12 of semiconductor substrate 10 can vary widely. Such layers may include, but are not limited to, silicon nitride, silicon oxide, polysilicon, oxide, doped oxide (such as boron-doped oxide), various spin-on glass materials (such as PSG and BPSG), an ashable hard mask (AHM), materials such as carbon or carbon doped with various materials (such as boron), or any other type of material or layer formed on a semiconductor substrate, including materials currently known or used and materials discovered or used in the future. Therefore, it should be understood that this list of materials is not exhaustive.

[0054] In the particular embodiment shown, layer 12 serves as a mask for defining features 14 to be fabricated into the depth or bulk of semiconductor substrate 10. Typically, layer 12 is uniformly deposited onto the underlying surface of substrate 10. As is known in the art, layer 12 is then patterned to expose certain portions of substrate 10. Thus, patterned layer 12 serves to define features 14 to be fabricated on substrate 10.

[0055] In a nominal or "starting" vertical etch, as shown, two features 14 are defined. Each feature 14 after the nominal etch is defined by a depth 16 and sidewalls 18. For clarity, vertical etching is intended to be broadly interpreted to include any etching into the depth of the exposed area of substrate 10, as defined by the pattern mask defined by layer 12. It should also be understood that for simplicity, only two features 14 are shown. In actual embodiments, a significantly greater number of features 14 can be fabricated on substrate 10.

[0056] In a subsequent first deposition process, an amorphous carbon liner 20 is formed on the sidewalls 18 of the feature 14. The amorphous carbon liner 20 generally extends down to or near the bottom of the depth 16 of the feature 14.

[0057] Next, a second vertical etching process is performed on substrate 10 to extend depth 16 of feature 14. As a result of the second vertical etching process, amorphous carbon liner 20 no longer reaches the bottom of depth 16 of feature 14.

[0058] In the second deposition process, the amorphous carbon liner 20 is replenished and extends down to at or near the bottom of the depth 16 of the feature 14 defined by the second vertical etch process.

[0059] In the third iteration, feature 14 is again etched vertically. In this particular example, the depth 16 after the third vertical etching process reaches the desired or target depth. Therefore, no more vertical etching iterations are required in this example.

[0060] In an optional third deposition process, the amorphous carbon liner 20 is again replenished. It should be noted that this step is optional and may not be performed as described above.

[0061] Although not in Figure 2 , but any of the optional steps may be performed, including the conformal etch process 106, the densification step 110, and / or the etch-back process 112. In certain embodiments, these steps may be performed in each iteration of (a) the vertical etch of step 102 and (b) the deposition of the amorphous carbon liner of step 108. In other embodiments, these steps may be performed in some but not all iterations of (a) and / or (b).

[0062] It should be noted that for the second and third iterations, the amorphous carbon liner 20 is shown to be thicker after the supplemental operation (b) than immediately after each vertical etching process (a). It should be understood that the figures are illustrative only and not drawn to scale. Since the thickness of the amorphous carbon liner 20 is typically in the range of several angstroms, a drawing to scale is not feasible.

[0063] Only three iterations of (a) vertical etching and (b) deposition are described and shown. It should be understood that any number of iterations may be used. In some cases, fewer iterations may be required to reach the desired depth 16 of the feature 14, while in other cases, more iterations may be required.

[0064] The number of iterations of (a) and (b) required for a given feature 14 depends on various factors. These factors may include, but are not limited to, the desired depth of the feature, the thickness of the deposited amorphous carbon liner 20, the critical dimension (CD) tolerance of the feature 14, the desired aspect ratio of the feature 14, the timing of when the amorphous carbon liner 20 needs to be replenished, and / or any combination thereof. It should be understood that this list of factors is not exhaustive, and other factors may also be considered.

[0065] It should also be understood that features 14 may take on a variety of shapes. Such shapes may include, but are not limited to, cylinders, holes, trenches, slits, geometric shapes, non-geometric shapes, or any other shape that may be fabricated on a semiconductor substrate such as semiconductor substrate 10.

[0066] It should also be noted that in some embodiments, the amorphous carbon liner 20 deposited on the sidewalls 18 of the vertical etched features 14 can be removed during subsequent processing steps of the semiconductor substrate 10. For example, the amorphous carbon liner 20 can be removed during an "ashing" step, which is typically an isotropic etching step.

[0067] Simultaneous etching

[0068] As amorphous carbon liner 20 forms, the amorphous carbon material tends to deposit thicker in the region defined by mask layer 12 and the upper region of feature 14 (i.e., the "neck" of feature 14), while depositing thinner or not at all at lower depths of feature 14. As excess amorphous carbon liner material accumulates in the neck, it partially or completely closes the opening. This condition, known as "pinch-off" or "capping," prevents amorphous carbon material from depositing onto sidewalls 18 at lower depths of feature 14. As a result, the thickness of amorphous carbon liner 20 is non-uniform and may be very thin or non-existent near the bottom of feature 14.

[0069] In co-pending, commonly assigned application U.S. Provisional Application No. 62 / 856,595, filed on June 3, 2019, and entitled “Carbon Based Liner for Critical Dimension Control During High Aspect Ratio Feature Etches,” performing a localized etch at the entrance or neck of feature 14 to mitigate pinch-off conditions is described. By performing the localized etch, the neck feature 14 remains open for at least a longer period of time, thereby allowing amorphous carbon material to be deposited at a lower depth within the feature 14. As a result, the uniformity and depth of deposition of the amorphous carbon liner 20 are improved. In variations of this approach, etching can occur during, just before, or just after the amorphous carbon deposition. U.S. Provisional Application No. 62 / 856,595 is incorporated herein by reference for all purposes.

[0070] While localized etching is relatively effective in delaying the pinch-off condition, it does have its limitations. Specifically, if the localized etching is performed for too long, the exposed layer 12 may be unintentionally etched, thereby degrading the mask. As layer 12 is etched, the shape of the mask may be adversely altered, and any underlying layers in the stack may be damaged and / or degraded.

[0071] Mask encapsulation to prevent degradation

[0072] refer to Figure 3 , flow chart 200 shows the steps for packaging layer 12 defining a mask for defining features 14 .

[0073] In an initial step 202, one or more layers 12 are deposited or otherwise formed on a substrate 10. The one or more layers 12 are then patterned to form a mask, exposing portions of the underlying substrate 10 where features 14 are to be fabricated.

[0074] In step 204, a nominal etch is performed to create one or more features 14 (see, for example, Figure 2 (see the graph labeled “Nominal Etch” in the ).

[0075] In step 206, the one or more layers 12 defining the mask are encapsulated in an etch-resistant material. Encapsulation is typically performed using one of several well-known substrate processing techniques. For example, depending on the material, an encapsulation layer can be grown or deposited on the one or more layers 12.

[0076] In step 208 , an amorphous carbon liner 20 is deposited onto the nominally etched sidewalls 18 defining the features 14 .

[0077] In step 210, an etch back of the amorphous carbon liner 20 is performed. Again, the purpose of this etch back step is to prevent pinch-off conditions at the opening or neck of the feature 14. By clearing the neck and preventing pinch-off, at least two beneficial effects are achieved. First, the amorphous carbon liner 20 is able to be deposited more uniformly on the sidewalls 18 and penetrate deeper into the depth of the feature 14. Second, with a deeper and more uniform liner 20, subsequent feature etching (described below) can continue longer before requiring replenishment of the liner 20. As a result, the feature 14 can be etched to a greater depth.

[0078] The specific encapsulation material used in step 206 depends largely on the liner material deposited on the sidewalls 18 of the feature 14. For example, when the amorphous carbon liner 20 is deposited in step 208, suitable etching chemicals used in step 210 may include oxygen (O2), nitrous oxide (N2O), carbon dioxide (CO2), hydrogen (H2), or a combination thereof. Using these chemicals, etch-resistant materials suitable for encapsulating and protecting the mask layer 12 may include, but are not limited to, silicon oxide (SiO2), silicon nitride (SiN) and / or amorphous silicon, any of which may be formed using well-known techniques. For example, it is well known to deposit oxides such as (SiO2) and nitrides such as (SiN). Alternatively, oxides such as (SiO2) may be grown, provided that the underlying layer is a suitable material, such as amorphous silicon. The thickness of the etch-resistant material used for encapsulation can vary greatly. In various embodiments, the thickness can range from 0.5 nm to 50 nm.

[0079] It should be understood that the examples provided herein are merely illustrative and should not be construed as limiting. Rather, a variety of different materials may be used to form the liner 20 on the sidewalls 18 of the feature 14. Depending on the liner material used, different etching chemistries may be selected, which in turn means that different etch-resistant encapsulation materials may also be used.

[0080] It should be further noted that steps 208 and 210 do not necessarily have to be performed in the order shown (ie, meaning, one after the other). Rather, the etch-back step 210 may be performed before, simultaneously with, or after the amorphous carbon liner 20 is deposited in step 208 .

[0081] In decision 212, a determination is made as to whether the amorphous carbon liner 20 has a desired profile, which is generally characterized by: (i) a desired thickness on the sidewalls 18, (ii) a desired depth within the feature 14, or a combination of (i) and (ii). In certain non-exclusive embodiments, the determination of the desired profile is confirmed from empirical data. By performing amorphous carbon liner 20 deposition multiple times using multiple substrates, historical data can be used to determine when the desired profile is achieved. If it is determined that the desired profile has not been achieved, deposition continues as provided in step 208.

[0082] In step 214, a determination is made as to whether the etch-resistant material needs to be replenished. Again, this determination is typically made using empirical data. By reviewing historical data from processing multiple substrates 10, the need for replenishment can typically be determined based on a combination of the type of etchant chemistry used and / or the cumulative amount of time the etch-resistant material has been exposed to the etchant chemistry during one or more iterations of the etch-back step 210. If replenishment of the etch-resistant material is determined to be necessary, control can be returned to step 206.

[0083] Likewise, it should be understood that the order of decisions 212 and 214 may be changed. The two decisions may be made substantially simultaneously, or alternatively, one may occur before the other, with 212 occurring first and 214 occurring second, or vice versa.

[0084] In step 216, when the amorphous carbon liner 20 has the desired profile and no additional etch-resistant material is required, feature etching is performed. As feature etching proceeds, the features 14 are etched to a deeper depth. Similarly, with a deeper and more uniform liner 20, feature etching can continue for a longer period of time than would otherwise be possible before the liner 20 requires replenishment. As a result, features 14 can be etched to a deeper depth and fewer iterations of the above-described process may be required.

[0085] In step 218, a determination is made as to whether the feature has been etched to the desired depth. This determination is also typically made using empirical data. If the feature 14 has reached its desired depth, the process is complete. If not, control returns to decision 212 and / or 214. Depending on the results of these two decisions, iterations of amorphous carbon liner deposition in step 208, liner back etching in step 210, and / or replenishment of etch-resistant material in step 206 may be performed before performing another iteration of feature etching in step 218. In this way, the carbon liner 20 is replenished to meet the desired profile before another feature etching in step 216, the neck of the feature 14 remains open and free of excess material, while etch-resistant material is replenished as appropriate to protect the mask layer 12 from degradation.

[0086] By following the steps and decisions defined in flowchart 200, features 14 can be etched to their desired depths. In cases where the desired depth is relatively deep (e.g., 4 microns or greater), multiple iterations of feature etching step 216 may be necessary. Similarly, the deposition of amorphous carbon liner 20 and / or the liner etch back of step 210 may also be repeated multiple times, depending on the results of decisions 212 and 214. For example, if liner 20 degrades during feature etching 216, etching may be stopped and steps 208 and 210 may be performed. Similarly, if it is determined during etch back step 210 that additional etch-resistant material is needed, the etch back is stopped and the mask is resealed in step 206.

[0087] It should also be noted that many of the steps outlined in flowchart 200 do not necessarily have to be performed sequentially (i.e., one after another). Instead, many of these steps can be performed in parallel. For example, steps 208 and 210 can be performed simultaneously or with partial overlap.

[0088] refer to Figures 4A-4C , showing the Figure 3 Flowchart 200 is a series of diagrams illustrating encapsulation of a mask to prevent degradation during fabrication of high aspect ratio features 14 .

[0089] exist Figure 4A In the figure, feature 14 is nominally etched to a nominal depth of 16, as shown. The location of feature 14 is determined by each Figure 3 At step 204 , one or more mask openings are defined in the mask layer 12 .

[0090] exist Figure 4B In the process, an anti-etching material 30 is deposited and / or grown so as to package the Figure 3 Step 206 defines the masking of layer 12. As shown, etch-resistant material 30 is packaged not only around the top surface of the opening defining feature 14, but also along the sidewalls of layer 12 defining the neck of feature 14.

[0091] In step 4C, amorphous carbon liner 20 is deposited on the top surface of layer 14 along the sidewalls of layer 12. During deposition, amorphous carbon material may intrude into the openings and / or necks of features 14, capping or pinching off access to the depth of features 14.

[0092] exist Figure 4D In the process, the amorphous carbon material on the neck or opening and sidewall of the intrusion layer 12 is formed by Figure 3 The etch back step 210 is substantially removed. As shown, the excess amorphous carbon material at the neck of the feature 14 is removed, thereby providing a clear entry profile for the deposition of amorphous carbon and the chemistry used to perform the feature etching into the depth of the feature 14 in step 216.

[0093] Encapsulating layer 12 of the mask defining features 14 with an etch-resistant material achieves a number of advantages. First, etch-back step 210 can be performed for a longer period of time than if the mask were not encapsulated. Second, with the neck of feature 14 substantially open, the entry profile enables amorphous carbon to be deposited deeper into and more uniformly on sidewalls 18 of feature 14. Third, because the amorphous carbon liner requires less replenishment, the feature etch in step 216 can also be performed for a longer period of time, resulting in a deeper etch of feature 14.

[0094] Substrate handling tools

[0095] The above-described process involves multiple deposition and etching steps. In various implementations, these deposition and etching steps can be steps that can be performed in a combination of process chambers or in a single process chamber.

[0096] Figure 5 5 is a diagram 50 illustrating an etch chamber 52 and a PECVD chamber 54 for performing various processing steps as described herein. In one non-exclusive embodiment, the etch steps 204, 216 are performed in the etch chamber 52, while the deposition steps 206, 208 are performed in the PECVD chamber 54. The circular arrows 56, 58 are intended to illustrate the iterative nature of the above-described process, wherein the substrate 10 is transferred between the two chambers as needed, depending on the processing step to be performed.

[0097] In a variation of this embodiment, the two chambers 52 and 54 can be provided on the same tool or on separate tools. In either case, the substrate 10 being processed is transferred between the two chambers 52 and 54.

[0098] In various other embodiments, commercially available tools such as the Kiyo or Flex etch tools and / or Vector deposition tools commercially offered by the assignee of the present application may be used.

[0099] In yet another variation of this embodiment, the etch-back step 210 can be performed in either chamber 52 or 54. In the former case, the substrate 10 is transferred between the two chambers 52, 54 to perform the amorphous carbon liner 20 deposition step 208 and the etch-back step 210. In the latter case, both steps 208, 210 can be performed simultaneously or one after the other in the same PECVD chamber 54 (i.e., first step 208, then step 210, or vice versa).

[0100] refer to Figure 6 , shows a PECVD tool 60 having the capability to perform etching and deposition operations in situ in the same chamber 62. For this embodiment, the nominal etching step 204, the encapsulation step 206, the amorphous carbon deposition step 208, the etch back step 210, and the feature etching step 216 are all or substantially all performed in the same chamber 62, thereby eliminating or reducing the need to transfer the substrate 10 between multiple chambers. Again, the iterative nature of many of the above steps is represented by arrows 64, 66 in the figure.

[0101] Exemplary PECVD Tools

[0102] Figure 7 is a schematic diagram of an exemplary PECVD tool 70 , which may be used for any or all of the deposition steps 206 , 208 and / or the etching steps 204 , 210 , and 216 .

[0103] The CVD tool 70 includes a process chamber 72 , a showerhead 74 , a substrate holder 76 for holding and positioning the substrate 10 to be processed, a radio frequency (RF) generator 80 , and a system controller 82 .

[0104] During operation, a reactant gas is supplied to the processing chamber 72 via a showerhead 74. Within the showerhead 74, the gas is distributed via one or more plenums (not shown) to a general area above the surface of the semiconductor substrate 10 to be processed in the chamber 72. An RF potential generated by an RF generator 80 is applied to an electrode (not shown) on the showerhead 74. (The RF potential can also be applied via an electrode (also not shown) disposed on the substrate holder 76.) This RF potential generates a plasma 84 within the processing chamber 72. In the plasma 84, excited electrons ionize or dissociate (i.e., "split") from the reactant gas, generating chemically reactive free radicals. As these free radicals react, they deposit on the semiconductor substrate 10 and form a thin film, including the amorphous carbon liner 20 described herein.

[0105] The plasma 84 within the chamber 72 may be achieved capacitively or inductively.

[0106] In various embodiments, the RF generator 80 can be a single RF generator or multiple RF generators capable of generating high, medium, and / or low RF frequencies. For example, in the case of high frequencies, the RF generator 80 can generate frequencies in the range of 2-100 MHz, preferably 13.56 MHz or 27 MHz. When generating low frequencies, the range is 50 KHz to 2 MHz, preferably 350 to 600 KHz.

[0107] System Controller

[0108] refer to Figure 8 , a block diagram of a system controller 82 according to a non-exclusive embodiment of the present invention. The system controller 82 is generally used to control the overall operation of the PEALD tool 70 and manage processing conditions during deposition, post-deposition and / or other processing operations.

[0109] The system controller 82 can have a variety of physical forms, ranging from an integrated circuit, a printed circuit board, a small handheld device, a personal computer, a server, or a supercomputer, any of which can have one or more processors. The system controller 82 can also include an electronic display device 404 (for displaying graphics, text, and other data), a non-volatile main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard drive), a removable storage device 410 (e.g., an optical drive), a user interface device 412 (e.g., a keyboard, touch screen, keypad, mouse, or other pointing device), and a communication interface 414 (e.g., a wireless network interface). The communication interface 414 enables software and data to be transferred between the system controller 82 and external devices via a link. The system controller 82 can also include a communication infrastructure 416 (e.g., a communication bus, a cross-over bar, or a network) to which the aforementioned devices / modules are connected.

[0110] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices (e.g., hard disks, flash memory, hard drive memory, CD-ROMs, and other forms of permanent memory), and should not be interpreted as covering transitory subject matter such as carrier waves or signals.

[0111] In certain embodiments, a system controller 82 running or executing system software or code controls all or at least most of the activities of the tool 70 to implement some or all of the processes described herein, including but not limited to, implementing Figure 1 and 3activities such as some or all of the steps described in; controlling the timing and decision making of the process for such operations, the frequency and power of the operation of the RF generator 80, the pressure within the process chamber 72, the flow rate, concentration and temperature of the reactants within the process chamber 72, the timing of purging the process chamber, etc.

[0112] The information transmitted via the communication interface 414 can be in the form of a signal that can be received by the communication interface 414 through a communication link, such as an electronic, electromagnetic, optical, or other signal, which carries the signal and can be a communication link implemented using wire or cable, optical fiber, telephone line, cellular phone link, radio frequency link, and / or other communication channels. Using such a communication interface, it is contemplated that one or more processors 402 can receive information from a network or can output information to a network. In addition, method embodiments can be executed solely on a processor or can be executed in conjunction with a remote processor over a network such as the Internet, which shares a portion of the processing.

[0113] Deposition of amorphous carbon liner

[0114] Various process flows can be used in dedicated PECVD chambers and / or dual-purpose etch and PECVD chambers to deposit the amorphous carbon liner 20. Such process flows involve defining the temperature range, pressure range, plasma source, controlling the flow rates of gases flowing into the chamber, and the actual precursors and other chemicals used in the chamber.

[0115] Examples and / or ranges for each of the above-listed parameters are provided in Table 1 provided below. Using these examples and / or ranges, a PECVD process can be used to deposit an amorphous carbon liner 20 on the sidewalls 18 of the feature 14 .

[0116] Table I

[0117]

[0118] None of the information provided in Table II above should be construed as limiting. Rather, it should be understood that the various ranges, examples, and factors used to define the process for a given deposition process are merely illustrative. Other ranges, examples, and factors may be used for the deposition of the amorphous carbon liner 20 as needed to meet specific design goals and process parameters.

[0119] Amorphous carbon

[0120] The amorphous carbon deposited to form liner 20 on sidewall 18 of feature 14 is preferably free reactive carbon with little or no crystalline structure. The amorphous carbon material can be stabilized by capping dangling T-T bonds with hydrogen. Amorphous carbon is often abbreviated as "aC" for general amorphous carbon, "HAC" for hydrogenated amorphous carbon, or "ta-C" for tetrahedral amorphous carbon, sometimes referred to as diamond-like carbon. In the context of the present invention, any of these types of amorphous carbon can be used to define liner 20 on sidewall 18 of feature 14.

[0121] The properties of the amorphous carbon liner 20 used herein vary depending on the parameters used during deposition. The primary method of characterizing amorphous carbon is by the presence of sp 2 With sp 3 The ratio of hybrid bonds. Graphite is composed purely of sp 2 hybrid bonds, while diamond is purely composed of sp 3 Hybrid bond composition. 3 The tetrahedral shape formed by the hybrid bond, so sp 3 Materials with a high hybrid bond ratio are referred to as tetrahedral amorphous carbon, or diamond-like carbon (due to many physical properties similar to diamond). Furthermore, the amount or level of hydrogen in the amorphous carbon liner 20 can be easily measured using spectroscopic methods, such as Rutherford backscattering spectroscopy (RBS). The ability to detect hydrogen content is particularly beneficial when performing the steps described above to densify the amorphous carbon liner 20.

[0122] Etch back step

[0123] In Table II provided below, exemplary values and / or ranges are provided for several parameters that may be implemented in a process chamber performing the pad mask etch back step 210. By using these values and / or ranges, an etch back process may be used to remove excess amorphous carbon material at the tops, openings, or necks of features 14 defined by the mask (i.e., layer 12).

[0124] Table II

[0125]

[0126] The process parameters defined above result in the use of a chemical that is capable of "gently" etching amorphous carbon in a highly controlled manner. By generating a relatively low-power plasma, oxygen and / or other free radicals (e.g., carbon or nitrogen) form volatile etchants that react with the amorphous carbon of the liner 20 at the top or opening of the feature 14. At high RF, the energy of the ions bombarding the surface of the layer 12 defining the mask is relatively low, resulting in a relatively slow etch rate. Therefore, the etching process is primarily a chemical etching process. Most of the free radicals react immediately upon contacting the pinch-off material, thereby producing etching byproducts that are pumped out of the process chamber. Because the free radicals have low energy and tend to react immediately with the pinch-off material or with the amorphous carbon liner 20 material immediately below the opening defined by the mask (e.g., a depth of 400 nanometers or less), relatively few free radicals have the opportunity to diffuse downward into the depth of the feature 14. Thus, the majority of liner 20 remains intact and is largely unaffected by the etch near layer 12, which primarily removes pinch-off material and opens the neck of feature 14, but generally does not penetrate the depth of feature 14 itself. Thus, liner 20 on the sidewalls of feature 14 remains substantially intact and is substantially unaffected by etch-back 210.

[0127] Characteristic properties / dimensions

[0128] By using the processing described herein, semiconductor substrates having features 14 with extremely high aspect ratios and very tight CD control can be achieved. For example, features 14 having depths greater than four (4) microns, aspect ratios greater than or equal to (50:1), and tight CDs in the range of 80-100 or less than 150 nanometers can be achieved. It should be understood that these characteristics are merely exemplary. Features 14 can be fabricated with deeper or shallower vertical depths, with larger or smaller aspect ratios, and / or with tighter or less tight CD measurements. However, in general, as semiconductor manufacturing technology improves and the demand for more dense semiconductor devices continues, features 14 with deeper depths, higher aspect ratios, and even tighter CD measurements may be achieved using the objectives described herein.

[0129] Although only a few embodiments have been described in detail, it should be understood that the present invention can be embodied in many other forms without departing from the spirit and scope of the disclosure provided herein. Therefore, the embodiments herein are to be considered as illustrative and not restrictive, and are not to be limited to the details provided herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. A method for fabricating features into a semiconductor substrate, the method comprising: (a) encapsulating openings and sidewalls of a mask defining features nominally etched into a semiconductor substrate with an etch-resistant material; (b) depositing an amorphous carbon liner on the sidewalls of the mask and the sidewalls of the etched features; (c) performing an amorphous carbon liner etch to remove excess amorphous carbon that may have been deposited around the opening or the sidewalls of the mask during deposition of the amorphous carbon liner, wherein the etch-resistant material prevents or mitigates etching around the opening and the sidewalls of the mask during etching of the amorphous carbon liner; as well as (d) performing feature etching to deepen the depth of the feature within the semiconductor substrate; The anti-etching material has etching resistance to chemicals used for etching amorphous carbon. 2 . The method of claim 1 , further comprising repeating (d) one or more times until the feature has been etched to a desired depth in the semiconductor substrate.

3. The method of claim 1, further comprising repeating (b) and (d) each one or more times until the feature has been etched to a desired depth in the semiconductor substrate. 4 . The method of claim 1 , further comprising periodically repeating (a) to replenish the etch-resistant material around the opening and the sidewalls of the mask.

5. The method of claim 1, wherein the amorphous carbon liner resists lateral etching of the feature during the feature etching.

6. The method according to claim 1, wherein The amorphous carbon liner enables tighter critical dimension (CD) control of the feature during the feature etch compared to performing the feature etch without the amorphous carbon liner.

7. The method of claim 1 , wherein encapsulating with the etch-resistant material enables one or more of the following: (i) the amorphous carbon liner etch occurs for a longer period of time before the mask degrades relative to a situation where the mask is not encapsulated; (ii) the amorphous carbon liner will be deposited deeper into the feature and more uniformly on the sidewalls of the feature because excess amorphous carbon deposits are removed around the opening and sidewalls of the mask during the amorphous carbon liner etch; or (iii) The feature etch is performed deeper because the amorphous carbon liner requires less replenishment because it extends deeper and more uniformly on the sidewalls of the feature.

8. The method according to claim 1, wherein The mask is one of the following: (i) Ashable hard mask (AHM); (ii) a carbon mask; or (iii) Doping materials.

9. The method according to claim 1, wherein The anti-etching material is one of: (i) silicon nitride; (ii) silicon oxide; or (iii) A combination of (i) and (ii).

10. The method of claim 1, before step (a), further comprising: providing a mask material on the semiconductor substrate; patterning the mask to define features; as well as A nominal etch is performed using the mask, the nominal etch defining the features in the substrate prior to packaging the mask.

11. A substrate processing tool comprising: processing room; a substrate holder for holding a substrate for processing in the processing chamber; as well as a controller configured to execute instructions to control processing steps within the processing chamber to process the substrate, the controller being configured to: (a) encapsulating openings and sidewalls of a mask defining features nominally etched into a semiconductor substrate with an etch-resistant material; (b) depositing an amorphous carbon liner on the sidewalls of the mask and the sidewalls of the etched features; (c) performing an amorphous carbon liner etch to remove excess amorphous carbon that may have been deposited around the opening or the sidewalls of the mask during deposition of the amorphous carbon liner; The anti-etching material has etching resistance to chemicals used for etching amorphous carbon.

12. The substrate processing tool of claim 11, wherein: The controller is further configured to repeat (b) and (c) one or more iterations to replenish the amorphous carbon liner.

13. The substrate processing tool of claim 11, wherein the controller is further configured to repeat (a) to replenish the etch-resistant material around the opening and the sidewalls of the mask.

14. The substrate processing tool of claim 11, wherein the controller is further configured to repeat (b) and (c) in one or more cycles to achieve a desired profile of the opening and the sidewalls of the mask.

15. The substrate processing tool of claim 11, wherein: The controller is further configured to perform one or more cycles of (b) and (c) to achieve a desired profile of the amorphous carbon liner.

16. The substrate processing tool of claim 15, wherein: The desired profile is characterized by: (i) desired uniformity of thickness of the amorphous carbon liner, (ii) a desired depth of the amorphous carbon liner within the feature; or (iii) Both (i) and (ii).

17. The substrate processing tool of claim 11, wherein the etch-resistant material is one of: (i) silicon nitride; (ii) silicon oxide; or (iii) A combination of (i) and (ii).

18. The substrate processing tool of claim 11, wherein: The controller is further configured to perform a nominal etch of the feature and one or more feature etch cycles to deepen the feature to a desired depth.

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