Module board, memory module and memory system

Abstract

A module board, a memory module, and a memory system are provided. The module board includes a first branch line for connecting a clock signal terminal provided on at least one surface to a first branch point, a first signal line for connecting the first branch point to a first module clock signal terminal, a second signal line for connecting the first module clock signal terminal to a kth module clock signal terminal with a first termination resistance terminal, a third signal line for connecting the first branch point to a k+1th module clock signal terminal, and a fourth signal line for connecting the k+1th module clock signal terminal to a 2kth module clock signal terminal with a second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0152459, filed on November 16, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of this disclosure relate to module boards, storage modules, and storage systems. Background Technology

[0004] A storage module may include multiple semiconductor storage devices mounted on a module board. Depending on whether the storage module also includes a buffer on the module board, it can be categorized into server-oriented storage modules and PC-oriented (client-oriented) storage modules.

[0005] Server-oriented storage modules include buffers so that signals of various levels applied from external devices (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.) can be converted (e.g., amplified) and the converted signals can be transmitted to multiple storage devices. Therefore, in server-oriented storage modules, even with heavy loads on multiple semiconductor storage devices, the quality of clock signals and / or command / address signals is not affected.

[0006] On the other hand, PC-oriented storage modules do not include buffers on the module board, so signals applied from external devices can be transmitted to multiple semiconductor memory devices without signal level conversion. Therefore, in PC-oriented storage modules, the quality of clock signals and / or command / address signals may degrade when the number of semiconductor memory devices is large. Summary of the Invention

[0007] Summary of the Invention One or more embodiments of the present disclosure provide a module board in which the quality of clock signals and / or command / address is not affected even when the load of multiple semiconductor memory devices is large, and a memory module including the module board.

[0008] The technical problems solved by one or more embodiments are not limited to those described above. Other technical problems not described herein will become clear to those skilled in the art through the following description.

[0009] According to an embodiment, a module board is provided, comprising: a plurality of stacked layers, the plurality of layers including a first layer to an nth layer; a first module clock signal terminal to a kth module clock signal terminal, the first module clock signal terminal to the kth module clock signal terminal being arranged at a first predetermined interval in an assembly region of at least one of the upper surface of the first layer and the lower surface of the nth layer; a (k+1)th module clock signal terminal to a 2kth module clock signal terminal, the (k+1)th module clock signal terminal to the 2kth module clock signal terminal being arranged at a second predetermined interval in the assembly region; a first terminated resistor terminal, the first terminated resistor terminal being configured to be adjacent to the kth module clock signal terminal; a second terminated resistor terminal, the second terminated resistor terminal being configured to be adjacent to the 2kth module clock signal terminal; and a plurality of terminals, the plurality of terminals being arranged on the at least one surface. The terminal area includes a clock signal terminal; a first branch line for connecting the clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to the first module clock signal terminal; a second signal line for sequentially connecting the first module clock signal terminal to the kth module clock signal terminal to the first terminating resistor terminal; a third signal line for connecting the first branch point to the (k+1)th module clock signal terminal; and a fourth signal line for sequentially connecting the (k+1)th module clock signal terminal to the 2kth module clock signal terminal to the second terminating resistor terminal, wherein the length of the third signal line is greater than the sum of the lengths of the first signal line and the second signal line.

[0010] According to an embodiment, a storage module including a module board is provided. The module board includes: a plurality of stacked layers, the plurality of layers including a first layer to an nth layer; a first module clock signal terminal to a kth module clock signal terminal, the first module clock signal terminal to the kth module clock signal terminal being arranged at a first predetermined interval in a component region on at least one surface of the upper surface of the first layer and the lower surface of the nth layer; a k+1th module clock signal terminal to a 2kth module clock signal terminal, the k+1th module clock signal terminal to the 2kth module clock signal terminal being arranged at a second predetermined interval in the component region; and a first termination resistor terminal, the first termination resistor terminal being configured to connect with the... The clock signal terminal of module k is adjacent to the clock signal terminal of module k; a first terminating resistor is connected to the first terminating resistor terminal; a second terminating resistor terminal is configured to be adjacent to the clock signal terminal of module 2k; a second terminating resistor is connected to the second terminating resistor terminal; a plurality of terminals are arranged in the terminal region of at least one surface, including a clock signal terminal; a first branch line is used to connect the clock signal terminal disposed on at least one surface to a first branch point; a first signal line is used to connect the first branch point to the clock signal terminal of the first module; a second signal line is used to sequentially connect the clock signal terminal of the first module to the clock signal terminal of module k to the first terminating resistor terminal; a third signal line is used to connect the first branch point to the clock signal terminal of module k+1; a fourth signal line is used to sequentially connect the clock signal terminal of module k+1 to the clock signal terminal of module 2k to the second terminating resistor terminal; a first semiconductor memory device to the kth semiconductor memory device, the first semiconductor memory device to the kth semiconductor memory device... The conductor memory devices each include a first memory clock signal terminal to a kth memory clock signal terminal installed at the first module clock signal terminal to the kth module clock signal terminal; and a (k+1)th semiconductor memory device to a 2kth semiconductor memory device, each of the (k+1)th to the 2kth semiconductor memory devices including a (k+1)th memory clock signal terminal to a 2kth memory clock signal terminal installed at the (k+1)th module clock signal terminal to the 2kth module clock signal terminal, wherein the length of the third signal line is greater than the sum of the length of the first signal line and the length of the second signal line.

[0011] According to an embodiment, a storage system including a control device is provided. The control device includes: a processor configured to generate internal commands, internal addresses, and internal data by executing a program; a clock signal generator configured to generate a clock signal; a command / address generator configured to receive the internal commands and the internal addresses from the processor based on the clock signal from the clock signal generator, and generate a command / address; and a data output interface configured to receive the internal data and generate 2k data entries. The storage system also includes a storage module comprising a module board. The module board includes: a plurality of stacked layers, the plurality of layers including a first layer to an nth layer; a first module terminal to a kth module terminal, the first module terminal to the kth module terminal being arranged at a first predetermined interval in an assembly region on at least one surface of the upper surface of the first layer and the lower surface of the nth layer; a (k+1)th module terminal to a 2kth module terminal, the (k+1)th module terminal to the 2kth module terminal being arranged at a second predetermined interval in the assembly region; a first terminated resistor terminal, the first terminated resistor terminal being configured to be adjacent to the kth module terminal; a first terminated resistor, the first terminated resistor being connected to the first terminated resistor terminal; a second terminated resistor terminal, the second terminated resistor terminal being configured to be adjacent to the 2kth module terminal; a second terminated resistor, the second terminated resistor being connected to the second terminated resistor terminal; a plurality of terminals, the plurality of terminals being arranged in the terminal region of the at least one surface; a first branch line, the first branch line being used to connect at least one of the plurality of terminals to a first branch point; a first signal line, the first signal line being used to connect the... A first branch point is connected to the first module terminal; a second signal line is used to sequentially connect the first module terminal to the kth module terminal to the first terminating resistor terminal; a third signal line is used to connect the first branch point to the (k+1)th module terminal; a fourth signal line is used to sequentially connect the (k+1)th module terminal to the 2kth module terminal to the second terminating resistor terminal; a first semiconductor memory device to a kth semiconductor memory device, each of the first semiconductor memory devices to the kth semiconductor memory device includes a first memory terminal to a kth memory terminal installed at the first module terminal to the kth module terminal; and a (k+1)th semiconductor memory device to a 2kth semiconductor memory device, each of the (k+1)th semiconductor memory device to the 2kth semiconductor memory device includes a (k+1)th memory terminal to a 2kth memory terminal installed at the (k+1)th module terminal to the 2kth module terminal, wherein the length of the third signal line is greater than the sum of the lengths of the first signal line and the second signal line. Attached Figure Description

[0012] Figure 1A This is a diagram showing a module board according to an embodiment.

[0013] Figure 1B This is a cross-sectional view of the module board 100 according to an embodiment.

[0014] Figure 2 This is a schematic diagram illustrating the arrangement of clock signal lines according to an embodiment.

[0015] Figure 3 This is a diagram showing the arrangement of clock signal lines according to an embodiment.

[0016] Figure 4 This is a conceptual diagram illustrating the arrangement of command / address lines according to an embodiment.

[0017] Figure 5 This is a diagram illustrating the arrangement of command / address lines according to an embodiment.

[0018] Figure 6 This is a conceptual diagram illustrating the arrangement of command / address lines according to an embodiment.

[0019] Figure 7 This is a diagram illustrating the arrangement of command / address lines according to an embodiment.

[0020] Figure 8 This is a diagram illustrating the configuration of a storage module according to an embodiment.

[0021] Figure 9 This is a diagram illustrating a semiconductor memory device according to an embodiment.

[0022] Figure 10 This is a diagram illustrating the configuration of a semiconductor memory device according to an embodiment.

[0023] Figure 11 This is a diagram illustrating a storage system according to an embodiment.

[0024] Figure 12 This is a block diagram illustrating the configuration of a control device according to an embodiment. Detailed Implementation

[0025] In the following description, a module board and a storage module including the module board according to various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] It should be understood that when an element, component, layer, pattern, structure, region, etc., of a semiconductor device (hereinafter collectively referred to as an "element") is described as being "above," "over," "below," "under," "connected to," or "coupled to" another element of the semiconductor device, it may be directly above, above, below, under, or connected to the other element, or intermediate elements may be present. Conversely, when an element of a semiconductor device is described as being directly "above," "over," "below," "under," "directly connected to," or "directly coupled to" another element of the semiconductor device, no intermediate elements are present. Throughout this disclosure, the same reference numerals denote the same elements.

[0027] Spatial relative terms such as “above,” “over,” “on top,” “above,” “below,” “below,” “under,” and “below” are used herein for descriptive purposes to describe the relationship of one element to other (one or more) elements as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of semiconductor devices in use or operation. For example, if the semiconductor device in the figure were flipped, an element described as “below” or “under” other elements would be oriented “above” other elements. Therefore, the term “below” can include both above and below orientations. Semiconductor devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0028] As used herein, when a statement such as “at least one” precedes a list of elements, it modifies the elements of the entire list and not individual elements. For example, the statement “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the term “identical” is used to compare dimensions of two or more elements, the term can encompass dimensions of “substantially identical.”

[0029] It should be understood that although the terms first, second, third, fourth, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, the first element discussed below may be referred to as the second element.

[0030] One or more embodiments are described herein with reference to schematic cross-sectional views (and intermediate structures) as examples. Therefore, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Thus, one or more embodiments should not be construed as limited to a specific shape of the region illustrated herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an implantation region illustrated as rectangular will typically have circular or curved features and / or an implantation concentration gradient at its edges, rather than a binary variation from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the device regions, nor are they intended to limit the scope of the inventive concept. Furthermore, in the figures, the dimensions and relative dimensions of layers and regions may be enlarged for clarity.

[0031] The terms such as “unit” or “module” used in one or more embodiments of this disclosure refer to a unit for processing at least one function or operation, and can be implemented in hardware, software or a combination of hardware and software.

[0032] The terms "unit" or "module" can be implemented by a program stored in an addressable storage medium and executable by a processor.

[0033] For example, the term "unit" or "module" can include software components, object-oriented software components, class components and task components, processes, functions, properties, programs, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays and / or variables.

[0034] For the sake of brevity, conventional components of semiconductor devices may be described or omitted in detail herein. However, even if a component is described or illustrated in the semiconductor devices of this disclosure, it may not be included in the claimed semiconductor device unless it is stated to be included in the claimed semiconductor device.

[0035] Figure 1AThis is a diagram illustrating a module board according to an embodiment. The module board 100 may include a component region 10 comprising a predetermined number of storage regions 10-1 to 10-4 (containing a predetermined number (e.g., four) semiconductor memory devices) arranged from a left portion to a central portion of at least one of the upper or lower surfaces of the module board 100 (e.g., the upper surface), and a predetermined number of storage regions 10-5 to 10-8 (containing a predetermined number of semiconductor memory devices) arranged from a central portion to a right portion of at least one of the upper and lower surfaces of the module board 100. A terminal (e.g., tab) region 20 may be disposed in an edge region on one side (e.g., the lower side) of a surface of the module board 100, and a plurality of terminals TR may be arranged in a row (in the form of stripes) in the terminal region 20. A plurality of module terminals MTR1, MTR2…MRT8 may be respectively arranged in the storage regions 10-1 to 10-8 at corresponding positions in the plurality of memory terminals (e.g., solder balls) of the semiconductor memory devices. However, the number of storage areas is not limited to this, and can include any number of storage areas. Multiple module terminals MTR1, MTR2…MRT8 can be terminals to which data, commands / addresses, clock signals, control signals, power, etc., are applied. Multiple terminals TR can be terminals to which data, commands / addresses, clock signals, control signals, and power are transmitted. Module board 100 may include cutouts 12-1, 12-2, 12-3 and holes 12-4 and 12-5, which can serve as reference points for the position of module board 100.

[0036] Figure 1B This is a cross-sectional view of the module board 100 according to an embodiment.

[0037] Reference Figure 1BModule board 100 may be a printed circuit board configured by stacking multiple layers L1 to Ln, where n is an integer greater than or equal to 1. Multiple terminals TR may be arranged on the upper surface of the first layer L1 and the lower surface of the nth layer Ln of module board 100. Multiple storage areas 10⁻¹ to 10⁻⁸ may be provided on at least one of the upper surface of the first layer L1 and the lower surface of the nth layer of module board 100. Signal lines (e.g., lines for transmitting data, command / address, clock signals, and control signals) and / or power lines may be arranged on the upper and / or lower surfaces of layers L1 to Ln of module board 100. Multiple terminals TR may be connected to signals (e.g., data, command / address, clock signals, and control signals) and / or power applied from external devices (e.g., central processing unit (CPU), graphics processing unit (GPU)). Multiple terminals TR may transmit signals and / or power through corresponding vias in the first layer L1 to corresponding signal lines and / or power lines arranged on at least one of the other layers L2 to Ln. Signals and / or power applied to multiple terminals TR can be transmitted to multiple module terminals MTR1, MTR2...MTR8 through signal lines and paths arranged on at least two of the n layers L1 to Ln of the module board 100.

[0038] Figure 2 This is a schematic diagram illustrating the arrangement of clock signal lines according to an embodiment. CKT refers to the clock signal terminal among the plurality of terminals TR of the module board 100. MCKT1 to MCKT8 refer to the module clock signal terminals of the eight module terminals MTR1 to MTR8 arranged in the storage areas 10-1 to 10-8. MRTT1 and MRTT2 refer to the first terminating resistor terminal and the second terminating resistor terminal arranged in the component area 10, respectively.

[0039] Reference Figure 2 The clock signal terminal CKT can be connected to the branch point dp via the branch line dsl and can be connected from the branch point dp to the first point p1 via the first signal line sl1. The first point p1 can correspond to the point of the clock signal terminal MCKT1 of the setting module in storage area 10-1.

[0040] Point p1 can be connected to point p5 via the second signal line sl2, passing sequentially through points p2, p3, and p4. Points p2, p3, and p4 can correspond to the clock signal terminals MCKT2, MCKT3, and MCKT4 of the arrangement modules in storage areas 10-2, 10-3, and 10-4, respectively. Point p5 can correspond to the first terminating resistor terminal MRTT1 connected to the first terminating resistor. A first predetermined interval d1 can be set between point p1 and point p2, between point p2 and point p3, and between point p3 and point p4. The length of the first signal line sl1 can be less than the first predetermined interval d1. Furthermore, a second predetermined interval d2 can be set between the first point p1 and the first module clock signal terminal MCKT1, the second point p2 and the second module clock signal terminal MCKT2, the third point p3 and the third module clock signal terminal MCKT3, the fourth point p4 and the fourth module clock signal terminal MCKT4, and the fifth point p5 and the first terminating resistor terminal MRTT1. The length of the first signal line sl1 can be greater than the second predetermined interval d2. However, the predetermined interval is not limited to this; the first predetermined interval and the second predetermined interval can vary between points and / or between points and module clock signal terminals.

[0041] Branch point dp can be connected to the sixth point p6 via the third signal line sl3. The sixth point p6 can correspond to the point of the clock signal terminal MCKT5 of the setting module in storage area 10-5. The length of the third signal line sl3 can be greater than the sum of the lengths of the first signal line sl1 and the second signal line sl2. However, the length of the signal line is not limited to this, and the length of the signal line can be configured differently.

[0042] Point p6 (sixth point) can be connected to point p10 (tenth point) via the fourth signal line sl4, which passes sequentially through points p7 (seventh point), p8 (eighth point), and p9 (ninth point). The length of the fourth signal line sl4 can be equal to the length of the second signal line sl2. Points p7 (seventh point), p8 (eighth point), and p9 (ninth point) can correspond to the clock signal terminals MCKT6, MCKT7, and MCKT8 of the arrangement modules in storage areas 10-6, 10-7, and 10-8, respectively. Point p10 (tenth point) can be the point where the second terminating resistor terminal MRTT2 is set. The first predetermined interval d1 can be set between point p6 and point p7, between point p7 and point p8, and between point p8 and point p9. In addition, the second predetermined interval d2 can be set between the sixth point p6 and the fifth module clock signal terminal MCKT5, the seventh point p7 and the sixth module clock signal terminal MCKT6, the eighth point p8 and the seventh module clock signal terminal MCKT7, the ninth point p9 and the eighth module clock signal terminal MCKT8, and the tenth point p10 and the second terminating resistor terminal MRTT2.

[0043] Figure 3 This is a diagram showing the arrangement of clock signal lines according to an embodiment. Figure 3 The illustration shows one of them. Figure 2 The arrangement of the clock signal lines shown is an example implemented on the module board 100, and an example is illustrated in which the clock signal terminal CKT is located in the central part of the terminal area 20.

[0044] Reference Figure 3 The clock signal terminal CKT and path v11 on the upper surface of the first layer L1 of the module board 100 can be connected via the first sub-branch line dsl1. Path v11 can be connected to path v21 of the second layer L2, and path v21 can be connected to path v22 via the second sub-branch line dsl2. Path v22 is configured to be adjacent to the clock signal path vck21 of the second layer L2 corresponding to the module clock signal terminal MCKT1. Path v22 can be connected to path v32 of the third layer L3. The first sub-branch line dsl1 and the second sub-branch line dsl2 can correspond to... Figure 2 The branch line dsl2.

[0045] The path v32 of the third layer L3 can be connected to the clock signal path vck31 of the third layer L3 corresponding to the module clock signal terminal MCKT1 via the first signal line sl1. The clock signal paths vck31, vck32, vck33, and vck34 of the third layer L3 corresponding to the module clock signal terminals MCKT1, MCKT2, MCKT3, and MCKT4, and the path v33 of the third layer L3 corresponding to the first-terminated resistor terminal MRTT1, can be connected to each other via the second signal line sl2. The path v32 of the third layer L3 can be connected to the clock signal path vck35 of the third layer L3 corresponding to the module clock signal terminal MCKT5 via the third signal line sl3. Furthermore, the clock signal paths vck35, vck36, vck37, and vck38 of the third layer L3 corresponding to the module clock signal terminals MCKT5, MCKT6, MCKT7, and MCKT8, and the path v34 of the third layer L3 corresponding to the second-terminated resistor terminal MRTT2, can be connected to each other via the fourth signal line sl4.

[0046] The module clock signal terminals MCKT1 to MCKT4, the first terminating resistor terminal MRTT1, the module clock signal terminals MCKT5 to MCKT8, and the second terminating resistor terminal MRTT2, arranged on the first layer L1, can be connected to the clock signal paths vck21 to vck24, vck23, vck25 to vck28, and vck24 arranged on the second layer L2 via clock signal paths vck11 to vck14, path v13, clock signal paths vck15 to vck18, and path v14 arranged on the first layer L1. They can also be connected to the clock signal paths vck31 to vck34, path v33, clock signal paths vck35 to vck38, and path v34 arranged on the third layer L3. Figure 3 The diagram shows the module clock signal terminals MCKT1 to MCKT4, the first terminating resistor terminal MRTT1, the module clock signal terminals MCKT5 to MCKT8, and the second terminating resistor terminal MRTT2, as well as the clock signal paths vck11 to vck14, path v13, clock signal paths vck15 to vck18, and path v14 connected to them. Furthermore, the vertical connections between these paths are illustrated with dashed lines, each dashed line corresponding to... Figure 2 The second predetermined interval d2 is shown in the figure.

[0047] Although Figure 3 The illustration shows an example where the first signal line sl1 to the fourth signal line sl4 are arranged on a third layer L3. However, one or more embodiments are not limited to this, and the first signal line sl1 to the fourth signal line sl4 may also be arranged on a second layer L2. Furthermore, the first signal line sl1 and / or the fourth signal line sl4 may be distributed and arranged on at least two layers, rather than on a single layer. The first signal line sl1 to the fourth signal line sl4 may be arranged on at least one of the n layers L1 to Ln.

[0048] Reference above Figure 2 and Figure 3 The described clock signal line arrangement can have an asymmetric Y-topology. According to this structure, the difference between the length of the first signal line sl1 from branch point dp to the first point p1 and the length of the third signal line sl3 from branch point dp to the sixth point p6 results in significant signal attenuation at both points p1 and p6. Signal attenuation can be reduced when the first predetermined interval d1 between the first point p1 and the fourth point p4, and between the sixth point p6 and the ninth point p9, is shorter. That is, the lengths of the second signal line sl2 from the first point p1 where signal attenuation begins to the fifth point p5, and the fourth signal line sl4 from the sixth point p6 where signal attenuation begins to the tenth point p10, can be configured to be shorter.

[0049] For example, command / address lines can also be arranged with an asymmetric Y topology.

[0050] Figure 4 This is a conceptual diagram illustrating the arrangement of command / address lines according to an embodiment. Command / address terminals (CATs) may be terminals among the plurality of terminals TR of module board 100. MCAT1 to MCAT8 may refer to the module command / address terminals among the eight module terminals MTR1 to MTR8 arranged in storage areas 10-1 to 10-8.

[0051] Reference Figure 4 The command / address terminals CAT and p11 can be connected to each other via the fifth signal line SL5. The length of the fifth signal line SL5 can be... Figure 2 The length of the branch line dsl shown is the sum of the length of the first signal line sl1, to match the timing between the clock signal applied through the clock signal terminal CKT and the command / address applied through the command / address terminal CAT. Point 11 p11 can correspond to the point of setting the module command / address terminal MCAT1 in storage area 10-1. Points 11 to 19 p19 can be connected via the sixth signal line sl6. Points 12 to 18 p18 can correspond to the points of MCAT2 to MCAT8 of the module arrangement in storage areas 10-2 to 10-8, and point 19 p19 can correspond to the point of setting the third terminating resistor terminal MRTT3. The distance between point 14 p14 and point 15 p15 can be a third predetermined interval d3 greater than the first predetermined interval d1.

[0052] Figure 5 This is a diagram illustrating the arrangement of command / address lines according to an embodiment. Figure 5 The illustration shows one of them. Figure 4 The example shown illustrates the arrangement of command / address lines on module board 100, and illustrates an example in which the command / address terminal CAT is located in the central portion of terminal area 20.

[0053] Reference Figure 5 The command / address terminal CAT and path v15 on the upper surface of the first layer L1 of the module board 100 can be connected via the first sub-signal line sl51. Path v15 can be connected to path v25 of the second layer L2, and path v25 can be connected via the second sub-signal line sl52 to the command / address path vca21 of the second layer L2 corresponding to the module command / address terminal MCAT1. The first sub-signal line sl51 and the second sub-signal line sl52 can correspond to... Figure 4 The fifth signal line shown is sl5.

[0054] The module command / address terminals MCAT1 to MCAT8 and the third terminating resistor terminal MRTT3, located on the first layer L1, can be connected via command / address paths vca11 to vca18 and path v16 located on the first layer L1 to command / address paths vca21 to vca28 and path v26 located on the second layer L2. Figure 5 The diagram shows the module's command / address terminals MCAT1 to MCAT8, the third terminating resistor terminal MRTT3, and the command / address paths vca11 to vca18 and path v16 connected to them. Here, the vertical connections between these paths are represented by dashed lines, and each dashed line corresponds to... Figure 4 The second predetermined interval d2 is shown in the figure.

[0055] Reference above Figure 4 and Figure 5 The described command / address line layout can have a fly-by topology.

[0056] Although Figure 5 The illustration shows an example of the fifth signal line sl52 and the sixth signal line sl6 arranged on the second layer L2. However, the fifth signal line sl52 and the sixth signal line sl6 can also be arranged on other layers, such as layers L3 to Ln. Furthermore, the fifth signal line sl52 and / or the sixth signal line sl6 can be distributed and arranged on at least two different layers, rather than on a single layer. The fifth signal line sl52 and the sixth signal line sl6 can be arranged on at least one of the n layers L1 to Ln.

[0057] Figure 6 This is a conceptual diagram illustrating the arrangement of command / address lines according to an embodiment. CAT refers to one of the multiple terminals TR of the module board 100, while MCAT1 to MCAT8 refer to the module command / address terminals of the eight module terminals MTR1 to MTR8 arranged in storage areas 10-1 to 10-8.

[0058] Reference Figure 6 The command / address terminal CAT can be connected to branch point dp' via branch line dsl', and from branch point dp' to point eleven p11 via the seventh signal line sl7. Point eleven p11 corresponds to the point of the command / address terminal MCAT1 in the setting module in storage area 10-1. The sum of the lengths of branch line dsl' and the seventh signal line sl7 can be equal to... Figure 2The length of the branch line dsl shown is the sum of the length of the first signal line sl1, to match the timing between the clock signal applied through the clock signal terminal CKT and the command / address applied through the command / address terminal CAT. Point 11 p11 can be connected to point 20 p20 via the eighth signal line sl8, passing sequentially through point 13 p13, point 15 p15, and point 17 p17. Points 13 p13, 15 p15, and 17 p17 can correspond to the command / address terminals MCAT3, MCAT5, and MCAT7 of the arrangement modules in storage areas 10-3, 10-5, and 10-7, respectively, and point 20 p20 can correspond to the point where the fourth terminating resistor terminal MRTT4 is set. A fourth predetermined interval d4 can be set between point 11 p11 and point 13 p13, and between point 15 p15 and point 17 p17. The length of the fourth predetermined interval d4 can be twice the length of the first predetermined interval d1 (e.g., d4 = 2 × d1).

[0059] Branch point dp' can be connected to point twelfth p12 via the ninth signal line sl9. Point twelfth p12 can correspond to the point of the setting module command / address terminal MCAT2 in storage area 10-2. The length of the ninth signal line sl9 can be equal to the length of the seventh signal line sl7.

[0060] Point 12 (p12) can be connected to point 19 (p19) via the tenth signal line (sl10) passing sequentially through points 14 (p14), 16 (p16), and 18 (p18). Points 14 (p14), 16 (p16), and 18 (p18) can correspond to the command / address terminals MCAT4, MCAT6, and MCAT8 of the arrangement modules in storage areas 10-4, 10-6, and 10-8, respectively, and point 19 (p19) can correspond to the point where the third terminating resistor terminal MRTT3 is arranged. A fourth predetermined interval (e.g., d4 = 2 × d1) can be set between point 12 (p12) and point 14 (p14), and between point 16 (p16) and point 18 (p18). The length of the tenth signal line (sl10) can be equal to the length of the eighth signal line (sl8).

[0061] Figure 7 This is a diagram illustrating the arrangement of command / address lines according to an embodiment. Figure 7 The illustration shows one of them. Figure 6 The example shown illustrates the arrangement of command / address lines on module board 100, and illustrates an example where the command / address terminal CAT is located in the central part of terminal area 20.

[0062] Reference Figure 7 The command / address terminals CAT and path v15 located on the upper surface of the first layer L1 of the module board 100 can be connected via the third sub-branch line dsl3.

[0063] Path v15 can connect to path v25 in the second layer L2, and path v25 can connect to path v26 in the second layer L2 via the fourth sub-branch dsl4. The third sub-branch dsl3 and the fourth sub-branch dsl4 can correspond to... Figure 6 The branch line dsl' is shown. Path v26 can be connected to the command / address path vca21 located on the second layer L2 via the seventh signal line sl7. Command / address paths vca21, vca23, vca25, and vca27, as well as path v25, can be connected to each other via the eighth signal line sl8. Command / address paths vca21, vca23, vca25, and vca27 can be arranged at positions corresponding to the positions of the command / address terminals MCAT1, MCAT3, MCAT5, and MCAT7 of the module located on the first layer L1, and path v25 can be located at a position corresponding to the position of the fourth terminating resistor terminal MRTT4 of the module located on the first layer L1.

[0064] Path v26 can be connected to path v36 on the third layer L3, and path v36 can be connected to the command / address path vca32 on the third layer L3 via the ninth signal line sl9. Command / address paths vca32, vca34, vca36, and vca38, as well as path v37, can be connected to each other via the tenth signal line sl10. Command / address paths vca32, vca34, vca36, and vca38 can be arranged at positions corresponding to the positions of the command / address terminals MCAT2, MCAT4, MCAT6, and MCAT8 on the first layer L1, respectively. Path v37 can be arranged at a position corresponding to the position of the third terminating resistor terminal MRTT3 on the first layer L1.

[0065] The module command / address terminals MCAT1 to MCAT8 and the third terminating resistor terminal MRTT3, located on the first layer L1, can be connected via command / address paths vca11 to vca18 and paths v15 and v17 located on the first layer L1 to command / address paths vca21 to vca28 and paths v25 and v27 located on the second layer L2. Figure 7 The diagram shows the module's command / address terminals MCAT1 to MCAT8 and the third terminating resistor terminal MRTT3, as well as the command / address paths vca11 to vca18 and paths v15 and v17 connected to them. The vertical connections between these paths are illustrated as dashed lines, and each dashed line corresponds to... Figure 6 The second predetermined interval d2 is shown.

[0066] The above reference Figure 6 and Figure 7The described command / address line arrangement can have a symmetrical Y topology.

[0067] Although Figure 7 The illustration shows an example where the seventh signal line sl7 and the eighth signal line sl8 are arranged on the second layer L2, and the ninth signal line sl9 and the tenth signal line sl10 are arranged on the third layer L3. However, the seventh signal line sl7 and the eighth signal line sl8, as well as the ninth signal line sl9 and the tenth signal line sl10, can also be arranged on two different layers among the other layers L3 to Ln. In another embodiment, the seventh signal line sl7 to the tenth signal line sl10 can also be arranged on either the second layer L2 or the third layer L3. That is, the seventh signal line sl7 to the tenth signal line sl10 can also be arranged on at least one layer among the second layer L2 to the nth layer Ln. The seventh signal line sl7 to the tenth signal line sl10 can also be distributed and arranged on at least three layers.

[0068] The arrangement of the command / address lines according to the embodiments can have one of an asymmetric Y topology, a fly-through topology, and a symmetric Y topology.

[0069] According to one or more embodiments, clock signal lines and command / address lines can be arranged on the same layer, as long as they do not overlap each other. However, when clock signal lines and command / address lines need to be arranged such that they need to overlap each other, they can be arranged on different layers.

[0070] Figure 8 This is a diagram illustrating the configuration of a storage module according to an embodiment. Storage module 200 may include a module board 100, a plurality (e.g., eight) of semiconductor memory devices M1 to M8, and first terminating resistors RTT1 to third terminating resistors RTT3. Terminals of the module board 100 may include a clock signal terminal CKT, a command / address terminal CAT, and a plurality (e.g., first to eighth) of data terminals DQT1 to DQT8.

[0071] Reference Figure 8 Module board 100 can apply clock signal CK to semiconductor memory devices M1 to M8 via clock signal terminal CKT. The clock signal lines can be arranged in the aforementioned asymmetric Y topology. Module board 100 can apply command / address CA to semiconductor memory devices M1 to M8 via command / address terminal CAT. Furthermore, the command / address lines can be arranged as described above. Figure 4 and Figure 5The described fly-through topology. Module board 100 may have control signal lines for applying control signals CON to semiconductor memory devices M1 to M8 via control signal terminals, and the arrangement of the control signal lines may be the same as the arrangement of the command / address lines. Each of the plurality of semiconductor memory devices M1 to M8 may be a memory device with a large load or large capacity. Examples of devices may include double data rate (DDR) (e.g., DDR3, DDR4, or DDR5) semiconductor memory devices, dual-die package (DDP) semiconductor memory devices, or high bandwidth memory (HBM) devices. Memory module 200 may be an unbuffered dual in-line memory module (UDIMM) without a buffer, or a small outline dual in-line memory module (SODIMM).

[0072] Module board 100 can transmit first data DQ1 to eighth data DQ8 to semiconductor memory devices M1 to M8 respectively via first data terminals DQT1 to eighth data terminals DQT8, or can transmit first data DQ1 to eighth data DQ8 output from semiconductor memory devices M1 to M8 to first data terminals DQT1 to eighth data terminals DQT8 respectively. Each of the first data DQ1 to eighth data DQ8 can be a predetermined number of bits (e.g., 4 bits, 8 bits, or 16 bits) of data.

[0073] When the command / address lines are arranged in an asymmetric Y topology or a symmetric Y topology, the module board 100 may include a third terminating resistor and a fourth terminating resistor.

[0074] Figure 9 This is a diagram illustrating a semiconductor memory device according to an embodiment. The semiconductor memory device 300 may be a DDP semiconductor memory device.

[0075] Reference Figure 9 The DDP semiconductor memory device 300 may include a package substrate PSUB, a first die D1, and a second die D2. The first die D1 and the second die D2 may be stacked sequentially on the package substrate PSUB. The package substrate PSUB may include an upper pad UPAD disposed on the upper surface of the package substrate PSUB, a lower pad LPAD disposed on the lower surface of the package substrate PSUB, and signal lines for connecting the pads corresponding to the upper pad UPAD and the lower pad LPAD. The DDP semiconductor memory device 300 may include a memory terminal B (e.g., a solder ball) attached to the lower pad LPAD.

[0076] A first redistribution layer RDL1 can be disposed on the upper surface of a first die D1, and a second redistribution layer RDL2 can be disposed on the upper surface of a second die D2. The first redistribution layer RDL1 can redistribute the positions of the pads (not shown) of the first die D1. For example, the pads (not shown) of the first die D1 located in the central portion of the first die D1 can be connected via the first redistribution layer RDL1 to the pads RDL1P located at the edge portion of the upper surface of the first redistribution layer RDL1. The second redistribution layer RDL2 can redistribute the positions of the pads (not shown) of the second die D2. For example, the pads (not shown) of the second die D2 located in the central portion of the second die D2 can be connected via the second redistribution layer RDL2 to the pads RDL2P located at the edge portion of the upper surface of the second redistribution layer RDL2. Corresponding pads in the upper pad UPAD and pad RDL1P can be wire-bonded to each other via lead WB, and corresponding pads in the upper pad UPAD and pad RDL2P can be wire-bonded to each other via lead WB. Furthermore, the DDP semiconductor memory device 300 may include a sealant ENC for sealing the package substrate PSUB, the first die D1, and the second die D2.

[0077] Figure 10 This is a diagram illustrating the configuration of a semiconductor memory device according to an embodiment. Figure 10 The diagram illustrates memory terminal B and... Figure 9 The connection between the first die D1 and the second die D2 is shown.

[0078] Reference Figure 10 The memory terminal B may include a first memory control signal terminal BCON1, a second memory control signal terminal BCON2, a memory clock signal terminal BCK, a memory command / address terminal BCA, and a memory data terminal BDQ. Here, each signal has a representative terminal.

[0079] A first memory control signal terminal BCON1, including a first memory chip select signal terminal BCS1, a first memory clock enable signal terminal BCKE1, and a first memory die top-end signal terminal BODT1, can be connected to the first die D1. A second memory control signal terminal BCON2, including a second memory chip select signal terminal BCS2, a second memory clock enable signal terminal BCKE2, and a second memory die top-end signal terminal BODT2, can be connected to the second die D2. The memory clock signal terminal BCK, the memory command / address terminal BCA, and the memory data terminal BDQ can all be connected to the first die D1 and the second die D2.

[0080] Reference Figure 10The operation of the first die D1 and the second die D2 will be described below.

[0081] The first die D1 can be selected in response to the first chip select signal CS1, the first clock enable signal CKE1, and the first die termination signal ODT1 applied to each terminal of the first memory control signal terminal BCON1. ​​When the first die D1 is selected, data DQ can be input or output in response to the clock signal CK and the command / address.

[0082] The second die D2 can be selected in response to the second chip select signal CS2, the second clock enable signal CKE2, and the second die termination signal ODT2 applied to each terminal of the second memory control signal terminal BCON2. When the second die D2 is selected, data DQ can be input or output in response to the clock signal CK and the command / address.

[0083] For example, Figure 10 Each of the first die D1 and the second die D2 shown can be a DDR (e.g., DDR4) semiconductor memory device.

[0084] Although not shown, the arrangement of the control signal lines can be similar to the arrangement of the command / address lines and have one of the following structures: asymmetric Y topology, fly-through topology, and symmetric Y topology.

[0085] Figure 11 This is a diagram illustrating a storage system according to an embodiment. The storage system 1000 may include at least one storage module 200 and a control device 400.

[0086] exist Figure 11 In the above reference, storage module 200 can be... Figures 1A to 7 The module board described is 100 and above (refer to the above). Figures 8 to 10 The described storage module. Figure 11 middle, Figure 1A The data terminals in the TR are represented by DQT, the command / address terminals by CAT, the clock signal terminals by CKT, and the control signal terminals by CONT.

[0087] The control device 400 may be, for example, a central processing unit (CPU) or a graphics processing unit (GPU). The control device 400 may send a first multi-bit command / address, a control signal CA, and a clock signal CK. The control device 400 may send and receive eight second multi-bit data lines DQ1 to DQ8.

[0088] Figure 12This is a block diagram illustrating the configuration of a control device according to an embodiment. The control device 400 may include a processor 400-2, a command / address and control signal generator 400-4, a clock signal generator 400-6, and a data input and output unit 400-8.

[0089] The following will describe Figure 12 The function of each block shown.

[0090] Processor 400-2 can generate command COM, address ADD, and control signal con by executing a program according to external command ECOM, and can send and receive data DATA. For example, processor 400-2 can receive external command ECOM by communicating with various input devices such as keyboard, mouse, touch sensor, sound sensor, fingerprint sensor, or motion recognition sensor, and can generate command COM, address ADD, internal control signal CONT, and data DATA by executing a program according to external command ECOM. Processor 400-2 can receive and process data DATA, and can output data DATA to various output devices, such as display unit or sound output unit. Processor 400-2 can additionally generate clock signal control signal ckcon and transmit clock signal control signal ckcon to clock signal generator 400-6.

[0091] Command / address and control signal generator 400-4 can receive command COM and address ADD in response to the internal clock signal CK received from clock signal generator 400-6 to generate a first pre-defined command / address CA. Command / address and control signal generator 400-4 can also generate control signal CON in response to the internal control signal con.

[0092] The clock signal generator 400-6 can generate internal clock signal CK and clock signal CK in response to the clock signal control signal ckcon received from the processor 400-2.

[0093] The data input and output unit 400-8 can receive data DATA in response to the internal clock signal CK to generate eight second pre-defined data bits DQ1 to DQ8, or it can receive eight second pre-defined data bits DQ1 to DQ8 to generate data DATA. For example, the data input and output unit 400-8 can generate eight second pre-defined data bits DQ1 to DQ8 in response to the internal clock signal CK according to the DDR protocol.

[0094] According to one or more embodiments of this disclosure, the clock signal lines and / or command / address lines of the module board can be arranged in an asymmetric Y-topology, so that even if the number of multiple semiconductor memory devices mounted on the module board is large, the quality of the clock signal and command / address will not be affected. Therefore, the operational reliability of the memory module and memory system can be improved.

[0095] While one or more embodiments of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the inventive concept and without altering its essential characteristics. Therefore, the above embodiments are merely exemplary models and should be considered in a descriptive sense only, and not for limiting purposes.

Claims

1. A module board, the module board comprising: Multiple stacked layers, the multiple layers including a first layer to an nth layer; The first module clock signal terminal to the kth module clock signal terminal are arranged at a first predetermined interval in the component region of at least one of the upper surface of the first layer and the lower surface of the nth layer; The clock signal terminals of the (k+1)th module to the clock signal terminals of the 2kth module are arranged in the component area at a second predetermined interval; The first terminal is connected to a resistor terminal, and the first terminal is connected to a resistor terminal, which is set to be adjacent to the clock signal terminal of the kth module. The second terminal is connected to a resistor terminal, and the second terminal is connected to a resistor terminal, which is positioned adjacent to the clock signal terminal of the 2k module. Multiple terminals are arranged in a terminal region on at least one surface, and include a clock signal terminal; A first branch line, the first branch line being used to connect the clock signal terminal disposed on the at least one surface to a first branch point; The first signal line is used to connect the first branch point to the clock signal terminal of the first module. The second signal line is used to sequentially connect the clock signal terminals of the first module to the clock signal terminals of the kth module to the first terminating resistor terminal. The third signal line is used to connect the first branch point to the clock signal terminal of the (k+1)th module; as well as The fourth signal line is used to sequentially connect the clock signal terminals of the (k+1)th module to the clock signal terminals of the 2kth module to the second terminating resistor terminal. The length of the third signal line is greater than the sum of the lengths of the first signal line and the second signal line.

2. The module board according to claim 1, wherein, The first predetermined interval is equal to the second predetermined interval, the length of the second signal line is equal to the length of the fourth signal line, and the length of the second signal line is greater than the length of the first signal line.

3. The module board according to claim 2, wherein, The first signal line, the second signal line, the third signal line, and the fourth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

4. The module board according to claim 2, wherein, The module board also includes: The first module command / address terminal to the kth module command / address terminal are arranged in the component area at the first predetermined interval; The (k+1)th module command / address terminals to the 2kth module command / address terminals are arranged in the component region at the second predetermined interval; and The third terminal is a resistor, and this third terminal is configured to be adjacent to the command / address terminal of the 2k module. The plurality of terminals also includes command / address terminals.

5. The module board according to claim 4, wherein, The module board also includes: The second branch line is used to connect the command / address terminal disposed on the at least one surface to the second branch point; The fifth signal line is used to connect the second branch point to the command / address terminal of the first module; and The sixth signal line is used to sequentially connect the first module command / address terminal to the second module command / address terminal to the third terminating resistor terminal. Wherein, the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

6. The module board according to claim 5, wherein, The fifth signal line and the sixth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

7. The module board according to claim 4, wherein, The module board also includes: The fourth terminal is a resistor terminal, which is configured to be adjacent to the command / address terminal of the k-th module; The second branch line is used to connect the command / address terminal disposed on the at least one surface to the second branch point; The fifth signal line is used to connect the second branch point to the command / address terminal of the first module; The sixth signal line is used to sequentially connect the first module command / address terminal to the kth module command / address terminal to the fourth terminal resistor terminal; The seventh signal line is used to connect the second branch point to the command / address terminal of the (k+1)th module; and The eighth signal line is used to sequentially connect the (k+1)th module command / address terminals to the 2kth module command / address terminals to the third terminating resistor terminal. The length of the seventh signal line is greater than the sum of the lengths of the fifth signal line and the sixth signal line.

8. The module board according to claim 7, wherein, The length of the sixth signal line is equal to the length of the eighth signal line. The length of the sixth signal line is greater than the length of the fifth signal line, and The sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

9. The module board according to claim 8, wherein, The fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

10. The module board according to claim 4, wherein, The module board includes: The fourth terminal is a resistor terminal, which is configured to be adjacent to the command / address terminal of the 2k-1 module. The second branch line is used to connect the command / address terminal disposed on the at least one surface to the second branch point; The fifth signal line is used to connect the second branch point to the command / address terminal of the first module; The sixth signal line is used to sequentially connect the odd-numbered module command / address terminals from the first module command / address terminal to the 2k-1th module command / address terminal to the fourth terminating resistor terminal; A seventh signal line, wherein the seventh signal line is used to connect the second branch point to the second module command / address terminal in the first module command / address terminal to the second module command / address terminal in the 2k-1 module command / address terminal; and The eighth signal line is used to sequentially connect the even-numbered module command / address terminals from the second module command / address terminal to the 2kth module command / address terminal to the third terminating resistor terminal. Wherein, the length of the fifth signal line is equal to the length of the seventh signal line, and the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

11. The module board according to claim 10, wherein, The fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

12. A storage module, the storage module comprising: Module board, the module board comprising: Multiple stacked layers, the multiple layers including a first layer to an nth layer; The first module clock signal terminal to the kth module clock signal terminal are arranged at a first predetermined interval in the component region of at least one of the upper surface of the first layer and the lower surface of the nth layer; The clock signal terminals of the (k+1)th module to the clock signal terminals of the 2kth module are arranged in the component area at a second predetermined interval; The first terminal is connected to a resistor terminal, and the first terminal is connected to a resistor terminal, which is set to be adjacent to the clock signal terminal of the kth module. The first terminal is connected to a resistor, and the first terminal is connected to the first terminal resistor terminal; The second terminal is connected to a resistor terminal, and the second terminal is connected to a resistor terminal, which is positioned adjacent to the clock signal terminal of the 2k module. The second end is connected to a resistor, and the second end is connected to the second end resistor terminal; Multiple terminals are arranged in a terminal region on at least one surface, and include a clock signal terminal; A first branch line, the first branch line being used to connect the clock signal terminal disposed on the at least one surface to a first branch point; The first signal line is used to connect the first branch point to the clock signal terminal of the first module. The second signal line is used to sequentially connect the clock signal terminals of the first module to the clock signal terminals of the kth module to the first terminating resistor terminal. The third signal line is used to connect the first branch point to the clock signal terminal of the (k+1)th module; The fourth signal line is used to sequentially connect the clock signal terminals of the (k+1)th module to the clock signal terminals of the 2kth module to the second terminating resistor terminal; First semiconductor memory devices to k-th semiconductor memory devices, each of the first semiconductor memory devices to the k-th semiconductor memory device includes a first memory clock signal terminal to the k-th memory clock signal terminal respectively installed at the first module clock signal terminal to the k-th module clock signal terminal; and Semiconductor memory devices k+1 to 2k, each comprising a memory clock signal terminal (k+1 to 2k) respectively mounted at the clock signal terminals of the k+1 module to the 2k module. The length of the third signal line is greater than the sum of the lengths of the first signal line and the second signal line.

13. The storage module according to claim 12, wherein, The first predetermined interval is equal to the second predetermined interval, the length of the second signal line is equal to the length of the fourth signal line, and the length of the second signal line is greater than the length of the first signal line.

14. The storage module according to claim 13, wherein: Each of the first to the second semiconductor memory devices is a dual-core packaged semiconductor memory device comprising a stacked first die and a second die; Each of the first die and the second die is a double data rate semiconductor memory device; and The storage module is an unbuffered dual in-line memory module or a small dual in-line memory module.

15. The storage module according to claim 13, wherein, The first signal line, the second signal line, the third signal line, and the fourth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

16. The storage module according to claim 13, wherein, The module board also includes: The first module command / address terminal to the kth module command / address terminal are arranged in the component area at the first predetermined interval; The (k+1)th module command / address terminals to the 2kth module command / address terminals are arranged in the component region at the second predetermined interval; and The third terminal is a resistor, and this third terminal is configured to be adjacent to the command / address terminal of the 2k module. in: First memory command / address terminals to kth memory command / address terminals are also installed at the first module command / address terminals to the kth module command / address terminals, respectively; and The clock signal terminals of the (k+1)th memory to the clock signal terminals of the 2kth memory are also respectively installed at the command / address terminals of the (k+1)th module to the command / address terminals of the 2kth module.

17. The storage module according to claim 16, further comprising: The second branch line is used to connect the command / address terminal disposed on the at least one surface to the second branch point; The fifth signal line is used to connect the second branch point to the command / address terminal of the first module; as well as The sixth signal line is used to sequentially connect the first module command / address terminal to the second module command / address terminal to the third terminating resistor terminal. Wherein, the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

18. The storage module according to claim 17, wherein, The fifth signal line and the sixth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

19. The storage module according to claim 16, further comprising: The fourth terminal is a resistor terminal, which is configured to be adjacent to the command / address terminal of the k-th module; The second branch line is used to connect the command / address terminal disposed on the at least one surface to the second branch point; The fifth signal line is used to connect the second branch point to the command / address terminal of the first module; The sixth signal line is used to sequentially connect the first module command / address terminal to the kth module command / address terminal to the fourth terminal resistor terminal; The seventh signal line is used to connect the second branch point to the command / address terminal of the (k+1)th module; as well as The eighth signal line is used to sequentially connect the (k+1)th module command / address terminals to the 2kth module command / address terminals to the third terminating resistor terminal. The length of the seventh signal line is greater than the sum of the lengths of the fifth signal line and the sixth signal line.

20. The storage module according to claim 19, wherein, The length of the sixth signal line is equal to the length of the eighth signal line. The length of the sixth signal line is greater than the length of the fifth signal line, and The sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

21. The storage module according to claim 20, wherein, The fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

22. The storage module according to claim 16, further comprising: The fourth terminal is a resistor terminal, which is configured to be adjacent to the command / address terminal of the 2k-1 module. The second branch line is used to connect the command / address terminal disposed on the at least one surface to the second branch point; The fifth signal line is used to connect the second branch point to the command / address terminal of the first module; The sixth signal line is used to sequentially connect the odd-numbered module command / address terminals from the first module command / address terminal to the 2k-1th module command / address terminal to the fourth terminating resistor terminal; The seventh signal line is used to connect the second branch point to the command / address terminal of the (k+1)th module; as well as The eighth signal line is used to sequentially connect the even-numbered module command / address terminals from the second module command / address terminal to the 2kth module command / address terminal to the third terminating resistor terminal. Wherein, the length of the fifth signal line is equal to the length of the seventh signal line, and the sum of the length of the second branch line and the length of the fifth signal line is equal to the sum of the length of the first branch line and the length of the first signal line.

23. The storage module according to claim 22, wherein, The fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line are disposed on at least one surface of the first layer to the nth layer, excluding the at least one surface.

24. A storage system, comprising: A control device, comprising: a processor configured to generate internal commands, internal addresses, and internal data by executing a program; a clock signal generator configured to generate a clock signal; a command / address generator configured to receive the internal commands and the internal addresses from the processor based on the clock signal from the clock signal generator, and generate a command / address; a data output interface configured to receive the internal data and generate 2k data entries; and Storage module, the storage module comprising: Module board, the module board comprising: a plurality of stacked layers, the plurality of layers including a first layer to an nth layer; a first module terminal to a kth module terminal, the first module terminal to the kth module terminal being arranged at a first predetermined interval in an assembly region on at least one surface of the upper surface of the first layer and the lower surface of the nth layer; a (k+1)th module terminal to a 2kth module terminal, the (k+1)th module terminal to the 2kth module terminal being arranged at a second predetermined interval in the assembly region; a first terminated resistor terminal, the first terminated resistor terminal being configured to be adjacent to the kth module terminal; a first terminated resistor, the first terminated resistor being connected to the first terminated resistor terminal; a second terminated resistor terminal, the second terminated resistor terminal being configured to be adjacent to the 2kth module terminal; a second terminated resistor... A resistor, the second-terminated resistor being connected to a second-terminated resistor terminal; a plurality of terminals, the plurality of terminals being arranged in a terminal region on the at least one surface; a first branch line, the first branch line being used to connect at least one of the plurality of terminals to a first branch point; a first signal line, the first signal line being used to connect the first branch point to a first module terminal; a second signal line, the second signal line being used to sequentially connect the first module terminal to the k-th module terminal to the first-terminated resistor terminal; a third signal line, the third signal line being used to connect the first branch point to the (k+1)-th module terminal; and a fourth signal line, the fourth signal line being used to sequentially connect the (k+1)-th module terminal to the 2k-th module terminal to the second-terminated resistor terminal. First semiconductor memory devices to k-th semiconductor memory devices, each of the first semiconductor memory devices to the k-th semiconductor memory device includes a first memory terminal to a k-th memory terminal respectively mounted at the first module terminal to the k-th module terminal; and Semiconductor memory devices k+1 to 2k, wherein each of the semiconductor memory devices k+1 to 2k comprises a memory terminal k+1 to a memory terminal 2k respectively mounted at the module terminal k+1 to the module terminal 2k. The length of the third signal line is greater than the sum of the lengths of the first signal line and the second signal line.

25. The storage system according to claim 24, wherein, The length of the second signal line is equal to the length of the fourth signal line, and the length of the second signal line is greater than the length of the first signal line.

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