Low input supply and low output impedance charge pump circuit

Abstract

Embodiments of the present disclosure relate to low-input power supply and low-output impedance charge pump circuits. The charge transfer transistor of a positive or negative charge pump is biased at its gate terminal with a control voltage that provides a higher level of gate-source voltage to reduce the switch resistance when passing a boosted (positive or negative) voltage to the voltage output of the charge pump. The control voltage is generated using a bootstrap circuit whose operating polarity (i.e., negative or positive) is opposite to the polarity (i.e., positive or negative) of the charge pump.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 115,835, filed on November 19, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a charge pump circuit configured to generate positive and negative voltages. Background Art

[0004] refer to Figure 1A , Figure 1A A circuit diagram of a positive charge pump circuit 100p is shown. Circuit 100p includes an n-channel MOS transistor MN1, whose source terminal is coupled to power supply node 102 and whose drain terminal is coupled to intermediate node NA1; and an n-channel MOS transistor MN2, whose source terminal is coupled to power supply node 102 and whose drain terminal is coupled to intermediate node NA2. Circuit 100p also includes a p-channel MOS transistor MP1, whose source terminal is coupled to output node 104 and whose drain terminal is coupled to node NA1; and a p-channel MOS transistor MP2, whose source terminal is coupled to output node 104 and whose drain terminal is coupled to intermediate node NA2. The gate terminals of transistors MN1 and MP1 are connected together and further connected to intermediate node NA2. The gate terminals of transistors MN2 and MP2 are connected together and further connected to intermediate node NA1. Transistors MN1, MN2, MP1, and MP2 form a CMOS latch circuit.

[0005] Capacitor C1 has one terminal coupled to node NA1 and the other terminal coupled to receive the logical inversion of clock signal CK, which is generated by CMOS inverter circuit 106. CMOS inverter circuit 106 is powered by positive power supply voltage Vdd and receives clock signal CK as an input. Capacitor C2 has one terminal coupled to node NA2 and the other terminal coupled to receive the logical inversion of clock signal CKN (which is the logical inversion of clock signal CK). This logical inversion is generated by CMOS inverter circuit 108. Inverter circuit 108 is powered by positive power supply voltage Vdd and receives clock signal CKN as an input.

[0006] The load 107 of the circuit 100 p is schematically represented by a load capacitor Cload having one terminal coupled to the output node 104 and a second terminal coupled to a ground node, and a current source Iload coupled between the output node 104 and the ground node.

[0007] The power supply node 102 is configured to receive a positive power supply voltage Vdd. The output node 104 is configured to generate a multiplied positive output voltage Vpos, where Vpos is approximately 2*Vdd.

[0008] refer to Figure 1B , Figure 1B A circuit diagram for a negative charge pump circuit 100n is shown. Circuit 100n includes a p-channel MOS transistor MP1, whose source terminal is coupled to power supply node 102 and whose drain terminal is coupled to intermediate node NA1; and a p-channel MOS transistor MP2, whose source terminal is coupled to power supply node 102 and whose drain terminal is coupled to intermediate node NA2. Circuit 100n also includes an n-channel MOS transistor MN1, whose source terminal is coupled to output node 104 and whose drain terminal is coupled to intermediate node NA1; and an n-channel MOS transistor MN2, whose source terminal is coupled to output node 104 and whose drain terminal is coupled to intermediate node NA2. The gate terminals of transistors MN1 and MP1 are connected together and further connected to intermediate node NA2. The gate terminals of transistors MN2 and MP2 are connected together and further connected to intermediate node NA1. Transistors MN1, MN2, MP1, and MP2 form a CMOS latch circuit.

[0009] One terminal of capacitor C1 is coupled to node NA1, and the other terminal is coupled to receive the logical inversion of clock signal CK, which is generated by CMOS inverter circuit 106. CMOS inverter circuit 106 is powered by positive power supply voltage Vdd and receives clock signal CK as an input. One terminal of capacitor C2 is coupled to node NA2, and the other terminal is coupled to receive the logical inversion of clock signal CKN (which is the logical inversion of clock signal CK). This logical inversion is generated by CMOS inverter circuit 108. CMOS inverter circuit 108 is powered by positive power supply voltage Vdd and receives clock signal CKN as an input.

[0010] The load 107 of the circuit 100 n is schematically represented by a load capacitor Cload having one terminal coupled to the output node 104 and a second terminal coupled to the ground node, and a current source Iload coupled between the positive supply voltage Vdd and the output node 104 .

[0011] The power supply node 102 is configured to receive a ground voltage Vgnd. The output node 104 is configured to generate a multiplied negative output voltage Vneg, wherein Vneg is approximately equal to -Vdd.

[0012] The output impedance at the output node 104 is related to the frequency of the clock signals CK and CKN and the on-resistance (Rds_on) of the switch transistors MN1, MN2, MP1, and MP2 that perform the charge transfer. The output impedance is given by the following formula:

[0013]

[0014] Where: C is the capacitance of the flying capacitor (i.e., C1 or C2 depending on the clock phase).

[0015] The on-resistance (Rds_on) of transistors MN1, MN2, MP1, and MP2 is given by the following formula:

[0016]

[0017] Where: L is the length of the transistor, W is the width of the transistor, C OX is the gate capacitance, V GS is the gate-source voltage, and V TH is the threshold voltage.

[0018] If the transistor width W is reduced, the on-resistance (Rds_on) increases, and the voltage drop across each switching transistor is larger, and the efficiency is correspondingly reduced.

[0019] The switch capacitance is given by:

[0020] C SW =C OX *W*L eff

[0021] Where: L eff is the effective length of the transistor switch.

[0022] Note that if the transistor width W increases, the capacitance on the upper plate of the capacitor will increase, and the corresponding charge loss will increase, and the efficiency will decrease.

[0023] Now refer to Figure 2A , Figure 2A A circuit diagram of a positive charge pump circuit 200p is shown (see also U.S. patent application Ser. No. 16 / 911,967, filed Jun. 25, 2020). Figure 2A, which is incorporated herein by reference). Circuit 200p includes a (positive) bootstrap circuit comprising: an n-channel MOS transistor MN1, whose source terminal is coupled to power supply node 202 and whose drain terminal is coupled to intermediate node NA1; and an n-channel MOS transistor MN2, whose source terminal is coupled to power supply node 202 and whose drain terminal is coupled to intermediate node NA2. Transistors MN1 and MN2 are cross-coupled in the following manner: the gate terminal of transistor MN1 is coupled to the drain terminal of transistor MN2 at node NA2, and the gate terminal of transistor MN2 is coupled to the drain terminal of transistor MN1 at node NA1.

[0024] One terminal of the bootstrap capacitor Cbs1 is coupled to the node NA1, and the other terminal is coupled to receive the logical inversion of the clock signal CK, CK1N, generated by the CMOS inverter circuit 206p, which is powered by the positive power supply voltage Vdd and receives the clock signal CK as an input. One terminal of the bootstrap capacitor Cbs2 is coupled to the node NA2, and the other terminal is coupled to receive the logical inversion of the clock signal CKN (which is the logical inversion of the clock signal CK), CK1, generated by the CMOS inverter circuit 208p, which is powered by the positive power supply voltage Vdd and receives the clock signal CKN as an input.

[0025] CMOS switching circuit 210p has a first terminal coupled to receive a positive power supply voltage Vdd and a second terminal at an intermediate node NB1. The source terminal of p-channel MOS transistor MP1 in switching circuit 210p is coupled to node NA1, while the source terminal of n-channel MOS transistor MN3 in switching circuit 210p is coupled to receive a clock signal CKN. A second terminal is located at the common drain of transistors MP1 and MN3. The gates of transistors MP1 and MN3 are coupled to the first terminal (Vdd).

[0026] CMOS switching circuit 212p has a first terminal coupled to receive a positive power supply voltage Vdd and a second terminal at an intermediate node NB2. The source terminal of p-channel MOS transistor MP2 in switching circuit 212p is coupled to node NA2, and the source terminal of n-channel MOS transistor MN4 in switching circuit 212p is coupled to receive a clock signal CK. A second terminal is located at the common drain of transistors MP2 and MN4. The gates of transistors MP2 and MN4 are coupled to the first terminal (Vdd).

[0027] Circuits 210 p and 212 p with bootstrap circuits form a bootstrap-based level shift circuit.

[0028] CMOS switching circuit 220p has a first terminal coupled to node NB1 and a second terminal located at intermediate node NC1. The source terminal of n-channel MOS transistor MN5 in switching circuit 220p is coupled to power supply node 202, and the source terminal of p-channel MOS transistor MP3 in switching circuit 220p is coupled to output node 204. The second terminal is at the common drain of transistors MN5 and MP3. The gate terminals of transistors MN5 and MP3 are coupled to the first terminal (NB1).

[0029] CMOS switching circuit 222p has a first terminal coupled to node NB2 and a second terminal at an intermediate node NC2. The source terminal of n-channel MOS transistor MN6 in switching circuit 222p is coupled to power supply node 202, and the source terminal of p-channel MOS transistor MP4 in switching circuit 222p is coupled to output node 204. The second terminal is at the common drain of transistors MN6 and MP4. The gate terminals of transistors MN6 and MP4 are coupled to the first terminal (NB2).

[0030] One terminal of capacitor C1 is coupled to node NC1, and the other terminal is coupled to receive the logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 216p, which is powered by positive power supply voltage Vdd and receives clock signal CK1N as input. One terminal of capacitor C2 is coupled to node NC2, and the other terminal is coupled to receive the logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 218p, which is powered by positive power supply voltage Vdd and receives clock signal CK1 as input.

[0031] The load 207 of the circuit 200 p is schematically represented by a load capacitor Cload having one terminal coupled to the output node 204 and a second terminal coupled to a ground node, and a current source Iload coupled between the output node 204 and the ground node.

[0032] The power supply node 202 is configured to receive a positive power supply voltage Vdd. The output node 204 is configured to generate a multiplied positive output voltage Vpos, where Vpos is approximately 2*Vdd.

[0033] Figure 2B Shown for Figure 2A 2. The waveforms of the clock signals CK, CKN, CK1 and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, NC1 and NC2 for the operation of the circuit 200p are shown in FIG. Figure 2BSignal propagation delays are not shown in the waveforms.It will be further noted that the voltage levels of the clock signals are idealized, and in implementation the voltages will be substantially equal (eg, within 1-20%), but not necessarily equal to the ideal Vdd and 2*Vdd voltage levels.

[0034] The circuit formed by transistors MN1 and MN2, bootstrap capacitors Cbs1 and Cbs2, and inverters 206p and 208p is a positive bootstrap circuit. The positive bootstrap circuit operates in response to clock signals CK and CKN referenced to power supply Vdd and ground to generate clock signals at nodes NA1 and NA2 referenced to 2*Vdd and Vdd. When clock signal CK is at a logic high (Vdd), clock signal CK1N output by inverter 206p is at a logic low (Gnd). Transistor MN1 is turned on because node NA2 is raised to a voltage level of 2*Vdd by capacitor Cbs2 (i.e., transistor MN1 is turned on because the gate voltage of transistor MN1 exceeds Vdd by more than Vth at its source terminal), and bootstrap capacitor Cbs1 is charged to the Vdd voltage level. In the next phase of the clock signal, clock signal CK is at a logic low, and clock signal CK1N output by inverter 206p is at a logic high. Transistor MN1 is turned off because node NA2 is at the Vdd voltage level (i.e., because the gate voltage of transistor MN1 is equal to the source voltage Vdd and therefore does not exceed Vth and is turned off), and the voltage at node NA1 is raised to a 2*Vdd voltage level by means of the bootstrap voltage Vdd stored on capacitor Cbs1. A similar process occurs in response to the phase of clock signals CKN and CK1.

[0035] The circuit arrangement formed by CMOS switching circuits 210p and 212p acts as a level shifting stage, shifting the clock signals referenced to 2*Vdd and Vdd at nodes NA1 and NA2 to generate clock signals referenced to 2*Vdd and ground at nodes NB1 and NB2. Consider the following regarding the operation of circuit 210p: When clock signal CKN is logic low, transistor MN3 is turned on (i.e., because the gate voltage of transistor MN3 at its source terminal exceeds ground by more than Vth), and node NB1 is clamped to ground. Transistor MP1 is turned off because node NA1 is at Vdd. In the next phase of the clock signal, clock signal CKN is logic high, causing transistor MN3 to turn off (i.e., because the gate voltage of transistor MN3 is equal to the source voltage Vdd and therefore does not exceed Vth). In the same phase, node NA1 is at a voltage level of 2*Vdd (as discussed above), and transistor MP1 is turned on (i.e., Vgs of transistor MP1 exceeds Vth), passing the 2*Vdd voltage level to node NB1. A similar process occurs for circuit 212p in response to the phase of clock signal CK.

[0036] The circuit arrangement formed by capacitors C1 and C2 and inverters 216p and 218p operates in response to clock signals CK1 and CK1N referenced to power supply Vdd and ground to generate clock signals at nodes NC1 and NC2 referenced to 2*Vdd and Vdd. Consider the following operation related to the circuit having capacitor C1 and inverter 216p: When clock signal CK1N is logic high, the output of inverter 216p is logic low. Simultaneously, as described below, transistor MN5 is turned on and capacitor C1 is charged to the Vdd voltage level. At the next phase of the clock signal, clock signal CK1N is logic low, and the output of inverter 216p is logic high. The voltage at node NC1 is raised to the 2*Vdd voltage level by means of capacitor C1. A similar process occurs for the circuit having capacitor C2 and inverter 218p in response to the phase of clock signal CK1.

[0037] The circuit arrangement formed by CMOS switching circuits 220p and 222p functions as a charge transfer driver stage to selectively pass the 2*Vdd voltage at nodes NC1 and NC2 to output node 204 to drive capacitive and current load 207. Consider the following regarding the operation of circuit 220p: When clock signals CKN and CK1N are both logic high, the voltage at node NB1 is at a 2*Vdd voltage level, and transistor MN5 is turned on (i.e., Vgs of transistor MN5 exceeds Vth), thereby charging capacitor C1 to the Vdd voltage level. At the next phase of the clock signals, when clock signals CKN and CK1N are both logic low, the voltage at node NB1 is at ground level, and transistor MP3 is turned on (i.e., Vgs of transistor MP3 exceeds Vth), thereby passing the 2*Vdd voltage level at node NC1 to output node 204. A similar process occurs for circuit 222p in response to the phases of clock signals CK and CK1.

[0038] One advantage of the circuit implementation is that it increases the Vgs of the charge transfer switch transistor to reduce the on-resistance (Rds_on). Figure 1A Compared with the charge pump circuit, the output impedance is correspondingly reduced.

[0039] Now refer to Figure 3A , Figure 3AA circuit diagram of a negative charge pump circuit 200n is shown (see also FIG. 2E of U.S. patent application Ser. No. 16 / 911,967, filed on June 25, 2020, which is incorporated herein by reference). Circuit 200n includes a negative bootstrap circuit comprising a p-channel MOS transistor MP1 having a source terminal coupled to power supply node 202 and a drain terminal coupled to an intermediate node NA1; and a p-channel MOS transistor MP2 having a source terminal coupled to power supply node 202 and a drain terminal coupled to an intermediate node NA2. Transistors MP1 and MP2 are cross-coupled in the following manner: the gate terminal of transistor MP1 is coupled to the drain terminal of transistor MP2 at node NA2, and the gate terminal of transistor MP2 is coupled to the drain terminal of transistor MP1 at node NA1.

[0040] One terminal of the bootstrap capacitor Cbs1 is coupled to the node NA1, and the other terminal is coupled to receive the logical inversion of the clock signal CK, CK1N, generated by the CMOS inverter circuit 206n, which is powered by the positive power supply voltage Vdd and receives the clock signal CK as an input. One terminal of the bootstrap capacitor Cbs2 is coupled to the node NA2, and the other terminal is coupled to receive the logical inversion of the clock signal CKN (which is the logical inversion of the clock signal CK), CK1, generated by the CMOS inverter circuit 208n, which is powered by the positive power supply voltage Vdd and receives the clock signal CKN as an input.

[0041] CMOS switching circuit 210n has a first terminal coupled to receive ground voltage Gnd and a second terminal at an intermediate node NB1. The source terminal of p-channel MOS transistor MP3 in switching circuit 210n is coupled to receive clock signal CKN, and the source terminal of n-channel MOS transistor MN1 in switching circuit 210n is coupled to node NA1. A second terminal is located at the common drain of transistors MP3 and MN1. The gates of transistors MP3 and MN1 are coupled to a first terminal (Gnd).

[0042] CMOS switching circuit 212n has a first terminal coupled to receive ground voltage Gnd and a second terminal at intermediate node NB2. The source terminal of p-channel MOS transistor MP4 in switching circuit 212n is coupled to receive clock signal CK, and the source terminal of n-channel MOS transistor MN2 in switching circuit 212n is coupled to NA2. A second terminal is located at the common drain of transistors MP4 and MN2. The gate terminals of transistors MP4 and MN2 are coupled to a first terminal (Gnd).

[0043] Circuits 210n and 212n with bootstrap circuits form a bootstrap-based level shifting circuit.

[0044] CMOS switching circuit 220n has a first terminal coupled to node NB1 and a second terminal located at an intermediate node NC1. The source terminal of p-channel MOS transistor MP5 in switching circuit 220n is coupled to power supply node 202, and the source terminal of n-channel MOS transistor MN3 in switching circuit 220n is coupled to output node 204. The second terminal is at the common drain of transistors MP5 and MN3. The gates of transistors MP5 and MN3 are coupled to the first terminal (NB1).

[0045] CMOS switching circuit 222n has a first terminal coupled to node NB2 and a second terminal at an intermediate node NC2. The source terminal of p-channel MOS transistor MP6 in switching circuit 222n is coupled to node 202, and the source terminal of n-channel MOS transistor MN4 in switching circuit 222n is coupled to output node 204. The second terminal is at the common drain of transistors MP6 and MN4. The gates of transistors MP6 and MN4 are coupled to the first terminal (NB2).

[0046] One terminal of capacitor C1 is coupled to node NC1, and the other terminal is coupled to receive the logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 216n, which is powered by positive power supply voltage Vdd and receives clock signal CK1N as an input. One terminal of capacitor C2 is coupled to node NC2, and the other terminal is coupled to receive the logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 218n, which is powered by positive power supply voltage Vdd and receives clock signal CK1 as an input.

[0047] The load 207 of the circuit 200 n is schematically represented by a load capacitor Cload having one terminal coupled to the output node 204 and a second terminal coupled to the ground node, and a current source Iload coupled between the positive supply voltage Vdd and the output node 204 .

[0048] The power supply node 202 is configured to receive a ground voltage Vgnd. The output node 204 is configured to generate a multiplied negative output voltage Vneg, wherein Vneg is approximately -Vdd.

[0049] Figure 3B Shown for Figure 3A1 and 2. The waveforms of the clock signals CK, CKN, CK1 and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, NC1 and NC2 for the operation of the circuit 200n are shown in FIG. Figure 3B Signal propagation delays are not shown in the waveforms.It will be further noted that the voltage levels of the clock signals are idealized, and in implementation the voltages will be substantially equal (eg, within 1-20%) but not necessarily equal to the Vdd and -Vdd voltage levels.

[0050] The circuit arrangement formed by transistors MP1 and MP2, bootstrap capacitors Cbs1 and Cbs2, and inverters 206n and 208n is a negative bootstrap circuit that operates in response to clock signals CK and CKN referenced to power supply Vdd and ground to generate clock signals referenced to -Vdd and ground at nodes NA1 and NA2. When clock signal CKN is at a logic low (Gnd), clock signal CK1 output by inverter 208n is at a logic high (Vdd). Transistor MP2 is turned on because node NA1 is raised to a -Vdd voltage level by capacitor Cbs1 (i.e., transistor MP2 is turned on because the gate voltage of transistor MP2 is lower than the ground voltage at its source terminal by more than Vth), and bootstrap capacitor Cbs2 is charged to the ground voltage level at node NA2. At the next phase of the clock signal, clock signal CKN is at a logic high, and clock signal CK1 output by inverter 208n is at a logic low. Transistor MP2 is turned off because node NA1 is at the ground voltage level (i.e., because the gate voltage of transistor MP2 is equal to the source voltage ground and therefore does not exceed Vth and is turned off), and the voltage at node NA2 is raised to the -Vdd voltage level by means of the bootstrapped ground voltage stored on capacitor Cbs2. A similar process occurs in response to the phase of clock signals CK and CK1N.

[0051] The circuit arrangement formed by CMOS switching circuits 210n and 212n functions as a level shifting stage to shift the -Vdd and ground-referenced clock signals at nodes NA1 and NA2, thereby generating -Vdd and +Vdd-referenced clock signals at nodes NB1 and NB2. Consider the following regarding the operation of circuit 212n: When clock signal CK is logic high, transistor MP4 is turned on (i.e., because its gate voltage is more than Vth below its source terminal), transistor MN2 is turned off (i.e., because node NA2 is grounded), and node NB2 is clamped to Vdd. In the next phase of the clock signal, clock signal CK is logic low, causing transistor MP4 to turn off (i.e., because its gate voltage is equal to its source voltage, ground, and therefore does not exceed Vth). In the same phase, node NA2 is at a -Vdd voltage level (see discussion above), and transistor MN2 is turned on (i.e., Vgs of transistor MN2 exceeds Vth), thereby passing the -Vdd voltage level to node NB2. A similar process occurs for circuit 210n in response to the phase of clock signal CKN.

[0052] The circuit formed by capacitors C1, C2 and inverters 216n, 218n operates in response to clock signals CK1 and CK1N, which are referenced to power supply Vdd and ground, to generate clock signals at nodes NC1 and NC2, which are referenced to -Vdd and ground. Consider the following operation related to the circuit having capacitor C2 and inverter 218n: When clock signal CK1 is logic low, the output of inverter 218n is logic high. Simultaneously, as discussed below, transistor MP6 is turned on and capacitor C2 is discharged to ground voltage level. In the next phase of the clock signal, clock signal CK1 is logic high, and the output of inverter 218n is logic low. The voltage at node NC2 is raised to -Vdd voltage level by means of capacitor C2. A similar process occurs in the circuit having capacitor C1 and inverter 216n in response to the phase of clock signal CK1N.

[0053] The circuit arrangement formed by CMOS switching circuits 220n and 222n functions as a charge transfer driver stage to selectively pass the −Vdd voltage at nodes NC1 and NC2 to output node 204 to drive capacitive and current load 207. Consider the following regarding the operation of circuit 222n: When clock signals CK and CK1 are both logic low, the voltage at node NB2 is at a −Vdd voltage level, and transistor MP6 is turned on (i.e., Vgs of transistor MP6 exceeds Vth), thereby discharging capacitor C2 to a ground voltage level. In the next phase of the clock signals, when clock signals CK and CK1 are both logic high, the voltage at node NB2 is at a Vdd level, and transistor MN4 is turned on (i.e., Vgs of transistor MN4 exceeds Vth), thereby passing the −Vdd voltage level at node NC2 to node 204. A similar process occurs for circuit 220n in response to the phases of clock signals CKN and CK1N.

[0054] One advantage of the circuit implementation is that it increases the Vgs of the charge transfer switch transistor to reduce the on-resistance (Rds_on). Figure 1B Compared with the charge pump circuit, the output impedance is correspondingly reduced. Summary of the Invention

[0055] In one embodiment, a positive charge pump circuit is configured to generate an output voltage from an input voltage, wherein the output voltage has a more positive voltage level than the input voltage. The positive charge pump circuit includes: a negative bootstrap circuit configured to generate a control signal in response to a first clock signal, wherein the control signal switches between a ground voltage and a negative voltage; a boost circuit configured to generate a positive boosted voltage in response to a second clock signal; and a charge transfer transistor having a drain terminal coupled to receive the positive boosted voltage and a source terminal coupled to an output node, wherein a gate terminal of the charge transfer transistor is biased by a negative voltage of the control signal to conduct and pass the positive boosted voltage to the output node to generate the output voltage.

[0056] In one embodiment, a negative charge pump circuit is configured to generate an output voltage from an input voltage, wherein the negative voltage level of the output voltage is more negative than the voltage level of the input voltage. The negative charge pump circuit includes: a positive bootstrap circuit configured to generate a control signal in response to a first clock signal, wherein the control signal switches between a first positive voltage and a second positive voltage, wherein the voltage level of the second positive voltage is more positive than the voltage level of the first positive voltage; a boost circuit configured to generate a negative boosted voltage in response to a second clock signal; and a charge transfer transistor having a drain terminal coupled to receive the negative boosted voltage and a source terminal coupled to an output node, wherein a gate terminal of the charge transfer transistor is biased by the second positive voltage of the control signal to conduct and pass the negative boosted voltage to the output node to generate the output voltage.

[0057] In one embodiment, a positive charge pump circuit is configured to generate an output voltage from an input voltage, wherein a positive voltage level of the output voltage is more positive than a voltage level of the input voltage. The positive charge pump circuit includes: a negative bootstrap circuit configured to generate a first control signal in response to a first clock signal, wherein the first control signal switches between a ground voltage and a negative voltage; a positive bootstrap circuit configured to generate a second control signal in response to the first clock signal, wherein the second control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a boost circuit configured to generate a positive boost voltage at an intermediate node in response to the second clock signal; a first charge transfer transistor, whose drain terminal is coupled to the intermediate node and whose source terminal is coupled to the input voltage, wherein a gate terminal of the first charge transfer transistor is turned on by a second positive voltage gate bias of the second control signal to support the boost circuit; and a second charge transfer transistor, whose drain terminal is coupled to the intermediate node and whose source terminal is coupled to the output node, wherein a gate terminal of the second charge transfer transistor is turned on by a negative voltage gate bias of the first control signal and passes the positive boost voltage to the output node and generates the output voltage.

[0058] In one embodiment, a negative charge pump circuit is configured to generate an output voltage from an input voltage, wherein a negative voltage level of the output voltage is more negative than a voltage level of the input voltage. The negative charge pump circuit includes: a negative bootstrap circuit configured to generate a first control signal in response to a first clock signal, wherein the first control signal switches between a ground voltage and a negative voltage; a positive bootstrap circuit configured to generate a second control signal in response to the first clock signal, wherein the second control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a boost circuit configured to generate a negative boost voltage at an intermediate node in response to the second clock signal; a first charge transfer transistor having a drain terminal coupled to the intermediate node and a source terminal coupled to an input voltage, wherein a gate terminal of the first charge transfer transistor is turned on by a negative voltage gate bias of the first control signal to support the boost circuit; and a second charge transfer transistor having a drain terminal coupled to the intermediate node and a source terminal coupled to an output node, wherein a gate terminal of the second charge transfer transistor is turned on by a second positive voltage gate bias of the second control signal and passes the negative boost voltage to the output node and generates the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0060] Figure 1AThis is the circuit diagram of the positive charge pump circuit;

[0061] Figure 1B is a circuit diagram of a negative charge pump circuit;

[0062] Figure 2A This is the circuit diagram of the positive charge pump circuit;

[0063] Figure 2B Pictured Figure 2A The operating waveform of the circuit;

[0064] Figure 3A is a circuit diagram of a negative charge pump circuit;

[0065] Figure 3B Pictured Figure 3A The operating waveform of the circuit;

[0066] Figure 4A This is the circuit diagram of the positive charge pump circuit;

[0067] Figure 4B Pictured Figure 4A The operating waveform of the circuit;

[0068] Figure 4C Shown Figure 4A A more general circuit configuration of a positive charge pump circuit;

[0069] Figure 5A is a circuit diagram of a negative charge pump circuit;

[0070] Figure 5B Pictured Figure 5A The operating waveform of the circuit;

[0071] Figure 5C Shown Figure 5A A more general circuit configuration of a negative charge pump circuit;

[0072] Figure 6A This is the circuit diagram of the positive charge pump circuit;

[0073] Figure 6B Pictured Figure 6A The operating waveform of the circuit;

[0074] Figure 6C Shown Figure 6A A more general circuit configuration of a positive charge pump circuit;

[0075] Figure 7A is a circuit diagram of a negative charge pump circuit;

[0076] Figure 7B Pictured Figure 7A The operating waveform of the circuit; and

[0077] Figure 7C Shown Figure 7A A more general circuit configuration of a negative charge pump circuit. DETAILED DESCRIPTION

[0078] refer to Figure 4A , Figure 4A A circuit diagram of a positive charge pump circuit 300p is shown. Circuit 300p includes an n-channel MOS transistor MN1, whose source terminal is coupled to power supply node 302 and whose drain terminal is coupled to intermediate node NC1; and an n-channel MOS transistor MN2, whose source terminal is coupled to power supply node 302 and whose drain terminal is coupled to intermediate node NC2. Transistors MN1 and MN2 are cross-coupled in the following manner: the gate terminal of transistor MN1 is coupled to the drain terminal of transistor MN2 at node NC2, and the gate terminal of transistor MN2 is coupled to the drain terminal of transistor MN1 at node NC1. Circuit 300p also includes a p-channel MOS transistor MP1, whose source terminal is coupled to output node 304 and whose drain terminal is coupled to node NC1; and a p-channel MOS transistor MP2, whose source terminal is coupled to output node 304 and whose drain terminal is coupled to intermediate node NC2. The transistors MN1 and MP1 form a CMOS switching circuit 320 p , and the transistors MN2 and MP2 form a CMOS switching circuit 322 p .

[0079] Positive charge pump circuit 300p further includes a negative bootstrap circuit 305n, which includes: a p-channel MOS transistor MP3, whose source terminal is coupled to the ground node and whose drain terminal is coupled to the intermediate node NA1; and a p-channel MOS transistor MP4, whose source terminal is coupled to the ground node and whose drain terminal is coupled to the intermediate node NA2. Transistors MP3 and MP4 are cross-coupled in the following manner: the gate terminal of transistor MP3 is coupled to the drain terminal of transistor MP4 at node NA2, and the gate terminal of transistor MP4 is coupled to the drain terminal of transistor MP3 at node NA1.

[0080] One terminal of the bootstrap capacitor Cbs1 is coupled to the node NA1 and the other terminal is coupled to receive the logical inversion of the clock signal CK, which is generated by the CMOS inverter circuit 306n. The CMOS inverter circuit 306n is powered by the positive power supply voltage Vdd and receives the clock signal CK as an input. One terminal of the bootstrap capacitor Cbs2 is coupled to the node NA2 and the other terminal is coupled to receive the logical inversion of the clock signal CKN (which is the logical inversion of the clock signal CK). The logical inversion CK1 is generated by the CMOS inverter circuit 308n. The CMOS inverter circuit 308n is powered by the positive power supply voltage Vdd and receives the clock signal CKN as an input.

[0081] CMOS switching circuit 310p has a first terminal that receives a positive power supply voltage Vdd, a second terminal that is coupled to receive a ground voltage Gnd, and a third terminal located at an intermediate node NB1. The source terminal of p-channel MOS transistor MP5 in switching circuit 310p is coupled to the gate terminal of transistor MN1 in CMOS switching circuit 320p (i.e., intermediate node NC2), and the source terminal of n-channel MOS transistor MN3 in switching circuit 310p is coupled to an intermediate node NA1 of negative bootstrap circuit 305n. A third terminal is located at the common drain of transistors MP5 and MN3, which is connected to the gate terminal of transistor MP1 in CMOS switching circuit 320p. The gate of transistor MP5 is coupled to the first terminal (Vdd), and the gate of transistor MN3 is coupled to the second terminal (Gnd).

[0082] CMOS switching circuit 312p has a first terminal that receives a positive power supply voltage Vdd, a second terminal that is coupled to receive a ground voltage Gnd, and a third terminal located at an intermediate node NB2. The source terminal of p-channel MOS transistor MP6 in switching circuit 312p is coupled to the gate terminal of transistor MN2 in CMOS switching circuit 322p (i.e., intermediate node NC1), and the source terminal of n-channel MOS transistor MN4 in switching circuit 312p is coupled to an intermediate node NA2 of negative bootstrap circuit 305n. The third terminal is located at the common drain of transistors MP6 and MN4. The gate of transistor MP6 is coupled to the first terminal (Vdd), and the gate of transistor MN4 is coupled to the second terminal (Gnd).

[0083] Circuits 310p and 312p with bootstrap circuit 305n form a bootstrap-based level shifting circuit.

[0084] One terminal of capacitor C1 is coupled to node NC1, and the other terminal is coupled to receive the logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 316p, which is powered by positive power supply voltage Vdd and receives clock signal CK1N as an input. One terminal of capacitor C2 is coupled to node NC2, and the other terminal is coupled to receive the logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 318p, which is powered by positive power supply voltage Vdd and receives clock signal CK1 as an input.

[0085] The load 307 of the circuit 300 p is schematically represented by a load capacitor Cload having one terminal coupled to the output node 304 and a second terminal coupled to a ground node, and a current source Iload coupled between the output node 304 and the ground node.

[0086] The power supply node 302 is configured to receive a positive power supply voltage Vdd. The output node 304 is configured to generate a multiplied positive output voltage Vpos accordingly using the positive charge pump circuit 300, wherein Vpos is approximately 2*Vdd.

[0087] Figure 4B Shown for Figure 4A 300p and the waveforms of the clock signals CK, CKN, CK1 and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, NC1 and NC2 for the operation of the circuit 300p. It should be noted that, in order to facilitate understanding of the operation of the circuit 300p, Figure 4B Signal propagation delays are not shown in the waveforms.It will be further noted that the voltage levels of the clock signals are idealized and in implementation the voltages will be substantially equal (eg, within 1-20%) but not necessarily equal to the ideal ±Vdd and 2*Vdd voltage levels.

[0088] The circuit arrangement formed by transistors MP3 and MP4, bootstrap capacitors Cbs1 and Cbs2, and inverters 306n and 308n is a negative bootstrap circuit that operates in response to clock signals CK and CKN referenced to power supply Vdd and ground to generate clock signals referenced to -Vdd and ground at nodes NA1 and NA2. When clock signal CKN is at a logic low (Gnd), clock signal CK1 output by inverter 308n will be at a logic high (Vdd). Transistor MP4 is turned on because node NA1 is raised to a -Vdd voltage level by capacitor Cbs1 (i.e., because transistor MP4's gate voltage is lower than the ground voltage of its source terminal by more than Vth, turning it on), and bootstrap capacitor Cbs2 is charged to ground voltage level at node NA2. In the next phase of the clock signal, clock signal CKN is at a logic high, and clock signal CK1 output by inverter 308n is at a logic low. Transistor M4 is turned off because node NA1 is at the ground voltage level (i.e., because the gate voltage of transistor MP4 is equal to the source voltage ground and therefore does not exceed Vth and is turned off) and the voltage at node NA2 is raised to the -Vdd voltage level by means of the bootstrapped ground voltage stored on capacitor Cbs2. A similar process occurs in response to the phase of clock signals CK and CK1N.

[0089] The circuit arrangement formed by capacitors C1 and C2 and inverters 316p and 318p operates in response to clock signals CK1 and CK1N referenced to power supply Vdd and ground to generate clock signals at nodes NC1 and NC2 referenced to 2*Vdd and Vdd. Consider the following operation related to the circuit having capacitor C1 and inverter 316p: When clock signal CK1N is logic high, the output of inverter 316p is logic low. Simultaneously, as described below, transistor MN1 is turned on and capacitor C1 is charged to the Vdd voltage level. In the next phase of the clock signal, clock signal CK1N is logic low, and the output of inverter 316p is logic high. The voltage at node NC1 is raised to the 2*Vdd voltage level by means of capacitor C1. A similar process occurs for the circuit having capacitor C2 and inverter 318p in response to the phase of clock signal CK1.

[0090] The circuit arrangement formed by CMOS switching circuits 310p and 312p acts as a level shifting stage, shifting the clock signals referenced to -Vdd and ground at nodes NA1 and NA2 to generate clock signals referenced to -Vdd and +2*Vdd at nodes NB1 and NB2. Consider the following regarding the operation of circuit 312p: When node NA2 is grounded, transistor MN4 is off (i.e., because the gate voltage of transistor MN4 is equal to the source voltage, ground, and therefore does not exceed Vth). Simultaneously, the voltage at node NC1 has been raised to a voltage level of 2*Vdd via inverter 316p and capacitor C1 in response to the operation of clock CK1n. In this case, transistor MP6 is on (i.e., because the gate voltage of transistor MP6 is more than Vth lower than the source terminal), and the voltage at node NB2 is driven to 2*Vdd. Conversely, when node NA2 is at -Vdd, transistor MN4 is on (i.e., because the gate voltage of transistor MN4 is more than Vth lower than the source terminal), and the voltage at node NB2 is driven to -Vdd. A similar process occurs with respect to circuit 210p.

[0091] The circuit arrangement formed by CMOS switching circuits 320p and 322p functions as a charge transfer driver stage to selectively pass the 2*Vdd voltage at nodes NC1 and NC2 to output node 304 to drive capacitive and current load 307. Consider the following regarding the operation of circuit 322p: When the voltage at node NC2 is Vdd due to transistor MN2 being on, the voltage at node NB2 is 2*Vdd. In this case, transistor MP2 is off (i.e., because the gate voltage of transistor MP2 is greater than the source voltage and therefore does not exceed Vth). When the voltage at node NC2 rises to 2*Vdd, the voltage at node NB2 is -Vdd, and transistor MP2 is turned on (i.e., Vgs of transistor MP2 exceeds Vth), thereby passing the 2*Vdd voltage level at node NC2 to output node 304. A similar process occurs for circuit 320p in response to the opposite phase.

[0092] One advantage of the circuit implementation is that when the gate is driven by -Vdd, especially when combined with the operation of transistors MP1 and MP2, the Vgs of the associated charge transfer switch transistors is increased to reduce the on-resistance (Rds_on).

[0093] Figure 4C Shown in Figure 4A A more general circuit configuration of a positive charge pump circuit 300p is shown. Circuit 300p is configured to increase the gate-source voltage (Vgs) of charge transfer transistors (switches) MP1 and MP2 to reduce their "on" resistance. A negative voltage bootstrap circuit 305n generates a negative voltage (-Vdd) at nodes NA1 and NA2. This voltage is selectively switched in response to a clock signal generated by a clock circuit for application to the gate terminals of transistors MP1 and MP2, thereby providing a voltage boost. Under the control of switching circuits 310p and 312p, the gate drive signals for transistors MP1 and MP2 alternate between -Vdd and 2*Vdd in response to the clock signal. A boosted voltage of 2*Vdd is generated at nodes NC1 and NC2 and passed by transistors MP1 and MP2 when their gate terminals are gate biased with a -Vdd voltage. The effective Vgs of transistors MP1 and MP2 during the charge transfer phase is accordingly 3*Vdd, resulting in significantly reduced switch resistance.

[0094] refer to Figure 5A , Figure 5AA circuit diagram of a negative charge pump circuit 300n is shown. Circuit 300n includes a p-channel MOS transistor MP1, whose source terminal is coupled to power supply node 302 and whose drain terminal is coupled to intermediate node NC1; and a p-channel MOS transistor MN2, whose source terminal is coupled to power supply node 302 and whose drain terminal is coupled to intermediate node NC2. Transistors MP1 and MP2 are cross-coupled in the following manner: the gate terminal of transistor MP1 is coupled to the drain terminal of transistor MP2 at node NC2, and the gate terminal of transistor MP2 is coupled to the drain terminal of transistor MP1 at node NC1. Circuit 300n also includes an n-channel MOS transistor MN1, whose source terminal is coupled to output node 304 and whose drain terminal is coupled to node NC1; and an n-channel MOS transistor MN2, whose source terminal is coupled to output node 304 and whose drain terminal is coupled to intermediate node NC2. Transistors MP1 and MN1 form a CMOS switching circuit 320n, and transistors MP2 and MN2 form a CMOS switching circuit 322n.

[0095] Negative charge pump circuit 300n further includes a positive bootstrap circuit 305p, which includes an n-channel MOS transistor MN3 having a source terminal coupled to power supply voltage node Vdd and a drain terminal coupled to intermediate node NA1; and an n-channel MOS transistor MN4 having a source terminal coupled to power supply voltage node Vdd and a drain terminal coupled to intermediate node NA2. Transistors MN3 and MN4 are cross-coupled in the following manner: the gate terminal of transistor MN3 is coupled to the drain terminal of transistor MN4 at node NA2, and the gate terminal of transistor MN4 is coupled to the drain terminal of transistor MN3 at node NA1.

[0096] One terminal of the bootstrap capacitor Cbs1 is coupled to the node NA1, and the other terminal is coupled to receive the logical inversion of the clock signal CK, CK1N, generated by the CMOS inverter circuit 306p, which is powered by the positive power supply voltage Vdd and receives the clock signal CK as an input. One terminal of the bootstrap capacitor Cbs2 is coupled to the node NA2, and the other terminal is coupled to receive the logical inversion of the clock signal CKN (which is the logical inversion of the clock signal CK), CK1, generated by the CMOS inverter circuit 308p, which is powered by the positive power supply voltage Vdd and receives the clock signal CKN as an input.

[0097] CMOS switching circuit 310n has a first terminal coupled to receive ground voltage Gnd, a second terminal coupled to receive power supply voltage Vdd, and a third terminal at intermediate node NB1. The source terminal of n-channel MOS transistor MN5 in switching circuit 310n is coupled to the gate terminal of transistor MP1 in CMOS switching circuit 320n (i.e., intermediate node NC2), and the source terminal of p-channel MOS transistor MP3 in switching circuit 310n is coupled to intermediate node NA1 of positive bootstrap circuit 305p. The third terminal is at the common drain of transistors MN5 and MP3, which is connected to the gate terminal of transistor MN1 in CMOS switching circuit 320n. The gate of transistor MN5 is coupled to the first terminal (Gnd), while the gate of transistor MP3 is coupled to the second terminal (Vdd).

[0098] CMOS switching circuit 312n has a first terminal coupled to receive ground voltage Gnd, a second terminal coupled to receive power supply voltage Vdd, and a third terminal at intermediate node NB2. The source terminal of n-channel MOS transistor MN6 in switching circuit 312n is coupled to the gate terminal of transistor MP2 in CMOS switching circuit 322n (i.e., intermediate node NC1), and the source terminal of p-channel MOS transistor MP4 in switching circuit 312n is coupled to intermediate node NA2 of positive bootstrap circuit 305p. The third terminal is located at the common drain of transistors MN6 and MP4. The gate of transistor MN6 is coupled to the first terminal (Gnd), while the gate of transistor MP4 is coupled to the second terminal (Vdd).

[0099] Circuits 310n and 312n with the bootstrap circuit 305p form a bootstrap-based level shift circuit.

[0100] One terminal of capacitor C1 is coupled to node NC1, and the other terminal is coupled to receive the logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 316n, which is powered by positive power supply voltage Vdd and receives clock signal CK1N as an input. One terminal of capacitor C2 is coupled to node NC2, and the other terminal is coupled to receive the logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 318n, which is powered by positive power supply voltage Vdd and receives clock signal CK1 as an input.

[0101] The load 307 of the circuit 300n is schematically represented by a load capacitor Cload having one terminal coupled to the output node 304 and a second terminal coupled to the ground node, and a current source Iload coupled between the output node 304 and a supply voltage Vdd.

[0102] The power supply node 302 is configured to receive a ground voltage Vgnd. The output node 304 is configured to generate a multiplied negative output voltage Vneg, which is approximately -Vdd, using the negative charge pump circuit 300.

[0103] Figure 5B Shown for Figure 5A 300n and the waveforms of the clock signals CK, CKN, CK1, and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, NC1, and NC2 for the operation of the circuit 300n. Note that, in order to facilitate understanding of the operation of the circuit 300n, Figure 5B Signal propagation delays are not shown in the waveforms.It will be further noted that the voltage levels of the clock signals are idealized and in implementation the voltages will be substantially equal (eg, within 1-20%) but not necessarily equal to the ideal ±Vdd and 2*Vdd voltage levels.

[0104] The circuit arrangement formed by transistors MN3 and MN4, bootstrap capacitors Cbs1 and Cbs2, and inverters 306p and 308p is a positive bootstrap circuit that operates in response to clock signals CK and CKN referenced to power supply Vdd and ground to generate clock signals at nodes NA1 and NA2 referenced to 2*Vdd and Vdd. When clock signal CK is at a logic high (Vdd), clock signal CK1N output by inverter 306p will be at a logic low (Gnd). Transistor MN3 is turned on because node NA2 is raised to a voltage level of 2*Vdd by capacitor Cbs2 (i.e., because the gate voltage of transistor MN3 exceeds Vdd by more than Vth at its source terminal, causing it to turn on), and bootstrap capacitor Cbs1 is charged to the Vdd voltage level. In the next phase of the clock signal, clock signal CK is at a logic low, and clock signal CK1N output by inverter 306p is at a logic high. Transistor MN3 is turned off because node NA2 is at the Vdd voltage level (i.e., because the gate voltage of transistor MN1 is equal to the source voltage Vdd and therefore does not exceed Vth and is turned off), and the voltage at node NA1 is raised to the 2*Vdd voltage level by the bootstrap voltage Vdd stored on capacitor Cbs1. A similar process occurs in response to the phase of clock signals CKN and CK1.

[0105] The circuit arrangement formed by capacitors C1, C2 and inverters 316n, 318n operates in response to clock signals CK1 and CK1N referenced to power supply Vdd and ground to generate clock signals at nodes NC1 and NC2 referenced to -Vdd and ground. Consider the following operation related to the circuit having capacitor C2 and inverter 318n: When clock signal CK1 is logic low, the output of inverter 318n is logic high. Simultaneously, as described below, transistor MP2 turns on and capacitor C2 is discharged to ground voltage level. In the next phase of the clock signal, clock signal CK1 is logic high and the output of inverter 318n is logic low. The voltage at node NC2 is raised to -Vdd voltage level by means of capacitor C2. Similar processes occur in the circuit having capacitor C1 and inverter 316n in response to the phase of clock signal CK1N.

[0106] The circuit arrangement formed by CMOS switching circuits 310n and 312n functions as a level shifter, shifting the Vdd and +2*Vdd-referenced clock signals at nodes NA1 and NA2, thereby generating -Vdd and +2*Vdd-referenced clock signals at nodes NB1 and NB2. Consider the following regarding the operation of circuit 312n: When node NA2 is at Vdd, transistor MP4 is turned off (i.e., because the gate voltage of transistor MP4 is equal to the source voltage and therefore does not exceed Vth). Simultaneously, the voltage at node NC1 has been raised to a voltage level of -Vdd via inverter 316n and capacitor C1 in response to the operation of clock CK1N. In this case, transistor MN6 is turned on (i.e., because the gate voltage of transistor MP6 is more than Vth lower than the source terminal), and the voltage at node NB2 is driven to -Vdd. Conversely, when node NA2 is at 2*Vdd, transistor MP4 is on (ie, because the gate voltage of transistor MP4 is more than Vth lower than the source terminal) and the voltage at node NB2 is driven to 2*Vdd. A similar process occurs for circuit 310n.

[0107] The circuit arrangement formed by CMOS switching circuits 320n and 322n functions as a charge transfer driver stage to selectively pass the −Vdd voltage at nodes NC1 and NC2 to output node 304 to drive capacitive and current load 307. Consider the following operation of circuit 322n: When the voltage at node NC2 is at ground Gnd due to transistor MP2 being on, the voltage at node NB2 is at −Vdd. In this case, transistor MN2 is off (i.e., because the gate voltage of transistor MN2 does not exceed Vth). When the voltage at node NC2 rises to −Vdd, the voltage at node NB2 is 2*Vdd, and transistor MN2 is turned on (i.e., Vgs of transistor MN2 exceeds Vth), passing the −Vdd voltage level at node NC2 to output node 304. A similar process occurs for circuit 320n in response to the opposite phase.

[0108] One advantage of the circuit implementation is that when the gate is driven by +2*Vdd, especially in conjunction with the operation of transistors MN1 and MN2, the Vgs of the charge transfer switch transistor is increased to reduce the on-resistance (Rds_on).

[0109] Figure 5C Shown in Figure 5A A more general circuit configuration of a negative charge pump circuit 300n is shown. Circuit 300n is configured to increase the gate-source voltage (Vgs) of charge transfer transistors (switches) MN1 and MN2 to reduce their "on" resistance. A positive voltage bootstrap circuit 305p generates a positive voltage (2*Vdd) at nodes NA1 and NA2. This voltage is selectively switched in response to a clock signal generated by a clock circuit to be applied to the gate terminals of transistors MN1 and MN2 to provide a boost. The gate drive signals for transistors MN1 and MN2 alternate between -Vdd and 2*Vdd under the control of switching circuits 310n and 312n. The boosted voltage of -Vdd is generated at nodes NC1 and NC2 and passes through transistors MN1 and MN2 when their gate terminals are gate biased with a 2*Vdd voltage. The effective Vgs of transistors MN1 and MN2 during the charge transfer phase is correspondingly 3*Vdd, resulting in significantly reduced switch resistance.

[0110] refer to Figure 6A , Figure 6AA circuit diagram of a positive charge pump circuit 400p is shown. Circuit 400p includes an n-channel MOS transistor MN1, whose source terminal is coupled to power supply node 402 and whose drain terminal is coupled to intermediate node NC1; and an n-channel MOS transistor MN2, whose source terminal is coupled to power supply node 402 and whose drain terminal is coupled to intermediate node NC2. Circuit 400p also includes a p-channel MOS transistor MP1, whose source terminal is coupled to output node 404 and whose drain terminal is coupled to node NC1; and a p-channel MOS transistor MP2, whose source terminal is coupled to output node 404 and whose drain terminal is coupled to intermediate node NC2. The gates of transistors MN1 and MP1 are coupled to node ND1, and the gates of transistors MN2 and MP2 are coupled to node ND2. Transistors MN1 and MP1 form CMOS switching circuit 420p, and transistors MN2 and MP2 form CMOS switching circuit 422p.

[0111] Positive charge pump circuit 400p further includes a positive bootstrap circuit 405p, which includes an n-channel MOS transistor MN3 having a source terminal coupled to power supply voltage node Vdd and a drain terminal coupled to intermediate node NA1; and an n-channel MOS transistor MN4 having a source terminal coupled to power supply voltage node Vdd and a drain terminal coupled to intermediate node NA2. Transistors MN3 and MN4 are cross-coupled in the following manner: the gate terminal of transistor MN3 is coupled to the drain terminal of transistor MN4 at node NA2, and the gate terminal of transistor MN4 is coupled to the drain terminal of transistor MN3 at node NA1.

[0112] One terminal of the bootstrap capacitor Cbs1 is coupled to the node NA1, and the other terminal is coupled to receive the logical inversion of the clock signal CK, which is generated by the CMOS inverter circuit 406. The CMOS inverter circuit 406 is powered by the positive power supply voltage Vdd and receives the clock signal CK as an input. One terminal of the bootstrap capacitor Cbs2 is coupled to the node NA2, and the other terminal is coupled to receive the logical inversion of the clock signal CKN (which is the logical inversion of the clock signal CK). The logical inversion CK1 is generated by the CMOS inverter circuit 408. The CMOS inverter circuit 408 is powered by the positive power supply voltage Vdd and receives the clock signal CKN as an input.

[0113] Positive charge pump circuit 400p further includes a negative bootstrap circuit 405n, which includes: a p-channel MOS transistor MP3, whose source terminal is coupled to the ground node and whose drain terminal is coupled to the intermediate node NB1; and a p-channel MOS transistor MP4, whose source terminal is coupled to the ground node and whose drain terminal is coupled to the intermediate node NB2. Transistors MP3 and MP4 are cross-coupled in the following manner: the gate terminal of transistor MP3 is coupled to the drain terminal of transistor MP4 at node NB2, and the gate terminal of transistor MP4 is coupled to the drain terminal of transistor MP3 at node NB1.

[0114] One terminal of the bootstrap capacitor Cbs3 is coupled to the node NB1 and the other terminal is coupled to receive the logical inversion of the clock signal CK generated by the CMOS inverter circuit 406. One terminal of the bootstrap capacitor Cbs4 is coupled to the node NB2 and the other terminal is coupled to receive the logical inversion of the clock signal CKN generated by the CMOS inverter circuit 408.

[0115] CMOS switching circuit 410p has a first terminal coupled to receive a positive power supply voltage Vdd, a second terminal coupled to receive a ground voltage Gnd, and a third terminal at an intermediate node ND1. The source terminal of p-channel MOS transistor MP5 in switching circuit 410p is coupled to node NA1 at the output of positive bootstrap circuit 405p, and the source terminal of n-channel MOS transistor MN5 in switching circuit 410p is coupled to an intermediate node NB1 at the output of negative bootstrap circuit 405n. A third terminal is located at the common drain of transistors MP5 and MN5, which is connected to the gate terminals of transistors MP1 and MN1 in CMOS switching circuit 420p. The gate of transistor MP5 is coupled to the first terminal (Vdd), while the gate of transistor MN5 is coupled to the second terminal (Gnd).

[0116] CMOS switching circuit 412p has a first terminal coupled to receive a positive power supply voltage Vdd, a second terminal coupled to receive a ground voltage Gnd, and a third terminal located at an intermediate node ND2. The source terminal of p-channel MOS transistor MP6 in switching circuit 412p is coupled to node NA2 at the output of positive bootstrap circuit 405p, and the source terminal of n-channel MOS transistor MN6 in switching circuit 412p is coupled to an intermediate node NB2 at the output of negative bootstrap circuit 405n. A third terminal is located at the common drain of transistors MP6 and MN6, which is connected to the gate terminals of transistors MP2 and MN2 in CMOS switching circuit 422p. The gate of transistor MP6 is coupled to the first terminal (Vdd), while the gate of transistor MN6 is coupled to the second terminal (Gnd).

[0117] The circuits 410 p and 412 p with the bootstrap circuits 405 p and 405 n form a bootstrap-based level shifting circuit.

[0118] One terminal of capacitor C1 is coupled to node NC1 and the other terminal is coupled to receive the logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 416p, which is powered by positive power supply voltage Vdd and receives clock signal CK1N as an input. One terminal of capacitor C2 is coupled to node NC2 and the other terminal is coupled to receive the logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 418p, which is powered by positive power supply voltage Vdd and receives clock signal CK1 as an input.

[0119] The load 407 of the circuit 400 p is schematically represented by a load capacitor Cload having one terminal coupled to the output node 404 and a second terminal coupled to a ground node, and a current source Iload coupled between the output node 404 and the ground node.

[0120] The power supply node 402 is configured to receive a positive power supply voltage Vdd. The output node 404 is configured using the positive charge pump circuit 400p to correspondingly generate a multiplied positive output voltage Vpos, where Vpos is approximately 2*Vdd.

[0121] Figure 6B Shown for Figure 6A 4. The waveforms of the clock signals CK, CKN, CK1, and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, ND1, ND2, NC1, and NC2 for the operation of the circuit 400p are shown in FIG. 4. It should be noted that, in order to facilitate understanding of the operation of the circuit 400p, Figure 6B Signal propagation delays are not shown in the waveforms.It will be further noted that the voltage levels of the clock signals are idealized and in implementation the voltages will be substantially equal (eg, within 1-20%) but not necessarily equal to the ideal ±Vdd and 2*Vdd voltage levels.

[0122] The bootstrap-based level shifting circuitry formed by circuits 410p and 412p and bootstrap circuits 405p and 405n operates to generate respective clock signals at nodes ND1 and ND2 that switch between a -Vdd voltage level and a +2*Vdd voltage level. Specifically, positive bootstrap circuit 405p operates to generate clock signals at nodes NA1 and NA2 that switch between a Vdd voltage level and a 2*Vdd voltage level (in a manner described in detail elsewhere herein). Transistors MP5 and MP6 of circuits 410p and 412p, respectively, turn on in response to the 2*Vdd voltage level and pass this voltage to nodes ND1 and ND2. Negative bootstrap circuit 405n operates to generate clock signals at nodes NB1 and NB2 (in a manner described in detail elsewhere herein) that switch between a -Vdd voltage level and a ground voltage level. Transistors MN5 and MN6 of circuits 410p and 412p, respectively, turn on in response to the -Vdd voltage level and pass this voltage to nodes ND1 and ND2.

[0123] The circuit arrangement formed by capacitors C1 and C2 and inverters 416p and 418p operates in response to clock signals CK1 and CK1N referenced to power supply Vdd and ground to generate clock signals at nodes NC1 and NC2 referenced to 2*Vdd and Vdd. Consider the following operation related to the circuit having capacitor C1 and inverter 416p: When clock signal CK1N is logic high, the output of inverter 416p is logic low. Simultaneously, transistor MN1 is turned on by the 2*Vdd voltage level at node ND1, and capacitor C1 is charged to the Vdd voltage level. In the next phase of the clock signal, clock signal CK1N is logic low, and the output of inverter 416p is logic high. The voltage at node NC1 is boosted to the 2*Vdd voltage level by capacitor C1. A similar process occurs for the circuit having capacitor C2 and inverter 318p in response to the phase of clock signal CK1.

[0124] When the voltages at nodes NC1 and NC2 are at the boosted 2*Vdd voltage levels, respectively, charge transfer transistors MP1 and MP2 are responsive to the −Vdd voltage level at nodes ND1 and ND2 , passing this voltage to output node 404 .

[0125] One advantage of the circuit implementation is that when the gate is driven by -Vdd, especially in conjunction with the operation of transistors MP1 and MP2, the Vgs of the charge transfer switch transistor is increased, thereby reducing the on-resistance (Rds_on).

[0126] Figure 6C The Figure 6A1 and 2. A more general circuit configuration of a positive charge pump circuit 400p is shown. Circuit 400p is configured to increase the gate-source voltage (Vgs) of charge transfer transistors (switches) MP1 and MP2 to reduce their "on" resistance. Negative voltage bootstrap circuit 405n generates a negative voltage (-Vdd) at nodes NB1 and NB2, and positive voltage bootstrap circuit 405p generates a positive voltage (2*Vdd) at nodes NA1 and NA2. These voltages are selectively switched in response to a clock signal generated by a clock circuit, thereby being applied to the common gate terminal of transistors MN1, MN2, MP1, and MP2. Specifically, the -Vdd voltage provides a boost for transistors MP1 and MP2. Under the control of switching circuits 410p and 412p, the gate drive signals of transistors MP1 and MP2 alternate between -Vdd and 2*Vdd in response to the clock signal. A boosted voltage of 2*Vdd is generated at nodes NC1 and NC2 and passed by transistors MP1 and MP2 when their gate terminals are gate biased with a -Vdd voltage. The effective Vgs of transistors MP1 and MP2 during the charge transfer phase is accordingly 3*Vdd, which results in a significantly reduced switch resistance.

[0127] refer to Figure 7A , Figure 7A A circuit diagram of a negative charge pump circuit 400n is shown. Circuit 400n includes a p-channel MOS transistor MP1, whose source terminal is coupled to power supply node 402 and whose drain terminal is coupled to intermediate node NC1; and a p-channel MOS transistor MP2, whose source terminal is coupled to power supply node 402 and whose drain terminal is coupled to intermediate node NC2. Circuit 400n also includes an n-channel MOS transistor MN1, whose source terminal is coupled to output node 404 and whose drain terminal is coupled to node NC1; and an n-channel MOS transistor MN2, whose source terminal is coupled to output node 404 and whose drain terminal is coupled to intermediate node NC2. The gates of transistors MN1 and MP1 are coupled to node ND1, and the gates of transistors MN2 and MP2 are coupled to node ND2. Transistors MN1 and MP1 form CMOS switching circuit 420n, and transistors MN2 and MP2 form CMOS switching circuit 422n.

[0128] Negative charge pump circuit 400n further includes a positive bootstrap circuit 405p, which includes an n-channel MOS transistor MN3 having a source terminal coupled to power supply voltage node Vdd and a drain terminal coupled to intermediate node NA1; and an n-channel MOS transistor MN4 having a source terminal coupled to power supply voltage node Vdd and a drain terminal coupled to intermediate node NA2. Transistors MN3 and MN4 are cross-coupled at node NA2 with the gate terminal of transistor MN3 coupled to the drain terminal of transistor MN4 and at node NA1 with the gate terminal of transistor MN4 coupled to the drain terminal of transistor MN3.

[0129] One terminal of the bootstrap capacitor Cbs1 is coupled to the node NA1, and the other terminal is coupled to receive the logical inversion of the clock signal CK, which is generated by the CMOS inverter circuit 406. The CMOS inverter circuit 406 is powered by the positive power supply voltage Vdd and receives the clock signal CK as an input. One terminal of the bootstrap capacitor Cbs2 is coupled to the node NA2, and the other terminal is coupled to receive the logical inversion of the clock signal CKN (which is the logical inversion of the clock signal CK). The logical inversion CK1 is generated by the CMOS inverter circuit 408. The CMOS inverter circuit 408 is powered by the positive power supply voltage Vdd and receives the clock signal CKN as an input.

[0130] Negative charge pump circuit 400n further includes a negative bootstrap circuit 405n, which includes: a p-channel MOS transistor MP3, whose source terminal is coupled to the ground node and whose drain terminal is coupled to the intermediate node NB1; and a p-channel MOS transistor MP4, whose source terminal is coupled to the ground node and whose drain terminal is coupled to the intermediate node NB2. Transistors MP3 and MP4 are cross-coupled in the following manner: the gate terminal of transistor MP3 is coupled to the drain terminal of transistor MP4 at node NB2, and the gate terminal of transistor MP4 is coupled to the drain terminal of transistor MP3 at node NB1.

[0131] One terminal of the bootstrap capacitor Cbs3 is coupled to the node NB1 and the other terminal is coupled to receive the logical inversion of the clock signal CK generated by the CMOS inverter circuit 406. One terminal of the bootstrap capacitor Cbs4 is coupled to the node NB2 and the other terminal is coupled to receive the logical inversion of the clock signal CKN generated by the CMOS inverter circuit 408.

[0132] CMOS switching circuit 410n has a first terminal coupled to receive a positive power supply voltage Vdd, a second terminal coupled to receive a ground voltage Gnd, and a third terminal at an intermediate node ND1. The source terminal of p-channel MOS transistor MP5 in switching circuit 410p is coupled to node NA1 at the output of positive bootstrap circuit 405p, and the source terminal of n-channel MOS transistor MN5 in switching circuit 410p is coupled to an intermediate node NB1 at the output of negative bootstrap circuit 405n. A third terminal is located at the common drain of transistors MP5 and MN5, which is connected to the gate terminals of transistors MP1 and MN1 in CMOS switching circuit 420n. The gate of transistor MP5 is coupled to the first terminal (Vdd), while the gate of transistor MN5 is coupled to the second terminal (Gnd).

[0133] CMOS switching circuit 412n has a first terminal coupled to receive a positive power supply voltage Vdd, a second terminal coupled to receive a ground voltage Gnd, and a third terminal at an intermediate node ND2. The source terminal of p-channel MOS transistor MP6 in switching circuit 412n is coupled to node NA2 at the output of positive bootstrap circuit 405p, and the source terminal of n-channel MOS transistor MN6 in switching circuit 412p is coupled to intermediate node NB2 at the output of negative bootstrap circuit 405n. A third terminal is located at the common drain of transistors MP6 and MN6, which is connected to the gate terminals of transistors MP2 and MN2 in CMOS switching circuit 422n. The gate of transistor MP6 is coupled to the first terminal (Vdd), while the gate of transistor MN6 is coupled to the second terminal (Gnd).

[0134] The circuits 410n and 412n with the bootstrap circuits 405p and 405n form a bootstrap-based level shifting circuit.

[0135] One terminal of capacitor C1 is coupled to node NC1, and the other terminal is coupled to receive the logical inversion of clock signal CK1N, which is generated by CMOS inverter circuit 416n, which is powered by positive power supply voltage Vdd and receives clock signal CK1N as an input. One terminal of capacitor C2 is coupled to node NC2, and the other terminal is coupled to receive the logical inversion of clock signal CK1, which is generated by CMOS inverter circuit 418n, which is powered by positive power supply voltage Vdd and receives clock signal CK1 as an input.

[0136] The load 407 of the circuit 400n is schematically represented by a load capacitor Cload having one terminal coupled to the output node 404 and a second terminal coupled to a ground node, and a current source Iload coupled between the output node 404 and a power supply node Vdd.

[0137] The power supply node 402 is configured to receive a ground voltage Vgnd. The output node 404 is configured using the negative charge pump circuit 400n to generate a multiplied negative output voltage Vneg, where Vneg is approximately -Vdd.

[0138] Figure 7B Shown for Figure 7A 4. The waveforms of the clock signals CK, CKN, CK1, and CK1N and the signals at the nodes NA1, NA2, NB1, NB2, ND1, ND2, NC1, and NC2 for the operation of the circuit 400n are shown in FIG. 4. It should be noted that, in order to facilitate understanding of the operation of the circuit 400n, Figure 7B Signal propagation delays are not shown in the waveforms.It will be further noted that the voltage levels of the clock signals are idealized and in implementation the voltages will be substantially equal (eg, within 1-20%) but not necessarily equal to the ideal ±Vdd and 2*Vdd voltage levels.

[0139] The bootstrap-based level shifting circuitry formed by circuits 410n and 412n and bootstrap circuits 405p and 405n operates to generate respective clock signals at nodes ND1 and ND2 that switch between a -Vdd voltage level and a +2*Vdd voltage level. Specifically, positive bootstrap circuit 405p operates to generate clock signals at nodes NA1 and NA2 that switch between a Vdd voltage level and a 2*Vdd voltage level (in a manner described in detail elsewhere herein). Transistors MP5 and MP6 of circuits 410n and 412n, respectively, turn on in response to the 2*Vdd voltage level and pass this voltage to nodes ND1 and ND2. Negative bootstrap circuit 405n operates to generate clock signals at nodes NB1 and NB2 (in a manner described in detail elsewhere herein) that switch between a -Vdd voltage level and a ground voltage level. Transistors MN5 and MN6 of circuits 410n and 412n, respectively, turn on in response to the -Vdd voltage level and pass this voltage to nodes ND1 and ND2.

[0140] The circuit arrangement formed by capacitors C1, C2 and inverters 416n, 418n operates in response to clock signals CK1 and CK1N referenced to power supply Vdd and ground to generate clock signals at nodes NC1 and NC2 referenced to -Vdd and ground. Consider the following operation related to the circuit having capacitor C1 and inverter 416n: When clock signal CK1N is logic low, the output of inverter 416n is logic high. Simultaneously, transistor MP1 is turned on by the -Vdd voltage level at node ND1, and capacitor C1 is charged to the ground voltage level. In the next phase of the clock signal, clock signal CK1N is logic high, and the output of inverter 416n is logic low. The voltage at node NC1 is raised to the -Vdd voltage level by means of capacitor C1. A similar process occurs for the circuit having capacitor C2 and inverter 418n in response to the phase of clock signal CK1.

[0141] When the voltages at nodes NC1 and NC2 are at the elevated −Vdd voltage level, respectively, charge transfer transistors MN1 and MN2 respond to the +2*Vdd voltage level at nodes ND1 and ND2 to pass that voltage to output node 404 .

[0142] One advantage of the circuit implementation is that when the gate is driven by 2*Vdd, especially in conjunction with the operation of transistors MN1 and MN2, the Vgs of the charge transfer switch transistor is increased to reduce the on-resistance (Rds_on).

[0143] Figure 7C The Figure 7A 4. A more general circuit configuration of a negative charge pump circuit 400n is shown. Circuit 400n is configured to increase the gate-source voltage (Vgs) of charge transfer transistors (switches) MN1 and MN2 to reduce their "on" resistance. Negative voltage bootstrap circuit 405n generates a negative voltage (-Vdd) at nodes NB1 and NB2, and positive voltage bootstrap circuit 405p generates a positive voltage (2*Vdd) at nodes NA1 and NA2. These voltages are selectively switched in response to a clock signal generated by a clock circuit to be applied to the common gate terminal of transistors MN1, MN2, MP1, and MP2. Specifically, the 2*Vdd voltage provides a boost for transistors MN1 and MN2. Under the control of switching circuits 410n and 412n, the gate drive signals of transistors MN1 and MN2 alternate between -Vdd and 2*Vdd in response to the clock signal. When the gate terminals of transistors MN1 and MN2 are gate biased by a 2*Vdd voltage, the boosted voltage of -Vdd generated at nodes NC1 and NC2 is passed by transistors MN1 and MN2. The effective Vgs of transistors MN1 and MN2 during the charge transfer phase is accordingly 3*Vdd, which results in significantly reduced switch resistance.

[0144] The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiments of the present invention. However, various modifications and variations will become apparent to those skilled in the relevant arts in view of the foregoing description when read in conjunction with the accompanying drawings and the appended claims. Nevertheless, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined by the appended claims.

Claims

1. A positive charge pump circuit configured to generate an output voltage from an input voltage, wherein the output voltage has a more positive voltage level than the input voltage, the positive charge pump circuit comprising: a negative bootstrap circuit configured to generate a control signal in response to a first clock signal, wherein the control signal switches between a ground voltage and a negative voltage; a boost circuit configured to generate a positive boost voltage in response to a second clock signal; as well as a charge transfer transistor having a drain terminal coupled to receive the positive boosted voltage and a source terminal coupled to an output node, wherein a gate terminal of the charge transfer transistor is biased by the negative voltage of the control signal to conduct and pass the positive boosted voltage to the output node and generate the output voltage.

2. The positive charge pump circuit of claim 1, wherein the first clock signal is a logical inversion of the second clock signal.

3. The positive charge pump circuit according to claim 1 further includes a level shift circuit, which is configured to receive the control signal and generate a level shift control signal that switches between the level of the positive boost voltage and the level of the negative voltage, and wherein the level shift control signal is applied to the gate terminal of the charge transfer transistor.

4. The positive charge pump circuit according to claim 3 , wherein the level shift circuit comprises: a first MOS transistor of a first conductivity type having a source coupled to receive the control signal; and a second MOS transistor of a second conductivity type having a source coupled to receive a signal at a level of the positive boosted voltage, wherein a common drain of the first MOS transistor and the second MOS transistor is configured to generate the level shift control signal.

5. The positive charge pump circuit of claim 4, wherein the first MOS transistor is gate-biased by a first voltage, and wherein the second MOS transistor is gate-biased by a second voltage, wherein a level of the second voltage is more positive than a level of the first voltage.

6. The positive charge pump circuit according to claim 1 , wherein the boost circuit comprises: a boost transistor having a source terminal coupled to the input voltage and a drain terminal generating the positive boost voltage; a capacitor having a first terminal coupled to the drain terminal of the boost transistor and to the drain terminal of the charge transfer transistor; as well as An inverter circuit has an input coupled to receive the second clock signal and an output coupled to the second terminal of the capacitor.

7. The positive charge pump circuit of claim 1 , wherein the negative bootstrap circuit comprises: a negative bootstrap transistor having a source terminal coupled to the ground voltage and having a drain terminal generating the control signal; a capacitor having a first terminal coupled to the drain terminal of the negative bootstrap transistor; as well as An inverter circuit has an input coupled to receive the first clock signal and an output coupled to the second terminal of the capacitor.

8. A negative charge pump circuit configured to generate an output voltage from an input voltage, wherein a negative voltage level of the output voltage is more negative than a voltage level of the input voltage, the negative charge pump circuit comprising: a positive bootstrap circuit configured to generate a control signal in response to a first clock signal, wherein the control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a boost circuit configured to generate a negative boost voltage in response to a second clock signal; as well as a charge transfer transistor having a drain terminal coupled to receive the negative boosted voltage and a source terminal coupled to an output node, wherein a gate terminal of the charge transfer transistor is biased by the second positive voltage of the control signal to conduct and pass the negative boosted voltage to the output node and generate the output voltage.

9. The negative charge pump circuit of claim 8, wherein the first clock signal is a logical inversion of the second clock signal.

10. The negative charge pump circuit according to claim 8 further includes a level shift circuit, which is configured to receive the control signal and generate a level shift control signal that switches between the level of the negative boost voltage and the level of the second positive voltage, and wherein the level shift control signal is applied to the gate terminal of the charge transfer transistor.

11. The negative charge pump circuit according to claim 10 , wherein the level shift circuit comprises: a first MOS transistor of a first conductivity type having a source coupled to receive the control signal; and a second MOS transistor of a second conductivity type having a source coupled to receive a signal at a level of the negative boosted voltage, wherein a common drain of the first MOS transistor and the second MOS transistor is configured to generate the level shift control signal.

12. The negative charge pump circuit of claim 11, wherein the first MOS transistor is gate-biased by a first voltage, and wherein the second MOS transistor is gate-biased by a second voltage, wherein a level of the first voltage is more positive than a level of the second voltage.

13. The negative charge pump circuit according to claim 8, wherein the boost circuit comprises: a boost transistor having a source terminal coupled to the input voltage and a drain terminal generating the negative boost voltage; a capacitor having a first terminal coupled to the drain terminal of the boost transistor and to the drain terminal of the charge transfer transistor; as well as An inverter circuit has an input coupled to receive the second clock signal and an output coupled to the second terminal of the capacitor.

14. The negative charge pump circuit according to claim 8, wherein the positive bootstrap circuit comprises: a positive bootstrap transistor having a source terminal coupled to the positive supply voltage and having a drain terminal generating the control signal; a capacitor having a first terminal coupled to the drain terminal of the positive bootstrap transistor; as well as An inverter circuit has an input coupled to receive the first clock signal and an output coupled to the second terminal of the capacitor.

15. A positive charge pump circuit configured to generate an output voltage from an input voltage, wherein the output voltage has a more positive voltage level than the input voltage, the positive charge pump circuit comprising: a negative bootstrap circuit configured to generate a first control signal in response to a first clock signal, wherein the first control signal switches between a ground voltage and a negative voltage; a positive bootstrap circuit configured to generate a second control signal in response to the first clock signal, wherein the second control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a boost circuit configured to generate a positive boost voltage at the intermediate node in response to a second clock signal; a first charge transfer transistor having a drain terminal coupled to the intermediate node and a source terminal coupled to receive the input voltage, wherein a gate terminal of the first charge transfer transistor is biased by the second positive voltage of the second control signal to turn on the first charge transfer transistor and pass the input voltage to the intermediate node; as well as a second charge transfer transistor having a drain terminal coupled to the intermediate node and a source terminal coupled to the output node, wherein a gate terminal of the second charge transfer transistor is biased by the negative voltage of the first control signal to turn on the second charge transfer transistor and pass the positive boosted voltage to the output node and generate the output voltage.

16. The positive charge pump circuit of claim 15, wherein the first clock signal is the logical inversion of the second clock signal.

17. A positive charge pump circuit according to claim 15, wherein the gate terminals of the first charge transfer transistor and the second charge transfer transistor are connected to each other to receive a third control signal, wherein the third control signal switches between the negative voltage of the first control signal and the second positive voltage of the second control signal. 18 . The positive charge pump circuit of claim 17 , further comprising a level shift circuit configured to receive the first control signal and the second control signal and generate the third control signal.

19. The positive charge pump circuit of claim 18 , wherein the level shift circuit comprises: a first MOS transistor of a first conductivity type having a source coupled to receive the first control signal; and a second MOS transistor of a second conductivity type having a source coupled to receive the second control signal, wherein a common drain of the first MOS transistor and the second MOS transistor is configured to generate the third control signal.

20. The positive charge pump circuit of claim 19, wherein the first MOS transistor is gate biased by a first voltage, and wherein the second MOS transistor is gate biased by a second voltage, wherein the second voltage is more positive in level than the first voltage.

21. The positive charge pump circuit according to claim 15, wherein the boost circuit comprises: a capacitor having a first terminal coupled to the drain terminal of the first charge transfer transistor and the drain terminal of the second charge transfer transistor; as well as An inverter circuit has an input coupled to receive the second clock signal and an output coupled to the second terminal of the capacitor.

22. The positive charge pump circuit of claim 15, wherein the negative bootstrap circuit comprises: a negative bootstrap transistor having a source terminal coupled to the ground voltage and a drain terminal generating the first control signal; a capacitor having a first terminal coupled to the drain terminal of the negative bootstrap transistor; as well as An inverter circuit has an input coupled to receive the first clock signal and an output coupled to the second terminal of the capacitor.

23. The positive charge pump circuit of claim 15, wherein the positive bootstrap circuit comprises: a positive bootstrap transistor having a source terminal coupled to the input voltage and a drain terminal generating the second control signal; a capacitor having a first terminal coupled to the drain terminal of the positive bootstrap transistor; as well as An inverter circuit has an input coupled to receive the first clock signal and an output coupled to the second terminal of the capacitor.

24. A negative charge pump circuit configured to generate an output voltage from an input voltage, wherein a negative voltage level of the output voltage is more negative than a voltage level of the input voltage, the negative charge pump circuit comprising: a negative bootstrap circuit configured to generate a first control signal in response to a first clock signal, wherein the first control signal switches between a ground voltage and a negative voltage; a positive bootstrap circuit configured to generate a second control signal in response to the first clock signal, wherein the second control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a boost circuit configured to generate a negative boost voltage at the intermediate node in response to a second clock signal; a first charge transfer transistor having a drain terminal coupled to the intermediate node and a source terminal coupled to receive the input voltage, wherein a gate terminal of the first charge transfer transistor is biased by the negative voltage of the first control signal to turn on the first charge transfer transistor and pass the input voltage to the intermediate node; as well as a second charge transfer transistor having a drain terminal coupled to the intermediate node and a source terminal coupled to the output node, wherein a gate terminal of the second charge transfer transistor is biased by the second positive voltage of the second control signal to turn on the second charge transfer transistor and pass the negative boosted voltage to the output node and generate the output voltage.

25. The negative charge pump circuit of claim 24, wherein the first clock signal is the logical inversion of the second clock signal.

26. The negative charge pump circuit of claim 24, wherein the gate terminals of the first charge transfer transistor and the second charge transfer transistor are connected to each other to receive a third control signal, wherein the third control signal switches between the negative voltage of the first control signal and the second positive voltage of the second control signal. 27 . The negative charge pump circuit of claim 26 , further comprising a level shift circuit configured to receive the first control signal and the second control signal and generate the third control signal.

28. The negative charge pump circuit of claim 27, wherein the level shift circuit comprises: a first MOS transistor of a first conductivity type having a source coupled to receive the first control signal; and a second MOS transistor of a second conductivity type having a source coupled to receive the second control signal, wherein a common drain of the first MOS transistor and the second MOS transistor is configured to generate the third control signal.

29. The negative charge pump circuit of claim 28, wherein the first MOS transistor is gate biased by a first voltage, and wherein the second MOS transistor is gate biased by a second voltage, wherein the second voltage is more positive in level than the first voltage.

30. The negative charge pump circuit of claim 24, wherein the voltage boost circuit comprises: a capacitor having a first terminal coupled to the drain terminal of the first charge transfer transistor and the drain terminal of the second charge transfer transistor; as well as An inverter circuit has an input coupled to receive the second clock signal and an output coupled to the second terminal of the capacitor.

31. The negative charge pump circuit of claim 24, wherein the negative bootstrap circuit comprises: a negative bootstrap transistor having a source terminal coupled to the ground voltage and a drain terminal generating the first control signal; a capacitor having a first terminal coupled to the drain terminal of the negative bootstrap transistor; as well as An inverter circuit has an input coupled to receive the first clock signal and an output coupled to the second terminal of the capacitor.

32. The negative charge pump circuit of claim 24, wherein the positive bootstrap circuit comprises: a positive bootstrap transistor having a source terminal coupled to the input voltage and a drain terminal generating the second control signal; a capacitor having a first terminal coupled to the drain terminal of the positive bootstrap transistor; as well as An inverter circuit has an input coupled to receive the first clock signal and an output coupled to the second terminal of the capacitor.

33. A positive charge pump circuit configured to generate an output voltage from an input voltage, wherein the output voltage has a more positive voltage level than the input voltage, the positive charge pump circuit comprising: a negative bootstrap circuit configured to generate a negative voltage in response to a first clock signal; a boost circuit configured to generate a positive boost voltage in response to a second clock signal; a switching circuit coupled to receive the negative voltage from the negative bootstrap circuit and to receive the positive boost voltage from the boost circuit, and configured to switch a control signal between the negative voltage and the positive boost voltage; as well as a charge transfer transistor having a drain terminal coupled to receive the positive boosted voltage and a source terminal coupled to an output node, wherein the control signal is applied to a gate terminal of the charge transfer transistor, wherein the negative voltage of the control signal turns on the charge transfer transistor to pass the positive boosted voltage to the output node and generate the output voltage.

34. A negative charge pump circuit configured to generate an output voltage from an input voltage, wherein a negative voltage level of the output voltage is more negative than a voltage level of the input voltage, the negative charge pump circuit comprising: a positive bootstrap circuit configured to generate a positive voltage in response to a first clock signal; a boost circuit configured to generate a negative boost voltage in response to a second clock signal; a switching circuit coupled to receive the positive voltage from the positive bootstrap circuit and to receive the negative boost voltage from the boost circuit, and configured to switch a control signal between the positive voltage and the negative boost voltage; as well as a charge transfer transistor having a drain terminal coupled to receive the negative boosted voltage and a source terminal coupled to an output node, wherein the control signal is applied to a gate terminal of the charge transfer transistor, wherein the positive voltage of the control signal turns on the charge transfer transistor to pass the negative boosted voltage to the output node and generate the output voltage.

35. A positive charge pump circuit configured to generate an output voltage from an input voltage, wherein the output voltage has a more positive voltage level than the input voltage, the positive charge pump circuit comprising: a negative bootstrap circuit configured to generate a negative voltage in response to a first clock signal; a positive bootstrap circuit configured to generate a positive voltage in response to the first clock signal; a boost circuit configured to generate a positive boost voltage in response to a second clock signal; a switching circuit coupled to receive the negative voltage from the negative bootstrap circuit and to receive the positive voltage from the positive bootstrap circuit and configured to switch a control signal between the negative voltage and the positive voltage; as well as a charge transfer transistor having a drain terminal coupled to receive the positive boosted voltage and a source terminal coupled to an output node, wherein the control signal is applied to a gate terminal of the charge transfer transistor, wherein the negative voltage of the control signal turns on the charge transfer transistor to pass the positive boosted voltage to the output node and generate the output voltage.

36. A negative charge pump circuit configured to generate an output voltage from an input voltage, wherein a negative voltage level of the output voltage is more negative than a voltage level of the input voltage, the negative charge pump circuit comprising: a positive bootstrap circuit configured to generate a positive voltage in response to a first clock signal; a negative bootstrap circuit configured to generate a negative voltage in response to the first clock signal; a boost circuit configured to generate a negative boost voltage in response to a second clock signal; a switching circuit coupled to receive the positive voltage from the positive bootstrap circuit and to receive the negative voltage from the negative bootstrap circuit and configured to switch a control signal between the positive voltage and the negative voltage; as well as a charge transfer transistor having a drain terminal coupled to receive the negative boosted voltage and a source terminal coupled to an output node, wherein the control signal is applied to a gate terminal of the charge transfer transistor, wherein the positive voltage of the control signal turns on the charge transfer transistor to pass the negative boosted voltage to the output node and generate the output voltage.

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