Undefined lifecycle state identifier for managing the security of integrated circuit devices

Abstract

A method and system for managing the security of a system-on-chip (SoC) integrated electronic circuit (IC) device (102) using an undefined lifecycle state identifier is described herein. As part of the technology, the SoC IC device (102) may include a first set of logic integrated electronic circuits (122) that determines that a first bit value combination (312) fails to correspond to a known lifecycle state identifier. The first set of logic integrated electronic circuits (122) may then provide a second bit value combination (402) corresponding to the undefined lifecycle state identifier to a second set of logic integrated electronic circuits (120). The second set of logic integrated electronic circuits (120) may then place the SoC IC device (102) in an undefined lifecycle state (404).

Description

Background Art

[0001] The concept of lifecycle states is used in the integrated circuit (IC) industry to define the functionality of complex devices, such as system-on-chip (SoC) IC devices, which may include, for example, logic integrated electronic circuits, memory integrated electronic circuits, and input / output. Lifecycle states can change over the lifecycle of the SoC IC device and include, for example, a test lifecycle state, a production lifecycle state, and a return lifecycle state. Generally speaking, the logic integrated electronic circuits may control access to information stored by the SoC IC device and the security operations performed by the SoC IC device.

[0002] Generally speaking, an identifier indicating the lifecycle state of a SoC IC device (i.e., a lifecycle state identifier) ​​can be input into the lifecycle state maintenance logic, and the access and / or security level of the SoC IC device can be implemented through the logical behavior of the lifecycle state maintenance logic using the lifecycle state identifier as an input. In order to prevent malicious hacking attacks on the lifecycle state identifier, designers and manufacturers of SoC IC devices have attempted to increase the size of the bit field of the lifecycle state identifier under the premise that it will be more difficult for hackers to change the combination of bit values ​​to the desired lifecycle state. However, the method of increasing the size of the bit field of the lifecycle state identifier has some unintended consequences, including an increase in the number of unknown lifecycle state identifiers, which will: (i) increase the burden on the design engineer team to evaluate and test the logical behavior of the lifecycle state maintenance logic, and (ii) increase the chance of undefined SoC IC device behavior that may lead to security vulnerabilities. Summary of the Invention

[0003] This document describes a method and system for managing the security of a system-on-chip (SoC) integrated circuit (IC) device using an undefined lifecycle state identifier. As part of the technology, the SoC IC device may include a first set of logic integrated electronic circuits that determines that a first bit value combination fails to correspond to a known lifecycle state identifier. The first set of logic integrated electronic circuits may then provide a second bit value combination corresponding to the undefined lifecycle state identifier to a second set of logic integrated electronic circuits. The second set of logic integrated electronic circuits may then place the SoC IC device in an undefined lifecycle state.

[0004] In some aspects, a method performed by a SoC (System on Chip Integrated Circuit) device is described. The method includes retrieving, by a first set of logic integrated electronic circuitry, a first bit value combination from a non-volatile memory storage unit. The first set of logic integrated electronic circuitry determines that the first bit value combination fails to correspond to a known lifecycle state identifier. The first set of logic integrated electronic circuitry then provides a second bit value combination corresponding to an undefined lifecycle state identifier to a second set of logic integrated electronic circuitry. The second set of logic integrated electronic circuitry then places the SoC (System on Chip Integrated Circuit) device into an undefined lifecycle state that prevents undefined SoC IC behavior from leaking data or functionality available through the SoC (System on Chip Integrated Circuit) device.

[0005] In other aspects, a device is described. The device includes a non-volatile memory storage unit and logic integrated electronic circuits, the logic integrated electronic circuits including a first group of logic integrated electronic circuits and a second group of logic integrated electronic circuits. The first group of logic integrated electronic circuits is configured to retrieve a first bit value combination from the non-volatile memory storage unit and determine that the first bit value combination fails to correspond to a known lifecycle state identifier. The first group of logic integrated electronic circuits is further configured to provide a second bit value combination corresponding to an undefined lifecycle state identifier to the second group of logic integrated electronic circuits. The second group of logic integrated electronic circuits is configured to place the device in a secure undefined lifecycle state that prevents undefined device behavior that could result in the disclosure of data or functionality available through the device.

[0006] The details of one or more embodiments are set forth in the accompanying drawings and the following description. Additional features and advantages will be apparent from the description, drawings, and claims. This Summary is provided to introduce the inventive subject matter that will be further described in the Detailed Description. Accordingly, the reader should not interpret this Summary as describing essential technical features, nor as limiting the scope of protection of the inventive subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following describes details of one or more aspects of managing the security of a SoC IC device using an undefined lifecycle state identifier. The same reference numerals are used in different instances in the specification and drawings to represent similar mechanisms:

[0008] Figure 1 An example operating environment is shown that enables aspects of managing security of a SoC IC device using undefined lifecycle state identifiers.

[0009] Figure 2 Example details of one or more lifecycle state identifiers that may be defined by bit value combinations are shown.

[0010] Figure 3 An example scenario is shown in which the state retention logic integrated electronic circuit of a SoC IC device inadvertently compromises the security of the SoC IC device.

[0011] Figure 4 An example scenario showing that the secure logic integrated electronic circuit of the SoC IC device maintains the security of the SoC IC device.

[0012] Figure 5 An example method for managing security of a SoC IC device using an undefined lifecycle state identifier is shown. DETAILED DESCRIPTION

[0013] This document describes a method and system for managing the security of an integrated circuit (IC) device using an undefined lifecycle state identifier. As part of the technology, a SoC IC device may include a first set of logic integrated electronic circuits that determines that a first bit value combination fails to correspond to a known lifecycle state identifier. The first set of logic integrated electronic circuits may then provide a second bit value combination corresponding to the undefined lifecycle state identifier to a second set of logic integrated electronic circuits. The second set of logic integrated electronic circuits may then place the SoC IC device in an undefined lifecycle state.

[0014] In general, the state retention logic integrated electronic circuit can control access to information stored by the SoC IC device and security operations performed by the SoC IC device. In addition, in general, the level of access and security can vary with the life cycle state. As an example, the logical behavior of the SoC IC device in the test life cycle state can enable a test engineer to configure the functions of the SoC IC device, track the manufacturing history of the SoC IC device, or verify the security keys stored in the SoC IC device. After the SoC IC device is produced for a consumer, the logical behavior of the SoC IC device in the production life cycle state can enable the consumer to store, access, or transmit personal information from the SoC IC device. During the return life cycle state of the SoC IC device (sometimes referred to as the return material authorization (RMA) life cycle state), the logical behavior of the SoC IC device can allow a technician to access the debug function of the probing SoC IC device.

[0015] An identifier indicating the lifecycle state of a SoC IC device (i.e., a lifecycle state identifier) ​​can be input into lifecycle state maintenance logic, and access and / or security levels of the SoC IC device can be enforced through the logical behavior of the lifecycle state maintenance logic using the lifecycle state identifier as an input. A known lifecycle state identifier or a specific bit value combination within a bit field can be input into the lifecycle state maintenance logic to "set" the SoC IC device to perform according to intentionally designed (and tested) logical behavior, including allowing a user to access information stored on the SoC IC device or granting a user the ability to execute code using the SoC IC device. However, the complexity of the lifecycle state maintenance logic on SoC IC devices often prevents design engineering teams from considering and testing the impact of lifecycle state identifiers whose bit value combinations may differ from the bit value combinations associated with the determined known lifecycle state identifiers.

[0016] For lifecycle state identifiers that are not considered or tested during the design of the logic integrated electronic circuits of the SoC IC device, the behavior of the lifecycle state maintenance logic is generally unknown and compromises the security of the SoC IC device. Such lifecycle state identifiers (i.e., unknown lifecycle state identifiers) may be introduced through reliability failures that change the bit values ​​in the non-volatile memory storage cells assigned to store the lifecycle state identifiers. In other cases, the unknown lifecycle state identifiers may be maliciously introduced by hackers using various mechanisms. Alternatively, the hacker may simply change the bit values ​​of the non-volatile memory storage cells that store the lifecycle state identifiers in order to set the logic behavior of the SoC IC device to execute in one of many unknown lifecycle states, which may still provide the hacker with access to sensitive information or allow the hacker to instruct the SoC IC device to execute malicious code.

[0017] Generally speaking, the number of unknown lifecycle state identifiers depends on the size of the bit field that can be allocated within the non-volatile memory integrated electronic circuit. For example, a design engineer team can design the state retention logic to have four specific logical behaviors for four specific lifecycle state identifier combinations. However, if the size of the bit field allocated to the lifecycle state identifier is 4 bits, there may be 16 possible combinations of lifecycle state identifiers, leaving 12 unknown lifecycle state identifiers. These 12 unknown lifecycle state identifiers can implement 12 corresponding unknown logical behaviors based on the lifecycle state retention logic. If the size of the bit field allocated to the lifecycle state identifier is 8 bits, there may be 256 combinations of lifecycle state identifiers, leaving 252 unknown lifecycle state identifiers. These 252 unknown lifecycle state identifiers can implement 252 corresponding unknown logical behaviors based on the lifecycle state retention logic.

[0018] Security logic capable of detecting and verifying the lifecycle state of a SoC IC device may be combined with lifecycle state retention logic to address unknown lifecycle state identifiers. Upon determining that a lifecycle state identifier that may be stored in a memory storage unit is unknown, the security logic may provide the undefined lifecycle state identifier to the state retention logic, which in turn protects the security of the SoC IC device.

[0019] While the features and concepts of using undefined lifecycle state identifiers can be implemented in any number of different environments and devices, aspects are described below in the context of example operating environments, example lifecycle state identifier details, example scenarios, example methods, and additional examples.

[0020] Sample operating environment

[0021] Figure 1 An example operating environment 100 is shown that enables the use of undefined lifecycle state identifiers to manage security aspects of a SoC IC device. As shown, a SoC IC device 102 is mounted to a printed circuit board (PCB) 104, which can be included as part of a computing device that implements one or more security protocols. As non-limiting examples, the computing device can be a smartphone 106, a personal digital assistant 108, a tablet computer 110, a laptop computer 112, or a workstation 114.

[0022] The SoC IC device 102 may include logic integrated electronic circuitry 116 and non-volatile memory integrated electronic circuitry 118 fabricated onto a common silicon die. The logic integrated electronic circuitry 116 may include a set of logic integrated electronic circuits (e.g., state-retention logic integrated electronic circuitry 120, which may include logic inputs, AND gates, OR gates, XOR gates, NAND gates, NOR gates, XNOR gates, and NOT gates) that support lifecycle state retention operations performed by the SoC IC device 102. Different binary data combinations (e.g., combinations of bit values ​​such as 1s and 0s) may be input to the state-retention logic integrated electronic circuitry 120 as part of an operating system, wireless communication application, web browsing application, etc., executed by the computing device.

[0023] The logic integrated electronic circuit 116 may also include another set of logic integrated electronic circuits (e.g., a security logic integrated electronic circuit 122 that may include logic inputs, AND gates, OR gates, XOR gates, NAND gates, NOR gates, XNOR gates, and NOR gates) that manage the security of the SoC IC device 102. Different binary data combinations (e.g., combinations of bit values ​​such as 1 and 0) may be input to the security logic integrated electronic circuit 122 as part of the security operations performed by the SoC IC device 102. The security operations may, for example, include detecting a lifecycle state of the SoC IC device 102 and determining whether the detected lifecycle state corresponds to a known lifecycle state or an unknown lifecycle state.

[0024] The non-volatile memory integrated electronic circuit 118 may include memory storage cells that store binary data. Examples of the non-volatile memory integrated electronic circuit 118 include a one-time programmable (OTP) memory integrated electronic circuit, a flash memory integrated electronic circuit (e.g., NAND), a read-only memory integrated electronic circuit (ROM), a ferroelectric random access memory integrated electronic circuit (RAM), or an electronic fuse (e-fuse). In some cases, a portion of the memory storage cells within the non-volatile memory integrated electronic circuit 118 (e.g., the lifecycle state identifier cell 124) may be dedicated to storing a bit field containing a bit value combination corresponding to the lifecycle state of the SoC IC device 102.

[0025] In some cases, a team of design engineers may design the logic integrated electronic circuit 116 and the non-volatile memory integrated electronic circuit 118 to jointly perform operations for managing the security of the SoC IC device 102. As an example, the security logic integrated electronic circuit 122 may be designed to retrieve a first bit value combination from the lifecycle state identifier unit 124. The security logic integrated electronic circuit 122 may be designed to determine that the first bit value combination fails to decode into a known lifecycle state identifier (e.g., if input to the state retention logic integrated electronic circuit 120, the bit value combination would cause the state retention logic integrated electronic circuit 120 to perform according to known logical behavior for a given lifecycle state).

[0026] In the event that the first bit value combination fails to decode into a known lifecycle state identifier, the security logic integrated electronic circuit 122 may provide a second bit value combination corresponding to an undefined lifecycle state to the state retention logic integrated electronic circuit 120. The state retention logic integrated electronic circuit 120 may be designed such that upon receiving the second bit value combination corresponding to the undefined lifecycle state, the state retention logic integrated electronic circuit 120 places the SoC IC device 102 in the undefined lifecycle state. In the undefined lifecycle state, the SoC IC device 102 is secure, thereby preventing unauthorized agents (e.g., malicious hackers) from accessing the SoC IC device 102. Preventing unauthorized agents from accessing the SoC IC device 102 may prevent the leakage of sensitive information, the execution of non-secure code, and the like.

[0027] Although the SoC IC device 102 is described in the context of a single SoC IC device that includes both the logic integrated electronic circuit 116 and the non-volatile memory integrated electronic circuit 118, a combination of discrete IC devices can also perform the same functions. For example, a discrete processor IC device (e.g., a processor IC device having one or both of the state-retention logic integrated electronic circuit 120 and the security logic integrated electronic circuit 122) can cooperate with a discrete non-volatile memory IC device having the lifecycle state identifier unit 124 to perform one or more functions described herein. In addition, a memory IC device can include volatile memory storage cells (such as dynamic random access memory (DRAM) storage cells) as opposed to non-volatile memory storage cells.

[0028] Example lifecycle state identifier details

[0029] Figure 2 2 shows an example detail of one or more life cycle state identifiers that can be defined by a combination of bit values. The lookup table 202 includes a bit field having a size of four bits, which can be used to evaluate a SoC IC device (e.g., Figure 1In some cases, portions of the lookup table 202 (e.g., bit fields corresponding to known states, unknown lifecycle states, and / or combinations thereof) may be stored in a non-volatile memory integrated electronic circuit (e.g., Figure 1 Some portions of the lookup table 202 (e.g., bit fields corresponding to known lifecycle states, unknown lifecycle states, and / or combinations thereof) may also be partially or fully stored in logic registers (e.g., Figure 1 The logic integrated electronic circuit 116 of the SoC IC device 102 in the embodiment includes a state retention logic integrated electronic circuit 120 and / or a security logic integrated electronic circuit 122) or another type of memory integrated electronic circuit (for example, a DRAM memory integrated electronic circuit, which can be part of a computing device having the SoC IC device 102).

[0030] As shown, the size of the bit field allows for up to 16 bit value combinations (e.g., life cycle states). In the lookup table 202, bit value combinations #1, #3, #4, #6, #7, #9, #10, #11, #13, and #16 correspond to unknown life cycle states (e.g., if bit value combinations #1, #3, #4, #6, #7, #9, #10, #11, #13, or #16 are input to a set of state-keeping logic integrated electronic circuits, such as Figure 1 If the state retention logic integrated electronic circuit 120 in the SoC IC device 102 is not maintained, the safety condition of the SoC IC device 102 may be compromised).

[0031] Another example Figure 2 As shown, bit value combination #2 corresponds to the test life cycle state, bit value combination #5 corresponds to the production life cycle state, bit value combination #8 corresponds to the debug life cycle state, bit value combination #14 corresponds to the RMA life cycle state, and bit value combination #15 corresponds to the recovery life cycle state. Each of these bit value combinations corresponds to a known life cycle state and a corresponding safety condition (for example, if bit value combination #2, #5, #8, #14, or #15 is input to a set of state-retention logic integrated electronic circuits, such as Figure 1 The state retention logic integrated electronic circuit 120 in the Figure 1 The corresponding security conditions implemented by the SoC IC device 102 in will be changed accordingly).

[0032] In addition, if Figure 2 As shown, bit value combination #12 corresponds to an undefined lifecycle state and an undefined safety condition (e.g., if bit value combination #12 is input to a set of state-retaining logic integrated electronic circuits, such as Figure 1 The state retention logic integrated electronic circuit 120 in the Figure 1 The security conditions implemented by the SoC IC device 102 in will correspond to undefined security conditions that prevent unauthorized agents from accessing the SoC IC device 102).

[0033] Generally speaking, a design engineer may deploy the first portion of the logic of a SoC IC device (e.g., Figure 1 The secure logic integrated electronic circuit 122 in the SoC IC device can verify that the input bit value combination is decoded as a bit value combination of a valid life cycle state by comparing the retrieved bit value combination with the stored available bit value combinations corresponding to the known life cycle state and / or the unknown life cycle state. In the event that the bit value combination is decoded as a valid life cycle state, the bit value combination can be input to the second portion of the logic integrated electronic circuit of the SoC IC device (for example, after verifying that the bit value combination is decoded as a valid life cycle state, Figure 1 The secure logic integrated electronic circuit 122 in the Figure 1 The state retention logic integrated electronic circuit 120 in the device is used to implement the corresponding security level.

[0034] However, in the event that the bit value combination does not decode to a valid lifecycle state, the first portion of the logic integrated electronic circuit may further decode the bit value combination by passing another bit value combination corresponding to the undefined lifecycle state to the second portion of the logic integrated electronic circuit (e.g., Figure 1 The secure logic integrated electronic circuit 122 in the embodiment may pass a bit value combination corresponding to an undefined life cycle state to the Figure 1 In this case, the second part of the logic integrated electronic circuit (eg, Figure 1 The state retention logic integrated electronic circuit 120 in the SoC IC device (eg, Figure 1 The SoC IC device 102 in the embodiment of the present invention is placed in an undefined lifecycle state, in which the SoC IC device is secure and access to the SoC IC device is restricted. In some cases, transitioning from the undefined lifecycle state to another lifecycle state with a different degree of security (e.g., the RMA lifecycle state) may require a first portion of the logic integrated electronic circuit (e.g., Figure 1 The safety logic integrated electronic circuit 1221 in the embodiment and / or the second part of the logic (e.g., Figure 1 The state-holding logic integrated electronic circuit 120 in the system provides an authorization message to enable the conversion.

[0035] Example scenario

[0036] Figure 3 An example scenario 300 is shown in which the state retention logic integrated electronic circuit of a SoC IC device inadvertently compromises the security of the SoC IC device. In some cases, the state retention logic integrated electronic circuit may be Figure 1 The state retention logic integrated electronic circuit 120 in the.

[0037] like Figure 3 As shown, compared to transitioning from the test lifecycle state 302 (e.g., corresponding to the test lifecycle state identifier 304 having one bit value combination) to the RMA lifecycle state 306 (e.g., corresponding to the RMA lifecycle state identifier 308 having another bit value combination), the SoC IC device (e.g., Figure 1 The SoC IC device 102 in FIG. 1 has transitioned to an unknown lifecycle state 310 (e.g., corresponding to an unknown lifecycle state identifier 312 having another bit value combination). In some cases, the SoC IC device may be subject to a physical attack that destroys a memory cell of the non-volatile memory integrated electronic circuit that stores a bit field containing a bit value combination (e.g., Figure 1 Examples of physical attacks include sabotaging the power supply of the SoC IC device, introducing glitches into the clock mechanism of the SoC IC device, or laser flaw detection of the memory cells of the non-volatile memory integrated electronic circuit of the SoC IC device. In other cases, the SoC IC device may experience reliability failures within the memory cells of the non-volatile memory integrated electronic circuit.

[0038] exist Figure 3 In the scenario shown, there is no safety logic integrated electronic circuit (e.g. Figure 1In the absence of the security logic integrated electronic circuit, the state retention logic integrated electronic circuit 120 retrieves an unknown bit value combination (e.g., corresponding to the unknown lifecycle state identifier 312) from a cell of the non-volatile memory integrated electronic circuit. Because the state retention logic integrated electronic circuit 120 has not been designed or tested for the unknown lifecycle state identifier 312, the unknown lifecycle state retention logic behavior results, which causes the state retention logic integrated electronic circuit 120 to inadvertently place the SoC IC device in an unknown lifecycle state 310 with a compromised security condition 314. When the SoC IC device is in the unknown lifecycle state 310 with the compromised security condition 314, the unknown behavior of the state retention logic integrated electronic circuit 120 may enable an unauthorized agent 316 (e.g., a malicious hacker remote from the SoC IC device, a user prohibited from the SoC IC device, spyware, etc.) to obtain stored information, instruct the SoC IC device to execute non-secure code, etc.

[0039] Figure 4 An example scenario 400 is shown in which a secure logic integrated electronic circuit of a SoC IC device maintains the security of the SoC IC device. In some cases, the secure logic integrated electronic circuit may be Figure 1 The security logic integrated electronic circuit 122 in the embodiment of the present invention and in some cases, the state retention logic integrated electronic circuit may be Figure 1 The state retention logic integrated electronic circuit 120 in the.

[0040] like Figure 4 As shown, compared to transitioning from the test lifecycle state 302 (e.g., corresponding to the test lifecycle state identifier 304 having one bit value combination) to the RMA lifecycle state 306 (e.g., corresponding to the RMA lifecycle state identifier 308 having another bit value combination), the SoC IC device (e.g., Figure 1 The SoC IC device 102 in FIG. 1 has transitioned to an unknown lifecycle state 310 (e.g., corresponding to an unknown lifecycle state identifier 312 having another bit value combination). In some cases, the SoC IC device may be subject to a physical attack that destroys a memory cell of the non-volatile memory integrated electronic circuit that stores a bit field containing a bit value combination (e.g., Figure 1Examples of physical attacks include sabotaging the power supply to the SoC IC device, introducing glitches into the clock mechanism of the SoC IC device, or laser flaw detection of the memory cells of the non-volatile memory integrated electronic circuit of the SoC IC device. In other cases, the SoC IC device may experience reliability failures within the memory cells of the non-volatile memory integrated electronic circuit.

[0041] However, with Figure 3 In contrast, there is a secure logic integrated electronic circuit 122 on the SoC IC device. Figure 4 As shown, the secure logic integrated electronic circuit 122 (as compared to the state retention logic integrated electronic circuit 120) retrieves a bit value combination (e.g., corresponding to the unknown lifecycle state identifier 312) from a memory storage unit of the non-volatile memory integrated electronic circuit. In some cases, the secure logic integrated electronic circuit 122 may determine that the retrieved bit value combination fails to match a known lifecycle state identifier (e.g., the retrieved bit value combination fails to match a known lifecycle state identifier such as Figure 2 Alternatively, the secure logic integrated electronic circuit 122 may determine that the retrieved bit value combination matches a predetermined unknown lifecycle state identifier (e.g., the retrieved bit value combination matches a predetermined unknown lifecycle state identifier such as Figure 2 bit value combination #10 shown in the lookup table 202).

[0042] The safety logic integrated electronic circuit 122 may include a combination of one or more logic comparators formed from logic inputs, AND gates, OR gates, XOR gates, NAND gates, NOR gates, XNOR gates, and / or NOR gates. Additionally, in some cases, the safety logic integrated electronic circuit 122 may perform operations including obtaining a comparison from a lookup table (e.g., Figure 2 The operation of retrieving one or more bit value combinations from the lookup table 202 in the example.

[0043] In some cases, the secure logic integrated electronic circuit 122 may retrieve a bit value combination (e.g., corresponding to the unknown lifecycle state identifier 312) from the memory storage unit when the SoC IC device experiences a power-up condition or a reset condition. Alternatively, the secure logic integrated electronic circuit 122 may retrieve the value combination from the memory storage unit at a regular, continuous rhythm during operation of the SoC IC device, thereby continuously monitoring the lifecycle state of the SoC IC device.

[0044] In response to determining that the bit value combination fails to correspond to a known lifecycle state identifier (e.g., the retrieved bit value combination fails to correspond to the RMA lifecycle state identifier 308), the secure logic integrated electronic circuit 122 provides the undefined lifecycle state identifier 402 (e.g., the bit value combination corresponding to the undefined lifecycle state 404) to the state retention logic integrated electronic circuit 120. The secure logic integrated electronic circuit 122 may also provide the undefined lifecycle state identifier 402 to a unit of the non-volatile memory integrated electronic circuit (e.g., an overwrite Figure 1 to ensure that subsequent queries of the cells of the non-volatile memory integrated electronic circuit (by the state retention logic integrated electronic circuit 120, the security logic integrated electronic circuit 122, or other logic integrated electronic circuits of the IC device) will return a valid (e.g., current) lifecycle state identifier.

[0045] In response, the state retention logic integrated electronic circuit 120 places the SoC IC device in an undefined lifecycle state 404 having a secure security condition 406. When the SoC IC device is in the undefined lifecycle state 404, the SoC IC device may have limited functionality for security purposes (e.g., functionality of the SoC IC device may be limited to authenticated access permissions). Generally speaking, when in the undefined lifecycle state 404, the state retention logic integrated electronic circuit 120 may prevent the SoC IC device from engaging in undefined behavior that could potentially leak data or functionality available through the SoC IC device.

[0046] The secure logic integrated electronic circuit 122 can be designed to allow an authorized agent 408 (e.g., a technician, a security agent with authorization or permission) to generate an authorization message 410 and trigger a transition to a subsequent lifecycle state. For example, when the SoC IC device is in the undefined lifecycle state 404, the authorized agent 408 can provide the secure logic integrated electronic circuit 122 with the authorization message 410. The authorization message 410 can include, for example, a cryptographic signature, a message authentication code (MAC), or a password. In such a case, the secure logic integrated electronic circuit 122 can verify the content of the authorization message 410.

[0047] After verifying the content of the authorization message 410, the secure logic integrated electronic circuit 122 may provide a recovery lifecycle state identifier 412 (e.g., Figure 2The recovery lifecycle state identifier 412 causes the state retention logic integrated electronic circuit 120 to place the SoC IC device in a subsequent lifecycle state (e.g., the recovery lifecycle state 414). The recovery lifecycle state 414 can be secure, thereby protecting the security of the SoC IC device while allowing diagnosis and / or testing of the SoC IC device. However, while the SoC IC device is in the recovery lifecycle state 414, the state retention logic integrated electronic circuit 120 can prevent code execution.

[0048] Example method using an undefined lifecycle state identifier

[0049] Figure 5 Details of an example method 500 for managing security of a SoC IC device using an undefined lifecycle state identifier are shown. The method illustrated by a series of operation blocks 502 to 508 may be performed by Figure 1 The method may also include performing one or more elements of the SoC IC device 102. Figures 2 to 4 The order of operation blocks 502 to 508 (including the basic or specific elements of operation blocks 502 to 508) is not limited to Figure 5 The diagram or the following Figure 5 Operation blocks 502 to 508 or portions of operation blocks 502 to 508 may also be performed by a combination of one or more discrete IC devices having integrated electronic circuits similar to those included on the SoC IC device 102 .

[0050] At block 502, a first set of logic integrated electronic circuits (e.g., Figure 1 The secure logic integrated electronic circuit 122 in the SoC IC device) is stored in a non-volatile memory unit (e.g., Figure 1 The life cycle state identifier unit 124 in the embodiment of the present invention) retrieves a first bit value combination (e.g., corresponding to Figure 3 In some cases, the first set of logic integrated electronic circuitry may retrieve the first bit value combination in response to a power-up or reset condition experienced by the SoC IC device. In other cases, the first set of logic integrated electronic circuitry may retrieve the first bit value combination from a memory storage unit of the SoC IC device at a repeated, predetermined cadence during operation of the SoC IC device.

[0051] At block 504, the first set of logic integrated electronic circuits determines that the first bit value combination fails to correspond to a known lifecycle state identifier. In some cases, determining that the first bit value combination fails to correspond to a known lifecycle state identifier may include comparing the first bit value combination to one or more bit value combinations retrieved from a lookup table.

[0052] At block 506, the first set of logic integrated electronic circuits sends data to the second set of logic integrated electronic circuits (eg, Figure 1 The state retention logic integrated electronic circuit 120 in the embodiment provides a second bit value combination (eg, corresponding to Figure 4 Furthermore, in some cases, the first group of logic integrated electronic circuits may provide the second bit value combination to the non-volatile memory storage unit (e.g., "overwriting" the first bit value combination within the non-volatile memory storage unit with the second bit value combination to ensure that queries of the non-volatile memory storage unit return a valid life cycle state).

[0053] At block 508, the second set of logic integrated electronic circuitry places the SoC IC device in an undefined lifecycle state in which the SoC IC device is secure. While in the undefined lifecycle state, the second set of logic integrated electronic circuitry prevents unauthorized agents from accessing data or functionality available through the SoC IC device.

[0054] Method 500 may be expanded to include additional operations. For example, after being placed in an undefined lifecycle state, the first set of logical integrated electronic circuits may receive an authorization message (e.g., Figure 4 The first set of logic may decrypt the key to determine that the external agent is an authorized external agent. The first set of logic integrated electronic circuitry may then provide a third bit value combination (e.g., corresponding to Figure 4 In response, the second set of logic integrated electronic circuitry may place the SoC IC device in a recovery lifecycle state in which the SoC IC device is secure, wherein testing or diagnosis of the SoC IC device is permitted (while preventing access to data or functionality available through the SoC IC device).

[0055] Although techniques for managing the security of integrated circuit (IC) devices using undefined lifecycle state identifiers are presented herein, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example approaches that can implement the security of integrated circuit (IC) devices using undefined lifecycle state identifiers.

[0056] Additional Examples

[0057] Several examples are described in the following paragraphs:

[0058] In one example, a method performed by a SoC IC device is provided. The method may include: retrieving, by a first set of logic integrated electronic circuitry of the SoC IC device, a first bit value combination from a non-volatile memory storage unit of the SoC IC device; determining, by the first set of logic integrated electronic circuitry, that the first bit value combination fails to correspond to a known lifecycle state identifier; providing, by the first set of logic integrated electronic circuitry, a second bit value combination to a second set of logic integrated electronic circuitry of the SoC IC device, the second bit value combination corresponding to an undefined lifecycle state identifier; and placing, by the second set of logic integrated electronic circuitry, the SoC IC device in an undefined lifecycle state in which the SoC IC device is secure, the undefined lifecycle state preventing undefined behavior of the SoC IC device that results in disclosure of data or functionality available through the SoC IC device.

[0059] The first set of logic integrated electronic circuits may retrieve a first bit value combination in response to the SoC IC device experiencing a power-up condition.

[0060] The first set of logic integrated electronic circuits may retrieve a first bit value combination in response to the SoC IC device experiencing a reset condition.

[0061] The first set of logic integrated electronic circuits retrieves a first bit value combination at a repetitive predetermined cadence during operation of the SoC IC device.

[0062] Determining that the first bit value combination fails to correspond to a known lifecycle state identifier may include comparing the first bit value combination to one or more bit combinations retrieved from a lookup table.

[0063] An authorization message may be received by a first set of logic integrated electronic circuitry from an external agent. The first set of logic integrated electronic circuitry may verify the contents of the authorization message and provide a third bit value combination corresponding to a recovery lifecycle state identifier to a second set of logic integrated electronic circuitry. The second set of logic integrated electronic circuitry may place the system-on-chip integrated circuit device into a recovery lifecycle state in which the system-on-chip integrated circuit device is secure, the recovery lifecycle state allowing testing or diagnosis of the system-on-chip integrated circuit device while preventing access to data or functionality available through the system-on-chip integrated circuit device.

[0064] Verifying the content of the authorization message may include verifying an encrypted signature or a message authentication code.

[0065] The content of the verification authorization message may include: a verification password.

[0066] The first set of logic integrated electronic circuits may provide a second bit value combination to the non-volatile memory storage cell.

[0067] In another example, one or more computer-readable media are provided, carrying instructions configured to cause a computer device to perform the method of the above examples or any method described herein.

[0068] In another example described herein, an apparatus is provided that is configured to perform the method of the above example or any method described herein. For example, the apparatus may include: a non-volatile memory storage unit; and logic integrated electronic circuitry, the logic integrated electronic circuitry including a first set of logic integrated electronic circuitry and a second set of logic integrated electronic circuitry, the logic integrated electronic circuitry configured to: retrieve a first bit value combination from the non-volatile memory storage unit using the first set of logic integrated electronic circuitry; determine using the first set of logic integrated electronic circuitry that the first bit value combination fails to correspond to a known lifecycle state identifier; provide a second bit value combination to the second set of logic integrated electronic circuitry using the first set of logic integrated electronic circuitry, the second bit value combination corresponding to an undefined lifecycle state identifier; and place the apparatus in an undefined lifecycle state using the second set of logic integrated electronic circuitry, the undefined lifecycle state preventing undefined behavior of the apparatus that results in disclosure of data or functionality available through the apparatus.

[0069] The non-volatile memory storage cells may include one-time programmable cells.

[0070] The first logic electronic circuit and the second logic electronic circuit may each include a respective logic input.

[0071] The first set of logic integrated electronic circuits may include one or more comparators.

[0072] The apparatus may include a SoC IC device having a first set of logic integrated electronic circuits, a non-volatile memory storage unit, and a second set of logic integrated electronic circuits.

[0073] In some examples, at least one of the first group of logic integrated electronic circuits, the non-volatile memory storage cells, or the second group of logic integrated electronic circuits is part of a discrete integrated circuit device that does not include each of the first group of logic integrated electronic circuits, the non-volatile memory storage cells, and the second group of logic integrated electronic circuits.

Claims

1. A method performed by a system-on-chip integrated circuit device, the method comprising: retrieving, by a first set of logic integrated electronic circuits of the system-on-chip integrated circuit device, a first bit value combination from a non-volatile memory storage unit of the system-on-chip integrated circuit device; determining, by the first set of logical integrated electronic circuits, that the first bit value combination fails to correspond to a known lifecycle state identifier; providing, by the first group of logic integrated electronic circuits, a second bit value combination to a second group of logic integrated electronic circuits of the system-on-chip integrated circuit device, the second bit value combination corresponding to an undefined lifecycle state identifier; as well as The system-on-chip integrated circuit device is placed into an undefined lifecycle state by the second set of logic integrated electronic circuits, wherein the system-on-chip integrated circuit device is secure in the undefined lifecycle state, wherein the undefined lifecycle state prevents undefined behavior of the system-on-chip integrated circuit device that results in leakage of data or functionality available through the system-on-chip integrated circuit device.

2. The method according to claim 1, wherein The first set of logic integrated electronic circuits retrieves the first bit value combination in response to the system on chip integrated circuit device experiencing a power-up condition.

3. The method according to claim 1, wherein The first set of logic integrated electronic circuits retrieves the first bit value combination in response to the system on chip integrated circuit device experiencing a reset condition.

4. The method according to claim 1, wherein The first set of logic integrated electronic circuits retrieves the first bit value combination at a repetitive predetermined cadence during operation of the system-on-chip integrated circuit device.

5. The method according to claim 1, wherein Determining that the first bit value combination fails to correspond to a known lifecycle state identifier includes comparing the first bit value combination to one or more bit combinations retrieved from a lookup table.

6. The method according to claim 1, further comprising: receiving, by said first set of logical integrated electronic circuits, an authorization message from an external agent; verifying, by the first set of logic integrated electronic circuits, the content of the authorization message; providing, by the first group of logic integrated electronic circuits, to the second group of logic integrated electronic circuits, a third bit value combination corresponding to a restore lifecycle state identifier; and The system-on-chip integrated circuit device is placed into a recovery lifecycle state by the second set of logic integrated electronic circuits, in which the system-on-chip integrated circuit device is secure, and the recovery lifecycle state allows testing or diagnosis of the system-on-chip integrated circuit device while preventing access to data or functions available through the system-on-chip integrated circuit device.

7. The method according to claim 6, wherein: Verifying the content of the authorization message includes verifying an encrypted signature or a message authentication code.

8. The method according to claim 6, wherein: Verifying the content of the authorization message includes: verifying the password.

9. The method according to any one of claims 1 to 8, further comprising: The second bit value combination is provided to the non-volatile memory storage unit by the first group of logic integrated electronic circuits.

10. An apparatus for managing security of a system-on-chip integrated circuit device using an undefined lifecycle state identifier, comprising: a non-volatile memory storage unit; as well as A logic integrated electronic circuit, comprising a first group of logic integrated electronic circuits and a second group of logic integrated electronic circuits, wherein the logic integrated electronic circuits are configured to: retrieving a first bit value combination from said non-volatile memory storage unit using said first set of logic integrated electronic circuits; determining, using the first set of logical integrated electronic circuits, that the first bit value combination fails to correspond to a known lifecycle state identifier; providing a second bit value combination to the second group of logic integrated electronic circuits using the first group of logic integrated electronic circuits, the second bit value combination corresponding to an undefined lifecycle state identifier; as well as The device is placed into an undefined lifecycle state using the second set of logic integrated electronic circuits, wherein the device is secure in the undefined lifecycle state, the undefined lifecycle state preventing undefined behavior of the device that results in disclosure of data or functionality available through the device.

11. The device according to claim 10, wherein The non-volatile memory storage cells include one-time programmable cells.

12. The device according to claim 10, wherein The first group of logic integrated electronic circuits and the second group of logic integrated electronic circuits each include a respective logic input.

13. The device according to claim 10, wherein The first set of logic integrated electronic circuits includes one or more comparators.

14. The device according to claim 10, wherein The apparatus includes a system-on-chip integrated circuit device having the first set of logic integrated electronic circuits, the non-volatile memory storage cells, and the second set of logic integrated electronic circuits.

15. The device according to any one of claims 10 to 14, wherein At least one of the first group of logic integrated electronic circuits, the non-volatile memory storage cells, or the second group of logic integrated electronic circuits is part of a discrete integrated circuit device that does not include each of the first group of logic integrated electronic circuits, the non-volatile memory storage cells, and the second group of logic integrated electronic circuits.

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