A multi-input neuron circuit for spiking neural networks

Abstract

The present invention claims a multi-input neuron circuit for a pulse neural network, belonging to the field of integrated circuit design. The circuit mainly includes: an input circuit, a reset circuit, a leakage circuit, a state judgment circuit and an action potential generating circuit. The present invention realizes three dynamic response modes of the LIF (Leaky Integrate and Fire) model, namely, tonic spiking (TS), class 1 excitability (Class 1 Excitability), and an integrator, and does not require additional digital circuit assistance, and adds a refractory period design on the basis of the LIF model to make the neuron function closer to the working mechanism of biological neurons. Among them, the neuron circuit input is divided into excitatory input and inhibitory input, and a multi-input design is added to the input end, so that the neuron circuit can be connected to multiple neuron circuits, which is closer to the connection mode between biological neurons.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a multi-input neuron circuit for a pulse neural network. Background Art

[0002] Artificial neural network (ANN) is an abstraction and simulation of the structure and function of biological nervous system, and plays an important role in information processing and pattern recognition. Traditional ANN uses the pulse firing frequency of biological neurons to encode information, and the output of neurons is generally expressed as a simulated quantity in a given interval. However, the biological nervous system responds to various changes in the internal and external environment of the organism in the form of a neuron firing pulse sequence, and more and more neuroscience research results show the importance of encoding and processing neural information based on precise pulse timing. Spiking neural network (SNN) is composed of basic units of a more biologically interpretable spiking neuron model, and uses pulse sequences to represent and process information. This encoding method integrates multiple aspects of information, such as time, space, frequency, and phase. As a new generation of artificial neural network computing model, spiking neural network has more powerful computing power than traditional artificial neural networks based on pulse frequency encoding information. It can simulate various neural signals and arbitrary continuous functions, which is very suitable for the processing of brain neural signals and is an effective tool for complex spatiotemporal information processing. The basic unit of the spiking neural network - the spiking neuron - emits a pulse at a specific point in time, which is then transmitted to the next neuron through the axon of the neuron. The size and shape of the pulse have nothing to do with the input of the neuron, but the time when the neuron emits the pulse depends on the input of the neuron.

[0003] There are three common spiking neuron models: the Hodgkin-Huxley (HH) model, the Izhikevich model, and the Leaky Integrate-and-Fire (LIF) model. The HH model is too complex and has too many dynamic variables, making it difficult to analyze the behavior of each variable and the relationship between variables. The Izhikevich model is based on the theory of dynamic systems and claims to have almost the same degree of biological rationality as the HH model. It also has a certain degree of computational simplicity and can simulate a variety of neuronal behaviors by adjusting parameters. The LIF model has a simple structure and depicts the discharge activity of neurons in the cerebral cortex. Although the neuronal behaviors that can be simulated are limited, the required simulation time is short and the computational efficiency is high, making it suitable for integrating large-scale neural networks. For various neuron models, the more complex the model, the more neuron behaviors that can be simulated, and the more accurately biological neurons can be simulated, but more complex circuits are required to achieve these neuron behaviors. Therefore, a trade-off needs to be made between the richness of biological features and the power consumption and area cost of neuron circuits.

[0004] The present invention provides a method for realizing a multi-input neuron circuit for a pulse neural network, which uses a LIF model to simulate neuron characteristics, meets the three dynamic response modes of the LIF model - tonic spiking, class 1 excitability, and integrator, and does not require additional digital circuit assistance. In addition, a refractory period design is added on the basis of the LIF model to make the neuron function closer to the working mechanism of biological neurons, and the refractory period is adjustable to make the neuron pulse emission frequency adjustable, so that the neuron circuit has adjustability when applied. For the previously applied patent - a pulse neural network neuron circuit based on the LIF (Leaky Integrate and Fire) model, its input is a given current source, and the input state is ideal. In actual applications, multiple neuron circuits need to be connected to each other through synaptic circuits that simulate biological synapses. The input end of the neuron circuit proposed in this patent is not connected to the synaptic circuit, which lacks applicability. This patent changes the input method of the neuron circuit, changing the current input to voltage input, which can directly match the synaptic circuit, and divides the neuron circuit input into excitatory input and inhibitory input, which is in line with the input mechanism of biological neurons, and adds a multi-input design, so that the neuron circuit can be connected through multiple synaptic circuits and multiple neuron circuits, which is closer to the connection method between biological neurons. Summary of the invention

[0005] The present invention aims to solve the above problems of the prior art. A multi-input neuron circuit for a pulse neural network is proposed. The technical solution of the present invention is as follows:

[0006] A multi-input neuron circuit for a pulse neural network, comprising: an input circuit, a reset circuit, a leakage circuit, a state judgment circuit and an action potential generating circuit, wherein the input circuit is connected to the input end of the reset circuit, the output end of the reset circuit is connected to the input end of the leakage circuit, the output end of the leakage circuit is connected to the input end of the state judgment circuit, and the output end of the state judgment circuit is connected to the action potential generating circuit;

[0007] The input circuit includes an excitatory input circuit and an inhibitory input circuit. The excitatory input circuit is composed of NMOS tubes M11-M1 n The current mirror composed of PMOS tube M2 and PMOS tube M3, the inhibitory input circuit is composed of PMOS tube M41-M4 n and a current mirror composed of NMOS tube M5 and NMOS tube M6; wherein NMOS tube M11-M1 n Receive excitatory signals from multiple other neurons, PMOS tubes M41-M4 n Receive inhibitory signals from multiple other neurons, and then convert the input signal into a current signal through a current mirror and pass it to the leakage circuit;

[0008] The leakage circuit uses an NMOS tube M9 and a capacitor C mem In parallel, it has two functions: when there is a signal input, the capacitor C mem The voltage across the two ends will store the input signal and increase or decrease with the input signal. This voltage is called the membrane voltage V mem ; When there is no signal input, the stored membrane voltage V mem It will leak through the NMOS tube M9 to the resting potential or until the next signal arrives;

[0009] The state judgment circuit is composed of a comparator, which is used to judge the membrane voltage V mem Whether the threshold voltage is reached, once the membrane voltage V mem If the threshold voltage is exceeded, a high-level signal is output to the action potential generating circuit;

[0010] The action potential generating circuit is composed of inverters INV1, INV2, INV3 and NMOS tube M10, wherein inverters INV1 and INV2 constitute an output buffer for receiving the signal output by the state judgment circuit. If it is a high-level signal, it is shaped into a standard pulse signal and output to other circuits; wherein inverter INV3 and NMOS tube M10 constitute a refractory period circuit, which outputs a reset signal V rst The reset circuit is used to realize the reset and refractory period characteristics of the neuron circuit, that is, after the neuron circuit outputs a pulse, the membrane voltage V mem Return to resting potential and not receive any input for a period of time;

[0011] The reset circuit is composed of a PMOS tube M7 and an NMOS tube M8. The gates of the PMOS tube M7 and the NMOS tube M8 are both reset by a reset voltage V rst Control, when the reset voltage V rst When the reset voltage V rst When the signal is high, the PMOS tube M7 is turned off and the NMOS tube M8 is turned on. The leakage circuit cannot receive the current signal from the input circuit, and its accumulated membrane voltage signal V mem It will be reset to the quiescent potential through the NMOS tube M8.

[0012] Furthermore, the input circuit includes NMOS tubes M11-M1 n , PMOS tube M2 and PMOS tube M3, PMOS tube M41-M4 n , NMOS tube M5 and NMOS tube M6, among which NMOS tube M11-M1 n The gates are connected to the external excitatory signal V inE1 -V inEn , NMOS tube M11-M1 n The drain of the PMOS tube M2 is connected to the gate and drain of the NMOS tube M11-M1. n The source of the PMOS tube M2 is grounded, the gate of the PMOS tube M2 is connected to the gate of the PMOS tube M3, and the source of the PMOS tube M2 and the PMOS tube M3 is connected to the operating voltage VDD; wherein the PMOS tubes M41-M4 n The gates of the inI1 -V inIn , PMOS tube M41-M4 n The drain of the NMOS tube M5 is connected to the gate and drain of the PMOS tube M41-M4 n The source of the NMOS tube M5 is connected to the operating voltage VDD, the gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6, the sources of the NMOS tube M5 and the NMOS tube M6 are grounded, and the drain of the PMOS tube M3 and the drain of the NMOS tube M6 are connected to the source of the PMOS tube M7.

[0013] Further, the state judgment circuit includes a comparator Comp, a negative input terminal of the comparator Comp is connected to a threshold voltage Vth, and an output terminal of the comparator Comp is connected to an input terminal of an inverter INV1;

[0014] The comparator Comp of the state judgment circuit includes: PMOS tube N1, PMOS tube N2, PMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, NMOS tube N7, NMOS tube N8, PMOS tube N9, PMOS tube N10, NMOS tube N11, wherein the gate of PMOS tube N1 is connected to the external bias voltage V comp The source of the PMOS tube N1 is connected to the operating voltage VDD, the drain of the PMOS tube N1 is connected to the source of the PMOS tube N2 and the source of the PMOS tube N3, and the gate of the PMOS tube N2 is connected to the voltage V mem The drain of the PMOS tube N2 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N4, the drain of the NMOS tube N5, the gate of the NMOS tube N6, and the gate of the NMOS tube N11 respectively, and the gate of the PMOS tube N3 is connected to the threshold voltage V th The drain of the PMOS tube N3 is connected to the gate of the NMOS tube N5, the drain of the NMOS tube N6, the drain of the NMOS tube N7, the gate of the NMOS tube N7, and the gate of the NMOS tube N8 respectively. The gate of the NMOS tube N4 is connected to the drain of the NMOS tube N4. The sources of the NMOS tubes N4, NMOS tubes N5, NMOS tubes N6, NMOS tubes N7, and NMOS tubes N8 are grounded. The gate of the NMOS tube N7 is connected to the drain of the NMOS tube N7. The drain of the NMOS tube N8 is connected to the drain of the PMOS tube N9 and the gate of the PMOS tube N9 respectively. The gate of the PMOS tube N9 is connected to the drain of the PMOS tube N9 and the gate of the PMOS tube N10 respectively. The source of the PMOS tube N9 and the source of the PMOS tube N10 are both connected to the operating voltage VDD. The drain of the PMOS tube N10 is connected to the drain of the PMOS tube N11, and the source of the NMOS tube N11 is grounded.

[0015] Furthermore, the reset circuit includes a PMOS tube M7 and an NMOS tube M8, and the gates of the PMOS tube M7 and the NMOS tube M8 are connected to a reset voltage V rst , the drains of the PMOS tube M7 and the NMOS tube M8 are connected, and the source of the NMOS tube M8 is grounded;

[0016] The leakage circuit includes a capacitor C mem and NMOS tube M9, capacitor C mem One end of the capacitor C is connected to the drain of the NMOS tube M9 and is connected to the drains of the PMOS tube M7 and the NMOS tube M8 and the positive input terminal of the comparator Comp. mem The other end and the source of NMOS tube M9 are grounded, and the gate of NMOS tube M9 is connected to the external bias voltage V leak .

[0017] Furthermore, the action potential generating circuit includes inverters INV1-INV3 and an NMOS tube M10, the output end of the inverter INV1 is connected to the input ends of the inverters INV2 and INV3, and the output end of the inverter INV2 outputs a signal V out , output signal V out Represents the output signal of the entire neuron circuit. The output end of the inverter INV3 outputs a reset signal V rst The ground terminal of the inverter INV3 is connected to the drain of the NMOS tube M10, and the gate of the NMOS tube M10 is connected to the external bias signal V ref , the source of the NMOS tube M10 is grounded.

[0018] Furthermore, the membrane capacitance C mem Acts as the cell membrane in biological neurons, with a membrane voltage V mem Represents the pressure difference between the inside and outside of the cell membrane in biological neurons; the comparator Comp is used to measure the membrane voltage V mem With the threshold voltage V th The comparison simulates the activation characteristics of biological neurons. Once the pressure difference between the inside and outside of the cell membrane exceeds the threshold voltage, an action potential is generated and transmitted to other neurons. The refractory period circuit composed of the inverter INV3 and the NMOS tube M10 simulates the refractory period characteristics of biological neurons. When the neuron outputs an action potential, the cell membrane pressure difference will immediately return to the resting potential and the cell membrane will not accept any input for a period of time.

[0019] Furthermore, the NMOS transistor M9 in the leakage circuit is in the subthreshold region, and the transistor can be adjusted by adjusting the external bias voltage V leak The leakage time constant of the control signal is adjusted to make the leakage rate adjustable.

[0020] Furthermore, the NMOS tube M10 of the refractory period circuit in the action potential generating circuit is also in the subthreshold region, which is used to control the reset signal V rst Slowly decay, thereby achieving the refractory period of the neuron circuit; by adjusting the gate voltage V ref The length of the refractory period can be adjusted, thereby adjusting the frequency of the pulse signal output by the neuronal circuit.

[0021] Furthermore, the formula of the LIF model is as follows:

[0022]

[0023] Among them, V i represents the membrane potential of neuron i, C i represents the membrane capacitance of neuron i, I leak represents the leakage current of neuron i, W ijrepresents the connection weight between neuron i and neuron j, s j represents the pulse signal output by neuron j, n represents that there are n neurons connected to neuron i, and W ij S j represents the current signal received by neuron i from neuron j. If V i >V th , then let s i =1, V i =0, if V i <V th , then let s i =0.

[0024] Furthermore, when the excitatory input terminal inputs a high level, the inhibitory input terminal inputs a high level and no current is generated, and the membrane voltage V mem Gradually increases; when the excitatory input terminal inputs a low level, no current is generated, and the inhibitory input terminal inputs a low level to generate an inhibitory current, and the membrane voltage V mem The membrane voltage V mem When the voltage reaches the threshold, a pulse signal V is output. out .

[0025] The advantages and beneficial effects of the present invention are as follows:

[0026] The present invention provides a multi-input neuron circuit for a pulse neural network, corresponding to the LIF model formula proposed in claim 9, and the neuron circuit realizes the three dynamic response modes of the LIF model - tonic spiking, class 1 excitability, and integrator, without the need for additional digital circuit assistance. Corresponding to claim 3, the neuron state judgment circuit uses a hysteresis comparator instead of a traditional inverter to judge the membrane voltage, which has higher judgment accuracy and lower power consumption than the inverter. Corresponding to claim 6, a capacitor is used to act as a cell membrane in a biological neuron, which can store charges to show the process of accumulating potential difference in biological neurons, and can also provide charges to leak through leakage resistors, which is reflected in the process of attenuation of the potential difference inside and outside the cell membrane of biological neurons when there is no stimulation input. Corresponding to claim 7, the leakage circuit uses a subthreshold MOS tube to realize the leakage resistor so that the leakage rate of the neuron membrane voltage is adjustable, and the pulse emission frequency of the neuron can be further adjusted. Corresponding to claim 8, the neuron circuit adds a refractory period design on the basis of the LIF model, which is closer to the working mechanism of biological neurons, and the adjustable refractory period also makes the pulse emission frequency of neurons adjustable. The adjustability of the refractory period and leakage rate makes the neuron circuit adjustable in practical applications. Corresponding to claim 10, the input end of the neuron circuit adds an excitatory input and an inhibitory input design, which reflects the change of the potential difference between the inside and outside of the cell membrane when biological neurons receive different stimuli, and the input end adds a multi-input design, so that the neuron circuit can be connected to multiple neuron circuits, which is also closer to the connection method between biological neurons. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a multi-input neuron circuit according to a preferred embodiment of the present invention;

[0028] Figure 2 A circuit diagram of a comparator in a state judgment circuit in a multi-input neuron circuit providing a preferred embodiment of the present invention;

[0029] Figure 3 A schematic diagram of a sustained pulse dynamic response mode of a multi-input neuron circuit providing a preferred embodiment of the present invention;

[0030] Figure 4 A schematic diagram of a type 1 excitatory dynamic response mode of a multi-input neuron circuit providing a preferred embodiment of the present invention;

[0031] Figure 5 A schematic diagram of a dynamic response mode of an integrator of a multi-input neuron circuit providing a preferred embodiment of the present invention;

[0032] Figure 6A schematic diagram of a multi-input neuron circuit outputting pulses when an inhibitory signal is inputted according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0034] The technical solution of the present invention to solve the above technical problems is:

[0035] In the embodiment of the present application, the multi-input neuron circuit adopts a method of connecting multiple MOS tubes in parallel and then connecting to a current mirror to respectively realize excitatory input and inhibitory input. The multiple MOS tubes in parallel are used to receive voltage signals after weight adjustment of pulses emitted by other neurons; a capacitor is used to act as a cell membrane function to reflect the change process of membrane voltage. When there is an excitatory signal input, the membrane voltage accumulates, and when there is no signal input, it leaks through the leakage resistor acted by the subthreshold MOS tube; a comparator and an output buffer are combined to realize the mechanism of biological neuron cell membrane emitting action potentials, and a pulse signal is emitted when the membrane voltage reaches the threshold voltage; a subthreshold MOS tube is connected to the ground terminal of the inverter to control the high level maintenance time of the reset signal, thereby controlling the reset circuit to realize the refractory period, realizing the refractory period of biological neurons and making the refractory period controllable to better meet the various working conditions required in practical applications.

[0036] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0037] Example

[0038] like Figure 1 As shown, a multi-input neuron circuit for a pulse neural network includes: an input circuit, a reset circuit, a leakage circuit, a state judgment circuit and an action potential generating circuit, wherein the input circuit is connected to the input end of the reset circuit, the output end of the reset circuit is connected to the leakage circuit, the leakage circuit is connected to the input end of the state judgment circuit, and the output end of the state judgment circuit is connected to the action potential generating circuit.

[0039] The input circuit includes an excitatory input circuit and an inhibitory input circuit. Both the excitatory input end and the inhibitory input end have multiple MOS tubes to receive external inputs and are used to connect to multiple other neurons; the leakage circuit is used to indicate the change in the pressure difference between the inside and outside of the cell membrane. When there is a signal input, the membrane voltage increases or decreases with the input signal. When there is no signal input, the membrane voltage leaks from the leakage resistor; the state judgment circuit is used to judge whether the membrane voltage reaches the threshold voltage, and once the membrane voltage reaches the threshold voltage, a high level is output; the action potential generating circuit is used to generate a pulse output signal and a reset signal; the reset circuit is used to realize membrane voltage reset and the refractory period characteristics of the neuron circuit.

[0040] The excitatory input circuit is composed of NMOS tubes M11-M1 n The current mirror composed of PMOS tube M2 and PMOS tube M3, the inhibitory input circuit is composed of PMOS tube M41-M4 n and a current mirror composed of NMOS tubes M5 and M6. n Receive excitatory signals from multiple other neurons, PMOS tubes M41-M4 n It receives inhibitory signals from multiple other neurons, and then converts the input signal into a current signal through a current mirror and passes it to the leakage circuit.

[0041] The leakage circuit uses an NMOS tube M9 and a capacitor C mem In parallel, it has two functions: when there is a signal input, the capacitor C mem The voltage across the two ends will store the input signal and increase or decrease with the input signal. This voltage is called the membrane voltage V mem ; When there is no signal input, the stored membrane voltage V mem It will leak through the NMOS tube M9 and leak to the quiescent potential or until the next signal arrives.

[0042] The state judgment circuit is composed of a comparator, which is used to judge the membrane voltage V mem Whether the threshold voltage is reached, once the membrane voltage V mem When the threshold voltage is exceeded, a high-level signal is output to the action potential generating circuit.

[0043] The action potential generating circuit is composed of inverters INV1, INV2, INV3 and NMOS tube M10. Inverters INV1 and INV2 form an output buffer for receiving the signal output by the state judgment circuit. If it is a high-level signal, it is shaped into a standard pulse signal and output to other circuits. Inverter INV3 and NMOS tube M10 form a refractory period circuit, which outputs a reset signal V rstThe reset circuit is used to realize the reset and refractory period characteristics of the neuron circuit, that is, after the neuron circuit outputs a pulse, the membrane voltage V mem Returns to resting potential and does not receive any input for a period of time.

[0044] The reset circuit is composed of a PMOS tube M7 and an NMOS tube M8. The gates of the PMOS tube M7 and the NMOS tube M8 are both reset by a reset voltage V rst Control, when the reset voltage V rst When the reset voltage V rst When the signal is high, the PMOS tube M7 is turned off and the NMOS tube M8 is turned on. The leakage circuit cannot receive the current signal from the input circuit, and its accumulated membrane voltage signal V mem It will be reset to the quiescent potential through the NMOS tube M8.

[0045] Preferably, the input circuit includes NMOS tubes M11-M1 n , PMOS tube M2 and PMOS tube M3, PMOS tube M41-M4 n , NMOS tube M5 and NMOS tube M6, among which NMOS tube M11-M1 n The gates are connected to the external excitatory signal V inE1 -V inEn , NMOS tube M11-M1 n The drain of the PMOS tube M2 is connected to the gate and drain of the NMOS tube M11-M1. n The source of the PMOS tube M2 is grounded, the gate of the PMOS tube M2 is connected to the gate of the PMOS tube M3, and the source of the PMOS tube M2 and the PMOS tube M3 is connected to the operating voltage VDD; wherein the PMOS tubes M41-M4 n The gates of the inI1 -V inIn , PMOS tube M41-M4 n The drain of the NMOS tube M5 is connected to the gate and drain of the PMOS tube M41-M4 n The source of the NMOS tube M5 is connected to the operating voltage VDD, the gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6, the sources of the NMOS tube M5 and the NMOS tube M6 are grounded, and the drain of the PMOS tube M3 and the drain of the NMOS tube M6 are connected to the source of the PMOS tube M7.

[0046] The reset circuit includes a PMOS tube M7 and an NMOS tube M8, and the gates of the PMOS tube M7 and the NMOS tube M8 are connected to a reset voltage V rst, the drains of the PMOS tube M7 and the NMOS tube M8 are connected, and the source of the NMOS tube M8 is grounded.

[0047] The leakage circuit includes a capacitor C mem and NMOS tube M9, capacitor C mem One end of the capacitor C is connected to the drain of the NMOS tube M9 and is connected to the drains of the PMOS tube M7 and the NMOS tube M8 and the positive input terminal of the comparator Comp. mem The other end and the source of NMOS tube M9 are grounded, and the gate of NMOS tube M9 is connected to the external bias voltage V leak .

[0048] The state judgment circuit comprises a comparator Comp, a negative input terminal of the comparator Comp is connected to a threshold voltage Vth, and an output terminal of the comparator Comp is connected to an input terminal of an inverter INV1.

[0049] The action potential generating circuit includes inverters INV1-INV3 and an NMOS tube M10. The output end of the inverter INV1 is connected to the input ends of the inverters INV2 and INV3. The output end of the inverter INV2 outputs a signal V out , output signal V out Represents the output signal of the entire neuron circuit. The output end of the inverter INV3 outputs a reset signal V rst The ground terminal of the inverter INV3 is connected to the drain of the NMOS tube M10, and the gate of the NMOS tube M10 is connected to the external bias signal V ref , the source of the NMOS tube M10 is grounded.

[0050] Preferably, the circuit of the comparator Comp of the state judgment circuit includes: PMOS tube N1, PMOS tube N2, PMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, NMOS tube N7, NMOS tube N8, PMOS tube N9, PMOS tube N10, NMOS tube N11, wherein the gate of PMOS tube N1 is connected to the external bias voltage V comp The source of the PMOS tube N1 is connected to the operating voltage VDD, the drain of the PMOS tube N1 is connected to the source of the PMOS tube N2 and the source of the PMOS tube N3, and the gate of the PMOS tube N2 is connected to the voltage V mem The drain of the PMOS tube N2 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N4, the drain of the NMOS tube N5, the gate of the NMOS tube N6, and the gate of the NMOS tube N11 respectively, and the gate of the PMOS tube N3 is connected to the threshold voltage V thThe drain of the PMOS tube N3 is connected to the gate of the NMOS tube N5, the drain of the NMOS tube N6, the drain of the NMOS tube N7, the gate of the NMOS tube N7, and the gate of the NMOS tube N8 respectively. The gate of the NMOS tube N4 is connected to the drain of the NMOS tube N4. The sources of the NMOS tubes N4, NMOS tubes N5, NMOS tubes N6, NMOS tubes N7, and NMOS tubes N8 are grounded. The gate of the NMOS tube N7 is connected to the drain of the NMOS tube N7. The drain of the NMOS tube N8 is connected to the drain of the PMOS tube N9 and the gate of the PMOS tube N9 respectively. The gate of the PMOS tube N9 is connected to the drain of the PMOS tube N9 and the gate of the PMOS tube N10 respectively. The source of the PMOS tube N9 and the source of the PMOS tube N10 are both connected to the operating voltage VDD. The drain of the PMOS tube N10 is connected to the drain of the PMOS tube N11, and the source of the NMOS tube N11 is grounded.

[0051] Preferably, the neuron circuit has both excitatory input and inhibitory input, and the multi-input design is more in line with the characteristics of biological neurons and multiple neurons connected to each other. mem Acts as the cell membrane in biological neurons, with a membrane voltage V mem Represents the pressure difference between the inside and outside of the cell membrane in biological neurons. The comparator Comp is used to measure the membrane voltage V mem With the threshold voltage V th The comparison simulates the activation characteristics of biological neurons. Once the pressure difference between the inside and outside of the cell membrane exceeds the threshold voltage, an action potential is generated and transmitted to other neurons. The refractory period circuit composed of the inverter INV3 and the NMOS tube M10 simulates the refractory period characteristics of biological neurons. When the neuron outputs an action potential, the cell membrane pressure difference will immediately return to the resting potential and the cell membrane will not accept any input for a period of time.

[0052] Preferably, the formula of the LIF model is as follows:

[0053]

[0054] Among them, V i represents the membrane potential of neuron i, C i represents the membrane capacitance of neuron i, I leak represents the leakage current of neuron i, W ij represents the connection weight between neuron i and neuron j, s j represents the pulse signal output by neuron j, n represents that there are n neurons connected to neuron i, and W ij S j represents the current signal received by neuron i from neuron j. If V i >V th , then let s i=1, V i =0, if V i <V th , then let s i =0.

[0055] Preferably, the NMOS transistor M9 in the leakage circuit is in a subthreshold region, and the transistor can be adjusted by adjusting the external bias voltage V leak The leakage time constant of the control signal is adjusted to make the leakage rate adjustable.

[0056] Preferably, the NMOS tube M10 of the refractory period circuit in the action potential generating circuit is also in the subthreshold region, which is used to control the reset signal V rst Slowly decay, thereby achieving the refractory period of the neuron circuit. By adjusting the gate voltage V ref The length of the refractory period can be adjusted, thereby adjusting the frequency of the pulse signal output by the neuronal circuit.

[0057] Figure 2 The diagram shows the schematic diagram of the comparator circuit structure in the state judgment circuit in the multi-input neuron circuit. The comparator is a hysteresis comparator. The NMOS tube N1 in the comparator receives the external bias voltage V comp The NMOS tube N2 in the comparator is the positive input terminal of the comparator, receiving the membrane voltage V from the leakage circuit. mem The PMOS tube N3 in the comparator is the negative input terminal of the comparator, receiving the threshold voltage V th The comparator determines the membrane voltage V mem With the threshold voltage V th The size generates a high level signal, which is used to generate a pulse signal.

[0058] Figure 3 The figure shows the continuous pulse (Tonic Spiking, TS) dynamic response mode of the multi-input neuron circuit. The TS dynamic response mode is the first of the three dynamic response modes that the LIF model can achieve. When a DC voltage signal is input to the neuron circuit, the neuron circuit continuously outputs pulses. In order to only reflect the TS dynamic response mode, a 200mV voltage signal is input to the excitatory input end of the neuron circuit, and the working voltage VDD is input to the inhibitory input end. The inhibitory input end does not generate current. When a signal is continuously input to the neuron circuit, the leakage circuit continuously accumulates the membrane voltage. Once the membrane voltage reaches the threshold voltage, a pulse signal V is generated through the state judgment circuit and the action potential generation circuit. out And the reset signal, the reset signal causes the reset circuit to reset the membrane voltage and enter the refractory period, until the reset signal decays to a low level, the neuron circuit begins to accumulate the membrane voltage again and enters the next cycle.

[0059] Figure 4 The figure shows the Class 1 excitability dynamic response mode of a multi-input neuron circuit. The CS dynamic response mode is the second of the three dynamic response modes that can be achieved by the LIF model. The frequency of the output pulse of the neuron circuit is proportional to the input signal. The larger the input voltage, the higher the output pulse frequency. In order to reflect the CS dynamic response mode, a sinusoidal signal is input to the excitatory input of the neuron circuit, and the working voltage VDD is input to the inhibitory input. The inhibitory input does not generate current. Figure 4 It can be seen that as the input signal voltage value increases, the output pulse V out The frequency gradually increases, and as the input signal voltage decreases, the output pulse V out The frequency gradually decreases. In the peak area of ​​the input sinusoidal signal, the output pulse V out The frequency is the highest, and it spreads to both sides with the peak value of the input sinusoidal signal, and the output pulse V out The frequency gradually decreases until the current is too small to drive the membrane capacitance.

[0060] Figure 5 The figure shows the integrator dynamic response mode of the multi-input neuron circuit. The Integrator dynamic response mode is the third of the three dynamic response modes that the LIF model can achieve. When a periodic pulse signal is input to the neuron circuit, the membrane voltage will increase with each input pulse signal. If there is no signal input, the membrane voltage will slowly decay with the leakage current until the membrane voltage accumulates and exceeds the threshold voltage, then a pulse signal is output. In order to reflect the Integrator dynamic response mode, a periodic square wave signal is input to the excitatory input of the neuron circuit. The high level of the square wave signal is 200mV, and the low level of the square wave signal is 0V. The working voltage VDD is input to the inhibitory input, and no current is generated at the inhibitory input. When the input square wave signal is high, the membrane voltage V mem Gradually increases, when the input square wave signal is low level, the membrane voltage V mem Slowly decays until the membrane voltage V mem When the voltage reaches the threshold, a pulse signal V is output. out .

[0061] Figure 6 The figure shows the output pulse when an inhibitory signal is input to the inhibitory input terminal of the neuron input circuit. A periodic square wave signal with a high level of 300mV and a low level of 0V is input to the excitatory input terminal of the neuron circuit, and a periodic square wave signal with a high level of 1.2V and a low level of 1V is input to the inhibitory input terminal. The two signals have the same period. When a high level is input to the excitatory input terminal, a high level input to the inhibitory input terminal does not generate current, and the membrane voltage Vmem Gradually increases; when the excitatory input terminal inputs a low level, no current is generated, and the inhibitory input terminal inputs a low level to generate an inhibitory current, and the membrane voltage V mem Significantly decreases with signal input, membrane voltage V mem When the voltage reaches the threshold, a pulse signal V is output. out .

[0062] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0063] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A multi-input neuron circuit for a spiking neural network, characterized in that: include: An input circuit, a reset circuit, a leakage circuit, a state judgment circuit and an action potential generating circuit, wherein the input circuit is connected to the input end of the reset circuit, the output end of the reset circuit is connected to the input end of the leakage circuit, the output end of the leakage circuit is connected to the input end of the state judgment circuit, and the output end of the state judgment circuit is connected to the action potential generating circuit; The input circuit includes an excitatory input circuit and an inhibitory input circuit. The excitatory input circuit is composed of NMOS tubes M11-M1 n The current mirror composed of PMOS tube M2 and PMOS tube M3, the inhibitory input circuit is composed of PMOS tube M41-M4 n and a current mirror composed of NMOS tube M5 and NMOS tube M6; wherein NMOS tube M11-M1 n Receive excitatory signals from multiple other neurons, PMOS tubes M41-M4 n Receive inhibitory signals from multiple other neurons, and then convert the input signal into a current signal through a current mirror and pass it to the leakage circuit; The leakage circuit uses an NMOS tube M9 and a capacitor C mem In parallel, it has two functions: when there is a signal input, the capacitor C mem The voltage across the two ends will store the input signal and increase or decrease with the input signal. This voltage is called the membrane voltage V mem ; When there is no signal input, the stored membrane voltage V mem It will leak through the NMOS tube M9 to the resting potential or until the next signal arrives; The state judgment circuit is composed of a comparator, which is used to judge the membrane voltage V mem Whether the threshold voltage is reached, once the membrane voltage V mem If the threshold voltage is exceeded, a high-level signal is output to the action potential generating circuit; The action potential generating circuit is composed of inverters INV1, INV2, INV3 and NMOS tube M10, wherein inverters INV1 and INV2 constitute an output buffer for receiving the signal output by the state judgment circuit. If it is a high-level signal, it is shaped into a standard pulse signal and output to other circuits; wherein inverter INV3 and NMOS tube M10 constitute a refractory period circuit, which outputs a reset signal V rst The reset circuit is used to realize the reset and refractory period characteristics of the neuron circuit, that is, after the neuron circuit outputs a pulse, the membrane voltage V mem Return to resting potential and not receive any input for a period of time; The reset circuit is composed of a PMOS tube M7 and an NMOS tube M8. The gates of the PMOS tube M7 and the NMOS tube M8 are both reset by a reset voltage V rst Control, when the reset voltage V rst When the reset voltage V rst When the signal is high, the PMOS tube M7 is turned off and the NMOS tube M8 is turned on. The leakage circuit cannot receive the current signal from the input circuit, and its accumulated membrane voltage signal V mem It will be reset to the resting potential through NMOS tube M8; Membrane capacitance C mem Acts as the cell membrane in biological neurons, with a membrane voltage V mem Represents the internal and external pressure difference of the cell membrane in biological neurons; the comparator Comp is used to measure the membrane voltage V mem With the threshold voltage V th The comparison simulates the activation characteristics of biological neurons. Once the pressure difference between the inside and outside of the cell membrane exceeds the threshold voltage, an action potential is generated and transmitted to other neurons. The refractory period circuit composed of the inverter INV3 and the NMOS tube M10 simulates the refractory period characteristics of biological neurons. When the neuron outputs an action potential, the cell membrane pressure difference will immediately return to the resting potential and the cell membrane will not accept any input for a period of time. The NMOS tube M9 in the leakage circuit is in the subthreshold region, and the tube can be adjusted by adjusting the external bias voltage V leak Control the signal leakage time constant to make the leakage rate adjustable; The NMOS tube M10 of the refractory period circuit in the action potential generating circuit is also in the subthreshold region, which is used to control the reset signal V rst Slowly decay, thereby achieving the refractory period of the neuron circuit; by adjusting the gate voltage V ref The length of the refractory period can be adjusted, thereby adjusting the frequency of the pulse signal output by the neuronal circuit; The model used in the neuron circuit is the LIF (Leaky Integrate and Fire) model, and its formula is as follows: Among them, V i represents the membrane potential of neuron i, C i represents the membrane capacitance of neuron i, I leak represents the leakage current of neuron i, W ij represents the connection weight between neuron i and neuron j, s j represents the pulse signal output by neuron j, n represents that there are n neurons connected to neuron i, and W ij S j Represents the current signal received by neuron i from neuron j. If V i >V th , then let s i =1, V i =0, if V i <V th , then let s i =0; When the excitatory input terminal inputs a high level, the inhibitory input terminal inputs a high level and no current is generated, and the membrane voltage V mem Gradually increases; when the excitatory input terminal inputs a low level, no current is generated, and the inhibitory input terminal inputs a low level to generate an inhibitory current, and the membrane voltage V mem The membrane voltage V mem When the voltage reaches the threshold, a pulse signal V is output. out .

2. A multi-input neuron circuit for a pulse neural network according to claim 1, characterized in that: The input circuit includes NMOS tubes M11-M1 n , PMOS tube M2 and PMOS tube M3, PMOS tube M41-M4 n , NMOS tube M5 and NMOS tube M6, among which NMOS tube M11-M1 n The gates are connected to the external excitatory signal V inE1 -V inEn , NMOS tube M11-M1 n The drain of the PMOS tube M2 is connected to the gate and drain of the NMOS tube M11-M1. n The source of the PMOS tube M2 is grounded, the gate of the PMOS tube M2 is connected to the gate of the PMOS tube M3, and the source of the PMOS tube M2 and the PMOS tube M3 is connected to the operating voltage VDD; wherein the PMOS tubes M41-M4 n The gates of the inI1 -V inIn , PMOS tube M41-M4 n The drain of the NMOS tube M5 is connected to the gate and drain of the PMOS tube M41-M4 n The source of the NMOS tube M5 is connected to the operating voltage VDD, the gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6, the sources of the NMOS tube M5 and the NMOS tube M6 are grounded, and the drain of the PMOS tube M3 and the drain of the NMOS tube M6 are connected to the source of the PMOS tube M7.

3. A multi-input neuron circuit for a pulse neural network according to claim 1, characterized in that: The state judgment circuit includes a comparator Comp, a negative input terminal of the comparator Comp is connected to a threshold voltage Vth, and an output terminal of the comparator Comp is connected to an input terminal of an inverter INV1; The comparator Comp of the state judgment circuit includes: PMOS tube N1, PMOS tube N2, PMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, NMOS tube N7, NMOS tube N8, PMOS tube N9, PMOS tube N10, NMOS tube N11, wherein the gate of PMOS tube N1 is connected to the external bias voltage V comp The source of the PMOS tube N1 is connected to the operating voltage VDD, the drain of the PMOS tube N1 is connected to the source of the PMOS tube N2 and the source of the PMOS tube N3, and the gate of the PMOS tube N2 is connected to the voltage V mem The drain of the PMOS tube N2 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N4, the drain of the NMOS tube N5, the gate of the NMOS tube N6, and the gate of the NMOS tube N11 respectively, and the gate of the PMOS tube N3 is connected to the threshold voltage V th The drain of the PMOS tube N3 is connected to the gate of the NMOS tube N5, the drain of the NMOS tube N6, the drain of the NMOS tube N7, the gate of the NMOS tube N7, and the gate of the NMOS tube N8 respectively. The gate of the NMOS tube N4 is connected to the drain of the NMOS tube N4. The sources of the NMOS tubes N4, NMOS tubes N5, NMOS tubes N6, NMOS tubes N7, and NMOS tubes N8 are grounded. The gate of the NMOS tube N7 is connected to the drain of the NMOS tube N7. The drain of the NMOS tube N8 is connected to the drain of the PMOS tube N9 and the gate of the PMOS tube N9 respectively. The gate of the PMOS tube N9 is connected to the drain of the PMOS tube N9 and the gate of the PMOS tube N10 respectively. The source of the PMOS tube N9 and the source of the PMOS tube N10 are both connected to the operating voltage VDD. The drain of the PMOS tube N10 is connected to the drain of the PMOS tube N11, and the source of the NMOS tube N11 is grounded.

4. A multi-input neuron circuit for a pulse neural network according to claim 1, characterized in that: The reset circuit includes a PMOS tube M7 and an NMOS tube M8, and the gates of the PMOS tube M7 and the NMOS tube M8 are connected to a reset voltage V rst , the drains of the PMOS tube M7 and the NMOS tube M8 are connected, and the source of the NMOS tube M8 is grounded; The leakage circuit includes a capacitor C mem and NMOS tube M9, capacitor C mem One end of the capacitor C is connected to the drain of the NMOS tube M9 and is connected to the drains of the PMOS tube M7 and the NMOS tube M8 and the positive input terminal of the comparator Comp. mem The other end and the source of NMOS tube M9 are grounded, and the gate of NMOS tube M9 is connected to the external bias voltage V leak .

5. The multi-input neuron circuit for a pulse neural network according to claim 1, characterized in that: The action potential generating circuit includes inverters INV1-INV3 and an NMOS tube M10. The output end of the inverter INV1 is connected to the input ends of the inverters INV2 and INV3. The output end of the inverter INV2 outputs a signal V out , output signal V out Represents the output signal of the entire neuron circuit. The output end of the inverter INV3 outputs a reset signal V rst The ground terminal of the inverter INV3 is connected to the drain of the NMOS tube M10, and the gate of the NMOS tube M10 is connected to the external bias signal V ref , the source of the NMOS tube M10 is grounded.

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