Fan-out packaging method

Abstract

The present application discloses a fan-out packaging method, comprising: sequentially forming a first photoresist layer and a second photoresist layer on a first surface of a carrier; wherein one of the first photoresist layer and the second photoresist layer is a positive photoresist and the other is a negative photoresist; simultaneously exposing and developing the first photoresist layer and the second photoresist layer, forming a plurality of first vias in the first photoresist layer and a plurality of second vias in the second photoresist layer located on the side periphery of the first photoresist layer; forming a blocking member in the first via and a conductive pillar in the second via; and removing the first photoresist layer and the second photoresist layer. By means of the above-described method, the present application can reduce the probability of chip warping, reduce the height of fan-out devices, and save material costs.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a fan-out packaging method. Background Art

[0002] In existing chip packaging methods, the chip is packaged into a complete chip packaging structure using plastic packaging materials. However, during subsequent use, the plastic packaging materials are prone to deformation due to shrinkage, causing the chip to shift within the packaging structure, thereby reducing the service life of the chip. Summary of the Invention

[0003] The main technical problem solved by the present application is to provide a fan-out packaging method that can reduce the deformation of the plastic packaging material caused by shrinkage and ensure the stability of the chip.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a fan-out packaging method, comprising: successively forming a first photoresist layer and a second photoresist layer on a first surface of a carrier; wherein, one of the first photoresist layer and the second photoresist layer is a positive photoresist, and the other is a negative photoresist; and the second photoresist layer covers the side surface of the first photoresist layer and the surface of the first photoresist layer facing away from the carrier; exposing and developing the first photoresist layer and the second photoresist at the same time, forming a plurality of first vias on the first photoresist layer, and forming a plurality of second vias on the second photoresist layer located on the periphery of the side surface of the first photoresist layer; wherein the height of the second via is greater than the height of the first via; forming a blocking member in the first via, and forming a conductive column in the second via; removing the first photoresist layer and the second photoresist layer.

[0005] Wherein, the blocking member has conductive properties; the steps of forming the blocking member in the first via hole and forming a conductive column in the second via hole include: filling the first via hole and the second via hole with conductive material at the same time to form the blocking member and the conductive column.

[0006] Among them, after the step of removing the first photoresist layer and the second photoresist layer, it includes: setting a first chip in the area surrounded by the multiple blocking members; forming a plastic sealing layer on the side of the carrier where the first chip is set, so that the first chip, the blocking members and the conductive columns form an integral structure; and removing the carrier.

[0007] Among them, before the step of successively forming the first photoresist layer and the second photoresist layer on the first surface of the carrier, it includes: arranging a first chip on the first surface of the carrier; wherein, when the first photoresist layer and the second photoresist layer are formed on the first surface of the carrier, the side of the second photoresist layer facing away from the carrier is relatively away from the carrier on the side of the first chip facing away from the carrier; after the step of removing the first photoresist layer and the second photoresist layer, it includes: forming a plastic sealing layer on the side of the carrier where the first chip is arranged, so that the first chip, the blocking member and the conductive column form an integral structure; and removing the carrier.

[0008] Among them, the first chip includes a functional surface and a non-functional surface arranged back to back, and the non-functional surface of the first chip faces the carrier; when the first photoresist layer and the second photoresist layer are exposed and developed at the same time, a plurality of third vias are formed on the photoresist layer covering the functional surface of the first chip, and one of the third vias corresponds to a pad on the functional surface of the first chip; a conductive column is formed in the second via and a conductive bump is formed in the third via.

[0009] Among them, the step of forming a plastic sealing layer on the side of the carrier board where the first chip is provided includes: forming a plastic sealing layer on the side of the carrier board where the first chip is provided, the plastic sealing layer covering the conductive pillars and the gaps in the space enclosed by the conductive pillars; wherein the plastic sealing layer is flush with the surface of the conductive pillars on the side facing away from the carrier board.

[0010] The first chip includes a first functional surface and a first non-functional surface arranged in opposite directions, and the first non-functional surface of the first chip faces the carrier board; before the step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged, the step further includes: arranging at least one second chip on the side of the first functional surface of the first chip facing away from the carrier board, and forming an underfill between at least the second functional surface of the second chip and the carrier board, and the blocking member is located in the underfill; wherein the second functional surface of the second chip faces the first functional surface of the first chip, and the second chip spans at least a portion of the first chip and at least a portion of the first chip. At least part of the blocking members are partially adjacent, and the pads on the second functional surface of the second chip are electrically connected to the pads on the first functional surface of the first chip at the corresponding position and the blocking members; the step of forming a plastic encapsulation layer on the side of the carrier where the first chip is provided includes: forming the plastic encapsulation layer on the side of the carrier where the first chip is provided, and the plastic encapsulation layer covers the conductive columns, the second chip and the gap in the space enclosed by the conductive columns; grinding the plastic encapsulation layer from the side of the plastic encapsulation layer away from the carrier so that the surfaces of the plastic encapsulation layer, the conductive columns and the second chip away from the carrier are flush.

[0011] The first chip includes a first functional surface and a first non-functional surface arranged in back to back relationship, and the first functional surface of the first chip faces the carrier board; the step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged includes: forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged, the plastic encapsulation layer covering the conductive pillars and the gaps in the space enclosed by the conductive pillars; the plastic encapsulation layer is flush with the surface of the conductive pillars on the side facing away from the carrier board.

[0012] Wherein, after the step of removing the carrier board, it also includes: forming a first rewiring layer and a second rewiring layer on both sides of the length direction of the conductive column respectively; wherein, the first rewiring layer is electrically connected to at least one end of the conductive column and the first chip, and the second rewiring layer is electrically connected to the other end of the conductive column; a first conductive connector is set on the side of the first rewiring layer away from the conductive column, and a second conductive connector is set on the side of the second rewiring layer away from the conductive column.

[0013] Wherein, before the step of forming a plastic sealing layer on the side of the carrier board where the first chip is provided, the method includes: forming an insulating glue at least around the periphery of the plurality of blocking members.

[0014] The beneficial effects of the present application are: different from the prior art, the present application forms multiple blocking members and multiple conductive pillars on the carrier by arranging a first photoresist layer and a second photoresist layer, one of which is a positive photoresist and the other is a negative photoresist, on the carrier, wherein the multiple blocking members and the multiple conductive pillars are equivalent to cofferdam retaining walls, which help to limit the movement of the plastic encapsulation material in the fan-out device, thereby reducing the deformation of the plastic encapsulation material due to shrinkage and reducing the probability of warping of the first chip; in addition, the conductive pillars can also realize a three-dimensional vertical interconnection structure, which is beneficial to reducing the height of the fan-out device, and the design of blocking members and conductive pillars of different heights can effectively save material costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0016] Figure 1 1 is a flow chart of an embodiment of the fan-out packaging method of the present application;

[0017] Figure 2 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S101;

[0018] Figure 3 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S102;

[0019] Figure 4 is a schematic cross-sectional structural diagram of another embodiment corresponding to step S102;

[0020] Figure 5a is a schematic cross-sectional structural diagram corresponding to an embodiment of step S103;

[0021] Figure 5b is a cross-sectional structural diagram corresponding to another embodiment of step S103;

[0022] Figure 6 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S104;

[0023] Figure 7 is a flow chart corresponding to an embodiment after step S104;

[0024] Figure 8a is a schematic cross-sectional structural diagram corresponding to an embodiment of step S201;

[0025] Figure 8b is a schematic cross-sectional structural diagram corresponding to an embodiment after step S201;

[0026] Figure 9 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S202;

[0027] Figure 10 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S203;

[0028] Figure 11 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S204;

[0029] Figure 12 1 is a flow chart of another embodiment of the fan-out packaging method of the present application;

[0030] Figure 13 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S301;

[0031] Figure 14 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S302;

[0032] Figure 15 1 is a flow chart of another embodiment of the fan-out packaging method of the present application;

[0033] Figure 16 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S401;

[0034] Figure 17 It is a schematic cross-sectional structural diagram corresponding to an embodiment of step S402. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] See also Figure 1 , Figure 1 : is a flow chart of an embodiment of the fan-out packaging method of the present application, the method comprising:

[0037] S101: forming a first photoresist layer and a second photoresist layer on a first surface of a carrier substrate in sequence.

[0038] See also Figure 2 , Figure 2 This is a schematic cross-sectional view of an embodiment corresponding to step S101. The specific implementation process of this step includes: first, forming a first photoresist layer 20 on the first surface of the carrier 10, and then forming a second photoresist layer 30 on the first surface of the carrier. One of the first photoresist layer 20 and the second photoresist layer 30 is a positive photoresist, and the other is a negative photoresist; the second photoresist layer 30 covers the side surfaces of the first photoresist layer 20 and the surface of the first photoresist layer 20 facing away from the carrier 10; that is, the orthographic projection of the first photoresist layer 20 on the carrier 10 is located within the orthographic projection of the second photoresist layer 30 on the carrier 10. Specifically, the positive photoresist is insoluble in developer before exposure but becomes soluble in developer after exposure; the negative photoresist is soluble in developer before exposure but becomes insoluble in developer after exposure.

[0039] S102: exposing and developing the first photoresist layer and the second photoresist layer simultaneously.

[0040] When the first photoresist layer 20 is a negative photoresist and the second photoresist layer 30 is a positive photoresist, please refer to Figure 3 , Figure 3 This is a schematic cross-sectional view of an embodiment of step S102. The specific implementation process of step S102 includes: exposing and developing the first photoresist layer 20 and the second photoresist layer 30 simultaneously to form a plurality of first via holes 21 on the first photoresist layer 20, and forming a plurality of second via holes 31 on the second photoresist layer 30 located on the side periphery of the first photoresist layer 20. The height of the second via holes 31 is greater than the height of the first via holes 21. For details, please refer to Figure 3 In Figure a, a film 40 is placed on the side of the second photoresist layer 30 facing away from the carrier 10. The film 40 is provided with a plurality of openings 41. The film 40 is first exposed and then removed. Simultaneously, the first and second photoresist layers 20 and 30 are developed. In this embodiment, the first photoresist layer 20 is a negative photoresist and the second photoresist layer 30 is a positive photoresist. The second photoresist layer 30 at locations corresponding to the openings 41 is removed after development, while the first photoresist layer 20 at locations corresponding to the openings 41 is not removed after development. Furthermore, the second photoresist layer 30 located on the outer side of the first photoresist layer 20 and at locations corresponding to the openings 41 is removed after exposure and development to form a plurality of second vias 31. For the openings 41 whose orthographic projections on the first photoresist layer 20 are located within the first photoresist layer 20, the second photoresist layer 30 at the corresponding positions of these openings 41 is removed through exposure and development. In addition, the first photoresist layer 20 corresponding to the area enclosed by these openings 41 is not exposed because it is blocked by the film 40. Therefore, the first photoresist layer 20 corresponding to the area enclosed by the openings 41 is also removed to form the first via 21 because it is a negative photoresist layer. Based on the fact that the second photoresist layer 30 at the corresponding positions of these openings 41 is removed after development, and the first photoresist layer 20 corresponding to the area enclosed by the openings 41 is removed after development, there is no longer any photoresist layer connected to the second photoresist layer 30 at the area enclosed by the openings 41, and this part of the second photoresist layer 30 is also removed. After removing part of the first photoresist layer 20 and part of the second photoresist layer 30, as shown in FIG. Figure 3 As shown in Figure b.

[0041] When the first photoresist layer 20 is a positive photoresist and the second photoresist layer 30 is a negative photoresist, please refer to Figure 4 , Figure 4 is a schematic cross-sectional view of another embodiment of step S102. In this embodiment, the specific implementation process of step S102 includes: Figure 4As shown in Figure a, a film 40 is placed on the side of the second photoresist layer 30 facing away from the carrier 10. The film 40 is provided with a plurality of openings 41. The film 40 is first exposed to light. After exposure, the film 40 is removed, and the first and second photoresist layers 20, 30 are simultaneously developed. Regarding the openings 41 located on the outer side of the first photoresist layer 20, the middle portion of the second photoresist layer 30 surrounding the openings 41 is not exposed. Since the second photoresist layer 30 is a negative-tone photoresist, this portion of the second photoresist layer 30 is removed to form the second vias 31. For the openings 41 on the first photoresist layer 20 whose orthographic projections are located within the first photoresist layer 20, the first photoresist layer 20 at the positions corresponding to these openings 41 is removed by development after exposure to form the first vias 21. In addition, the second photoresist layer 30 outside the positions corresponding to these openings 41 and not subjected to exposure is removed after development. Therefore, there is no longer any photoresist layer connected to the second photoresist layer 30 at the positions corresponding to the openings 41 on the first photoresist layer 20 whose orthographic projections are located within the first photoresist layer 20, and this portion of the second photoresist layer 30 is also removed. After removing part of the first photoresist layer 20 and part of the second photoresist layer 30, as shown in FIG. Figure 4 As shown in Figure b.

[0042] S103: forming a blocking member in the first via hole and forming a conductive pillar in the second via hole.

[0043] When the first photoresist layer 20 is a negative photoresist and the second photoresist layer 30 is a positive photoresist, please refer to Figure 5a , Figure 5a This is a schematic cross-sectional structure diagram corresponding to an embodiment of step S103. Specifically, the specific implementation process of the above step S103 includes: filling the first via 21 and the second via 31 with a conductive material at the same time to form a blocking member 22 and a conductive column 32. The blocking member 22 is flush with the surface of the first photoresist layer 20 at one end facing away from the carrier 10, and the conductive column 32 is flush with the surface of the second photoresist layer 30 at one end facing away from the carrier 10. The blocking member 22 has conductive properties. The conductive material can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. The conductive column 32 is conducive to realizing a three-dimensional vertical interconnection structure of the fan-out device, and the blocking member 22 helps to improve the stability of the fan-out device.

[0044] When the first photoresist layer 20 is a positive photoresist and the second photoresist layer 30 is a negative photoresist, please refer to Figure 5b , Figure 5bFIG2 is a schematic cross-sectional view of another embodiment of step S103. Specifically, in this embodiment, step S103 includes simultaneously filling the first via hole 21 and the second via hole 31 with a conductive material to form a blocking member 22 and a conductive pillar 32. The end of the blocking member 22 facing away from the carrier 10 is flush with the surface of the first photoresist layer 20, and the end of the conductive pillar 32 facing away from the carrier 10 is flush with the surface of the second photoresist layer 30.

[0045] S104: removing the first photoresist layer and the second photoresist layer.

[0046] See also Figure 6 , Figure 6 2 is a schematic cross-sectional structural diagram corresponding to step S104 in one embodiment. Specifically, the step S104 includes: removing the first photoresist layer 20 and the second photoresist layer 30 to expose the blocking member 22 and the conductive pillar 32 to facilitate the execution of step S201 .

[0047] Further, see Figure 7 , Figure 7 This is a flow chart corresponding to an embodiment after step S104, which includes:

[0048] S201: placing a first chip in an area surrounded by a plurality of blocking members.

[0049] See also Figure 8a , Figure 8a This is a schematic cross-sectional structural diagram corresponding to an embodiment of step S201. Specifically, the implementation process of step S201 includes: in response to the first chip 100 including a first functional surface 101 and a first non-functional surface 102 arranged in back to back, the first non-functional surface 102 of the first chip 100 faces the carrier 10.

[0050] See also Figure 8b , Figure 8b FIG2 is a schematic cross-sectional view of an embodiment after step S201. Specifically, after step S201 is implemented, the process further includes forming insulating adhesive 25 around at least the periphery of the plurality of blocking members 22. The insulating adhesive 25 can be applied by dripping adhesive, and due to the surface tension of the adhesive, the surface of the insulating adhesive 25 is curved. Alternatively, the insulating adhesive 25 can be applied around the periphery of the plurality of blocking members 22 by dispensing adhesive or other methods. The insulating adhesive 25 can be cylindrical, conical, or other shapes, without limitation. The application of the insulating adhesive 25 around the periphery of the blocking members 22 can provide a certain degree of securement for the blocking members 22.

[0051] S202: Disposing at least one second chip on a side of a first functional surface of the first chip facing away from the carrier, and forming an underfill between at least a second functional surface of the second chip and the carrier.

[0052] See also Figure 9 , Figure 9 is a schematic cross-sectional structural diagram corresponding to an embodiment of step S202, Figure 9 It is only indicative. Figure 9 Only two second chips 200 are shown, but in actual applications, one, two, three, or other second chips 200 may be provided. The specific implementation process of step S202 includes: disposing at least one second chip 200 on the side of the first functional surface 101 of the first chip 100 facing away from the carrier 10. The second chip 200 includes a second functional surface 201 and a second non-functional surface 202 disposed opposite to each other. The second functional surface 201 of the second chip 200 faces the first functional surface 101 of the first chip 100. The second chip 200 spans at least a portion of the first chip 100 and at least a portion of the blocking member 22 at least partially adjacent to the first chip 100. The pads on the second functional surface 201 of the second chip 200 are electrically connected to the pads on the first functional surface 101 of the first chip 100 and the blocking member 22 at corresponding locations. In other words, a portion of the blocking member 22 can be electrically connected to the first chip 100 through the second chip 200. Specifically, conductive bumps may be provided on the pads of the first functional surface 101 of the first chip 100, and conductive bumps may be provided on at least a portion of the barrier 22 at least partially adjacent to the first chip 100, to facilitate connections between the second chip 200 and the first chip, and between the second chip 200 and the portion of the barrier 22. By providing at least one second chip 200 on the side of the first functional surface 101 of the first chip 100, packaging of multiple chips can be achieved and the overall height of the fan-out device can be reduced.

[0053] For further information, please refer to Figure 9 , step S202 also includes: forming an underfill 28 at least between the second functional surface 201 of the second chip 200 and the carrier 10, and the blocking member 22 is located in the underfill 28, so as to play a certain role in fixing and protecting the first chip 100, the second chip 200 and the blocking member 22. Specifically, in this application mode, the vertical cross-section of the underfill 28 is a trapezoid, which can improve the stability of the fan-out device; in other application modes, the vertical cross-section of the underfill 28 can also be a rectangle, etc. Optionally, the side of the underfill 28 facing away from the carrier 10 can be flush with the second functional surface 201 of the second chip 200, or it can be higher than the second functional surface 201 of the second chip 200, and this application does not limit this. In addition, in other embodiments, the underfill 28 may not be provided, that is, step S203 is directly executed after the second chip 200 is provided.

[0054] S203: forming a plastic packaging layer on the side of the carrier board where the first chip is disposed.

[0055] See also Figure 10 , Figure 10This is a schematic cross-sectional view of an embodiment corresponding to step S203. The specific implementation process of step S203 includes: forming a plastic encapsulation layer 60 on the side of the carrier 10 where the first chip 100 is provided, so that the first chip 100, the blocking member 22, and the conductive pillars 32 form an integral structure, and the plastic encapsulation layer 60 covers the conductive pillars 32, the second chip 200, and the gaps within the space enclosed by the conductive pillars 32. Furthermore, the plastic encapsulation layer 60 is ground from the side facing away from the carrier 10, so that the surfaces of the plastic encapsulation layer 60, the conductive pillars 32, and the second chip 200 facing away from the carrier 10 are flush. Grinding the plastic encapsulation layer 60 from the side facing away from the carrier 10 helps reduce the overall thickness of the packaged fan-out device and improves heat dissipation.

[0056] S204: removing the carrier board, and forming a first redistribution layer and a second redistribution layer on both sides of the conductive pillar in the length direction, respectively.

[0057] See also Figure 11 , Figure 11 This is a cross-sectional structural diagram corresponding to one embodiment of step S204. The specific implementation process of step S204 includes: removing the carrier 10, and forming a first redistribution layer 70 and a second redistribution layer 80 on both sides of the conductive pillar 32 in the longitudinal direction. In response to the electrical connection between the blocking member 22 and the first chip 100 via the second chip 200, and the electrical connection between the first redistribution layer 70 and the blocking member 22, the first redistribution layer 70 is electrically connected to at least one end of the conductive pillar 32 and the first chip 100, and the second redistribution layer 80 is electrically connected to the other end of the conductive pillar 32.

[0058] For further information, please refer to Figure 11 A first electrical connector 75 is provided on the side of the first redistribution layer 70 facing away from the conductive pillar 32, and a second electrical connector 85 is provided on the side of the second redistribution layer 80 facing away from the conductive pillar 32, to facilitate subsequent connection with a substrate or other integrated chip. Optionally, a plurality of solder balls 90 may be provided between the first redistribution layer 70 and the first electrical connector 75, and between the second redistribution layer 80 and the second electrical connector 85, to facilitate connection between the first redistribution layer 70 and the first electrical connector 75, and between the second redistribution layer 80 and the second electrical connector 85.

[0059] Of course, in another embodiment, before step S203, the first functional surface 101 of the first chip 100 faces the carrier 10. Figure 12 , Figure 12 This is a flow chart of another embodiment of the fan-out packaging method of the present application. The specific implementation process of this embodiment includes:

[0060] S301: Arrange a first chip in an area surrounded by a plurality of blocking members, and form a plastic packaging layer on a side of a carrier board where the first chip is arranged.

[0061] Specifically, see Figure 13 , Figure 13 This is a schematic cross-sectional view of an embodiment corresponding to step S301. The specific implementation process of step S301 includes: in response to the first chip 100 including a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other, the first functional surface 101 of the first chip 100 is oriented toward the carrier 10, and a plastic encapsulation layer 60 is formed on the side of the carrier 10 where the first chip 100 is disposed. The plastic encapsulation layer 60 covers the conductive pillars 32 and the gaps within the spaces enclosed by the conductive pillars 32. The plastic encapsulation layer 60 is flush with the surface of the conductive pillars 32 facing away from the carrier 10. The provision of the plastic encapsulation layer 60 provides a certain degree of fixation and protection for the first chip 100, the conductive pillars 32, and the barrier 22, and encapsulates them into a complete structure.

[0062] S302: removing the carrier board.

[0063] See also Figure 14 , Figure 14 This is a schematic cross-sectional view of an embodiment corresponding to step S302. The specific implementation process of step S302 includes: removing the carrier 10, and forming a first redistribution layer 70 and a second redistribution layer 80 on either side of the conductive pillar 32 in the longitudinal direction. A first electrical connector 75 is provided on the side of the first redistribution layer 70 facing away from the conductive pillar 32, and a second electrical connector 85 is provided on the side of the second redistribution layer 80 facing away from the conductive pillar 32. Optionally, a plurality of solder balls 90 may be provided between the first redistribution layer 70 and the first electrical connector 75, and between the second redistribution layer 80 and the second electrical connector 85.

[0064] In another embodiment, the first chip 100 may be provided first and then the first photoresist layer 20 and the second photoresist layer 30 may be formed in sequence. Figure 15 , Figure 15 This is a flow chart of another embodiment of the fan-out packaging method proposed in this application. The specific implementation process of this embodiment includes:

[0065] S401: firstly placing a first chip on a carrier board, and then forming a first photoresist layer and a second photoresist layer in sequence.

[0066] See also Figure 16 , Figure 16: This is a schematic cross-sectional view of an embodiment corresponding to step S401. Specifically, a first chip 100 is first placed on a carrier 10. The first chip 100 includes a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other. The first non-functional surface 102 of the first chip 100 faces the carrier 10. A first photoresist layer 20 and a second photoresist layer 30 are then formed on the first surface of the carrier 10. One of the first photoresist layer 20 and the second photoresist layer 30 is a positive photoresist, and the other is a negative photoresist. When the first photoresist layer 20 and the second photoresist layer 30 are formed on the first surface of the carrier 10, the side of the second photoresist layer 30 facing away from the carrier 10 is farther away from the carrier 10 than the side of the first chip 100 facing away from the carrier 10.

[0067] S402: forming a plurality of conductive pillars and a plurality of blocking members on a side of the carrier where the first chip is disposed.

[0068] See also Figure 17 , Figure 17 The cross-sectional structural diagram of an embodiment corresponding to step S402 is shown. The specific implementation process of step S402 includes: Figure 1 The method of step S102 in the above step S401 is to simultaneously expose and develop the first photoresist layer 20 and the second photoresist layer 30, and to use Figure 1 In step S103 , a plurality of conductive pillars 32 and a plurality of blocking members 22 are formed on the side of the carrier 10 where the first chip 100 is disposed, and the first photoresist layer 20 and the second photoresist layer 30 are removed.

[0069] Furthermore, after removing the first photoresist layer 20 and the second photoresist layer 30, the process further includes forming a plastic encapsulation layer on the side of the carrier 10 where the first chip 100 is provided, so that the first chip 100, the blocking member 22 and the conductive pillar 32 form an integral structure. Figure 7 The steps in will not be repeated here.

[0070] In this embodiment, step S402 may also include: simultaneously exposing and developing the first photoresist layer 20 and the second photoresist layer 30, forming a plurality of third vias in the photoresist layer covering the first functional surface 101 of the first chip 100, with each third via corresponding to a pad on the first functional surface 101 of the first chip 100. Furthermore, simultaneously forming the conductive pillars 32 in the second vias and the conductive bumps in the third vias. Since the side of the first chip 100 facing away from the substrate 10 is flush with the side of the first photoresist layer 20 facing away from the substrate 10, the third vias can be formed by exposing and developing only the second photoresist layer 30, thereby reducing the difficulty of forming the third vias. Forming the conductive bumps simultaneously with the conductive pillars 32 avoids the need to subsequently separately arrange conductive bumps on the first functional surface 101 of the first chip 100. Arranging the conductive bumps on the first functional surface 101 of the first chip 100 facilitates subsequent arrangement of a chip or a rewiring layer on the side of the first functional surface 101 of the first chip 100.

[0071] In this embodiment, step S401 may also be performed by placing the first functional surface 101 of the first chip 100 toward the carrier 10 , and then forming the first photoresist layer 20 and the second photoresist layer 30 in sequence to form the plurality of blocking members 22 and the conductive pillars 32 .

[0072] The present application forms a plurality of blocking members 22 and a plurality of conductive pillars 32 on the carrier board by arranging a first photoresist layer 20 and a second photoresist layer 30, one of which is a positive photoresist and the other is a negative photoresist, on the carrier board 10. The plurality of blocking members 22 and the plurality of conductive pillars 32 are equivalent to a cofferdam retaining wall, which helps to limit the movement of the plastic encapsulation material in the fan-out device, thereby reducing the deformation of the plastic encapsulation material due to shrinkage and reducing the probability of warping of the first chip 100. In addition, the conductive pillars 32 can also realize a three-dimensional vertical interconnection structure, which is beneficial to reducing the height of the fan-out device. The design of blocking members 22 and conductive pillars 32 of different heights can effectively save material costs.

[0073] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging method, characterized in that: include: forming a first photoresist layer and a second photoresist layer on a first surface of a carrier substrate in sequence; wherein one of the first photoresist layer and the second photoresist layer is a positive photoresist and the other is a negative photoresist; and the second photoresist layer covers a side surface of the first photoresist layer and a surface of the first photoresist layer facing away from the carrier substrate; Simultaneously exposing and developing the first photoresist layer and the second photoresist layer, forming a plurality of first via holes in the first photoresist layer and a plurality of second via holes in the second photoresist layer located on a side periphery of the first photoresist layer; wherein the height of the second via holes is greater than the height of the first via holes; forming a blocking member in the first via hole and forming a conductive pillar in the second via hole; removing the first photoresist layer and the second photoresist layer; The blocking member has a conductive property; the step of forming the blocking member in the first via hole and the step of forming the conductive column in the second via hole comprises: simultaneously filling the first via hole and the second via hole with a conductive material to form the blocking member and the conductive column; Among them, after the step of removing the first photoresist layer and the second photoresist layer, it includes: setting a first chip in the area surrounded by the multiple blocking members; forming a plastic sealing layer on the side of the carrier where the first chip is set, so that the first chip, the blocking members and the conductive columns form an integral structure; and removing the carrier.

2. The fan-out packaging method according to claim 1, wherein: Before the step of successively forming the first photoresist layer and the second photoresist layer on the first surface of the carrier, the method includes: arranging a first chip on the first surface of the carrier; wherein, when the first photoresist layer and the second photoresist layer are formed on the first surface of the carrier, the side of the second photoresist layer facing away from the carrier is farther away from the carrier than the side of the first chip facing away from the carrier; After the step of removing the first photoresist layer and the second photoresist layer, the method further comprises: forming a plastic packaging layer on a side of the carrier board where the first chip is provided, so that the first chip, the blocking member and the conductive pillar form an integral structure; Remove the carrier board.

3. The fan-out packaging method according to claim 2, wherein: The first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, and the first non-functional surface of the first chip faces the carrier board; When the first photoresist layer and the second photoresist layer are simultaneously exposed and developed, a plurality of third via holes are formed on the photoresist layer covering the first functional surface of the first chip, and one of the third via holes corresponds to a pad on the first functional surface of the first chip; A conductive bump is formed in the third via hole while a conductive column is formed in the second via hole.

4. The fan-out packaging method according to claim 3, wherein: The step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is provided includes: forming a plastic encapsulation layer on the side of the carrier board where the first chip is provided, the plastic encapsulation layer covering the conductive pillars and the gaps in the space enclosed by the conductive pillars; wherein the plastic encapsulation layer is flush with the surface of the conductive pillars on the side facing away from the carrier board.

5. The fan-out packaging method according to claim 1 or 2, wherein: The first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, and the first non-functional surface of the first chip faces the carrier board; Before the step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is disposed, the method further includes: disposing at least one second chip on a side of the first functional surface of the first chip facing away from the carrier board, and forming an underfill between at least the second functional surface of the second chip and the carrier board, with the blocking member being located within the underfill; wherein the second functional surface of the second chip faces the first functional surface of the first chip, the second chip spans at least a portion of the first chip and at least a portion of the blocking member adjacent to at least a portion of the first chip, and pads on the second functional surface of the second chip are electrically connected to pads on the first functional surface of the first chip at corresponding positions and to the blocking member; The step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is provided includes: forming the plastic encapsulation layer on the side of the carrier board where the first chip is provided, and the plastic encapsulation layer covers the conductive pillars, the second chip and the gap in the space enclosed by the conductive pillars; and grinding the plastic encapsulation layer from the side of the plastic encapsulation layer away from the carrier board so that the surfaces of the plastic encapsulation layer, the conductive pillars and the second chip on the side away from the carrier board are flush.

6. The fan-out packaging method according to claim 1 or 2, wherein: The first chip includes a first functional surface and a first non-functional surface arranged in back to back relationship, and the first functional surface of the first chip faces the carrier board; the step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged includes: forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged, the plastic encapsulation layer covering the conductive pillars and the gaps in the space enclosed by the conductive pillars; wherein the plastic encapsulation layer is flush with the surface of the conductive pillars on the side facing away from the carrier board.

7. The fan-out packaging method according to claim 1 or 2, wherein: After the step of removing the carrier board, the method further includes: A first redistribution layer and a second redistribution layer are respectively formed on both sides of the conductive pillar in the length direction; wherein the first redistribution layer is electrically connected to at least one end of the conductive pillar and the first chip, and the second redistribution layer is electrically connected to the other end of the conductive pillar; A first electrical connector is provided on a side of the first redistribution layer away from the conductive pillar, and a second electrical connector is provided on a side of the second redistribution layer away from the conductive pillar.

8. The fan-out packaging method according to claim 1 or 2, wherein: Before the step of forming a plastic sealing layer on the side of the carrier board where the first chip is provided, the method includes: Insulation glue is formed at least on the peripheries of the plurality of blocking members.

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