Gas dopant-doped deep trench superjunction high-voltage MOSFET

Abstract

The present invention discloses a manufacturing method and a superjunction MOSFET. The superjunction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type, with a deep trench formed in the epitaxial layer. The deep trench has an insulating layer with a thickness gradient formed on the surface of the deep trench. One or more regions of the epitaxial layer near the sidewalls of the deep trench are doped with a second conductivity type, where the second conductivity type is opposite to the first conductivity type. Finally, a MOSFET device structure is formed in the epitaxial layer.

Description

Technical Field

[0001] The present invention relates to a metal-oxide field effect transistor (MOSFET), and in particular to an improved super junction device and a preparation method thereof. Background Art

[0002] Integrated circuits such as microprocessors and memory devices include many metal-oxide-semiconductor field-effect transistors (MOSFETs), which provide basic switching functions for implementing logic gates, data storage, power switching, and more. Power MOSFETs are typically developed for applications requiring power switching and power amplification. In power MOSFETs, it is necessary to reduce the device's on-resistance (Rds-on) and increase its breakdown voltage (BV). In transistors, most of the breakdown voltage (BV) is supported by the drift region, which is lowly doped to provide a higher breakdown voltage (BV). However, a low-doped drift region also results in a high on-resistance (Rds-on). In other words, there is a trade-off between on-resistance (Rds-on) and breakdown voltage (BV). In fact, on-resistance (Rds-on) is proportional to 2.5 times the breakdown voltage (BV). This means that for conventional transistors, on-resistance (Rds-on) increases significantly with increasing breakdown voltage (BV).

[0003] The structure of superjunction devices has been used to provide a method to achieve low on-resistance (Rds-on) while maintaining a high off-state breakdown voltage (BV). Superjunction devices include alternating p-type and n-type doped pillars arranged in parallel and interconnected in a drift region. The alternating p-type and n-type pillars have a good charge balance. When a reverse bias voltage is applied between the drain and source, these pillars deplete each other at a relatively low voltage (i.e., horizontal depletion) to withstand a high breakdown voltage in the vertical direction. The on-resistance (Rds-on) of a superjunction device increases proportionally with the breakdown voltage (BV), which is much smaller than the increase in on-resistance of traditional semiconductor structures. Therefore, for the same high breakdown voltage (BV), the on-resistance (Rds-on) of a superjunction device can be significantly lower than that of a traditional MOSFET device (or conversely, for a given on-resistance (Rds-on), the breakdown voltage (BV) of a superjunction device can be significantly higher than that of a traditional MOSFET device).

[0004] Previous methods for manufacturing superjunction MOSFET devices involved time- and resource-intensive techniques. Generally speaking, there are two common techniques for manufacturing superjunction MOSFETs. The first involves multiple epitaxial layer deposition, with ion implantation between epitaxial layer deposition stages using a photolithographic mask to form P-type pillars. The second technique involves growing P-type epitaxial layers in trenches.

[0005] The technology for fabricating superjunction MOSFETs using ion-implanted P-type pillars into multiple epitaxial layers is expensive. This technique requires multiple epitaxial layer growth stages, masking stages, and ion implantation stages to create both the P-type and N-type pillars. The epitaxial growth and ion implantation stages are time-consuming, and with each mask, there is the risk of misalignment of the P implants due to alignment errors in the mask. Devices with misaligned P pillars are discarded, reducing the number of devices produced by the process and further increasing the cost of each device. Therefore, the multi-epilayer P-type pillar process is a very time-consuming and expensive process for manufacturing superjunction MOSFETs.

[0006] The second technique, growing P-type epitaxial layers in trenches, produces devices with suboptimal characteristics and is also very costly. This technique involves etching a deep, wide trench in the epitaxial layer and then filling it with P-type epitaxial material. The trench must be wide enough to accommodate the P-type filler. Therefore, creating devices with narrow pillars using this technique is not feasible. Furthermore, the P-type epitaxial material used to form the pillars is expensive and time-consuming to manufacture. Summary of the Invention

[0007] The present invention proposes a gas dopant doped deep trench super junction high voltage MOSFET and a preparation method thereof, which can reduce the on-resistance R ds-on , and makes super junction MOSFET fabrication more cost-effective and efficient.

[0008] In order to achieve the above object, the present invention discloses a method for preparing a super junction MOSFET, comprising:

[0009] a. preparing a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of a first conductivity type;

[0010] b. preparing a hard mask on the surface of the epitaxial layer;

[0011] c. Etching multiple deep trenches in the epitaxial layer through the hard mask;

[0012] d. doping the epitaxial layer region with a gaseous dopant of a second conductivity type near the sidewalls of the plurality of deep trenches, wherein the second conductivity type is opposite to the first conductivity type;

[0013] e. Prepare MOSFET device structure in the epitaxial layer.

[0014] Furthermore, the doping concentration of the epitaxial layer increases gradually in a direction away from the substrate.

[0015] Furthermore, the method further includes: before step d, preparing an insulating layer on each sidewall of the plurality of deep trenches.

[0016] Furthermore, the insulating layer on each sidewall of the plurality of deep trenches has a gradient thickness.

[0017] Furthermore, the insulating layer on each sidewall of the plurality of deep trenches is thinner near the bottom of the deep trench than near the top opening of the deep trench.

[0018] Furthermore, the epitaxial layer of the second conductivity type is doped to form a second conductivity type pillar in the epitaxial layer near the deep trench, and doping the epitaxial layer with the second conductivity type dopant includes using vapor phase doping.

[0019] Furthermore, the pillar portions of the second conductivity type in the epitaxial layer between adjacent deep trenches are separated by the epitaxial layer region therebetween and maintain charge balance with the epitaxial layer region.

[0020] Furthermore, the pillars of the second conductivity type in the epitaxial layer have a uniform doping concentration.

[0021] Furthermore, the method further includes: at step c), preparing a termination area trench in the epitaxial layer, wherein the termination area trench is wider than the deep trench.

[0022] Furthermore, the method further includes preparing an insulating layer and filling the termination area trench with oxide.

[0023] Furthermore, the MOSFET device structure includes a plurality of source regions and a body region on top of an epitaxial layer and a plurality of insulated gates.

[0024] Furthermore, the method further includes preparing a dielectric layer, wherein the dielectric layer forms a dielectric seal on the opening of each of the plurality of deep trenches and leaves an unfilled gap at the bottom of the trench.

[0025] The present invention also discloses a super junction MOSFET device, comprising:

[0026] a substrate heavily doped with a first conductivity type;

[0027] an epitaxial layer lightly doped with a first conductivity type on the substrate;

[0028] and multiple MOSFET device structures;

[0029] A plurality of deep trenches are formed in the epitaxial layer, wherein the deep trenches are surrounded by regions in the epitaxial layer doped with a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type.

[0030] The MOSFET device structure includes a plurality of body regions located on top of a region doped with the second conductivity type, wherein the region doped with the second conductivity type forms a pillar below the body region of the epitaxial layer;

[0031] Parts of the pillars in the epitaxial layer between adjacent deep trenches are separated by the epitaxial layer region therebetween and are charge balanced with the epitaxial layer region.

[0032] Furthermore, each of the plurality of deep trenches further includes a dielectric at an opening of the deep trench and a gap at a bottom of the deep trench.

[0033] Furthermore, the dielectric at the deep trench opening is silicon dioxide.

[0034] Furthermore, it also includes a termination area, which has a wide trench in the epitaxial layer, the wide trench is surrounded by a region doped with the second conductivity type, the region doped with the second conductivity type forms a pillar in the epitaxial layer, and the wide trench is filled with a dielectric.

[0035] Furthermore, the plurality of MOSFET device structures include a plurality of insulated gates.

[0036] Furthermore, the width of the multiple deep trenches is between 0.2 and 1 micrometers, and the regions doped with the second conductivity type extend from the bottoms of the multiple deep trenches into the epitaxial layer by 0.5 to 2 micrometers.

[0037] Furthermore, each of the plurality of deep trenches is lined with an insulating layer.

[0038] Furthermore, the plurality of deep trenches are lined with an oxide layer, and the oxide layer has a linear gradient thickness that decreases from top to bottom, with the thickness difference being between 40 and 200 angstroms.

[0039] The present invention has the following advantages:

[0040] The present invention does not require multiple epitaxial layer growth stages and mask stages for preparing super junction MOSFET devices, is time-saving and low-cost, and can quickly and economically prepare super junction MOSFET devices. The prepared super junction MOSFET devices have alternating P-type columns and N-type columns with fine spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Flowchart of an improved method for fabricating superjunction pillars in high-voltage MOSFETs.

[0042] Figure 2 Flowchart of an improved method for fabricating other MOSFET structures in superjunction high-voltage MOSFETs.

[0043] Figure 3 Flowchart of an improved method for fabricating a termination region structure in a superjunction high voltage MOSFET.

[0044] Figure 4Improved preparation method for super junction MOSFET with gradient doping n - Cross-section of the epitaxial layer substrate.

[0045] Figure 5 Cross-sectional view of a substrate with a hard mask and deep trenches in the epitaxial layer in an improved fabrication method for superjunction MOSFETs.

[0046] Figure 6 A cross-sectional view of a deep trench with an insulator on the sidewalls of the deep trench in an improved fabrication method for a super junction MOSFET.

[0047] Figure 7 A cross-sectional view of a substrate and an epitaxial layer doped with a second conductivity type pillar surrounding a deep trench in an improved method for fabricating a super junction MOSFET.

[0048] Figure 8 A cross-sectional view of a dielectric formed at the opening of a deep trench in an improved method for fabricating a superjunction MOSFET.

[0049] Figure 9 Cross-sectional view of the dielectric layer removed from the surface of the epitaxial layer in the improved fabrication method of superjunction MOSFET.

[0050] Figure 10 A cross-sectional view of a gate insulator formed over the body region and the epitaxial layer in an improved method for fabricating a superjunction MOSFET.

[0051] Figure 11 A cross-sectional view of forming a polysilicon gate through a polysilicon region mask in an improved method for fabricating a super junction MOSFET.

[0052] Figure 12 This is a cross-sectional view of forming gate polysilicon and gate dielectric, as well as gate polysilicon and gate dielectric in the termination region in an improved fabrication method for super junction MOSFET.

[0053] Figure 13 In the improved preparation method of super junction MOSFET, a comprehensive P - Type body ion implantation to form a cross-sectional view of the body region.

[0054] Figure 14 This is a cross-sectional view of a source region formed through a source region mask in an improved method for preparing a super junction MOSFET.

[0055] Figure 15 This is a cross-sectional view of the improved fabrication method for a super junction MOSFET, showing the formation of gate polysilicon, gate insulator, body region, and source region after high-temperature annealing.

[0056] Figure 16A cross-sectional view of forming source metal, gate metal, and drain metal in an improved method for fabricating a super junction MOSFET.

[0057] Figure 17 A cross-sectional view of a super junction MOSFET device. DETAILED DESCRIPTION

[0058] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact ratios, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0059] For convenience, the use of + or - after designating conductivity or net impurity carrier type (p or n) usually refers to the relative concentration of the specified type of net impurity carriers within the semiconductor material. + The material has a higher net n-type dopant (e.g., electron) concentration than the n material, and the n material has a higher net n-type dopant (e.g., electron) concentration than the n material. － The higher the carrier concentration of the material. Similarly, p + The material has a higher net p-type dopant (e.g., hole) concentration than the p-type material, and the p-type material has a higher net p-type dopant concentration than the p-type material. － It is important to note that it is the net concentration of carriers that is relevant, not necessarily the dopant content. For example, a material can be heavily doped with n-type dopants, but if the material is also heavily counterdoped with p-type dopants, the material can still have a relatively low net carrier concentration. As used herein, less than about 10 16 / cm 3 A dopant concentration greater than about 10 17 / cm 3 The dopant concentration of can be considered "heavily doped".

[0060] In order to minimize the on-resistance R ds-on Various aspects of the present invention disclose an improved method for fabricating superjunction MOSFETs and a novel configuration of the power MOSFET structure in superjunction devices. Specifically, the superjunction pillar includes a void with an oxide cap. This fabrication method provides a more cost-effective and efficient process for manufacturing superjunction MOSFETs.

[0061] The improved preparation method may generally include forming a lightly doped epitaxial layer of the first conductivity type on a heavily doped substrate of the first conductivity type. A silicon hard mask is formed on the surface of the epitaxial layer, and a deep trench is etched through the hard mask and into the epitaxial layer. An insulating layer with a thickness gradient is formed on the sidewall surface of the deep trench, and one or more regions of the epitaxial layer close to the sidewall of the deep trench are doped with a gas dopant of the second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. A MOSFET device structure is formed on or in the epitaxial layer. The method can prepare a device comprising a substrate heavily doped with the first conductivity type, an epitaxial layer lightly doped with the first conductivity type on the substrate, the epitaxial layer having a deep trench formed in the epitaxial layer, the deep trench being surrounded by a region doped with the second conductivity type in the epitaxial layer, wherein the second conductivity type is opposite to the first conductivity type, and the region doped with the second conductivity type forms a pillar in the epitaxial layer. The device may also include one or more MOSFET device structures.

[0062] Preparation method of super junction MOSFET

[0063] Figure 1 A flow chart illustrating an improved method for fabricating superjunction pillars in a high-voltage MOSFET according to various aspects of the present invention. The method begins with a substrate heavily doped with a first conductivity type. Typically, the substrate is heavily doped with a dopant of the first conductivity type, such as an N-type dopant. As shown in step 101, an epitaxial layer of the first conductivity type is formed on the substrate surface. The epitaxial layer is formed by epitaxy, or crystal growth. Figure 4 A side view of the substrate 401 and epitaxial layer 402 generated in step 101. Figure 4As shown, the epitaxial layer has a slight doping concentration gradient 403, with a lower doping concentration closer to the substrate and a higher doping concentration farther away from the substrate. The slight gradient of the epitaxial layer helps to form a uniform doping concentration column by gas diffusion. By starting with a relatively low concentration of dopant and gradually increasing the concentration as the epitaxial process continues to complete, a slight doping concentration gradient can be generated in the epitaxial process. After the epitaxial layer is formed, a hard mask is formed on the surface of the epitaxial layer as shown in step 102. The mask can be a three-layer hard mask, including a silicon nitride layer (SiN) sandwiched between two silicon dioxide (SiO2) layers. This three-layer hard mask can be formed by growing a thermal oxide layer on the surface of the epitaxial layer and then depositing a silicon nitride layer on the surface of the oxide and the back of the wafer by LPCVD. The silicon nitride layer is deposited by LPCVD in a furnace, and the silicon nitride layer is deposited on the surface and back of the silicon wafer. During the gas doping process, the silicon nitride on the back of the wafer will prevent the gas dopant from diffusing to the back of the wafer. A third oxide layer is then deposited via PECVD (plasma-enhanced CVD) only on the silicon nitride layer on top of the wafer surface, forming a three-layer oxide-nitride-oxide hard mask. The three-layer oxide-nitride-oxide hard mask advantageously resists penetration of dopant gases, thereby protecting the underlying epitaxial layers from diffusion and undesirable doping.

[0064] like Figure 5 As shown, the thickness of each layer of the oxide-nitride-oxide hard mask can vary. The thickness of the oxide layer 501 closest to the epitaxial layer 402 can be between 100 and 200 angstroms, measured from the surface of the epitaxial layer. The thickness of the nitride layer 501 can be between 1500 and 2000 angstroms, measured from the surface of the oxide layer, and the thickness of the top oxide layer can be between 4000 and 6000 angstroms, measured from the surface of the nitride layer. After forming the three oxide-nitride-oxide layers, deep trenches 504 are etched into the epitaxial layer 402 through the hard mask in step 103. The deep trenches can be formed by deep reactive ion etching (DRIE) and their depth can be between 40 and 60 microns. In some embodiments, the trench width is as narrow as possible, for example, 0.2 to 1 micron wide. The bottom of the deep trench does not reach the interface between the substrate 401 and the epitaxial layer 402. By way of example, and not limitation, there can be 3 to 10 microns of epitaxial layer between the bottom of the deep trench and the top of the substrate. The spacing between deep trenches 504 produced by DRIE may be between 2 and 10 microns.

[0065] Next, in step 104, Figure 6As shown, an oxide layer or other insulating layer 601 is formed on the surface of the deep trench 602. If the insulating layer is an oxide layer, it can be grown within the deep trench via a thermal oxidation process. The formed insulating layer 601 has a thickness gradient, wherein the thickest region of the insulating layer 601 is near the opening of the deep trench, and the thinnest region of the oxide layer is near the bottom of the deep trench. The thickness gradient of the insulating layer 601 can be linear or nearly linear, with the thickest portion of the oxide layer having a thickness of less than 300 angstroms and the thinnest portion having a thickness of greater than 60 angstroms when measured from the side of the deep trench wall. The difference between the thickest and thinnest portions of the insulating layer can be between 40 angstroms and 200 angstroms. In the case of an oxide layer such as silicon dioxide (SiO2), the insulating layer thickness gradient can be achieved by varying the temperature and pressure of the furnace during the thermal oxidation process. The temperature can vary between 1100°C and 700°C. The pressure can vary between 800 mTorr and 80 mTorr.

[0066] After forming an insulating layer in the deep trench 602 , the epitaxial layer may be doped with a second conductivity type (eg, P-type conductivity) to form a doped pillar adjacent to the deep trench in step 105 . Figure 7 A cross-sectional side view showing a substrate 401 and an epitaxial layer 702 having pillars 701 doped with a second conductivity type around a deep trench. The pillars can be formed by vapor phase doping. A hard mask is preferably selected that is not affected by the doping vapor used in the vapor phase doping to prevent doping of the top of the epitaxial layer. During the vapor phase doping process, the pressure can be varied between 20 and 200 mTorr. During the vapor phase doping process, the temperature can also be varied between 1000°C and 1000°C to 1200°C. The variation in temperature, or pressure, or both, can allow the dopants to be evenly distributed through the insulating layer to the walls and bottom of the deep trench. After the trench sidewalls are doped with gas dopants, a high temperature annealing process (1000°C to 1200°C) is performed to further drive the dopants to the designed width of the P-type column in combination with an in-situ gas doping process or a separate annealing process.

[0067] Any suitable second conductivity type dopant can be used for vapor phase doping. By way of example, and not limitation, if the epitaxial layer is doped with N-, the vapor phase dopant can be a P-type dopant, such as a boron-containing gas (e.g., diborane) or any other P-type dopant. The insulating layer also improves the uniform production of doped pillars in the epitaxial layer. The insulating layer (e.g., composed of silicon dioxide) has a thickness-dependent resistance to penetration of vapor phase dopants. Therefore, the thickness gradient of the insulating layer prevents the upper portion of the epitaxial layer near the opening in the deep trench from being doped at a higher concentration than the lower portion of the epitaxial layer near the deep trench. In addition, the slight doping gradient of the epitaxial layer can further improve the doping uniformity of the pillars. Vapor phase deposition can be used to produce pillars doped with the second conductivity type, with the second conductivity type pillars being 0.5 to 2 microns wide and 42 to 66 microns deep in the epitaxial layer. The actual doped region can extend from the bottom of the deep trench to 0.5 to 2 microns in the epitaxial layer. Outside the doped region pillars, regions of the epitaxial layer can form columns of the first conductivity type with a width between 0.5 and 2 microns. In a preferred embodiment, the second conductivity type doped region pillars between adjacent deep trenches are separated from the epitaxial layer region forming the first conductivity type quanta, and achieve substantial charge balance.

[0068] like Figure 1 As shown in step 106 in FIG. 1 , once the pillars doped with the second conductivity type hard mask are removed, a top dielectric layer can be formed on the surface of the epitaxial layer. Figure 8 As shown, a top dielectric layer 801 covers the surface of the epitaxial layer 702 and fills the opening 802 of the deep trench. The top dielectric layer 801 may leave a void or air gap 808 at the bottom of the deep trench. Generally speaking, voids or air gaps are not required in devices manufactured using trench filling. However, in devices of the type described herein, the void or air gap at the bottom of the deep trench acts as an insulator and has minimal or no effect on the function of the doped pillars. The top dielectric layer 801 may include any suitable dielectric material, such as, but not limited to, an oxide such as silicon dioxide. The top dielectric layer 801 may be formed by chemical vapor deposition, HDP (high density plasma) oxide, etc. In addition, a termination region 810 formed in the epitaxial layer 805 on the substrate 401 is shown. The termination region 810 has a termination trench 809 that is wider than the deep trench and can be formed by DRIE or other trench formation methods at the same time as the deep trench is formed. Similar to the deep trench, the termination trench 809 is surrounded by pillars 807 doped with a second conductivity type produced by vapor deposition using the same process. Unlike the deep trench, the dielectric layer 801 deposited in the termination region 810 fills the entire termination trench 809. The termination region 810 is used to separate the active region of the device containing the transistor structure from other regions of the device.

[0069] Finally, if Figure 1As shown in step 107, the dielectric layer on the surface of the epitaxial layer is removed. Figure 9 As shown, the polishing and etching process exposes the epitaxial layer 901 in the device region and the epitaxial layer in the termination region 902. The polishing and etching process also leaves dielectric at the opening of the deep trench 903, forming a dielectric plug in the deep trench and sealing the void at the bottom of the deep trench. As will be discussed below, exposing the epitaxial layer allows MOSFET device structures to be formed on the epitaxial layer and the epitaxial layer.

[0070] MOSFET device structure

[0071] like Figure 2 200a and Figure 10 As shown, after removing any remaining dielectric layer from step 107, a gate insulator layer 1213 is formed on the surface of the epitaxial layer 1010. The gate insulator 1213 can be, for example, a 400 angstrom to 1200 angstrom thick silicon dioxide (SiO2) layer that can be formed on the device surface by thermal oxide growth, chemical vapor deposition, etc. Then, as shown in FIG. Figure 2 As shown in 200b, in Figure 11 A conductive gate layer 1320 is shown formed on top of the gate insulator 1213. The gate layer 1320 can be, for example but not limited to, polycrystalline silicon (polysilicon) that is 1000 to 6000 angstroms thick.

[0072] like Figure 11 As shown, a gate mask 1211 is applied to the surface of the deposited gate layer 1320. The gate mask 1211 can be made of any type of mask material, such as a phenol, epoxy resin or acrylic resin photoresist mask or a mechanically applied mask. Then, the gate structure 1310 can be formed by plasma dry etching of the gate layer 1320 using a photoresist as a mask. After the gate structure 1310 is formed between adjacent deep trenches having edges away from the doped region pillars of the second conductivity type, the gate mask 1211 can be formed by, for example, using Figure 12 Alternatively, an insulated trench gate (not shown) may be formed in place of a planar gate.

[0073] like Figure 2 As shown in 201 , the body region is formed after creating the MOSFET gate structure 1310 . Figure 1310. The pattern of gate structure 1310 is used as a mask on the surface of epitaxial layer 1010 before ions 1013 are implanted into epitaxial layer 1010 through the open spaces in the pattern of gate structure 1310 to form body region 1014. Any doping process, such as but not limited to ion implantation, can be used to form the body region. Body region 1014 can be heavily doped with a second conductivity type dopant (e.g., a P-type dopant if the epitaxial layer is N-type) in the termination region. The termination region polysilicon gate pattern covers the entire termination silicon region to prevent implantation of the body region within epitaxial layer 1010 in the termination region, such as Figure 3 As described in 301. A high temperature (e.g., 1000°C to 1200°C) annealing process is performed to diffuse the body region 1014 below the polysilicon gate to form a body covering layer with a polysilicon structure. The body region 1014 overlaps with the top of the second conductivity type doped region pillar. After the body region is formed, a Figure 2 As an example and not as a limitation, the source region shown in 202 is Figure 14 As shown, a source mask 1111 is applied to the surface of the epitaxial layer. Similar to the gate mask 1211 discussed above, the source mask 1111 can be any type of mask, such as a phenol, epoxy, or acrylic photoresist mask or a mechanical application mask. Then, source regions 1114 can be formed in the body region 1110 by doping (e.g., implanting ions 1113) in the gaps in the source region mask 1111. Figure 15 As shown, after implantation, the source mask 1111 can be removed by plasma ashing and removal with a stripping solution or any other known mask removal technique, such as, but not limited to, planarization or polishing. The mask in the termination 1012 can also be removed at this time by similar or identical methods.

[0074] In the termination region, the termination gate mask 1212 and the termination insulator 1214 may be formed as shown in FIG. Figure 3 302 is formed. A termination insulator 1214 can be formed on top of the termination trench 809. The termination insulator 1214 can also be formed in the same process as the gate insulator layer 1213 and can be an oxide formed on the device surface by thermal oxide deposition, such as Figure 10 The terminal gate layer 1321 can be deposited by chemical vapor deposition as shown. Figure 11The gate layer 1320 shown is created in the same process. A termination gate mask 1212 can be located on top of the termination trench 809 on the termination gate layer 1321. The termination gate mask 1212 can be created in the same process as the patterning process of the gate mask 1211. The termination gate mask 1212 can be any type of mask, such as a phenol, epoxy, or acrylic photoresist mask or a mechanical application mask. After forming the termination gate 1311, the termination mask 1212 can be removed, for example, by cleaning with a removal solution.

[0075] Various aspects of the present invention include embodiments in which the gate mask 1211 and the termination gate mask 1213 are formed in different processes. Similarly, the gate insulator 1212 and the termination insulator 1214 can be formed in separate processes.

[0076] Figure 16 Figure 1 shows the formation of source contacts 1477 in the corresponding source contact holes, gate contacts 1577 in the corresponding gate contact holes, and termination contacts 1777 in the corresponding termination contact holes. Isolation layer 1366 is deposited on top of the wafer surface after the source regions are formed. A contact mask is then implemented to form the source, polysilicon, and termination contact hole patterns. A process such as Figure 2 The contact mask shown at 203 is etched with plasma dry etching to form contact holes. After dry etching, the contact mask can be removed by plasma ashing and cleaning with a removal solution or any other known mask removal technique (such as, but not limited to, planarization or polishing). Source contact 1477, gate contact 1577, and termination contact 1777 can be formed in any suitable manner. By way of example, and not limitation, a barrier layer of Ti / TiN can be formed to align the contact holes, and the remaining portion of the hole can then be filled with tungsten to form a plug (W-plug) on ​​top of the barrier layer.

[0077] The source metal layer 1466, the gate metal layer 1566 and the termination metal layer 1766 may be formed as shown in FIG. Figure 2 The contact structure shown in 204 is then formed on the surface of the device. Figure 16 As shown, a metal layer can be deposited on the surface of isolation layer 1366 and contacts 1477 and 1577, and a metal photoresist mask can be applied to the surface of the metal layer. Separate source metal layer 1466, gate metal layer 1566, and termination metal layer 1766 can be formed by plasma dry etching the metal layers through the openings in the metal mask.

[0078] Another conductive layer 1313 may be formed at the bottom of the substrate 401. The conductive layer 1313 may be a metal layer for a drain.

[0079] like Figure 17As shown, the complete device may include the formation 205 of a source contact electrode 1401 , a gate contact electrode 1402 , and a drain contact electrode 1404 .

[0080] Device

[0081] Figure 17 The figure shows a complete superjunction MOSFET device with vapor-phase doped pillars according to various aspects of the present invention. The superjunction MOSFET device includes a substrate region 1405 heavily doped with a first conductivity type, an epitaxial layer 1406 lightly doped with the first conductivity type, and superjunction pillars 1408 doped with a second conductivity type. The superjunction pillars can be 42 to 66 microns deep from the surface of the epitaxial layer. The spacing between the superjunction pillars 1408 can be 2 to 10 microns, and the spaces between the superjunction pillars form epitaxial pillars of the first conductivity type with a width of 0.5 to 2 microns. The superjunction pillars 1408 formed in the epitaxial layer leave 3 to 10 microns of epitaxial layer 1406 between the bottom of the superjunction pillars and the substrate region 1405. The superjunction pillars 1408 surround deep trenches 1409, with voids at the bottom and a dielectric 1410 at the top of the deep trenches to seal the deep trenches. The deep trench may be 40 to 60 microns deep from the epitaxial layer surface, and the superjunction pillars may extend from the deep trench into the epitaxial layer 0.5 to 2 microns. Deep trench 1409 also includes an insulator layer, such as an oxide layer, on the walls. The insulator layer on the deep trench walls has a thickness gradient, with the thickest portion near the deep trench opening and the thinnest portion at the bottom of the deep trench.

[0082] Body regions 1407 may be formed in epitaxial layer 1406 near and above the tops of superjunction pillars 1408. Body regions 1407 may contact at least one of superjunction pillars 1408 and may be more heavily doped with the second conductivity type than the superjunction pillars. Portions of the superjunction pillars below body regions 1407 between adjacent deep trenches 1409 are separated by the epitaxial layer region therebetween and are substantially charge balanced with the epitaxial layer region. Source regions 1412 may be formed in body regions 1407 and more heavily doped with the first conductivity type than the epitaxial layer. Source contacts 1401 may be formed on surfaces of source regions 1412 and body regions 1407. Formation of source contacts 1401 shorts body regions 1407 to source regions 1412. Gates 1413 may be formed on surfaces of epitaxial layer 1406. Gates 1413 may be formed between the surfaces of the body regions and may contact body regions 1407. In addition, gate 1413 may overlap the surface of source region 1412. Gate 1413 may include an insulator layer on the surface of the epitaxial layer and a metal layer on top of the insulator layer. Gate contact 1402 may be in conductive contact with gate 1413. Drain metal 1411 may be formed at the bottom of substrate region 1405, and drain contact 1404 may be in conductive contact with drain metal 1411.

[0083] The termination region includes a substrate region 1420 and an epitaxial layer region 1421. The substrate region 1420 is heavily doped with the first conductivity type, the epitaxial layer region 1421 is lightly doped with the first conductivity type, and a superjunction termination region pillar 1422 doped with the second conductivity type is formed in the epitaxial region 1421. The termination region pillar 1422 surrounds a termination region trench 1423 filled with an insulator 1423. A termination region gate 1424 can be formed on the surface of the insulator above the opening of the termination region trench 1423 and on the termination region pillar 1422.

[0084] It should be noted that the substrate region 1405, substrate region 1420, and termination region for the MOSFET device can be different portions of a common substrate. Similarly, the epitaxial layer 1406, epitaxial layer region 1421, and termination region for the MOSFET device can be different portions of a common epitaxial layer formed on a common substrate.

[0085] Various aspects of the present invention allow for rapid and economical fabrication of superjunction devices featuring fine-pitch alternating N and P columns.

[0086] Although the present invention has been described in detail with respect to certain preferred versions, various alternatives, modifications and equivalent versions may exist. Therefore, the scope of the present invention should not be determined by the above description, but rather by reference to the appended claims and all equivalents thereof. Any option (whether preferred or not) may be combined with any other option (whether preferred or not). In the following claims, unless otherwise stated, the indefinite article "a" or "an" refers to the quantity of one or more items in the following content. Unless the function is explicitly indicated by "meaning to be", the appended claims should not be considered as limitations of meaning and function. Any item that is not precisely specified for a specific function in the claims should be understood as the "meaning to be".

Claims

1. A method for preparing a super junction MOSFET, characterized in that: include: a) forming a lightly doped epitaxial layer of the first conductivity type on a heavily doped substrate of the first conductivity type; b) forming a hard mask on the surface of the epitaxial layer; c) etching a plurality of deep trenches in the epitaxial layer through the hard mask; d) doping a region of the epitaxial layer with a gaseous dopant of a second conductivity type near sidewalls of the plurality of deep trenches, wherein the second conductivity type is opposite to the first conductivity type; e) preparing a MOSFET device structure in the epitaxial layer; Before step d), an insulating layer is formed on each sidewall of the plurality of deep trenches; the insulating layer on each sidewall of the plurality of deep trenches has a gradient thickness; the insulating layer on each sidewall of the plurality of deep trenches is thinner near the bottom of the deep trench than near the top opening of the deep trench; In which, the epitaxial layer is doped with the second conductive type to form a second conductive type pillar in the epitaxial layer near the deep trench, and wherein doping the epitaxial layer with the second conductive type dopant includes using gas phase doping; the second conductive type pillar portion in the epitaxial layer between adjacent deep trenches is separated by the epitaxial layer region between them and maintains charge balance with the epitaxial layer region.

2. The method according to claim 1, wherein The doping concentration of the epitaxial layer increases gradually in a direction away from the substrate.

3. The method according to claim 1, wherein The pillars of the second conductivity type in the epitaxial layer have a uniform doping concentration.

4. The method according to claim 1, wherein Also includes: In step c), a termination trench is prepared in the epitaxial layer, wherein the termination trench is wider than the deep trench.

5. The method according to claim 4, wherein The method also includes preparing an insulating layer and filling the termination area trench with oxide.

6. The method according to claim 1, wherein The MOSFET device structure includes multiple source and body regions on top of an epitaxial layer and multiple insulated gates.

7. The method according to claim 1, wherein The method further includes forming a dielectric layer that forms a dielectric seal over the opening of each of the plurality of deep trenches and leaves an unfilled void at the bottom of the trench.

8. A super junction MOSFET device, characterized in that: include: a substrate heavily doped with a first conductivity type; an epitaxial layer lightly doped with a first conductivity type on the substrate; and multiple MOSFET device structures; A plurality of deep trenches are formed in the epitaxial layer, wherein the deep trenches are surrounded by regions in the epitaxial layer doped with a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. The MOSFET device structure includes a plurality of body regions located on top of a region doped with the second conductivity type, wherein the region doped with the second conductivity type forms a pillar below the body region of the epitaxial layer; wherein portions of the epitaxial layer pillars between adjacent deep trenches are separated by the epitaxial layer region therebetween and are charge balanced with the epitaxial layer region; Each of the multiple deep trenches is lined with an insulating layer; the multiple deep trenches are lined with an oxide layer, and the oxide layer has a linear gradient thickness that decreases from top to bottom, and the difference is between 40-200 angstroms.

9. The device according to claim 8, wherein Each of the plurality of deep trenches further includes a dielectric at an opening of the deep trench and a void at a bottom of the deep trench.

10. The device according to claim 9, wherein The dielectric at the deep trench opening is silicon dioxide.

11. The device according to claim 8, wherein The invention also includes a termination area having a wide trench in the epitaxial layer, wherein the wide trench is surrounded by a region doped with the second conductivity type, the region doped with the second conductivity type forms a pillar in the epitaxial layer, and the wide trench is filled with a dielectric.

12. The device according to claim 8, wherein The plurality of MOSFET device structures includes a plurality of insulated gates.

13. The device according to claim 8, wherein The width of the plurality of deep trenches is between 0.2 and 1 micrometers, and the region doped with the second conductivity type extends from the bottom of the plurality of deep trenches into the epitaxial layer by 0.5 to 2 micrometers.

14. The device according to claim 8, wherein The doping concentration of the epitaxial layer increases gradually in a direction away from the substrate.

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