Chip package structure and packaging method

Abstract

The application provides a chip packaging structure and a packaging method, and relates to the technical field of chip packaging. The chip packaging structure comprises a substrate, a chip one, a chip two, a film and a plastic package body. The chip one and the chip two are arranged on the substrate at intervals. The chip two is provided with a supporting column at the periphery. The supporting column is connected with the substrate. The film is arranged on the chip one, the chip two and the supporting column. The plastic package body is arranged on the side of the film far from the chip one, so that a closed cavity is formed between the chip one and the substrate. The supporting column supports the film. The supporting column is used for increasing the distance between the film and the substrate, so that the plastic package body can break through the film on the outer side of the chip two and be filled between the chip two and the substrate. The supporting column can make the plastic package body break through the film on the outer side of the chip two and be filled between the chip two and the substrate, and can prevent the plastic package body from breaking through the corresponding film of the chip one. The closed cavity at the bottom of the chip one is not polluted, the bottom of the chip two is completely filled, and the packaging quality is improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a chip packaging structure and packaging method. Background Technology

[0002] Surface acoustic wave (SAW) filters are widely used in receiver front-ends, duplexers, and receiver filters. The working principle of a SAW filter is that sound waves propagate on the surface of a chip. Utilizing the piezoelectric properties of piezoelectric materials, input and output transducers convert the input electromagnetic signal into mechanical energy. After processing, the mechanical energy is converted back into an electrical signal, thus filtering out unwanted signals and noise and improving reception quality.

[0003] To ensure proper filtering function, the functional area of ​​the filter chip must not come into contact with any material and must be designed as a cavity structure. Other non-filtering chips do not require a bottom cavity structure, and creating one at the bottom of a non-filtering chip can easily reduce product reliability. Traditional packaging methods often use a separator on the back of the filter chip to isolate the molding compound from the outside of the filter chip, thus creating a cavity structure at the bottom. This packaging method is prone to two types of failure: First, the separator may not be broken by the molding compound flow, resulting in cavities at the bottom of both the filter chip and non-filtering chips, leading to reduced product reliability. Second, the separator may be easily broken by the molding compound flow, causing contamination of the cavity structure at the bottom of the filter chip and impairing its filtering function. Summary of the Invention

[0004] The objectives of this invention include, for example, providing a chip packaging structure and packaging method that can ensure that the sealed cavity at the bottom of chip one is not contaminated, and also ensure that the molding compound between chip two and the substrate is completely filled, thereby improving packaging quality and thus improving the reception quality and reliability of the product.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a chip packaging structure, including a substrate, a first chip, a second chip, a coating film, and a molding compound. The first chip and the second chip are disposed at a distance on the substrate. A support post is provided around the second chip, and the support post is connected to the substrate. The coating film covers the first chip, the second chip, and the support post. The molding compound is disposed on the side of the coating film away from the first chip, so that a closed cavity is formed between the first chip and the substrate. The support post supports the coating film and is used to increase the distance between the coating film and the substrate, so that the molding compound can penetrate the coating film outside the second chip and fill the space between the second chip and the substrate.

[0007] In an optional embodiment, the area on the coating corresponding to the second chip is provided with a cut.

[0008] In an optional implementation, the size of the cut is at least twice the size of the encapsulated particle.

[0009] In an optional embodiment, a first solder resist layer is provided on the substrate at a position corresponding to the second chip, and a first pad is provided on the first solder resist layer. The first pad is electrically connected to the substrate, and the second chip is electrically connected to the first pad, such that the distance between the surface of the second chip away from the substrate and the substrate is greater than the distance between the surface of the first chip away from the substrate and the substrate.

[0010] In an optional embodiment, a second solder resist layer is provided on the substrate at a position corresponding to the first chip. The surface of the second solder resist layer corresponding to the first chip is flush with the surface of the first solder resist layer corresponding to the second chip, and the first solder resist layer and the second solder resist layer are continuously disposed.

[0011] In an optional embodiment, the first solder mask layer and / or the second solder mask layer are provided with grooves to expose the substrate.

[0012] In an optional embodiment, the first solder mask layer has a groove, the position of which is opposite to the position of the cut on the film. In an optional embodiment, a first support member is provided on the substrate, the first support member is disposed around the chip, the film is disposed on the first support member, and the end of the first support member away from the substrate has a groove.

[0013] In an optional embodiment, the first support member is serrated.

[0014] In an optional embodiment, the substrate is provided with a second pad, the first chip is electrically connected to the second pad, and a second support member is provided between the first chip and the substrate, the second support member being located around the second pad.

[0015] In an optional embodiment, the distance between the side of the second chip near the substrate and the substrate is greater than the distance between the surface of the first chip near the substrate and the substrate.

[0016] In an optional embodiment, the second chip has a heat dissipation layer on the side away from the substrate, and the coating is laid on the heat dissipation layer.

[0017] In an optional embodiment, the second chip has an adhesive layer on the side away from the substrate, and the heat dissipation layer is disposed on the side of the adhesive layer away from the second chip.

[0018] In an optional embodiment, the side of the second chip away from the substrate is not covered with the coating.

[0019] In an optional embodiment, the first chip, the second chip, and the support pillar are configured as component assemblies, and a plurality of component assemblies are spaced apart on the substrate. A dicing channel is provided between two adjacent component assemblies, and a support pillar is provided on the dicing channel. The film is laid on the support pillar.

[0020] In an optional implementation, the width of the cutting channel is greater than the width of the support column.

[0021] In a second aspect, the present invention provides a packaging method for fabricating a chip packaging structure as described in any of the foregoing embodiments, the method comprising:

[0022] Provide a substrate;

[0023] Support pillars are provided on the substrate;

[0024] Chip 1 and chip 2 are mounted on the substrate; wherein the support post is disposed around chip 2.

[0025] A film is laid on the substrate, wherein the film covers the first chip, the support pillar and the second chip;

[0026] A molding compound is disposed outside the coating film. The coating film is used to block the molding compound on the outside of the first chip to form a closed cavity between the first chip and the substrate. The molding compound is used to break through the coating film on the outside of the second chip. The support pillar is used to increase the distance between the coating film and the substrate in the corresponding area of ​​the second chip, so that the molding compound fills the space between the second chip and the substrate.

[0027] In an optional implementation, the step of providing a substrate includes:

[0028] A substrate is provided, wherein a second pad is provided on the substrate, and the second pad is used to connect to the chip.

[0029] A green paint layer is applied to the substrate to form a first solder resist layer at the corresponding position where the second chip is mounted, and a second solder resist layer at the corresponding position where the first chip is mounted. A first pad is provided on the first solder resist layer. The first pad is electrically connected to the substrate and is used to electrically connect to the second chip. The plane where the first pad is located is higher than the plane where the second pad is located, and / or the distance between the surface of the second chip away from the substrate and the substrate is greater than the distance between the surface of the first chip away from the substrate and the substrate.

[0030] The step of setting the support pillars on the substrate includes:

[0031] A support column and a first support member are provided on the substrate, and a groove is provided on the first support member.

[0032] In an optional embodiment, after the step of depositing the coating film on the substrate, the method further includes:

[0033] A cut is formed on the coating, the cut being located in the corresponding area of ​​the second chip, and the size of the cut is at least twice the size of the encapsulated particle.

[0034] The beneficial effects of the embodiments of the present invention include, for example:

[0035] The chip packaging structure provided in this embodiment of the invention features support pillars around chip two. These pillars support the surrounding film of chip two, increasing the distance between the film and the substrate and enhancing the surface tension of the film. This facilitates the molding compound flow breaking through the film on the outside of chip two and filling the space between chip two and the substrate, resulting in more complete filling of the bottom of chip two and improving the reliability of the chip two packaging. Simultaneously, the film is located on the back of chip one, forming a closed cavity between chip one and the substrate. This ensures that the functional areas of chip one are not contaminated, improving reception quality, resulting in high packaging quality and high reliability.

[0036] The packaging method provided in this invention ensures that the sealed cavity at the bottom of chip one is not contaminated, and also ensures that the molding compound between chip two and the substrate is completely filled, improving packaging quality and thus enhancing the product's reception quality and reliability. The packaging method is simple, highly operable, and highly efficient. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a first schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0039] Figure 2 This is a second schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0040] Figure 3 This is a third schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0041] Figure 4 This is a fourth schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0042] Figure 5 This is a fifth schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0043] Figure 6 This is a sixth schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0044] Figure 7 This is a seventh schematic diagram of a chip packaging structure provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of the main process of the packaging method provided in the embodiments of the present invention.

[0046] Icons: 100 - Chip package structure; 110 - Substrate; 111 - First solder resist layer; 113 - Second solder resist layer; 115 - First pad; 117 - Second pad; 120 - Chip 1; 121 - Enclosed cavity; 130 - Chip 2; 140 - Coating; 141 - Cutout; 150 - Molded package; 160 - Support pillar; 118 - Groove; 170 - First support member; 171 - Trench; 180 - Second support member; 191 - Heat dissipation layer; 193 - Adhesive layer; 195 - Cutting track. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0049] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0050] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0051] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0052] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0053] First Embodiment

[0054] Please refer to Figure 1 This embodiment provides a chip packaging structure 100, including a substrate 110, a first chip 120, a second chip 130, a film 140, and a molding compound 150. The first chip 120 and the second chip 130 are disposed on the substrate 110 at intervals. A support post 160 is provided around the second chip 130 and is connected to the substrate 110. The film 140 covers the first chip 120, the second chip 130, and the support post 160. The molding compound 150 is disposed on the side of the film 140 away from the first chip 120, so that a closed cavity 121 is formed between the first chip 120 and the substrate 110. The support post 160 supports the film 140 and increases the distance between the film 140 and the substrate 110, so that the molding compound 150 can penetrate the film 140 outside the second chip 130 and fill the space between the second chip 130 and the substrate 110. This packaging structure ensures a closed cavity 121 is formed at the bottom of chip 120, preventing contamination of the functional areas of chip 120 and improving product quality. Simultaneously, it ensures a more complete and intact filling of the molding compound 150 between the bottom of chip 130 and the substrate 110, improving product reliability. Chip 120 includes, but is not limited to, a surface acoustic wave (SAW) filter chip, which needs to implement filtering functionality within the closed cavity 121 structure. Chip 130 is a non-filtering chip, including, but not limited to, an antenna switch, a low-noise amplifier, a capacitor, an inductor, or other chips.

[0055] Combination Figure 2The support pillar 160 is disposed around the periphery of the second chip 130. Since the first chip 120 and the second chip 130 are spaced apart, the support pillar 160 is also located between the first chip 120 and the second chip 130. Optionally, a cutout 141 is provided on the coating 140 in the area corresponding to the second chip 130, that is, the cutout 141 of the coating 140 is located in the area corresponding to the second chip 130. It can be understood that the coating 140 area corresponding to the second chip 130 includes the coating 140 area directly opposite the second chip 130 and the coating 140 area between the support pillar 160 and the second chip 130. This arrangement weakens the strength of the coating 140 at the position of the second chip 130, making it easier for the molding flow of the molding compound 150 to break through the coating 140 corresponding to the second chip 130, so that the molding compound 150 can enter the bottom of the second chip 130, fill the gap between the second chip 130 and the substrate 110, and improve product reliability. In this embodiment, the size of the cut 141 is at least twice the size of the molded body 150 particle, which is beneficial for the molded body 150 to smoothly enter the bottom of the second chip 130.

[0056] A first solder resist layer 111 is provided on the substrate 110 at a position corresponding to the second chip 130. A first pad 115 is provided on the first solder resist layer 111, and the first pad 115 is electrically connected to the substrate 110. The second chip 130 is also electrically connected to the first pad 115, such that the distance between the surface of the second chip 130 away from the substrate 110 and the substrate 110 is greater than the distance between the surface of the first chip 120 away from the substrate 110 and the substrate 110. Optionally, a second pad 117 is provided on the substrate 110, and the first chip 120 is soldered to the second pad 117. The distance from the surface of the first pad 115 away from the substrate 110 to the substrate 110 is H1, and the distance from the surface of the second pad 117 away from the substrate 110 to the substrate 110 is H2. Due to the presence of the first solder resist layer 111, H1 is greater than H2, meaning the height of the first pad 115 is higher than the height of the second pad 117. Thus, when chip 120 and chip 2130 are of similar size, since the coating 140 is laid on the back of chip 120 and chip 2130, the distance from the coating 140 to the substrate 110 in the area of ​​chip 2130 is H3. Due to the presence of the first solder resist layer 111, H3 is the distance between the coating 140 and the first solder resist layer 111. The presence of the first solder resist layer 111 increases H1, thereby increasing the surface tension of the coating 140. This makes it easier for the molding flow of the molding compound 150 to break through the coating 140 in the area of ​​chip 2130 during molding. It is understandable that during molding, the molding fluid from the molding compound 150 impacts the gap between the bottom of the second chip 130 and the substrate 110. Due to the setting of the first solder mask layer 111, the gap between the bottom of the second chip 130 and the substrate 110 is increased, resulting in a larger impact area of ​​the molding fluid, which makes it easier for the coating 140 at the second chip 130 to crack, thereby allowing the bottom of the second chip 130 to be better filled by the molding compound 150.

[0057] Optionally, a second solder resist layer 113 is provided on the substrate 110 at the position corresponding to chip 120. The surface of the second solder resist layer 113 corresponding to chip 120 is flush with the surface of the first solder resist layer 111 corresponding to chip 230, and the first solder resist layer 111 and the second solder resist layer 113 are continuously disposed. This arrangement facilitates the placement of the solder resist layer and avoids a stepped structure formed by a portion of the substrate 110 having a solder resist layer and a portion not having one. If there is a stepped structure on the surface of the substrate 110, it will reduce the flowability of the molded package 150, easily causing the filling repacking problem and reducing the packaging quality. In this embodiment, the first solder resist layer 111 and the second solder resist layer 113 are continuously disposed and have flush surfaces, which can improve the flowability of the molded package 150 and avoid the filling repacking problem. It can be understood that since the first solder resist layer 111 and the second solder resist layer 113 are continuously disposed and have flush surfaces, that is, the area between chip 120 and chip 230 is also provided with a solder resist layer, in order to maintain the flatness and continuity of the structural surface and avoid filling repacking.

[0058] Combination Figure 3 The first solder resist layer 111 and / or the second solder resist layer 113 are provided with grooves 118 to expose the substrate 110. It is understood that the position and number of grooves 118 can be determined according to actual conditions. By creating grooves 118, the solder pads or copper layer on the substrate 110 can be exposed, or the substrate layer of the substrate 110, i.e., the bottom BT resin layer, can also be exposed; no specific limitation is made here. In this embodiment, when the groove 118 is created on the first solder resist layer 111 and the molding compound 150 is filled, the molding compound 150 fills into the groove 118, which can improve the bonding force between the molding compound 150 and the first solder resist layer 111, as well as the bonding force between the first solder resist layer 111 and the substrate layer of the substrate 110, and the bonding force between the coating 140 and the substrate layer of the substrate 110, thereby improving structural reliability, preventing structural delamination, and thus improving the bonding force between the coating 140 and the substrate 110, and the bonding force between the coating 140 and the first solder resist layer 111. Furthermore, the position of the groove 118 on the first solder resist layer 111 corresponds to the position of the cut 141 on the film 140 of the chip 2 130 region. That is, after the cut 141 is made on the film 140, for example by laser cutting, the groove 118 on the first solder resist layer 111 can be exposed from the cut 141. This arrangement can ensure that more molding compound 150 mold flow enters the groove 118, thereby improving the bonding force between the molding compound 150 and the substrate 110, and between the molding compound 150 and the first solder resist layer 111, and improving the structural reliability.

[0059] A groove 118 is formed in the second solder resist layer 113. When the molding compound 150 is filled, the molding compound 150 presses the overlay 140 into the groove 118. This improves the adhesion between the overlay 140 and the second solder resist layer 113, as well as the adhesion between the second solder resist layer 113 and the substrate layer of the substrate 110, and the adhesion between the overlay 140 and the substrate layer of the substrate 110. This enhances structural reliability, prevents structural delamination, and improves the adhesion between the overlay 140 and the substrate 110, as well as the adhesion between the overlay 140 and the first solder resist layer 111. In traditional packaging processes, after reliability testing of packaged products, structural delamination is common, leading to poor adhesion between the overlay 140 and the substrate 110.

[0060] Combination Figure 4 Optionally, a first support member 170 is provided on the substrate 110, and the first support member 170 is disposed around the chip 120. A film 140 is covered on the first support member 170, and a groove 171 is provided at the end of the first support member 170 away from the substrate 110. In this embodiment, the first support member 170 is similarly serrated. By providing the groove 171, it is beneficial to improve the bonding force between the film 140 and the second solder resist layer 113, thereby improving the bonding force between the edge of the chip 120 and the film 140, and preventing the film 140 at the edge of the chip 120 from being broken during molding. In addition, the first support member 170 can block the mold flow during molding, reduce the impact of the mold flow of the molding body 150 on the edge of the film 140, and prevent the film 140 from being broken. Optionally, the first support member 170 is disposed close to the edge of the chip 120, and its effect of blocking the mold flow is better.

[0061] In this embodiment, a second support member 180 is provided between the chip 120 and the substrate 110. The second support member 180 is located around the second pad 117, further blocking the mold flow and buffering the impact of the mold flow. This protects the coating 140 from being pushed into the bottom sidewall of the chip 120 by the mold flow from the molding compound 150, ensuring that the closed cavity 121 structure at the bottom of the chip 120 is not contaminated. Optionally, the second support member 180 is located at the bottom of the chip 120 and flush with the sidewall of the chip 120. Its blocking and buffering effect is better, further preventing the mold flow from breaking through the coating 140 and preventing the coating 140 or the mold flow from entering the closed cavity 121 at the bottom of the chip 120.

[0062] Combination Figure 5Optionally, the height of chip two 130 may be greater than the height of chip one 120, so that the distance between the film 140 on the back of chip two 130 and the substrate 110 is greater. That is, the height difference between the side surface of chip two 130 away from the substrate 110 and the substrate 110 is greater. This helps to increase the tension of the film 140, so that during molding, the mold flow of the molding compound 150 can easily break through the film 140 at the edge of chip two 130, so that the mold flow can better fill the bottom of chip two 130. It can be understood that increasing the distance between the bottom surface of chip two 130 and the substrate 110 or the first solder resist layer 111 also helps the mold flow to break through the film 140, so that the mold flow can better fill the bottom of chip two 130. Optionally, in the chip grinding step before chip mounting, the heights of chip 120 and chip 2130 can be controlled by the grinding process, and the grinding thickness of chip 120 can be controlled to be greater than that of chip 2130, so that the height of chip 2130 after grinding is greater than that of chip 120 after grinding. For example, the thickness of chip 120 after grinding is 200 micrometers, and the height of chip 2130 after grinding is 400 micrometers. With this setting, after chip mounting, the surface of chip 2130 away from the substrate 110 is higher than the surface of chip 120 away from the substrate 110, which increases the distance between the film 140 around chip 2130 and the substrate 110, thereby increasing the surface tension of the film 140, making it easier for the molding fluid of the molding compound 150 to break through the film 140 around chip 2130 and enter the bottom of chip 2130.

[0063] Combination Figure 6 In an optional embodiment, a heat dissipation layer 191 may be provided on the side of the second chip 130 away from the substrate 110, and a film 140 may be laid on the heat dissipation layer 191. The heat dissipation layer 191 may be made of materials such as metal or ceramic. The heat dissipation layer 191 not only serves to dissipate heat but also increases the distance between the film 140 and the substrate 110, thereby increasing the surface tension of the film 140. This makes it easier for the molding flow of the molding compound 150 to break through the film 140 at the edge of the second chip 130 during molding. Furthermore, an adhesive layer 193 may be provided on the side of the second chip 130 away from the substrate 110, and the heat dissipation layer 191 may be provided on the side of the adhesive layer 193 away from the second chip 130. The heat dissipation layer 191 can be bonded and fixed to the back of the second chip 130 by the adhesive layer 193. The adhesive layer 193 can also play a heat dissipation role, increase the distance between the coating 140 and the substrate 110, and increase the surface tension of the coating 140, so that the mold flow of the molding body 150 can easily break through the coating 140 at the edge of the second chip 130 during molding.

[0064] It is easy to understand that increasing the distance between the side of chip 2 130 closest to substrate 110 and substrate 110 facilitates the flow of molded material breaking through the coating 140 at the edge of chip 2 130 and entering the bottom of chip 2 130. That is, a larger gap between the bottom of chip 2 130 and substrate 110 makes it easier to break through the coating 140, allowing the molded material 150 to smoothly enter the bottom of chip 2 130 and fill it more completely. In this embodiment, the distance between the side of chip 2 130 closest to substrate 110 and substrate 110 is greater than the distance between the surface of chip 1 120 closest to substrate 110 and substrate 110. It should be noted that raising the bottom gap of chip 2 130 (the distance between the side of chip 2 130 near substrate 110 and substrate 110) or raising the height of the back of chip 2 130 can ensure that the film 140 on the outer periphery of chip 2 130 is broken through by the molding flow of encapsulant 150, which is conducive to the more complete and sufficient filling of the bottom of chip 2 130 by encapsulant 150, and improves structural reliability.

[0065] Combination Figure 7 Of course, in other alternative embodiments, the side of chip two 130 away from substrate 110 may not have a coating 140. That is, the coating 140 is selectively provided on substrate 110, and the coating 140 is only laid around chip one 120 to ensure that a closed cavity 121 is formed at the bottom of chip one 120. This also ensures that the molding compound 150 at the bottom of chip two 130 is filled more completely.

[0066] It can be understood that chip 120, chip 2130, and support post 160 are configured as component assemblies, and multiple component assemblies are spaced apart on substrate 110, with a cleaving channel 195 between adjacent component assemblies (see...). Figure 8 Support columns 160 are positioned on the cutting channel 195, and a film 140 is laid on the support columns 160. By positioning the support columns 160 on the cutting channel 195, in subsequent cutting processes, the components are separated into individual products by cutting along the cutting channel 195. This allows the support columns 160 to be removed from the structure, reducing the weight, volume, and size of individual products. Optionally, the width of the cutting channel 195 can be greater than the width of the support columns 160, allowing all support columns 160 to be removed. If there are multiple support columns 160 on the cutting channel 195, the width of the cutting channel 195 should be greater than the distance between the multiple support columns 160, so that all support columns 160 on the cutting channel 195 are removed along with the cutting channel 195.

[0067] The chip packaging structure 100 provided in this embodiment of the invention aims to ensure that the closed cavity 121 at the bottom of chip 120 is not affected, while ensuring that the molding flow of the molding compound 150 fully enters the bottom of chip 2130 and completely fills the bottom of chip 2130. Specifically, by setting support pillars 160, the surface tension of the coating 140 around chip 2 130 is increased; by setting a first solder resist layer 111, the height of the first pad 115 is raised, thereby increasing the gap at the bottom of chip 2 130 and increasing the distance between the back of chip 2 130 and the substrate 110, ensuring that the molding flow of molding compound 150 breaks through the coating 140 and enters the bottom of chip 2 130; by setting an adhesive layer 193 and a heat dissipation layer 191 on the back of chip 2 130, the distance between the back of chip 2 130 and the substrate 110 is increased, thereby increasing the surface tension of coating 140; by setting a notch 141 on coating 140, it is ensured that the molding flow of molding compound 150 breaks through coating 140 and enters the bottom of chip 2 130; by grinding chip 2 130, the gap at the bottom of chip 2 130 is increased; ensuring that the bottom of chip 2 130 is completely filled, thereby improving structural reliability. By providing a first support member 170 and a second support member 180 around the chip 120, and by providing a groove 171 on the first support member 170, the sealed cavity 121 at the bottom of the chip 120 is protected. Furthermore, the first solder resist layer 111 and the second solder resist layer 113 are continuously disposed and have flush surfaces, facilitating fabrication, improving packaging efficiency, and preventing backfilling. By creating grooves 118 in the first solder resist layer 111 and the second solder resist layer 113, the bonding force between the film 140, the substrate 110, and the solder resist layer is improved, preventing structural delamination and improving structural reliability.

[0068] It should be noted that the above-mentioned technical solutions can be combined arbitrarily without conflict or contradiction to form multiple implementation methods, so as to improve the reliability of the structure, ensure that the cavity structure at the bottom of chip 120 is not contaminated, and at the same time ensure that the bottom of chip 2130 can be fully filled with the encapsulant 150.

[0069] Second Embodiment

[0070] Combination Figure 8 This invention provides a packaging method for fabricating a chip packaging structure 100 as described in any of the foregoing embodiments. The main processes include fabricating a substrate 110, mounting the chip, vacuum coating 140, dicing the coating 140, molding, and dicing to form a single product. This packaging method mainly includes:

[0071] A substrate 110 is provided; support pillars 160 are disposed on the substrate 110; a first chip 120 and a second chip 130 are mounted on the substrate 110; wherein the support pillars 160 are disposed around the second chip 130; a film 140 is laid on the substrate 110, wherein the film 140 covers the first chip 120, the support pillars 160, and the second chip 130; a molding compound 150 is disposed outside the film 140, the film 140 is used to block the molding compound 150 from the outside of the first chip 120 to form a closed cavity 121 between the first chip 120 and the substrate 110; the molding compound 150 is used to break through the film 140 outside the second chip 130 to fill the space between the second chip 130 and the substrate 110. This ensures that the cavity structure at the bottom of the first chip 120 is not contaminated, and also ensures that the bottom of the second chip 130 is fully filled with the molding compound 150. The support pillars 160 can be made of copper pillars or laminated resin material.

[0072] Optionally, the step of providing a substrate 110 includes:

[0073] A substrate 110 is provided, and a green paint layer is coated on the substrate 110 to form a first solder resist layer 111 at the corresponding position of the second mounted chip 130 and a second solder resist layer 113 at the corresponding position of the first mounted chip 120. The first solder resist layer 111 has a first pad 115, which is electrically connected to the substrate 110 and to the second chip 130. This arrangement ensures that the distance between the surface of the second chip 130 away from the substrate 110 and the substrate 110 is greater than the distance between the surface of the first chip 120 away from the substrate 110 and the substrate 110. This arrangement helps to increase the distance between the film 140 on the back side of the second chip 130 (the side away from the substrate 110) and the substrate 110, increasing the surface tension of the film 140. The first solder resist layer 111 and the second solder resist layer 113 are continuously disposed and their surfaces are flush, avoiding uneven stepped structures and preventing problems with refilling during molding.

[0074] Optionally, support pillars 160 can be first set on the substrate 110, and then a green paint layer can be applied. The green paint layer surrounds the second pad 117, which buffers and blocks the mold flow. A first pad 115 is set on the green paint layer. The first pad 115 is electrically connected to the pads on the substrate 110 to raise the mounting position of the second chip 130.

[0075] Optionally, after applying the green paint layer, a first support member 170 is provided on the substrate 110. The first support member 170 can be disposed on the green paint layer. In this embodiment, the first support member 170 is disposed on the outer periphery of the chip 120, that is, the first support member 170 is disposed on the second solder resist layer 113. A trench 171 is provided on the first support member 170, and then a film 140 is laid on the substrate 110 using a vacuum film coating process 140. The trench 171 can increase the bonding force between the film 140 and the first support member 170, preventing the film 140 around the chip 120 from being broken.

[0076] Optionally, grooves 118 can be formed on the green paint layer, that is, grooves 118 can be formed on the first solder resist layer 111 and the second solder resist layer 113, in order to improve the bonding force with the encapsulated body 150, improve the structural reliability, and prevent structural delamination.

[0077] Following the step of laying the film 140 on the substrate 110, a notch 141 is formed on the film 140. The notch 141 is located in the corresponding area of ​​the second chip 130. The size of the notch 141 is at least twice the size of the molded encapsulant 150 particles to ensure that the molded encapsulant 150 flow can smoothly pass through the film 140 and enter the bottom of the second chip 130 during the subsequent molding process, ensuring that the bottom of the second chip 130 is completely filled by the molded encapsulant 150. It is easy to understand that if the diameter of the filled molded encapsulant 150 particles is approximately 25 micrometers, then the width of the notch 141 should be greater than 50 micrometers. The molded encapsulant 150 flow fills the cavity at the bottom of the second chip 130 through the notch 141, forming a non-cavity structure at the bottom of the second chip 130. The support pillars 160 provide support and increase the surface tension of the film 140. At the same time, it can improve the adhesion between the film 140 and the substrate 110, prevent the film 140 around the chip 120 from being torn during molding, and protect the sealed cavity 121 at the bottom of the chip 120. Of course, the cuts 141 on the film 140 can also be pre-set before being laid on the substrate 110, which is not specifically limited here.

[0078] It is understandable that the number of support columns (160) can be flexibly set according to the actual situation, and no specific limit is made here. For example Figure 1 In the schematic diagram of the cross-section shown, there are two support columns 160 on the cut surface. In other embodiments, there may be one, three, or five, etc. Cutting is performed along the cutting channel 195, the width of which is greater than the distance between the two support columns 160. That is, after cutting, the support columns 160 are removed along with the cutting channel 195, forming a product without support columns 160, which helps to reduce product weight and shrink product size and volume. Figure 8 The dashed line represents the 195mm cutting groove, and the distance between the two dashed lines represents the width of the 195mm cutting groove. Finally, the cut product is packaged, tested, and shipped to complete the process.

[0079] It is understandable that whether it is the support pillar 160 on the cutting channel 195 or the support pillar 160 around the second chip 130, the support pillar 160 is located between the first chip 120 and the second chip 130. The number of support pillars 160 can be one or more. If there are multiple support pillars 160, since the support pillars 160 protrude from the surface of the substrate 110, a structural groove is formed between two adjacent support pillars 160. When the encapsulant 150 is filled, the encapsulant 150 enters the structural groove, which can increase the bonding force between the coating 140 and the substrate 110 and further improve the reliability of the structure.

[0080] Optionally, depending on the actual process, a grinding step can be added to chip 120 before mounting chip 120; a grinding step can be added to chip 130 before mounting chip 230; a step can be added to create grooves 118 on the first solder mask layer 111 and the second solder mask layer 113; a step can be added to attach an adhesive layer 193 and a heat dissipation layer 191 to the back of chip 230; or, a film 140 can be selectively applied, without applying a film 140 to the area corresponding to chip 230. No specific limitation is made here. The above processes can also be added, deleted or combined according to the actual situation.

[0081] In this embodiment, other parts not mentioned are similar to those described in the first embodiment, and will not be repeated here.

[0082] In summary, the chip packaging structure 100 and packaging method provided by the embodiments of the present invention have the following beneficial effects:

[0083] The chip packaging structure 100 provided in this embodiment of the invention includes support pillars 160 around the second chip 130. The support pillars 160 support the film 140 surrounding the second chip 130, providing support for the film 140, increasing the distance between the film 140 and the substrate 110, and increasing the surface tension of the film 140. This allows the molding compound 150 to break through the film 140 on the outside of the second chip 130 and fill the space between the second chip 130 and the substrate 110, resulting in more complete filling of the bottom of the second chip 130 by the molding compound 150 and improving the reliability of the second chip 130 packaging. Simultaneously, the film 140 is located on the back of the first chip 120, forming a closed cavity 121 between the first chip 120 and the substrate 110, ensuring that the functional areas of the first chip 120 are not contaminated, improving reception quality, resulting in good packaging quality and high reliability. Furthermore, by raising the mounting position of chip 130, the distance between the top and / or bottom surfaces of chip 130 and the substrate 110 is increased. An adhesive layer 193 and a heat dissipation layer 191 are added to further increase the distance between the top surface of chip 130 and the substrate 110. A notch 141 is made in the film 140 of the corresponding area of ​​chip 130 to ensure that the molding flow of the molding compound 150 breaks through the film 140 of the corresponding area of ​​chip 130. A dicing channel 195 is provided between multiple spaced component combinations, and one or more support pillars 160 are provided on the dicing channel 195. This satisfies the requirement of forming a closed cavity 121 structure at the bottom of chip 120, while also forming a non-cavity structure at the bottom of chip 130. The support pillars 160 can also be removed in subsequent cutting processes.

[0084] The packaging method provided in this invention can ensure that the sealed cavity 121 at the bottom of chip 120 is not contaminated, and can also ensure that the molding compound 150 between chip 130 and substrate 110 is completely filled, thereby improving packaging quality and thus improving the signal reception quality and product reliability. The packaging method is simple, highly operable, and has high packaging efficiency.

[0085] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, The device includes a substrate, a first chip, a second chip, a film, and a molding compound. The first chip and the second chip are disposed on the substrate at intervals. The second chip has a support pillar around its periphery, which is connected to the substrate. The film covers the first chip, the second chip, and the support pillar. The molding compound is disposed on the side of the film away from the first chip, so that a closed cavity is formed between the first chip and the substrate. The support pillar supports the film and increases the distance between the film and the substrate, so that the molding compound can penetrate the film outside the second chip and fill the space between the second chip and the substrate.

2. The chip packaging structure according to claim 1, characterized in that, The area on the film corresponding to the second chip has a cut.

3. The chip packaging structure according to claim 2, characterized in that, The size of the cut is at least twice the size of the particles in the encapsulation.

4. The chip packaging structure according to claim 2, characterized in that, A first solder resist layer is provided on the substrate at a position corresponding to the second chip. A first pad is provided on the first solder resist layer. The first pad is electrically connected to the substrate. The second chip is electrically connected to the first pad, such that the distance between the surface of the second chip away from the substrate and the substrate is greater than the distance between the surface of the first chip away from the substrate and the substrate.

5. The chip packaging structure according to claim 4, characterized in that, A second solder resist layer is provided on the substrate at a position corresponding to the first chip. The surface of the second solder resist layer corresponding to the first chip is flush with the surface of the first solder resist layer corresponding to the second chip, and the first solder resist layer and the second solder resist layer are continuously disposed.

6. The chip packaging structure according to claim 5, characterized in that, The first solder mask layer and / or the second solder mask layer are provided with grooves to expose the substrate.

7. The chip packaging structure according to claim 5, characterized in that, The first solder mask layer has a groove, and the position of the groove is opposite to the position of the cut on the film.

8. The chip packaging structure according to claim 1, characterized in that, The substrate is provided with a first support member, which is located around the chip. The film is applied to the first support member, and a groove is provided at the end of the first support member away from the substrate.

9. The chip packaging structure according to claim 8, characterized in that, The first support member is serrated.

10. The chip packaging structure according to claim 8, characterized in that, The substrate has a second pad, the chip is electrically connected to the second pad, and a second support is provided between the chip and the substrate, the second support being located around the second pad.

11. The chip packaging structure according to claim 1, characterized in that, The distance between the side of the second chip closest to the substrate and the substrate is greater than the distance between the surface of the first chip closest to the substrate and the substrate.

12. The chip packaging structure according to claim 1, characterized in that, The second chip has a heat dissipation layer on the side away from the substrate, and the coating is laid on the heat dissipation layer.

13. The chip packaging structure according to claim 12, characterized in that, The second chip has an adhesive layer on the side away from the substrate, and the heat dissipation layer is located on the side of the adhesive layer away from the second chip.

14. The chip packaging structure according to claim 2, characterized in that, The incision for the coating is located in the coating area corresponding to the second chip. The coating area corresponding to the second chip includes the coating area directly opposite the second chip and the coating area between the support post and the second chip.

15. The chip packaging structure according to any one of claims 1 to 14, characterized in that, The first chip, the second chip, and the support pillar are configured as component assemblies, and multiple component assemblies are spaced apart on the substrate. A dicing channel is provided between two adjacent component assemblies, and a support pillar is provided on the dicing channel. The film is laid on the support pillar.

16. The chip packaging structure according to claim 15, characterized in that, The width of the cutting channel is greater than the width of the support column.

17. A packaging method, characterized in that, The method for fabricating a chip package structure as described in any one of claims 1 to 16 includes: Provide a substrate; Support pillars are provided on the substrate; Chip 1 and chip 2 are mounted on the substrate; wherein the support post is located on the periphery of chip 2; A film is laid on the substrate, wherein the film covers the first chip, the support pillar and the second chip; A molding compound is disposed outside the coating film. The coating film is used to block the molding compound from the outside of the first chip to form a closed cavity between the first chip and the substrate. The support pillar supports the coating film and is used to increase the distance between the coating film and the substrate in the corresponding area of ​​the second chip, so that the molding compound can break through the coating film on the outside of the second chip to fill the space between the second chip and the substrate.

18. The packaging method according to claim 17, characterized in that, The step of providing a substrate includes: A substrate is provided, wherein a second pad is provided on the substrate, and the second pad is used to connect to the chip. A green paint layer is applied to the substrate to form a first solder resist layer at the corresponding position where the second chip is mounted, and a second solder resist layer at the corresponding position where the first chip is mounted. A first pad is provided on the first solder resist layer. The first pad is electrically connected to the substrate and is used to electrically connect to the second chip. The plane where the first pad is located is higher than the plane where the second pad is located, and / or the distance between the surface of the second chip away from the substrate and the substrate is greater than the distance between the surface of the first chip away from the substrate and the substrate. The step of setting the support pillars on the substrate includes: A support column and a first support member are provided on the substrate, and a groove is provided on the first support member.

19. The packaging method according to claim 17, characterized in that, After the step of depositing the coating film on the substrate, the method further includes: A cut is formed on the coating, the cut being located in the corresponding area of ​​the second chip, and the size of the cut is at least twice the particle size of the encapsulant.

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