A single event upset hardened latch circuit

Abstract

The application discloses a single event upset hardened latch circuit, comprising a first delay element, a first inverter, a first gated inverter and a second gated inverter. When the level of a node at one end of a feedback loop formed by the first inverter and the first gated inverter in the latch is flipped by the impact of a single particle, the load delay characteristic of the first delay element can maintain the level of the node at the other end of the feedback loop unchanged, and the affected node level is restored after the ionizing radiation ends, thereby realizing single particle immunity of the latch.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a single-event upset hardened latch circuit. Background Technology

[0002] In a radiant environment, charged particles incident on a digital circuit chip induce ionizing radiation, generating a certain number of electron-hole pairs around the particle's trajectory. When enough electron-hole pairs accumulate along the particle's incident direction, the current generated by these pairs, collected by the depletion layer, causes a flip in the drain voltage level, resulting in a single-event flip (SET). When the SET occurs in combinational logic units, the voltage level recovers after the SET ends. However, when the SET occurs in sequential logic units (such as flip-flops, latches, etc.) or memory arrays, the flip is locked due to the feedback structure within the memory units, and the voltage level cannot be recovered.

[0003] As a structure with storage and memory functions in trigger circuits, latches are the core of single-event upset (SWE) hardening design for digital circuits. Hardening of latches needs to be considered to ensure that SWE can be recovered after ionizing radiation ends, thus achieving SWE immunity. Summary of the Invention

[0004] This invention solves the technical problem of how to achieve single-particle immunity in latches by providing a single-particle flip-flop reinforced latch circuit.

[0005] This invention provides the following technical solution:

[0006] A single-event upset hardened latch circuit includes a first delay element, a first inverter, a first gated inverter, and a second gated inverter;

[0007] The first inverter and the first gated inverter form a feedback loop. The first delay element is disposed between the first inverter and the first gated inverter. The first delay element has load delay characteristics.

[0008] The output terminal of the second gated inverter is connected to the input terminal of the first inverter. When the first gated inverter is turned on, the second gated inverter is turned off, and when the first gated inverter is turned off, the second gated inverter is turned on.

[0009] Preferably, the first delay element is disposed between the output terminal of the first inverter and the input terminal of the first gated inverter.

[0010] Preferably, the single-particle-flip hardened latch circuit further includes a second delay element, which has a load delay characteristic;

[0011] The second delay element is disposed between the output terminal of the first gated inverter and the input terminal of the first inverter.

[0012] Preferably, the first delay element is disposed between the output terminal of the first gated inverter and the input terminal of the first inverter.

[0013] Preferably, the single-particle-flip hardened latch circuit further includes a second delay element, which has a load delay characteristic;

[0014] The second delay element is disposed between the output terminal of the first inverter and the input terminal of the first gated inverter.

[0015] Preferably, when the first delay element is located in the branch where the first inverter is located, the second delay element is located in the branch where the first gated inverter is located; when the first delay element is located in the branch where the first gated inverter is located, the second delay element is located in the branch where the first inverter is located.

[0016] Preferably, the first delay element is a resistor;

[0017] The resistor is connected in series in the feedback loop.

[0018] Preferably, the first delay element is a capacitor;

[0019] The common terminal of the first inverter and the first gated inverter is connected to a fixed voltage level via the capacitor.

[0020] Preferably, the first delay element includes a resistor and a capacitor;

[0021] The resistor is connected in series in the feedback loop, and the signal output terminal of the resistor is connected to a fixed level via the capacitor.

[0022] Preferably, the second delay element is the same as the first delay element.

[0023] The technical solution provided by this invention has at least the following technical effects or advantages:

[0024] When the node level at one end of the feedback loop formed by the first inverter and the first gated inverter in the latch is affected by single-event radiation and the level flips, the load delay characteristic of the first delay element will keep the node level at the other end of the feedback loop unchanged. After the ionizing radiation ends, the affected node level will be restored, thus realizing the latch's single-event immunity. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a partial circuit diagram of a typical unhardened latch in an embodiment of the present invention;

[0027] Figure 2 This is another part of the circuit diagram of a typical unhardened latch in an embodiment of the present invention;

[0028] Figure 3 This is a circuit diagram of the first gated inverter and the second gated inverter in an embodiment of the present invention;

[0029] Figure 4 This is another circuit diagram of the first gated inverter and the second gated inverter in an embodiment of the present invention;

[0030] Figure 5 This is a circuit diagram of the single-particle flip-hardened latch circuit in an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of a latch reinforcement structure in an embodiment of the present invention;

[0032] Figure 7 This is another schematic diagram of the latch reinforcement structure in an embodiment of the present invention;

[0033] Figure 8 This is another schematic diagram of the latch reinforcement structure in an embodiment of the present invention;

[0034] Figure 9 This is another schematic diagram of the latch reinforcement structure in an embodiment of the present invention;

[0035] Figure 10 This is a schematic diagram of a first delay element and a second delay element in an embodiment of the present invention;

[0036] Figure 11 This is another schematic diagram of the first delay element or the second delay element in an embodiment of the present invention;

[0037] Figure 12 This is another schematic diagram of the first delay element or the second delay element in an embodiment of the present invention;

[0038] Figure 13 This is a schematic diagram of the DICE and GDICE reinforcement structures in an embodiment of the present invention. Detailed Implementation

[0039] This invention provides a single-particle flip-flop reinforced latch circuit, solving the technical problem of how to achieve single-particle immunity in latches.

[0040] To better understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0042] like Figure 1 As shown, a typical unhardened latch circuit includes a first inverter, a fourth inverter, a fifth inverter, a first gated inverter, and a second gated inverter. The input of the second gated inverter is the D terminal of the latch. The output of the second gated inverter is connected to the inputs of the first inverter and the fourth inverter, respectively. The output of the fourth inverter is the Q terminal of the latch. The output of the first inverter is also connected to the input of the fifth inverter, and the output of the fifth inverter is the Qn terminal of the latch. The output of the first inverter is also connected to the input of the first gated inverter, and the output of the first gated inverter is also connected to the input of the first inverter. The first inverter and the first gated inverter form a feedback loop.

[0043] Both the control terminals of the first and second gated inverters are connected to an external clock control signal. When the second gated inverter is on, the first gated inverter is off; when the second gated inverter is off, the first gated inverter is on. The latch can be configured such that: when the external clock control signal is high, the second gated inverter is on and the first gated inverter is off, and the latch is in the data transfer phase; when the external clock control signal is low, the second gated inverter is off and the first gated inverter is on, and the latch is in the data holding phase. Alternatively, the latch can be configured such that: when the external clock control signal is low, the second gated inverter is on and the first gated inverter is off, and the latch is in the data transfer phase; when the external clock control signal is high, the second gated inverter is off and the first gated inverter is on, and the latch is in the data holding phase. The type of latch is not limited here.

[0044] Generally, such as Figure 2As shown, a typical unhardened latch circuit also includes a second inverter and a third inverter. The input of the second inverter is connected to an external clock control signal, and its output is connected to the input of the third inverter. The output of the second inverter outputs a first clock control signal, and the output of the third inverter outputs a second clock control signal. The first and second clock control signals are used to control the on / off state of the first and second gated inverters.

[0045] For the specific circuit of the first gated inverter, such as Figure 3 As shown, the first gated inverter may include a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET. An external high-level voltage is connected to an external low-level voltage via the first, second, third, and fourth MOSFETs connected in series. The gate of the second MOSFET is connected to the gate of the third MOSFET and serves as the input terminal of the first gated inverter. The common terminal of the output terminals of the second and third MOSFETs is the output terminal of the first gated inverter. The first and second MOSFETs are PMOS transistors that conduct at low levels, while the third and fourth MOSFETs are NMOS transistors that conduct at high levels.

[0046] Figure 3 In the circuit, the gates of the first MOSFET and the fourth MOSFET together serve as the control terminals of the first gated inverter. When the gate of the first MOSFET is connected to the first clock control signal and the gate of the fourth MOSFET is connected to the second clock control signal, the latch enters the data holding stage when the external clock control signal is high. Figure 3 By modifying the circuit so that the gate of the first MOSFET is connected to the second clock control signal and the gate of the fourth MOSFET is connected to the first clock control signal, the specific circuit of the second gated inverter can be obtained. When the gate of the first MOSFET is connected to the second clock control signal and the gate of the fourth MOSFET is connected to the first clock control signal, the latch enters the data holding stage when the external clock control signal is low. Figure 3 By modifying the circuit so that the gate of the first MOSFET is connected to the first clock control signal and the gate of the fourth MOSFET is connected to the second clock control signal, the specific circuit of the second gated inverter can be obtained.

[0047] like Figure 4As shown, the first gated inverter may further include a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET. An external high-level signal is sequentially connected to an external low-level signal via the fifth and sixth MOSFETs connected in series. The gate of the fifth MOSFET is connected to the gate of the sixth MOSFET and both serve as inputs to the first gated inverter. The fifth MOSFET is a PMOS transistor that conducts at low levels, and the sixth MOSFET is an NMOS transistor that conducts at high levels. The seventh and eighth MOSFETs are connected in parallel. The common terminal of the outputs of the fifth and sixth MOSFETs is connected to the inputs of both the seventh and eighth MOSFETs. The output of the seventh MOSFET is connected to the output of the eighth MOSFET and both serve as outputs to the first gated inverter. The conduction levels of the seventh and eighth MOSFETs are opposite, and their control logic is also opposite.

[0048] Figure 4 In the circuit, the gates of the seventh and eighth MOSFETs serve together as the control terminals of the first gated inverter. When the seventh MOSFET is a PMOS, the eighth MOSFET is an NMOS; conversely, when the seventh MOSFET is an NMOS, the eighth MOSFET is a PMOS. Taking the seventh MOSFET as a PMOS and the eighth MOSFET as an NMOS as an example, when the gate of the seventh MOSFET is connected to the first clock control signal and the gate of the eighth MOSFET is connected to the second clock control signal, the latch enters the data holding stage when the external clock control signal is high. Figure 4 By modifying the circuit so that the gate of the seventh MOSFET is connected to the second clock control signal and the gate of the eighth MOSFET is connected to the first clock control signal, the specific circuit of the second gated inverter can be obtained. When the gate of the seventh MOSFET is connected to the second clock control signal and the gate of the eighth MOSFET is connected to the first clock control signal, the latch enters the data holding stage when the external clock control signal is low. Figure 4 By modifying the circuit so that the gate of the seventh MOSFET is connected to the first clock control signal and the gate of the eighth MOSFET is connected to the second clock control signal, the specific circuit of the second gated inverter can be obtained.

[0049] Since the seventh and eighth MOSFETs are turned on and off simultaneously, only one of them can be retained. If the seventh MOSFET is retained, it must be ensured that the seventh MOSFETs in the first and second gated inverters meet the following conditions: when the control signal of the seventh MOSFET in the first gated inverter is the first clock control signal, the control signal of the seventh MOSFET in the second gated inverter is the second clock control signal; when the control signal of the seventh MOSFET in the first gated inverter is the second clock control signal, the control signal of the seventh MOSFET in the second gated inverter is the first clock control signal.

[0050] A single-event upset (SWE) occurs at the connection point of the feedback loop formed by the first inverter and the first gated inverter, specifically at the connection between the output and input of the first gated inverter, or vice versa. If an SWE occurs while the latch is in the data holding phase, the feedback loop formed by the first inverter and the first gated inverter will lock the upset, preventing the voltage level from recovering.

[0051] like Figure 5 As shown, the single-event upset hardened latch circuit of this embodiment includes a conventional unhardened latch circuit and a first delay element. The first delay element is disposed between the first inverter and the first gated inverter, and the first delay element has a load delay characteristic. Figure 6 As shown, the first delay element can be disposed between the output terminal of the first inverter and the input terminal of the first gated inverter. In this case, the first delay element is used to reinforce the first inverter. Figure 7 As shown, the first delay element can also be disposed between the output terminal and the input terminal of the first gated inverter. In this case, the first delay element is used to strengthen the first gated inverter. When the node level at one end of the feedback loop formed by the first inverter and the first gated inverter is affected by single-event radiation and undergoes a level flip, the load delay characteristic of the first delay element will maintain the node level at the other end of the feedback loop unchanged. After the ionizing radiation ends, the affected node level will be restored, thus achieving single-event immunity of the latch.

[0052] Because the first delay element can only harden one of the first inverter and the first gated inverter, the effect of single-particle immunization is relatively weak. Therefore, such as Figure 8 As shown, the preferred single-event upset (SWE) hardened latch circuit in this embodiment further includes a second delay element. This second delay element also has load delay characteristics. The first delay element is disposed between the output of the first inverter and the input of the first gated inverter, and the second delay element is disposed between the output of the first gated inverter and the input of the first inverter. Thus, the first delay element hardens the first inverter, and the second delay element hardens the first gated inverter, resulting in good SWE immunity for the latch circuit. Of course, as... Figure 9 As shown, the second delay element can also be placed between the output of the first inverter and the input of the first gated inverter, and the first delay element can be placed between the output of the first gated inverter and the input of the first inverter. In this way, the first delay element can strengthen the first gated inverter, and the second delay element can strengthen the first inverter, resulting in good single-particle immunity of the latch circuit.

[0053] Experiments show that single-particle immunization is most effective when the first delay element and the second delay element are located in different branches. Specifically, when the first delay element is located in the branch containing the first inverter, the second delay element is located in the branch containing the first gated inverter; when the first delay element is located in the branch containing the first gated inverter, the second delay element is located in the branch containing the first inverter.

[0054] In this embodiment, the selection of the first delay element and the second delay element can vary. For example... Figure 10 As shown, the first and second delay elements can be resistors, which are connected in series in the feedback loop formed by the first inverter and the first gated inverter. Figure 11 As shown, the first and second delay elements can be capacitors, and the common terminal of the first inverter and the first gated inverter is connected to a fixed voltage level via a capacitor. Figure 12 As shown, the first and second delay elements may include a resistor and a capacitor. The resistor is connected in series between the first inverter and the first gated inverter in the feedback loop. The signal output terminal of the resistor is connected to a fixed voltage level via the capacitor. The fixed voltage level can be either power or ground.

[0055] Of course, this embodiment can also be achieved through methods such as Figure 13 (a) shows the DICE (Dual Inter-locked Storage Cell) or as shown in the image. Figure 13 (b) illustrates a GDICE (guard-gates DICE) structure that hardens the latch. Both DICE and GDICE are implemented by adding transmission channels and storage nodes, and employing an interlocking structure. A DICE is equivalent to a four-node storage unit; data is written to two nodes, and the levels of the other two nodes are generated by feedback, ultimately forming a four-node interlocking structure. The GDICE structure, based on the interlocking of the DICE structure, adds a pair of guard gates to each storage node. When the two inputs are different, the output has high impedance; therefore, if one of the two adjacent nodes of a node flips, its output remains unchanged. Their hardening principle is that when a node flips due to single-event radiation, the two adjacent nodes restore the node level after the ionizing radiation ends through the interlocking function. The hardening methods of DICE and GDICE, due to the addition of storage nodes and interlocking structures, increase the number of transistors in the circuit, increasing area overhead. Furthermore, when the radiation energy of the radiation environment is high or the transistor technology used in the latch is small, the interlocking structure cannot restore the node level caused by ionizing radiation, thus causing a single-event flip.

[0056] In this embodiment, only the first delay element and the second delay element are added, resulting in a small increase in area overhead. When the radiation energy of the radiation environment is high or the transistor process used in the latch is small, the delay can be increased by adjusting the load delay characteristics of the first delay element and the second delay element, i.e., increasing the load resistance or capacitance value, to achieve single-event immunity of the latch and avoid single-event upsets.

[0057] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0058] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A single-event upset hardened latch circuit, characterized in that, It includes a first delay element, a first inverter, a first gated inverter, and a second gated inverter; The first inverter and the first gated inverter form a feedback loop. The first delay element is disposed between the first inverter and the first gated inverter. The first delay element has load delay characteristics. The output of the second gated inverter is connected to the input of the first inverter. When the first gated inverter is turned on, the second gated inverter is turned off, and when the first gated inverter is turned off, the second gated inverter is turned on. The first delay element is disposed between the output terminal of the first inverter and the input terminal of the first gated inverter; or, the first delay element is disposed between the output terminal of the first gated inverter and the input terminal of the first inverter. The second delay element has a load delay characteristic; The second delay element is disposed between the output terminal of the first gated inverter and the input terminal of the first inverter; or, the second delay element is disposed between the output terminal of the first inverter and the input terminal of the first gated inverter. When the first delay element is located in the branch where the first inverter is located, the second delay element is located in the branch where the first gated inverter is located; when the first delay element is located in the branch where the first gated inverter is located, the second delay element is located in the branch where the first inverter is located.

2. The single-particle flip-hardened latch circuit as described in claim 1, characterized in that, The first delay element is a resistor; The resistor is connected in series in the feedback loop.

3. The single-particle flip-hardened latch circuit as described in claim 1, characterized in that, The first delay element is a capacitor; The common terminal of the first inverter and the first gated inverter is connected to a fixed voltage level via the capacitor.

4. The single-particle flip-hardened latch circuit as described in claim 1, characterized in that, The first delay element includes a resistor and a capacitor; The resistor is connected in series in the feedback loop, and the signal output terminal of the resistor is connected to a fixed level via the capacitor.

5. The single-particle flip-hardened latch circuit as described in claim 1, characterized in that, The second delay element is the same as the first delay element.

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