Method of writing data and non-volatile memory device

Abstract

Methods of writing data and non-volatile memory devices are disclosed. Each of a plurality of memory blocks of a non-volatile memory device is divided into two or more groups of word lines having different characteristics. Write commands are received for at least two memory blocks among the plurality of memory blocks. During a first portion time interval included in an entire write time interval for the two or more memory blocks, in response to receiving an address for one memory block among the two or more memory blocks, data write operations are performed on groups of word lines included in the one memory block. During a second other portion time interval included in the entire write time interval, in response to receiving addresses for the two or more memory blocks, data write operations are performed on groups of word lines included in the two or more memory blocks.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0159637, filed on November 25, 2020, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor memories, and more specifically, to a method of writing data to a non-volatile memory device and a non-volatile memory device for performing the method of writing data. Background Technology

[0003] Semiconductor memory is a digital electronic semiconductor device used for data storage. Semiconductor memory is generally classified into two categories based on whether it retains stored data when disconnected from power. These categories include volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data when disconnected from power, while non-volatile memory devices retain stored data. Although volatile memory devices can perform read and write operations at high speed, the content stored in them is lost during power outages. Because non-volatile memory devices retain their stored content even when power is off, they can be used to store data that needs to be permanently retained.

[0004] As the integration density of non-volatile memory devices increases, the size of a memory block within that device also increases. The input / output (I / O) efficiency of some word lines within the memory block can decrease as the block size increases. Therefore, performance variations may occur when performing data write operations on multiple memory blocks. Summary of the Invention

[0005] At least one example embodiment of this disclosure provides a method for writing data to a non-volatile memory device that can efficiently perform data write operations.

[0006] At least one example embodiment of this disclosure provides a non-volatile memory device for performing a method of writing data.

[0007] According to an example embodiment of the inventive concept, a method for writing data to a non-volatile memory device comprising a plurality of memory blocks is provided. In the method, each of the plurality of memory blocks is divided into two or more word line groups with different characteristics. Write commands are received for at least two of the plurality of memory blocks. During a first portion of a time interval encompassing the entire write time interval for the two or more memory blocks, a data write operation is performed on the word line group encompassing one of the two or more memory blocks in response to receiving an address of that memory block. During a second, additional portion of a time interval encompassing the entire write time interval, a data write operation is performed on the word line group encompassing the two or more memory blocks in response to receiving an address of that two or more memory blocks.

[0008] According to an exemplary embodiment of the inventive concept, a non-volatile memory device includes a memory cell array and control circuitry. The memory cell array includes a plurality of memory blocks. The control circuitry divides each of the plurality of memory blocks into two or more word line groups with different characteristics; receives write commands for at least two of the plurality of memory blocks; and, during a first portion of a time interval including the entire write time interval for the two or more memory blocks, performs a data write operation on the word line group included in one of the two or more memory blocks in response to receiving an address of one of the two or more memory blocks; and, during a second, other portion of a time interval including the entire write time interval, performs a data write operation on the word line group included in the two or more memory blocks in response to receiving an address of the two or more memory blocks.

[0009] According to an example embodiment of the inventive concept, a method for writing data to a non-volatile memory device is provided, the non-volatile memory device including a plurality of memory blocks. In the method, a first memory block among the plurality of memory blocks is divided into a first word line group having a first characteristic and a second word line group having a second characteristic. The second memory block among the plurality of memory blocks is divided into a third word line group having a first characteristic and a fourth word line group having a second characteristic. During a first write time interval, encompassing the entire write time interval for the first and second memory blocks, a data write operation is performed on the first select word line in response to receiving a first address included in the first word line group. During a second write time interval, encompassing the entire write time interval after the first write time interval, data write operations are performed on the second select word line and the third select word line in response to receiving a second address included in the first word line group and a third address included in the fourth word line group. During the second write time interval, in response to receiving the fourth address of the fourth select word line included in the second word line group and the fifth address of the fifth select word line included in the third word line group, a data write operation is performed on the fourth select word line and the fifth select word line. During the third write time interval, which is included in the entire write time interval after the second write time interval, in response to receiving the sixth address of the sixth select word line included in the third word line group, a data write operation is performed on the sixth select word line.

[0010] According to an exemplary embodiment of the inventive concept, a non-volatile memory device includes a memory cell array and control circuitry. The memory cell array includes a first memory block and a second memory block. The first memory block includes a first region having a first characteristic and a second region having a second characteristic. The second memory block includes a first region having the first characteristic and a second region having the second characteristic. The control circuitry is configured to: write data to the first and second regions of the first memory block during a first time period for writing to both the first and second memory blocks; write data to the first and second regions of the first and second memory blocks during a second time period of the write time interval; and write data to the first and second regions of the second memory block during a third time period of the write time interval.

[0011] In at least one embodiment, in the method of writing data to a non-volatile memory device, each memory block is divided into two or more word line groups according to its characteristics, and then the data write operation is performed by operating on the two or more memory blocks simultaneously. Alternatively, the data write operation can be performed only during a portion of the time interval by mixing word line groups included in different memory blocks and having different characteristics. Therefore, performance variations or fluctuations caused by word line characteristics can be reduced or mitigated, performance bottlenecks can be reduced or eliminated, and quality of service (QoS) degradation can be prevented. Attached Figure Description

[0012] The illustrative, non-limiting exemplary embodiments of the inventive concept will be more clearly understood from the following detailed descriptions in conjunction with the accompanying drawings.

[0013] Figure 1 This is a flowchart illustrating a method for writing data into a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0014] Figure 2 This is a block diagram illustrating a non-volatile memory device and a memory system including the non-volatile memory device according to an example embodiment of the inventive concept.

[0015] Figure 3 This is a block diagram illustrating a non-volatile memory device according to an example embodiment of the inventive concept.

[0016] Figure 4 This is a block diagram illustrating an example of a memory controller included in a memory system according to an exemplary embodiment of the inventive concept.

[0017] Figure 5 This is a block diagram illustrating a memory system according to an example embodiment of the inventive concept.

[0018] Figure 6 It is shown Figure 1 The flowchart illustrates an example of dividing each of multiple memory blocks into two or more word line groups.

[0019] Figure 7 It is used to describe Figure 6 The diagram illustrates the operation.

[0020] Figure 8 It is shown Figure 1 The flowchart illustrates examples of performing data write operations on word line groups included in one memory block and on word line groups included in two or more memory blocks.

[0021] Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I and Figure 10J It is used to describe Figure 8 The diagram illustrates the operation.

[0022] Figure 11 It is shown Figure 1 The flowchart shows another example of dividing each of multiple memory blocks into two or more word line groups.

[0023] Figure 12 It is used to describe Figure 11 The diagram illustrates the operation.

[0024] Figure 13 It is shown Figure 1 The flowchart illustrates examples of performing data write operations on word line groups included in one memory block and on word line groups included in two or more memory blocks.

[0025] Figure 14 , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F and Figure 15G It is used to describe Figure 13 The diagram illustrates the operation.

[0026] Figure 16 It is shown Figure 1 The flowchart illustrates an example of dividing each of multiple memory blocks into two or more word line groups.

[0027] Figure 17 It is used to describe Figure 16 The diagram illustrates the operation.

[0028] Figure 18 This is a flowchart illustrating a method for writing data into a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0029] Figure 19 It is shown Figure 18 A flowchart illustrating an example of updates in memory associated with information including at least two word line groups in each of multiple memory blocks.

[0030] Figure 20 This is a block diagram illustrating a storage device and a storage system including the storage device according to an example embodiment of the inventive concept.

[0031] Figure 21 This is a block diagram illustrating a data center including a storage system according to an example embodiment of the inventive concept. Detailed Implementation

[0032] The inventive concept will be described more fully with reference to the accompanying drawings, which illustrate various exemplary embodiments of the inventive concept. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals denote the same elements.

[0033] Figure 1 This is a flowchart illustrating a method for writing data into a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0034] Reference Figure 1 A method for writing data to a non-volatile memory device according to an example embodiment is performed using a non-volatile memory device comprising multiple memory blocks. Reference will be made to... Figures 2 to 5 Describes the detailed configuration of a non-volatile memory device and a memory system including the non-volatile memory device.

[0035] In the method of writing data to a non-volatile memory device according to an example embodiment, each of a plurality of memory blocks is divided into two or more word line groups with different characteristics (step S100). For example, each of the plurality of memory blocks may be connected to multiple word lines and may be divided based on multiple word lines. For example, each word line group may include at least one word line and memory cells connected thereto.

[0036] In some example embodiments, the distinct characteristics of two or more word line groups may be associated with or related to the performance (or efficiency) of each word line group or the location (or positioning) of each word line group. For example, the performance of each word line group may include programming performance or data retention performance. For example, the location of each word line group may indicate whether each word line group is arranged proximately to the edge or center of each memory block. For example, word lines of memory blocks closest to and / or furthest from the memory controller may be assigned to one word line group, and word lines located between those closest to and furthest from the memory controller may be assigned to another word line group, with the memory controller connected to the memory device. (See also...) Figure 6 The step S100 of performing grouping for each memory block is described in more detail.

[0037] Receive write commands for at least two of the multiple memory blocks (step S200). In other words, during a data write operation based on a write command, two or more memory blocks can be operated on or accessed simultaneously and / or once (or in a single operation).

[0038] During a portion of the entire write time interval (e.g., a first portion of the time interval) encompassing two or more memory blocks, in response to receiving an address of one of the two or more memory blocks, a data write operation is performed on the word line group included in one memory block (step S300). The entire write time interval represents the time interval from the start time of the data write operation for two or more memory blocks to the end time of the data write operation for two or more memory blocks.

[0039] Additionally, during a second time interval (e.g., a portion of the total write time interval excluding the first time interval), in response to receiving addresses for two or more memory blocks, a data write operation is performed on the word line group included in the two or more memory blocks (step S400). In one exemplary embodiment, the duration of the first time interval is the same as the duration of the second time interval.

[0040] In other words, in the method of writing data according to the example embodiment, when operating on two or more memory blocks simultaneously and / or at one time, only one memory block is used to perform the data write operation during a first partial time interval, and the data write operation is performed by mixing (e.g., interleaving, interleave) two or more memory blocks during a second other partial time interval, rather than mixing two or more memory blocks throughout the entire write time interval.

[0041] In one example embodiment, the data write operation in step S400 is performed on word line groups included in different memory blocks and having different characteristics. For example, the data write operation in step S400 can be performed by mixing or interleaving word line groups included in one memory block and having a first characteristic with word line groups included in another memory block and having a second characteristic different from the first characteristic. (Refer to...) Figure 6 The steps S300 and S400 for performing the data write operation are described in more detail.

[0042] In the method for writing data to a non-volatile memory device according to the example embodiment, each memory block is divided into two or more word line groups based on characteristics, and then the data write operation is performed by operating on the two or more memory blocks simultaneously. Alternatively, the data write operation is performed by mixing word line groups comprising different memory blocks and having different characteristics only during a portion of the time interval. Therefore, performance variations or fluctuations caused by word line characteristics can be reduced or mitigated, performance bottlenecks can be reduced or eliminated, and quality of service (QoS) degradation can be prevented.

[0043] Figure 2 This is a block diagram illustrating a non-volatile memory device and a memory system including the non-volatile memory device according to an example embodiment of the inventive concept.

[0044] Reference Figure 2 The memory system 10 includes a memory device 100 and a memory controller 200. The memory system 10 may support multiple channels CH1, CH2, ..., CHm, and the memory device 100 may be connected to the memory controller 200 through multiple channels CH1 to CHm. For example, the memory system 10 may be implemented as a storage device (such as a solid-state drive (SSD)).

[0045] The memory device 100 may include a plurality of non-volatile memory devices NVM11, NVM12, ..., NVM1n, NVM21, NVM22, ..., NVM2n, NVMm1, NVMm2, ..., NVMmn, where n and m are positive integers. Each of the non-volatile memory devices NVM11 to NVMmn can be connected to one of the multiple channels CH1 to CHm via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n can be connected to the first channel CH1 via paths W11, W12, ..., W1n; non-volatile memory devices NVM21 to NVM2n can be connected to the second channel CH2 via paths W21, W22, ..., W2n; and non-volatile memory devices NVMm1 to NVMmn can be connected to the m-th channel CHm via paths Wm1, Wm2, ..., Wmn. In one example embodiment, each of the non-volatile memory devices NVM11 to NVMmn is implemented as an arbitrary memory cell that operates according to individual commands from the memory controller 200. For example, each of the non-volatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, but the example embodiment is not limited thereto. For example, two or more memory blocks that are operated simultaneously according to the example embodiment may be included in a single non-volatile memory device (e.g., a chip or die).

[0046] The memory controller 200 can send signals to and receive signals from the memory device 100 through multiple channels CH1 to CHm. For example, the memory controller 200 can send commands CMDa, CMDb, ..., CMDm, addresses ADDRa, ADDRb, ..., ADDRm, and data DATAa, DATAb, ..., DATAm to the memory device 100 through channels CH1 to CHm, or it can receive data DATAa to DATAm from the memory device 100.

[0047] The memory controller 200 can select one of the non-volatile memory devices NVM11 to NVM1n connected to a given channel among channels CH1 to CHm by using a given channel, and can send signals to and receive signals from the selected non-volatile memory device. For example, the memory controller 200 can select non-volatile memory device NVM11 from the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 200 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 through the first channel CH1, or can receive data DATAa from the selected non-volatile memory device NVM11.

[0048] The memory controller 200 can send signals to and receive signals from the memory device 100 in parallel through different channels. For example, the memory controller 200 can send the command CMDb to the memory device 100 through the second channel CH2, while simultaneously sending the command CMDa to the memory device 100 through the first channel CH1. For example, the memory controller 200 can receive data DATAb from the memory device 100 through the second channel CH2, while simultaneously receiving data DATAa from the memory device 100 through the first channel CH1.

[0049] The memory controller 200 controls the overall operation of the memory device 100. The memory controller 200 can send signals to channels CH1 to CHm and can control each of the non-volatile memory devices NVM11 to NVM1n connected to channels CH1 to CHm. For example, the memory controller 200 can send command CMDa and address ADDRa to the first channel CH1 and can control a non-volatile memory device selected from NVM11 to NVM1n.

[0050] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 200. For example, non-volatile memory device NVM11 can program data DATAa based on the command CMDa, address ADDRa, and data DATAa provided from the memory controller 200 via the first channel CH1. For example, non-volatile memory device NVM21 can read data DATAb based on the command CMDb and address ADDRb provided from the memory controller 200 via the second channel CH2, and can send the read data DATAb to the memory controller 200 via the second channel CH2.

[0051] although Figure 2 An example is shown where memory device 100 communicates with memory controller 200 via m channels and includes n non-volatile memory devices corresponding to each channel. However, according to the example embodiment, the number of channels and the number of non-volatile memory devices connected to a channel may be varied.

[0052] Figure 3 This is a block diagram illustrating a non-volatile memory device according to an example embodiment of the inventive concept.

[0053] Reference Figure 3 The non-volatile memory device 500 includes a memory cell array 510, an address decoder 520, a page buffer circuit 530, a data input / output (I / O) circuit 540, a voltage generator 550, and a control circuit 560. Figure 2 The memory device 100 can be implemented using a non-volatile memory device 500.

[0054] The memory cell array 510 is connected to the address decoder 520 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 510 is also connected to the page buffer circuitry 530 via multiple bit lines (BL). The memory cell array 510 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and multiple bit lines (BL). The memory cell array 510 may be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, each memory block comprising multiple memory cells. Furthermore, each of the multiple memory blocks BLK1 to BLKz may be divided into multiple pages.

[0055] In one example embodiment, a plurality of memory cells included in memory cell array 510 are arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. The 3D vertical array structure may include a vertically oriented string of cells such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. Suitable constructions of memory cell arrays including 3D vertical array structures are described by reference to the following patent documents, all of which are incorporated herein by reference: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0056] The control circuit 560 is controlled from the outside (e.g., from...). Figure 2 The memory controller 200 receives commands CMD and address ADDR, and controls erase, program, and read operations of the non-volatile memory device 500 based on the commands CMD and address ADDR. Erasing operations may include executing an erase cycle sequence, and programming operations may include executing a programming cycle sequence. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0057] For example, control circuit 560 can generate control signal CON for controlling voltage generator 550 based on command CMD, and can generate control signal PBC for controlling page buffer circuit 530. It can also generate row address R_ADDR and column address C_ADDR based on address ADDR. Control circuit 560 can provide row address R_ADDR to address decoder 520, and can provide column address C_ADDR to data I / O circuit 540.

[0058] Control circuitry 560 may perform a method for writing data according to an example embodiment. Control circuitry 560 may include a lookup table (LUT) 570 used when performing the method for writing data according to the example embodiment. For example, lookup table 570 may include data written using... Figure 1The step S100 obtains information (e.g., word line group information) associated with two or more word line groups in each memory block. For example, the word line group information may indicate, for each memory block, which word lines are assigned to a first word line group having a first characteristic, which word lines are assigned to a second word line group having a second other characteristic, etc. In one example embodiment, the word line group information is determined when the non-volatile memory device 500 is manufactured and is pre-stored in the non-volatile memory device 500. In one example embodiment, as will be referred to... Figure 18 The word line information is updated in real time while the non-volatile memory device 500 is driven (or during operation).

[0059] In one exemplary embodiment, the control circuit 560 receives write commands for simultaneously operating two or more memory blocks BLK1 to BLKz, performing a data write operation on only one memory block during a partial write time interval, and performing a data write operation by mixing word line groups included in two or more memory blocks and having different characteristics during another partial write time interval.

[0060] Address decoder 520 can be connected to memory cell array 510 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0061] For example, in a data erase / write / read operation, the address decoder 520 can determine at least one of multiple word lines WL as the selected word line based on the row address R_ADDR, and can determine the remaining word lines in the multiple word lines WL other than the selected word line as unselected word lines.

[0062] In addition, during data erase / write / read operations, the address decoder 520 can determine at least one of the multiple string select lines SSL as the selected string select line based on the row address R_ADDR, and can determine the remaining string select lines other than the selected string select line as unselected string select lines.

[0063] Furthermore, during data erase / write / read operations, the address decoder 520 can determine at least one of the multiple ground selection lines GSL as the selected ground selection line based on the row address R_ADDR, and can determine the remaining or unselected ground selection lines in the multiple ground selection lines GSL other than the selected ground selection line as unselected ground selection lines.

[0064] Voltage generator 550 can generate the voltage VS required for the operation of non-volatile memory device 500 based on power PWR (e.g., the received power supply voltage) and control signal CON. Voltage VS can be applied to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL via address decoder 520. Additionally, voltage generator 550 can generate an erase voltage VERS for data erase operations based on power PWR and control signal CON. Eraser voltage VERS can be applied to memory cell array 510 directly or via bit line BL.

[0065] For example, during an erase operation, voltage generator 550 may apply an erase voltage VERS to the common-source line and / or bit line BL of a memory block (e.g., a selected memory block) via address decoder 520, and may apply an erase permission voltage (e.g., ground voltage) to all word lines or a portion of the word lines of the memory block. Additionally, during an erase verification operation, voltage generator 550 may apply an erase verification voltage simultaneously to all word lines of the memory block, or sequentially to the word lines one by one.

[0066] For example, during programming operations, voltage generator 550 can apply a programming voltage to the selected word line via address decoder 520, and can apply a programming pass voltage to the unselected word line. Additionally, during programming verification operations, voltage generator 550 can apply a programming verification voltage to the selected word line via address decoder 520, and can apply a verification pass voltage to the unselected word line.

[0067] Additionally, during normal read operations, voltage generator 550 can apply a read voltage to the selected word line via address decoder 520, and can also apply a read pass voltage to unselected word lines. During data recovery read operations, voltage generator 550 can apply a read voltage to the word line adjacent to the selected word line via address decoder 520, and can also apply a recovery read voltage to the selected word line.

[0068] Page buffer circuitry 530 may be connected to memory cell array 510 via multiple bit lines BL. Page buffer circuitry 530 may include multiple page buffers. In one example embodiment, each page buffer is connected to one bit line. In another example embodiment, each page buffer is connected to two or more bit lines.

[0069] Page buffer circuit 530 can store data DAT to be programmed into memory cell array 510, or can read data DAT sensed from memory cell array 510. In other words, depending on the operating mode of non-volatile memory device 500, page buffer circuit 530 can be used as a write driver or a sense amplifier.

[0070] Data I / O circuit 540 can be connected to page buffer circuit 530 via data line DL. Based on column address C_ADDR, data I / O circuit 540 can provide data DAT from outside the non-volatile memory device 500 to memory cell array 510 via page buffer circuit 530, or it can provide data DAT from memory cell array 510 to outside the non-volatile memory device 500.

[0071] Although a non-volatile memory device according to an example embodiment has been described based on a NAND flash memory device, the non-volatile memory device according to the example embodiment can be any non-volatile memory device. For example, the non-volatile memory device may include phase random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or thyristor random access memory (TRAM).

[0072] Figure 4 This is a block diagram illustrating an example of a memory controller included in a memory system according to an exemplary embodiment of the inventive concept.

[0073] Reference Figure 4 The memory controller 600 includes a processor 610, a memory (or buffer memory) 620, a flash translation layer (FTL) 630, a host interface 640 (e.g., interface circuitry), an error correction code (ECC) engine 650 (e.g., error correction circuitry), a memory interface 660 (e.g., interface circuitry), and an Advanced Encryption Standard (AES) engine 670 (e.g., logic circuitry, encryption circuitry, decryption circuitry, etc.). Figure 2 The memory controller 200 can be implemented using the memory controller 600.

[0074] Processor 610 may respond to a host device (e.g., via host interface 640) Figure 20 The host device 1100 receives commands and controls the operation of the memory controller 600. For example, the processor 610 can control the memory system (e.g., Figure 2 The operation of the memory system 10) can be controlled by using firmware to control the corresponding components to operate the memory system.

[0075] Memory 620 may store instructions and data executed and processed by processor 610. For example, memory 620 may be implemented using volatile memory with relatively small capacity and high speed, such as static random access memory (SRAM) or cache memory.

[0076] The FTL 630 can perform various functions, such as address mapping operations, wear-leveling operations, or garbage collection operations. Address mapping operations can be the translation of logical addresses received from a host device into addresses used for actually storing data in a non-volatile memory device (e.g., ...). Figure 3 The operation of physical addresses in a non-volatile memory device (500). Wear leveling operation can be a technique used to prevent excessive degradation of a particular block by allowing uniform use of multiple blocks of the non-volatile memory device. As an example, wear leveling operation can be implemented using firmware techniques that balance the erase count of physical blocks. Garbage collection operation can be a technique used to ensure available capacity in a non-volatile memory device by erasing existing blocks after copying valid data from existing blocks to new blocks.

[0077] The ECC engine 650 for error correction can use Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc., to perform coding and modulation, or can use the above codes or other error correction codes to perform ECC encoding and ECC decoding.

[0078] Host interface 640 provides a physical connection between the host device and the memory system. Host interface 640 provides an interface corresponding to the bus format of the host device for communication between the host device and the memory system. In one example embodiment, the bus format of the host device is a Small Computer System Interface (SCSI) or a Serial Attached SCSI (SAS) interface. In another example embodiment, the bus format of the host device may be a Universal Serial Bus (USB) format, a Peripheral Component Interconnect (PCI) Fast (PCIe) format, an Advanced Technology Attachment (ATA) format, a Parallel ATA (PATA) format, a Serial ATA (SATA) format, or a Non-Volatile Memory (NVM) Fast (NVMe) format.

[0079] Memory interface 660 can exchange data with non-volatile memory devices (e.g., 100, 500, etc.). Memory interface 660 can transfer data to or receive data read from a non-volatile memory device. In one example embodiment, memory interface 660 is connected to a non-volatile memory device via a single channel. In another example embodiment, memory interface 660 is connected to a non-volatile memory device via two or more channels. For example, memory interface 660 can be configured to conform to standard protocols (such as Toggle or Open NAND Flash Interface (ONFI)).

[0080] The AES engine 670 can perform at least one of encryption and decryption operations on data input to the memory controller 600 using a symmetric key algorithm. Although not shown in detail, the AES engine 670 may include an encryption module and a decryption module. In some example embodiments, the encryption and decryption modules may be implemented as separate modules or circuits. In other example embodiments, a single module or circuit capable of performing both encryption and decryption operations may be implemented within the AES engine 670.

[0081] Figure 5 This is a block diagram illustrating a memory system according to an example embodiment of the inventive concept.

[0082] Reference Figure 5 The memory system 20 includes a memory device 300 and a memory controller 400. The memory device 300 may correspond to... Figure 2 One of the non-volatile memory devices NVM11 to NVMmn, which is based on Figure 2 One of the channels CH1 to CHm in the middle is with Figure 2 The memory controller 200 communicates with the memory controller 400. The memory controller 400 may correspond to... Figure 2 The memory controller 200 in the middle.

[0083] The memory device 300 may include first to eighth pins (P11, P12, P13, P14, P15, P16, P17 and P18), a memory interface (e.g., memory interface circuitry) 310, control logic (e.g., control logic circuitry) 320 and a memory cell array 330.

[0084] The memory interface circuit 310 can receive a chip enable signal nCE from the memory controller 400 via its first pin P11. In response to the chip enable signal nCE, the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via its second pin P12 to its eighth pin P18. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via its second pin P12 to its eighth pin P18.

[0085] The memory interface circuit 310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 400 via pins P12 to P14. The memory interface circuit 310 can receive the data signal DQ from the memory controller 400 via pin P17, or can send the data signal DQ to the memory controller 400. Commands CMD, addresses ADDR, and data DATA can be sent via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals DQ.

[0086] The memory interface circuit 310 can obtain the command CMD from the data signal DQ received during the enable interval (e.g., high level state) of the command latch enable signal CLE based on the switching time of the write enable signal nWE. The memory interface circuit 310 can also obtain the address ADDR from the data signal DQ received during the enable interval (e.g., high level state) of the address latch enable signal ALE based on the switching time of the write enable signal nWE.

[0087] In one example embodiment, the write enable signal nWE is maintained in a static state (e.g., high or low) and toggles between high and low levels. For example, the write enable signal nWE may toggle during the interval in which command CMD or address ADDR is sent. Therefore, the memory interface circuitry 310 can obtain command CMD or address ADDR based on the switching time of the write enable signal nWE.

[0088] The memory interface circuit 310 can receive the read enable signal nRE from the memory controller 400 via its fifth pin P15. The memory interface circuit 310 can receive the data strobe signal DQS from the memory controller 400 via its sixth pin P16, or it can send the data strobe signal DQS to the memory controller 400.

[0089] In the data output operation of memory device 300, memory interface circuit 310 may receive a read enable signal nRE before outputting data DATA. The read enable signal nRE is switched via pin 5 P15. Memory interface circuit 310 may generate a data strobe signal DQS, which is switched based on the switching of the read enable signal nRE. For example, memory interface circuit 310 may generate data strobe signal DQS based on the switching start time of the read enable signal nRE, and data strobe signal DQS may begin switching after a predetermined delay (e.g., tDQSRE). Memory interface circuit 310 may transmit a data signal DQ including data DATA based on the switching time point of data strobe signal DQS. Therefore, data DATA may be aligned with the switching time point of data strobe signal DQS and may be sent to memory controller 400.

[0090] In the data input operation of the memory device 300, when a data signal DQ including data DATA is received from the memory controller 400, the memory interface circuit 310 can receive a switched data strobe signal DQS and the data DATA from the memory controller 400. The memory interface circuit 310 can obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit 310 can sample the data signal DQ at the rising and falling edges of the data strobe signal DQS and obtain the data DATA.

[0091] The command CMD, address ADDR, and data DATA obtained based on the write enable signal nWE and the data strobe signal DQS can correspond to the command, address, and data used to perform a data write operation according to the example embodiment.

[0092] The memory interface circuit 310 can send a ready / busy output signal nR / B to the memory controller 400 via pin 8 P18. The memory interface circuit 310 can also send status information of the memory device 300 to the memory controller 400 via the ready / busy output signal nR / B. When the memory device 300 is in a busy state (e.g., when an operation is being performed in the memory device 300), the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (e.g., when no operation is being performed in the memory device 300 or an operation has been completed), the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when the memory device 300 is reading data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 400. For example, when memory device 300 is programming data DATA into memory cell array 330 in response to a programming command, memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state to memory controller 400.

[0093] Control logic circuit 320 controls the overall operation of memory device 300. Control logic circuit 320 receives commands CMD and addresses ADDR from memory interface circuit 310. Control logic circuit 320 generates control signals for controlling other components of memory device 300 in response to the received commands CMD and addresses ADDR. For example, control logic circuit 320 generates various control signals for programming data DATA into memory cell array 330 or for reading data DATA from memory cell array 330.

[0094] The memory cell array 330 can store data DATA obtained from the memory interface circuit 310 under the control of the control logic circuit 320. The memory cell array 330 can also output the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320.

[0095] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the example embodiment is not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. In the following, examples in which the memory cells are NAND flash memory cells will be described primarily.

[0096] The memory controller 400 may include first pins to eighth pins (P21, P22, P23, P24, P25, P26, P27, and P28) and a controller interface (e.g., controller interface circuitry) 410. The first pins P21 to eighth pins P28 may correspond to the first pins P11 to P18 of the memory device 300, respectively.

[0097] The controller interface circuit 410 can send a chip enable signal nCE to the memory device 300 via the first pin P21. The controller interface circuit 410 can send signals to the memory device 300 and receive signals from the memory device 300 via the second pin P22 to the eighth pin P28, wherein the signals are selected by the chip enable signal nCE.

[0098] The controller interface circuit 410 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 300 via pins P22 to P24. The controller interface circuit 410 can send the data signal DQ to the memory device 300 or receive the data signal DQ from the memory device 300 via pin P27.

[0099] The controller interface circuit 410 can send a data signal DQ, including a command CMD or address ADDR, along with a switching write enable signal nWE to the memory device 300. The controller interface circuit 410 can also send the data signal DQ, including a command CMD, to the memory device 300 by sending a command latch enable signal CLE with an enabled state. Furthermore, the controller interface circuit 410 can send the data signal DQ, including an address ADDR, to the memory device 300 by sending an address latch enable signal ALE with an enabled state.

[0100] The controller interface circuit 410 can send the read enable signal nRE to the memory device 300 via the fifth pin P25. The controller interface circuit 410 can receive the data strobe signal DQS from the memory device 300 or send the data strobe signal DQS to the memory device 300 via the sixth pin P26.

[0101] In the data output operation of the memory device 300, the controller interface circuit 410 can generate a switching read enable signal nRE and send the read enable signal nRE to the memory device 300. For example, before the data DATA is output, the controller interface circuit 410 can generate the read enable signal nRE, which is changed from a static state (e.g., high level or low level) to a switching state. Therefore, the memory device 300 can generate a switching data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 410 can receive a data signal DQ including the data DATA along with the switching data strobe signal DQS from the memory device 300. The controller interface circuit 410 can obtain the data DATA from the data signal DQ based on the switching time of the data strobe signal DQS.

[0102] During data input operations of the memory device 300, the controller interface circuit 410 can generate a switching data strobe signal DQS. For example, before transmitting data DATA, the controller interface circuit 410 can generate the data strobe signal DQS, which changes from a static state (e.g., high or low level) to a switching state. The controller interface circuit 410 can then transmit a data signal DQ, including the data DATA, to the memory device 300 based on the switching timing of the data strobe signal DQS.

[0103] The controller interface circuit 410 can receive the ready / busy output signal nR / B from the memory device 300 via pin 8 P28. The controller interface circuit 410 can determine the status information of the memory device 300 based on the ready / busy output signal nR / B.

[0104] Figure 6 It is shown Figure 1 The flowchart illustrates an example of dividing each of multiple memory blocks into two or more word line groups. Figure 7 It is used to describe Figure 6 The diagram illustrates the operation.

[0105] Reference Figure 1 , Figure 6 and Figure 7In step S100, the first memory block BLK1 is divided into a first word line group WLG11 with a first characteristic and a second word line group WLG12a and WLG12b with a second characteristic (step S110). For example, the first memory block BLK1 may be connected to word lines WL11, WL12, WL13, WL14, WL15, WL16, WL17, WL18, WL19 and WL1A, and may include memory cells MC11, MC12, MC13, MC14, MC15, MC16, MC17, MC18, MC19 and MC1A connected to word lines WL11, WL12, WL13, WL14, WL15, WL16, WL17, WL18, WL19 and WL1A. Word lines WL13 to WL18 and memory cells MC13 to MC18 can be configured as the first word line group WLG11. Word lines WL11, WL12, WL19 and WL1A and memory cells MC11, MC12, MC19 and MC1A can be configured as the second word line groups WLG12a and WLG12b.

[0106] Additionally, the second memory block BLK2 is divided into a third word line group WLG21 with first characteristics and fourth word line groups WLG22a and WLG22b with second characteristics (step S120). For example, in the second memory block BLK2, word lines WL23, WL24, WL25, WL26, WL27 and WL28, as well as memory cells MC23, MC24, MC25, MC26, MC27 and MC28 connected to word lines WL23, WL24, WL25, WL26, WL27 and WL28, can be configured as the third word line group WLG21. Additionally, in the second memory block BLK2, word lines WL21, WL22, WL29 and WL2A, as well as memory cells MC21, MC22, MC29 and MC2A connected to word lines WL21, WL22, WL29 and WL2A, can be configured as the fourth word line group WLG22a and WLG22b.

[0107] In one example embodiment, the first and second characteristics are determined based on the programming performance of the word lines (e.g., programming speed and / or programming time). For example, the first word line group WLG11 and the third word line group WLG21 may include word lines with programming performance higher than a reference programming performance (or a first reference value). The second word line groups WLG12a and WLG12b and the fourth word line groups WLG22a and WLG22b may include word lines with programming performance lower than or equal to the reference programming performance.

[0108] In another example embodiment, the first and second characteristics are determined based on the data retention performance of the word lines. For example, the first word line group WLG11 and the third word line group WLG21 may include word lines with data retention performance higher than a reference data retention performance (or a second reference value). The second word line groups WLG12a and WLG12b and the fourth word line groups WLG22a and WLG22b may include word lines with data retention performance lower than or equal to the reference data retention performance.

[0109] In one example embodiment, the first and second characteristics are determined based on the position of word lines within the memory block. For example, the second word line groups WLG12a and WLG12b and the fourth word line groups WLG22a and WLG22b may include edge word lines (e.g., word lines arranged adjacent to the edges of the first memory block BLK1 and the second memory block BLK2). The first word line group WLG11 and the third word line group WLG21 may include center word lines (e.g., word lines arranged adjacent to the center of the first memory block BLK1 and the second memory block BLK2).

[0110] However, the inventive concept is not limited thereto, and the conditions and / or criteria used to determine the first and second characteristics may be varied depending on the example embodiments.

[0111] In one example embodiment, the number of bits of data stored in memory cells included in word line groups WLG11 and WLG21 having a first characteristic is different from the number of bits of data stored in memory cells included in word line groups WLG12a, WLG12b, WLG22a, and WLG22b having a second characteristic. For example, if the first characteristic is a superior characteristic to the second characteristic, then the memory cells included in word line groups WLG11 and WLG21 (e.g., memory cells MC13 to MC18 and MC23 to MC28) are three-level cells (TLC) (e.g., each cell stores three bits of data), and the memory cells included in word line groups WLG12a, WLG12b, WLG22a, and WLG22b (e.g., memory cells MC11, MC12, MC19, MC1A, MC21, MC22, MC29, and MC2A) are multi-level cells (MLC). In one embodiment, a TLC is replaced by a multi-level cell (MLC) storing two bits of data. However, the example embodiment is not limited thereto.

[0112] In one example embodiment, step S100 is performed once during the manufacture of the non-volatile memory device, and word line group information is stored in a lookup table (e.g., Figure 3 In the lookup table 570). In this example, when the non-volatile memory device is driven after the manufacturing process, step S100 can be replaced by loading the word line group information stored in the lookup table.

[0113] Figure 8 It is shown Figure 1 The flowchart illustrates examples of performing data write operations on word line groups included in one memory block and on word line groups included in two or more memory blocks. Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I and Figure 10J It is used to describe Figure 8 The diagram illustrates the operation.

[0114] Reference Figure 1 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I and Figure 10J In steps S300 and S400, the entire write time interval for the first memory block BLK1 and the second memory block BLK2 includes the first write time interval TW1, the second write time interval TW2 and the third write time interval TW3.

[0115] In the following description, an example embodiment will be given based on the premise that the first word line group WLG11 and the third word line group WLG21 have relatively good characteristics, while the second word line groups WLG12a and WLG12b and the fourth word line groups WLG22a and WLG22b have relatively poor or undesirable characteristics. In other words, data is written separately to the first word line group WLG11 or the third word line group WLG21 without mixing with another word line group, and data is written to the second word line groups WLG12a and WLG12b or the fourth word line groups WLG22a and WLG22b when mixing with another word line group, to prevent performance degradation. Furthermore, an example embodiment will be described based on the premise that two word lines are selected and data write operations are performed on the selected two word lines during a unit interval. Figure 10A In the subsequent illustrations, word lines and memory cells selected and written during a unit interval are partially shown by slanted shading.

[0116] In step S300, during the first write time interval TW1, the first addresses A13, A14, A15, and A16, including the first select word lines WL13 to WL16 in the first word line group WLG11, are received (step S310), and a data write operation is performed on the first select word lines WL13 to WL16 and the memory cells MC13 to MC16 connected to the first select word lines WL13 to WL16 based on the first addresses A13 to A16 (step S320). For example, as Figure 10B As shown, data write operations can be performed on word lines WL13 and WL14 and memory cells MC13 and MC14 during a unit interval. Subsequently, as... Figure 10C As shown, data write operations can be performed on word lines WL15, WL16 and memory cells MC15, MC16 during a unit interval.

[0117] In step S400, during the second write time interval TW2, the second addresses A17 and A18 of the second selected word lines WL17 and WL18 in the first word line group WLG11 and the third addresses A21 and A22 of the third selected word lines WL21 and WL22 in the fourth word line group WLG22a are received (step S410), and a data write operation is performed on the second selected word lines WL17 and WL18 and the third selected word lines WL21 and WL22 based on the second addresses A17 and A18 and the third addresses A21 and A22 (step S420). For example, as Figure 10D As shown, data write operations are performed on word lines WL17 and WL21 and memory cells MC17 and MC21 during a unit interval. Subsequently, as... Figure 10E As shown, data write operations are performed on word lines WL18 and WL22 and memory cells MC18 and MC22 during a unit interval. For example, two addresses in the word line group of the first memory block BLK1 with a first characteristic are received, and two addresses in the second memory block BLK2 with a second other characteristic are received; during the first time period of the second write time interval TW2, the position of the first memory block BLK1 corresponding to the first address of the two addresses of the first memory block BLK1 is written, and the position of the second memory block BLK2 corresponding to the first address of the two addresses of the second memory block BLK2 is written; and during the second time period after the first time period of the second write time interval TW2, the position of the first memory block BLK1 corresponding to the second address of the two addresses of the first memory block BLK1 is written, and the position of the second memory block BLK2 corresponding to the second address of the two addresses of the second memory block BLK2 is written.

[0118] Additionally, during the second write time interval TW2, the fourth addresses A19 and A1A of the fourth select word lines WL19 and WL1A in the second word line group WLG12b and the fifth addresses A23 and A24 of the fifth select word lines WL23 and WL24 in the third word line group WLG21 are received (step S430), and a data write operation is performed on the fourth select word lines WL19 and WL1A and the fifth select word lines WL23 and WL24 based on the fourth addresses A19 and A1A and the fifth addresses A23 and A24 (step S440). For example, as Figure 10F As shown, data write operations can be performed on word lines WL19 and WL23 and memory cells MC19 and MC23 during a unit interval. Subsequently, as... Figure 10G As shown, data write operations can be performed on word lines WL1A and WL24 and memory cells MC1A and MC24 within a unit interval. For example, two additional addresses in the word line group with the second characteristic of the first memory block BLK1 are received, and two additional addresses with the first characteristic of the second memory block BLK2 are received; during the third time period after the second time period of the second write time interval TW2, the position of the first memory block BLK1 corresponding to the first address of the two additional addresses of the first memory block BLK1 is written, and the position of the second memory block BLK2 corresponding to the first address of the two additional addresses of the second memory block BLK2 is written; during the fourth time period after the third time period of the second write time interval TW2, the position of the first memory block BLK1 corresponding to the second address of the two additional addresses of the first memory block BLK1 is written, and the position of the second memory block BLK2 corresponding to the second address of the two additional addresses of the second memory block BLK2 is written.

[0119] In one example embodiment, during the second write time interval TW2, the first memory block BLK1 and the second memory block BLK2 are accessed alternately. For example, the second addresses A17 to the fourth address A1A of the first memory block BLK1 and the third addresses A21 to the fifth address A24 of the second memory block BLK2 may be received alternately (e.g., in the order of A17, A21, A18, A22, A19, A23, A1A and A24).

[0120] In step S300, during the third write time interval TW3, the sixth addresses A25, A26, A27, and A28 of the sixth select word lines WL25, WL26, WL27, and WL28 included in the third word line group WLG21 are received (step S330), and a data write operation is performed on the sixth select word lines WL25 to WL28 based on the sixth addresses A25 to A28 (step S340). For example, as Figure 10H As shown, data write operations are performed on word lines WL25 and WL26 and memory cells MC25 and MC26 during a unit interval. Subsequently, as... Figure 10I As shown, data write operations can be performed on word lines WL27 and WL28 and memory cells MC27 and MC28 within a unit interval. For example, four addresses of the word line group with the first characteristic of the second memory block BLK2 are received; during the first time period of the third write time interval TW3, the positions of the second memory block BLK2 corresponding to the first two addresses of the four addresses are written; during the second time period after the first time period of the third write time interval TW3, the positions of the second memory block BLK2 corresponding to the last two addresses of the four addresses are written.

[0121] Because each memory block is accessed sequentially from the first word line to the last word line, it may be difficult to apply the word line mixing scheme to the first accessed second word line group WLG12a in the first memory block BLK1 and the last accessed fourth word line group WLG22b in the second memory block BLK2. Therefore, as Figure 10A As shown, during the initial operation time (e.g., in the early part of the first write time interval TW1), addresses A11 and A12 of word lines WL11 and WL12 included in the second word line group WLG12a are received, and data write operations are performed on word lines WL11 and WL12 and memory cells MC11 and MC12 based on addresses A11 and A12. Similarly, as Figure 10J As shown, during the final operation time (e.g., in the later part of the third write time interval TW3), addresses A29 and A2A of word lines WL29 and WL2A included in the fourth word line group WLG22b are received, and data write operations are performed on word lines WL29 and WL2A and memory cells MC29 and MC2A based on addresses A29 and A2A.

[0122] Figure 11 It is shown Figure 1 The flowchart shows another example of dividing each of multiple memory blocks into two or more word line groups. Figure 12 It is used to describe Figure 11 The diagram illustrates the operation. (The text then abruptly shifts to a seemingly unrelated topic: "Omitting and...") Figure 6 and Figure 7 Repeated description.

[0123] Reference Figure 1 , Figure 11 and Figure 12 In step S100, steps S110 and S120 can be respectively connected with... Figure 6 Steps S110 and S120 are basically the same.

[0124] The third memory block BLK3 is divided into a fifth word line group WLG31 with a first characteristic and a sixth word line group WLG32a and WLG32b with a second characteristic (step S130). For example, in the third memory block BLK3, word lines WL33, WL34, WL35, WL36, WL37 and WL38, as well as memory cells MC33, MC34, MC35, MC36, MC37 and MC38 connected to word lines WL33, WL34, WL35, WL36, WL37 and WL38, can be configured as the fifth word line group WLG31. Additionally, in the third memory block BLK3, word lines WL31, WL32, WL39, and WL3A, as well as memory cells MC31, MC32, MC39, and MC3A connected to word lines WL31, WL32, WL39, and WL3A, can be configured as the sixth word line group WLG32a and WLG32b.

[0125] Figure 13 It is shown Figure 1 The flowchart illustrates examples of performing data write operations on word line groups included in one memory block and on word line groups included in two or more memory blocks. Figure 14 , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F and Figure 15G It is used to describe Figure 13 The diagram illustrates the operation. (The text then abruptly shifts to a seemingly unrelated topic: "Omitting and...") Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I and Figure 10J Repeated description.

[0126] Reference Figure 13 , Figure 14 , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F and Figure 15GIn steps S300 and S400, the entire write time interval for the first memory block, the second memory block, and the third memory blocks BLK1 to BLK3 includes the first write time interval TW1, the second write time interval TW2, the third write time interval TW3', the fourth write time interval TW4, and the fifth write time interval TW5.

[0127] The operations in the first write time interval, the second write time interval, and the third write time intervals TW1 to TW3' can be referenced. Figure 8 , Figure 9 as well as Figures 10A to 10H The described operations are basically the same. For ease of explanation, in Figure 14 The first write time interval TW1 and the second write time interval TW2 are omitted.

[0128] In step S400, during the fourth write time interval TW4, the seventh addresses A27 and A28 of the seventh select word lines WL27 and WL28 included in the third word line group WLG21, and the eighth addresses A31 and A32 of the eighth select word lines WL31 and WL32 included in the sixth word line group WLG32a are received (step S450), and a data write operation is performed on the seventh select word lines WL27 and WL28 and the eighth select word lines WL31 and WL32 based on the seventh addresses A27 and A28 and the eighth addresses A31 and A32 (step S460). For example, as Figure 15A As shown, data write operations are performed on word lines WL27 and WL31 and memory cells MC27 and MC31 during a unit interval. Subsequently, as... Figure 15B As shown, data write operations are performed on word lines WL28 and WL32 and memory cells MC28 and MC32 during a unit interval.

[0129] Additionally, during the fourth write time interval TW4, the ninth addresses A29 and A2A of the ninth select word lines WL29 and WL2A in the fourth word line group WLG22b, and the tenth addresses A33 and A34 of the tenth select word lines WL33 and WL34 in the fifth word line group WLG31 are received (step S470), and a data write operation is performed on the ninth select word lines WL29 and WL2A and the tenth select word lines WL33 and WL34 based on the ninth addresses A29 and A2A and the tenth addresses A33 and A34 (step S480). For example, as Figure 15C As shown, data write operations are performed on word lines WL29 and WL33 and memory cells MC29 and MC33 during a unit interval. Subsequently, as... Figure 15DAs shown, data write operations are performed on word lines WL2A and WL34 and memory cells MC2A and MC34 during a unit interval.

[0130] In one example embodiment, during the fourth write time interval TW4, the second memory block BLK2 and the third memory block BLK3 are accessed alternately.

[0131] In step S300, during the fifth write time interval TW5, the eleventh addresses A35, A36, A37, and A38, including the eleventh select word lines WL35, WL36, WL37, and WL38 in the fifth word line group WLG31, are received (step S350), and a data write operation is performed on the eleventh select word lines WL35 to WL38 based on the eleventh addresses A35 to A38 (step S360). For example, as Figure 15E As shown, data write operations are performed on word lines WL35 and WL36 and memory cells MC35 and MC36 during a unit interval. Subsequently, as... Figure 15F As shown, data write operations are performed on word lines WL37 and WL38 and memory cells MC37 and MC38 during a unit interval.

[0132] like Figure 15G As shown, during the final operation time, the addresses A39 and A3A of word lines WL39 and WL3A included in the sixth word line group WLG32b are received, and data write operations are performed on word lines WL39 and WL3A and memory cells MC39 and MC3A based on addresses A39 and A3A.

[0133] Figure 16 It is shown Figure 1 The flowchart illustrates an example of dividing each of multiple memory blocks into two or more word line groups. Figure 17 It is used to describe Figure 16 The diagram illustrates the operation. (The text then abruptly shifts to a seemingly unrelated topic: "Omitting and...") Figure 6 and Figure 7 Repeated description.

[0134] Reference Figure 1 , Figure 16 and Figure 17In step S100, the first memory block BLK1' is divided into a first word line group WLG11' with a first characteristic, a second word line group WLG12a' and WLG12b' with a second characteristic, and a third word line group WLG13a' and WLG13b' with a third characteristic (step S115). For example, in the first memory block BLK1', word lines WL15 to WL18 and memory cells MC15 to MC18 can be set as the first word line group WLG11', word lines WL13, WL14, WL19 and WL1A and memory cells MC13, MC14, MC19 and MC1A can be set as the second word line group WLG12a' and WLG12b', and word lines WL11, WL12, WL1B and WL1C and memory cells MC11, MC12, MC1B and MC1C can be set as the third word line group WLG13a' and WLG13b'.

[0135] Additionally, the second memory block BLK2' is divided into a fourth word line group WLG21' with first characteristics, a fifth word line group WLG22a' and WLG22b' with second characteristics, and a sixth word line group WLG23a' and WLG23b' with third characteristics (step S125). For example, in the second memory block BLK2', word lines WL25 to WL28 and memory cells MC25 to MC28 can be configured as the fourth word line group WLG21', word lines WL23, WL24, WL29 and WL2A and memory cells MC23, MC24, MC29 and MC2A can be configured as the fifth word line group WLG22a' and WLG22b', and word lines WL21, WL22, WL2B and WL2C and memory cells MC21, MC22, MC2B and MC2C can be configured as the sixth word line group WLG23a' and WLG23b'.

[0136] The word line blending scheme according to the example embodiment can be applied in various ways. Figure 17 The memory blocks BLK1' and BLK2'.

[0137] Although example embodiments have been described based on two or three memory blocks and / or two or three word line groups within each memory block, the inventive concept is not limited thereto. For example, the number of memory blocks and / or the number of word line groups may be varied according to the example embodiments. Furthermore, although example embodiments have been described based on examples where the configurations of the memory blocks (e.g., the configurations of the word line groups) are all identical, the inventive concept is not limited thereto. For example, word line groups having the same characteristics and included in different memory blocks may include different numbers of word lines.

[0138] Figure 18This is a flowchart illustrating a method for writing data to a non-volatile memory device according to an exemplary embodiment of the inventive concept. (The remaining text is omitted.) Figure 1 Repeated description.

[0139] Reference Figure 18 In the method for writing data to a non-volatile memory device according to the example embodiment, steps S100, S200, S300, and S400 can be respectively connected with... Figure 1 Steps S100, S200, S300 and S400 are basically the same.

[0140] Update the information associated with at least two word line groups in each of the multiple memory blocks (step S500). For example, a lookup table (e.g., word line group information) including information (e.g., word line group information). Figure 3 The lookup table 570 in the table can be updated in real time while the non-volatile memory device is being driven or during runtime.

[0141] Figure 19 It is shown Figure 18 The flowchart illustrates an example of how updates are associated with information included in multiple memory blocks and at least two word line groups in each memory block. This information can identify, for each memory block, which word line group the corresponding memory block belongs to (e.g., a word line group with a first characteristic or a second characteristic).

[0142] Reference Figure 18 and Figure 19 In step S500, the number of program / erase (P / E) cycles is obtained for each memory block (step S510), and the number of P / E cycles is compared with a reference number (step S520).

[0143] When the number of P / E cycles is greater than the reference number (step S520: "Yes"), the configuration of two or more word line groups included in the corresponding memory block is changed (step S530). For example, if a portion of a memory block belongs to a first word line group with relatively good characteristics (e.g., a first characteristic), and the number of P / E cycles for that portion exceeds the reference number, then that portion or its word lines may be moved to a second word line group with a second other characteristic. When the number of P / E cycles is less than or equal to the reference number (step S520: "No"), the configuration of two or more word line groups included in the corresponding memory block is maintained (step S540). For example, the above operation may be repeated periodically and / or every predetermined number of P / E cycles.

[0144] As will be understood by those skilled in the art, the inventive concept can be implemented as a system, method, computer program product, and / or a computer program product implemented on one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be any tangible medium that may include or store a program used by or in conjunction with an instruction execution system, apparatus, or device. For example, a computer-readable medium can be a non-transitory computer-readable medium.

[0145] Figure 20 This is a block diagram illustrating a storage device and a storage system including the storage device according to an example embodiment of the inventive concept.

[0146] Reference Figure 20 The storage system 1000 includes a host device 1100 and a storage device 1200.

[0147] The host device 1100 controls the overall operation of the storage system 1000. Although Figure 20 Although not shown, host device 1100 may include a host processor and host memory. The host processor can control the operation of host device 1100. For example, the host processor can execute an operating system (OS). Host memory can store instructions and / or data executed and / or processed by the host processor. For example, the operating system executed by the host processor may include a file system for file management and device drivers for controlling peripheral devices including storage device 1200 at the operating system level.

[0148] Storage device 1200 is accessed by host device 1100. Storage device 1200 includes storage controller 1210 (e.g., control circuitry), multiple non-volatile memories (NVMs) 1220a, 1220b and 1220c and buffer memory 1230.

[0149] The storage controller 1210 can control the operation of the storage device 1200 and / or the operation of multiple non-volatile memories 1220a, 1220b, and 1220c based on commands and data received from the host device 1100. The multiple non-volatile memories 1220a, 1220b, and 1220c can store multiple data. For example, the multiple non-volatile memories 1220a, 1220b, and 1220c can store metadata or various user data. The buffer memory 1230 can store instructions and / or data executed and / or processed by the storage controller 1210, and can temporarily store data stored or to be stored in the multiple non-volatile memories 1220a, 1220b, and 1220c. This can be implemented in the form of the storage device 1200. Figure 2 The memory system 10 and / or Figure 5 The memory system 20. For example, the memory controller 1210 may correspond to... Figure 2 The memory controller 200 and / or Figure 5 The memory controller 400 in the memory, and the non-volatile memories 1220a, 1220b and 1220c can correspond to Figure 2 The memory device 100 and / or Figure 5 The memory device 300 in the middle.

[0150] In some example embodiments, storage device 1200 may be a solid-state drive (SSD), universal flash memory (UFS), multimedia card (MMC), or embedded multimedia card (eMMC). In other example embodiments, storage device 1200 may be one of a secure digital card (SD), microSD card, memory stick, chip card, universal serial bus (USB) card, smart card, and compact flash memory (CF) card.

[0151] Figure 21 This is a block diagram illustrating a data center including a storage system according to an example embodiment of the inventive concept.

[0152] Reference Figure 21 Data center 3000 can be a facility that collects various types of data and provides various services, and can be referred to as a data storage center. Data center 3000 can be a system for operating search engines and databases, and can be a computing system used by a company (such as a bank) or government agency. Data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently according to example embodiments, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may differ from each other.

[0153] Application server 3100 may include at least one processor 3110 and at least one memory 3120, and storage server 3200 may include at least one processor 3210 and at least one memory 3220. The operation of storage server 3200 will be described as an example. Processor 3210 may control the overall operation of storage server 3200 and may access memory 3220 to execute instructions and / or data loaded in memory 3220. Memory 3220 may include at least one of Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), Dual In-line Memory Module (DIMM), Optane DIMM, Non-Volatile DIMM (NVDIMM), etc. The number of processors 3210 and the number of memories 3220 included in storage server 3200 may be selected differently depending on the example embodiments. In some example embodiments, processor 3210 and memory 3220 may be provided as a processor-memory pair. In some example embodiments, the number of processors 3210 and the number of memories 3220 may differ from each other. Processors 3210 may include single-core or multi-core processors. The above description of storage server 3200 can be similarly applied to application server 3100. Application server 3100 may include at least one storage device 3150, and storage server 3200 may include at least one storage device 3250. In some example embodiments, application server 3100 does not include storage device 3150. The number of storage devices 3250 included in storage server 3200 may be selected differently depending on the example embodiments.

[0154] Application servers 3100 to 3100n and storage servers 3200 to 3200m can communicate with each other via network 3300. Network 3300 can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission, and optical switches providing high performance and / or high availability can be used. Depending on the access scheme of network 3300, storage servers 3200 to 3200m can be configured as file storage devices, block storage devices, or object storage devices.

[0155] In some example embodiments, network 3300 may be a storage-only network or a network dedicated to storage (such as a Storage Area Network (SAN)). For example, the SAN may be an FC-SAN using an FC network and implemented according to the FC protocol (FCP). In another example, the SAN may be an IP-SAN using a Transmission Control Protocol / Internet Protocol (TCP / IP) network and implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In other example embodiments, network 3300 may be a general-purpose network or a normal network (such as a TCP / IP network). For example, network 3300 may be implemented according to at least one of protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and Non-Volatile Memory Fast (NVMe) over a Network (NVMe-oF).

[0156] In the following description, an example embodiment will be based on application server 3100 and storage server 3200. The description of application server 3100 can be applied to another application server 3100n, and the description of storage server 3200 can be applied to another storage server 3200m.

[0157] Application server 3100 can store data requested by users or clients to one of storage servers 3200 to 3200m via network 3300. Additionally, application server 3100 can retrieve data requested by users or clients from one of storage servers 3200 to 3200m via network 3300. For example, application server 3100 can be implemented as a web server or a database management system (DBMS).

[0158] Application server 3100 can access memory 3120n or storage device 3150n included in another application server 3100n via network 3300, and / or can access memory 3220 to 3220m or storage device 3250 to 3250m included in storage servers 3200 to 3200m via network 3300. Therefore, application server 3100 can perform various operations on data stored in application servers 3100 to 3100n and / or storage servers 3200 to 3200m. For example, application server 3100 can execute commands for moving or copying data between application servers 3100 to 3100n and / or storage servers 3200 to 3200m. Data can be transferred directly or via storage devices 3250 to 3250m of storage servers 3200 to 3200m to storage devices 3220 to 3220m of application servers 3100 to 3100n. For example, data transmitted over network 3300 may be encrypted for security or privacy purposes.

[0159] In storage server 3200, interface 3254 provides a physical connection between processor 3210 and controller (CTRL) 3251 and / or a physical connection between network interface card (NIC) 3240 and controller 3251. For example, interface 3254 may be implemented based on a direct-attach storage (DAS) scheme where storage device 3250 is directly connected to a dedicated cable. For example, interface 3254 may be implemented based on at least one of various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Universal Flash Memory (UFS) interface, Embedded UFS (eUFS) interface, Compact Flash Memory (CF) card interface, etc.

[0160] Storage server 3200 may also include switch 3230 and NIC 3240. Switch 3230 may selectively connect processor 3210 to storage device 3250, or selectively connect NIC 3240 to storage device 3250, under the control of processor 3210. Similarly, application server 3100 may also include switch 3130 and NIC 3140.

[0161] In some example embodiments, NIC 3240 may include a network interface card, network adapter, etc. NIC 3240 can connect to network 3300 via a wired interface, wireless interface, Bluetooth interface, or optical interface. NIC 3240 may also include internal memory, a digital signal processor (DSP), a host bus interface, etc., and can be connected to processor 3210 and / or switch 3230 via the host bus interface. The host bus interface may be implemented as one of the above examples of interface 3254. In some example embodiments, NIC 3240 may be integrated with at least one of processor 3210, switch 3230, and storage device 3250.

[0162] In storage servers 3200 to 3200m and / or application servers 3100 to 3100n, the processor can send commands to storage devices 3150 to 3150n and 3250 to 3250m or memories 3120 to 3120n and 3220 to 3220m to program or retrieve data. For example, the data may be data corrected by an error-correcting code (ECC) engine. For example, the data may be processed via Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Check (CRC) information. For example, the data may be encrypted for security or privacy.

[0163] Storage devices 3150 to 3150n and 3250 to 3250m can send control signals and command / address signals to NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. When reading data from NAND flash memory devices 3252 to 3252m, the read enable (RE) signal can be input as a data output control signal and can be used to output data to the DQ bus. The RE signal can be used to generate a data strobe signal (DQS). Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0164] Controller 3251 controls the overall operation of storage device 3250. In some example embodiments, controller 3251 may include static random access memory (SRAM). Controller 3251 may write data to NAND flash memory device 3252 in response to a write command, or may read data from NAND flash memory device 3252 in response to a read command. For example, write and / or read commands may be provided from processor 3210 in storage server 3200, processor 3210m in another storage server 3200m, or processors 3110 to 3110n in application servers 3100 to 3100n. DRAM 3253 may temporarily store (e.g., buffer) data to be written to or read from NAND flash memory device 3252. Furthermore, DRAM 3253 may store metadata. Metadata may be data generated by controller 3251 for managing user data or NAND flash memory device 3252.

[0165] Storage devices 3150 to 3150m and 3250 to 3250m can be based on a reference. Figures 1 to 20 The non-volatile memory device and storage device described according to the example embodiments are implemented and can be implemented to perform the reference. Figures 1 to 20 The method described is for writing data to a non-volatile memory device according to an example embodiment.

[0166] The inventive concept can be applied to a variety of electronic devices and systems, including non-volatile memory devices and storage devices. For example, the inventive concept can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0167] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting the scope of the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from them. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments.

Claims

1. A method for writing data to a non-volatile memory device, the non-volatile memory device comprising a plurality of memory blocks, the method comprising: Each of the plurality of memory blocks is divided into two or more word line groups with different characteristics; Receive write commands for two or more of the plurality of memory blocks; During a first portion of the time interval, which is included in the entire write time interval for the two or more memory blocks, in response to receiving the address of the first memory block among the two or more memory blocks, a data write operation is performed only on the word line group included in the first memory block. as well as During a second time interval, which is included in the entire write time interval, in response to receiving addresses of the two or more memory blocks, data write operations are performed at least partially simultaneously on word line groups included in the first memory block and word line groups included in the second memory block, which is among the two or more memory blocks. The second time interval immediately follows the first time interval.

2. The method according to claim 1, wherein, The step of dividing each of the plurality of memory blocks into the two or more word line groups includes: The first memory block is divided into a first word line group with a first characteristic and a second word line group with a second characteristic; and The second memory block is divided into a third word line group with the first characteristic and a fourth word line group with the second characteristic.

3. The method according to claim 2, wherein, The first and second characteristics are determined based on programming performance. The first and third word line groups include word lines with programming performance superior to the reference programming performance, and The second and fourth word line groups include word lines with programming performance that is lower than or equal to the reference programming performance.

4. The method according to claim 2, wherein, The first and second characteristics are determined based on data retention performance. The first and third word line groups include word lines with data retention performance superior to that of the reference data retention system, and The second and fourth word line groups include word lines with data retention performance that is lower than or equal to the reference data retention performance.

5. The method according to claim 2, wherein, The first and second characteristics are determined based on the positions of word lines in the first and second memory blocks. The second and fourth word line groups include word lines arranged adjacent to the edges of the first and second memory blocks, and The first word line group and the third word line group include word lines arranged adjacent to the center of the first memory block and the second memory block.

6. The method according to claim 2, wherein, The number of bits of data stored in memory cells included in the first word line group is different from the number of bits of data stored in memory cells included in the second word line group.

7. The method according to claim 2, wherein, The steps of performing data write operations only on word line groups included in the first memory block include: During a first write time interval, which is included in the entire write time interval, a first address including a first select word line in a first word line group is received; and During the first write time interval, a data write operation is performed on the first select word line based on the first address.

8. The method according to claim 7, wherein, The steps of performing data write operations at least partially simultaneously on a sub-line group included in a first memory block and a word line group included in a second memory block include: During a second write time interval, which is included in the entire write time interval after the first write time interval, a second address including a second select word line in the first word line group and a third address including a third select word line in the fourth word line group are received; and During the second write time interval, data write operations are performed on the second select word line and the third select word line based on the second address and the third address.

9. The method according to claim 8, wherein, The step of performing data write operations at least partially simultaneously on a sub-line group included in the first memory block and a word line group included in the second memory block further includes: During the second write time interval, the fourth address included in the fourth select word line of the second word line group and the fifth address included in the fifth select word line of the third word line group are received; and During the second write time interval, data write operations are performed on the fourth select word line and the fifth select word line based on the fourth address and the fifth address.

10. The method according to claim 9, wherein, During the second write time interval, the second address of the first memory block and the third address of the second memory block are alternately received with the fourth address of the first memory block and the fifth address of the second memory block.

11. The method of claim 8, further comprising: During the third write time interval, which is included in the entire write time interval after the second write time interval, the fourth address, which is included in the third word line group, is received. as well as During the third write time interval, a data write operation is performed on the fourth select word line based on the fourth address.

12. The method according to claim 11, wherein, The step of dividing each of the plurality of memory blocks into the two or more word line groups further includes: The third memory block is divided into a fifth word line group with the first characteristic and a sixth word line group with the second characteristic.

13. The method of claim 12, further comprising: During the fourth write time interval, which is included in the entire write time interval after the third write time interval, the fifth address of the fifth select word line included in the third word line group and the sixth address of the sixth select word line included in the sixth word line group are received. as well as During the fourth write time interval, data write operations are performed on the fifth and sixth select word lines based on the fifth and sixth addresses.

14. The method according to claim 1, wherein, The step of dividing each of the plurality of memory blocks into the two or more word line groups includes: The first memory block is divided into a first word line group with a first characteristic, a second word line group with a second characteristic, and a third word line group with a third characteristic; and The second memory block is divided into a fourth word line group with the first characteristic, a fifth word line group with the second characteristic, and a sixth word line group with the third characteristic.

15. The method according to any one of claims 1 to 14, wherein, Information identifying which of the plurality of memory blocks corresponds to each of the two or more word line groups is stored in a lookup table within the non-volatile memory device.

16. The method according to any one of claims 1 to 14, further comprising: Update information stored in the non-volatile memory device that identifies which of the plurality of memory blocks corresponds to each of the two or more word line groups.

17. The method according to claim 16, wherein, The steps for updating the information include: Obtain the number of the first programming / erasing cycles for the first memory block; and When the number of first program / erase cycles is greater than the reference number, change the two or more word line groups included in the first memory block.

18. A non-volatile memory device, comprising: A memory cell array, comprising multiple memory blocks; as well as The control circuit is configured as follows: Each of the plurality of memory blocks is divided into two or more word line groups with different characteristics. Receive write commands for two or more of the plurality of memory blocks. During a first portion of the time interval encompassing the entire write time interval for the two or more memory blocks, in response to receiving the address of the first memory block among the two or more memory blocks, a data write operation is performed only on the word line group included in the first memory block, and During a second time interval, which is included in the entire write time interval, in response to receiving addresses of the two or more memory blocks, data write operations are performed at least partially simultaneously on word line groups included in the first memory block and word line groups included in the second memory block, which is among the two or more memory blocks. The second time interval immediately follows the first time interval.

19. The non-volatile memory device according to claim 18, wherein, The control circuit includes: The lookup table includes information identifying which of the plurality of memory blocks correspond to each of the two or more word line groups.

20. A method for writing data to a non-volatile memory device, the non-volatile memory device comprising a plurality of memory blocks, the method comprising: The first memory block among the plurality of memory blocks is divided into a first word line group with a first characteristic and a second word line group with a second characteristic; The second memory block among the plurality of memory blocks is divided into a third word line group with a first characteristic and a fourth word line group with a second characteristic; During the first write time interval, which is included in the entire write time interval for the first memory block and the second memory block, a data write operation is performed on the first select word line in response to receiving a first address included in the first select word line in the first word line group; During a second write time interval, which is included in the entire write time interval after the first write time interval, in response to receiving a second address included in the first word line group and a third address included in the fourth word line group, a data write operation is performed on the second select word line and the third select word line. During the second write time interval, in response to receiving the fourth address of the fourth select word line included in the second word line group and the fifth address of the fifth select word line included in the third word line group, a data write operation is performed on the fourth select word line and the fifth select word line; as well as During the third write time interval, which is included in the entire write time interval after the second write time interval, a data write operation is performed on the sixth select word line in response to receiving the sixth address of the sixth select word line included in the third word line group.

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