A Chip Random Test Case Regression Method, Device, Equipment and Readable Medium

Abstract

The present invention discloses a method for regression of chip random test cases, comprising the following steps: setting the random number of each test case, and generating the corresponding number of seeded test cases for each test case; sequentially submitting all the seeded test cases of each test case for testing based on a preset maximum number of runs; in response to detecting that a certain seeded test case fails the test, stopping submitting other unsubmitted seeded test cases generated by its corresponding test case for testing; and obtaining the failure reason of the failed seeded test case and retesting the failed seeded test case based on a preset policy. The present invention also discloses a device for regression of chip random test cases, a computer device, and a readable storage medium. The present invention performs random testing of random test cases for a fixed number of times, without the need for users to learn additionally and with simpler operations; the input content is simplified and clear, and the result file is explicit, and a better handling method is also proposed for the situation after the test case fails.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular, to a method, device, equipment and readable medium for regression of chip random test cases. Background Art

[0002] Chip verification plays an important role in the entire chip design process and is the most important link to ensure chip quality and shorten the chip cycle. With the continuous increase in chip scale, the internal modules of the chip are also becoming more and more complex. In order to ensure the sufficiency of verification, chip verification engineers often adopt the method of random test cases to cover all possible excitation situations as much as possible. However, the more complex the random situations of the random test cases, the more random excitations there are. In order to ensure the continuous convergence of the verification results, that is, to cover all situations as much as possible, regression testing needs to be continuously carried out. The process of performing random test case regression is often simple and boring, but a large amount of manpower and material resources have to be spent. Therefore, a simple and efficient random test case regression method is needed to greatly reduce the verification cost and shorten the verification cycle.

[0003] Currently, the tools used for test case management on the market, such as the VManger tool provided by the mainstream EDA manufacturer Cadence, require preparing input files such as CSV files of verification features and vsif files in advance, and then calling the Vmanager tool to manage the regression test cases defined in the CSV file and running the regression test cases with the vsif file. At the same time, it reflects all of this in the interface and integrates various functions, which can automatically merge the results to view code, flip, etc., coverage rate, etc. However, most of the tools used for test case management on the market are expensive, complex to use, and cumbersome to configure. Verification personnel need to learn the usage method in advance to complete their own requirements, with high verification costs and low usage efficiency. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a method, device, equipment and readable medium for regression of chip random test cases, which perform random tests on random cases for a fixed number of times, without the need for users to learn additionally, and the operation is relatively simpler than other tools on the market; the input content is simplified and clear, and the result file is clear, and a better processing method is also proposed for the situation after the case fails.

[0005] For the above purposes, one aspect of an embodiment of the present invention provides a regression method for chip random test cases, including the following steps: setting the random number of times for each test case, and generating the corresponding number of seed cases for each test case according to its random number of times; submitting all the seed cases of each test case for testing in sequence based on a preset maximum number of runs; in response to detecting that a certain seed case fails the test, stopping submitting the other unsubmitted seed cases generated by its corresponding test case for testing; and obtaining the failure reason of the failed seed case and retesting the failed seed case based on a preset strategy.

[0006] In some embodiments, setting the random number of times for each test case and generating the corresponding number of seed cases for each test case according to its random number of times includes: setting the random number of times corresponding to different types of test cases; obtaining the type of each test case, and generating the corresponding number of seed cases for each test case according to its type.

[0007] In some embodiments, submitting all the seed cases of each test case for testing in sequence based on a preset maximum number of runs includes: submitting a preset maximum number of seed cases for testing; in response to detecting that a seed case has completed the test, submitting a seed case to be submitted.

[0008] In some embodiments, the method further includes: saving the status of the seed case after testing to a log; if the seed case passes the test, saving it directly; if the seed case fails the test, extracting and saving the value of the seed case.

[0009] In some embodiments, in response to detecting that a certain seed case fails the test, stopping submitting the other unsubmitted seed cases generated by its corresponding test case for testing includes: in response to detecting that a certain seed case fails the test, deleting the other unsubmitted seed cases generated by its corresponding test case from the seed cases to be submitted, and submitting the unsubmitted seed cases generated by other test cases for testing.

[0010] In some embodiments, obtaining the failure reason of the failed seed case includes: obtaining the failure reason of the failed seed case and recording the value of the seed case.

[0011] In some embodiments, retesting the failed seed case based on a preset strategy includes: retesting all the failed seed cases; or retesting the seed cases with a specified failure reason.

[0012] On the other hand, an embodiment of the present invention further provides a regression device for chip random test cases, including: a first module configured to set the random number of times for each test case and generate the corresponding random number of seed cases for each test case; a second module configured to sequentially submit all the seed cases of each test case for testing based on a preset maximum number of runs; a third module configured to stop submitting other unsubmitted seed cases generated by the corresponding test case in response to detecting that a certain seed case fails the test; and a fourth module configured to obtain the failure reason of the failed seed case and retest the failed seed case based on a preset policy.

[0013] In yet another aspect, an embodiment of the present invention further provides a computer device, including: at least one processor; and a memory storing computer instructions that can be run on the processor. When the instructions are executed by the processor, the steps of the method include: setting the random number of times for each test case and generating the corresponding random number of seed cases for each test case; sequentially submitting all the seed cases of each test case for testing based on a preset maximum number of runs; stopping submitting other unsubmitted seed cases generated by the corresponding test case in response to detecting that a certain seed case fails the test; and obtaining the failure reason of the failed seed case and retesting the failed seed case based on a preset policy.

[0014] In some embodiments, setting the random number of times for each test case and generating the corresponding random number of seed cases for each test case includes: setting the random number of times corresponding to different types of test cases; obtaining the type of each test case and generating the corresponding random number of seed cases for the type of each test case.

[0015] In some embodiments, sequentially submitting all the seed cases of each test case for testing based on a preset maximum number of runs includes: submitting the preset maximum number of seed cases for testing; and submitting a seed case to be submitted in response to detecting that a seed case has completed testing.

[0016] In some embodiments, the method further includes: saving the status after the seed case is tested to a log; if the seed case passes the test, directly save it; if the seed case fails the test, extract the value of the seed case and then save it.

[0017] In some embodiments, in response to detecting that a certain seed use case test fails, stopping submitting other unsubmitted seed use cases generated by its corresponding test case for testing includes: in response to detecting that a certain seed use case test fails, deleting other unsubmitted seed use cases generated by its corresponding test case from the seed use cases to be submitted, and submitting unsubmitted seed use cases generated by other test cases for testing.

[0018] In some embodiments, obtaining the failure reason of a test failure seed use case includes: obtaining the failure reason of a test failure seed use case and recording the value of the seed use case.

[0019] In some embodiments, retesting a test failure seed use case based on a preset policy includes: retesting all test failure seed use cases; or retesting seed use cases with a specified failure reason.

[0020] Another aspect of the embodiments of the present invention further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above method steps.

[0021] The present invention has at least the following beneficial technical effects: performing a fixed number of random tests on random use cases, without the need for users to learn extra, and the operation is relatively simpler compared to other tools on the market; the input content is simplified and clear, and the result file is clear, and a better handling method is also proposed for the situation after use case failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic diagram of an embodiment of the chip random test case regression method provided by the present invention;

[0024] Figure 2 It is a schematic diagram of an embodiment of the chip random test case regression device provided by the present invention;

[0025] Figure 3 It is a schematic diagram of an embodiment of the computer device provided by the present invention;

[0026] Figure 4 It is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0028] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0029] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of a method for regression of chip random test cases is proposed. Figure 1 The following shows a schematic diagram of an embodiment of the method for regression of chip random test cases provided by the present invention. As Figure 1 shown, the method for regression of chip random test cases in the embodiments of the present invention includes the following steps:

[0030] 001. Set the random number of times for each test case, and generate the corresponding number of seed cases for each test case according to its random number of times;

[0031] 002. Sequentially submit all the seed cases of each test case for testing based on the preset maximum number of runs;

[0032] 003. In response to detecting that a certain seed case fails the test, stop submitting the other unsubmitted seed cases generated by its corresponding test case for testing; and

[0033] 004. Obtain the failure reason of the failed seed case, and retest the failed seed case based on a preset strategy.

[0034] In this embodiment, the user defines the test cases to be randomly tested in a CSV, sets the random number (random number of times), that is, how many times this test case is to be randomized, and then defines the preset maximum number of runs for the test case. The tool will collect this information, first generate the corresponding number of seed cases with the suffix _seed* according to the random number of times, then submit the maximum number of runs of test cases to the server side, and then continuously detect the status of these test cases. If one of the seed cases has finished running, the next seed case will be submitted. The test cases that have finished running will detect their simulation results. If it is PASS (passed), it will be directly reported in the result file. If it is FAIL (failed), the seed at the time of its running will be extracted. After the user sees that the test case fails, they can select the rerun function, and the tool will re-execute according to the seed at the time of the previous running failure for the user to analyze. After modifying the error, the rerun function can also be used to check whether the code error has been fixed.

[0035] In some embodiments of the present invention, setting the random number of times for each test case and generating the corresponding number of seeded test cases for each test case includes: setting the random number of times corresponding to different types of test cases; obtaining the type of each test case, and generating the corresponding number of seeded test cases for each test case according to its type.

[0036] In some embodiments of the present invention, submitting all the seeded test cases of each test case for testing in sequence based on a preset maximum number of runs includes: submitting the preset maximum number of seeded test cases for testing; in response to detecting that a seeded test case has completed testing, submitting a seeded test case to be submitted.

[0037] In this embodiment, taking the preset maximum number of runs as 5 as an example. First, submit 5 seeded test cases for testing. In response to a seeded test case completing testing, submit the next seeded test case to be submitted. That is, always keep 5 seeded test cases for parallel testing until all the seeded test cases to be submitted have been completely tested.

[0038] In some embodiments of the present invention, the method further includes: saving the status of the seeded test case after testing to a log; if the seeded test case passes the test, save it directly; if the seeded test case fails the test, extract the value of the seeded test case and then save it.

[0039] In some embodiments of the present invention, in response to detecting that a certain seeded test case fails the test, stopping submitting the other unsubmitted seeded test cases generated by its corresponding test case for testing includes: in response to detecting that a certain seeded test case fails the test, deleting the other unsubmitted seeded test cases generated by its corresponding test case from the seeded test cases to be submitted, and submitting the unsubmitted seeded test cases generated by other test cases for testing.

[0040] In some embodiments of the present invention, obtaining the failure reason of the failed seeded test case includes: obtaining the failure reason of the failed seeded test case and recording the value of the seeded test case.

[0041] In some embodiments of the present invention, retesting the failed seeded test case based on a preset strategy includes: retesting all the failed seeded test cases; or retesting the seeded test cases with a specified failure reason.

[0042] In this embodiment, there are at least two retesting modes. One is to retest according to the specified error type or fixed use cases, and the other is to directly perform a full retest.

[0043] The following further elaborates on the specific implementation of the present invention according to specific embodiments. In the property function, key information such as the functional description of the current module, whether it is random, and the maximum number of times a use case can run is defined. In the feature function, the detailed name and description of each verification target, measurement method, etc. are defined. The CSV file is as follows:

[0044]

[0045]

[0046] Based on the parameters defined in the above CSV file, the tool will extract the following information. The types of test cases that need to be randomly tested are two. Among them, aa_size_test needs to be randomly tested 10 times, and bb_size_test needs to be randomly tested 5 times. At the same time, the maximum number of runs submitted is 5. Then the tool will generate three different test cases, namely from aa_size_test_seed0 to aa_size_test_seed9, from bb_size0_test_seed0 to bb_size0_test_seed4, and from bb_size1_test_seed0 to bb_size1_test_seed4, generating 10, 5, and 5 seed use cases respectively. The output result file mainly contains the regression results of the test cases and the seeds used when the use cases fail, as follows:

[0047] aa_size_test_seed0 PASS

[0048] aa_size_test_seed1 PASS

[0049] aa_size_test_seed2 PASS

[0050] aa_size_test_seed3 PASS

[0051] aa_size_test_seed4 PASS

[0052] aa_size_test_seed5 PASS

[0053] aa_size_test_seed6 FAIL seed=4356219 aaa_error

[0054] bb_size0_test_seed0 PASS

[0055] bb_size0_test_seed1 PASS

[0056] bb_size0_test_seed2 PASS

[0057] bb_size0_test_seed3 PASS

[0058] bb_size0_test_seed4 PASS

[0059] bb_size1_test_seed0 FAIL seed=6490236 aaa_error

[0060] bb_size1_test_seed1 FAIL seed=7854327 bbb_error

[0061] During the process of testing random test cases, if the previous seed is randomly successful, only record PASS in the result file, and then test the next seed of this test case; if an error occurs in the previous seed, the following operations will be performed:

[0062] Stop testing the remaining seeds of this random test case. For example, if aa_size_test_seed6 fails, aa_size_test_seed7 that should have been run will no longer be tested. Instead, start the random test process of bb_size0_test until it all PASSes, and then start the random test of the bb_size1_test use case; obtain the seed value of this run from the result file of the use case run. For example, if aa_size_test_seed6 fails, the seed value is recorded as 4356219; analyze the approximate reason for the simulation failure of this use case from the result file for the user to view.

[0063] If the random test case fails, the following two problems need to be solved: one is how to quickly reproduce it for the testers to analyze the reason for the failure, and the other is to quickly know whether the modification is correct, whether the problem is solved, and whether new problems are introduced after knowing the reason for the failure and making relevant modifications; these two problems are closely related to the seed value. After having a fixed seed, the present invention supports the quick rerun function.

[0064] The rerun function has two modes. One is to retest according to the specified error type or fixed test cases, and the other is to directly perform a full retest. Taking the above results as an example, after specifying to retest the test cases that failed due to the bbb_error type, the bb_size1_test_seed1 will be tested according to seed = 7854327, and only this one test case will be tested. If you choose to directly perform a full retest, the three failed test cases will be tested according to their respective failed seeds.

[0065] It should be particularly noted that each step in each embodiment of the above chip random test case regression method can be crossed, replaced, added, or deleted with each other. Therefore, these reasonable permutation and combination transformations should also fall within the protection scope of the present invention for the chip random test case regression method, and the protection scope of the present invention should not be limited to the embodiments.

[0066] Based on the above purpose, the second aspect of the embodiments of the present invention proposes a chip random test case regression device. Figure 2 Shown is a schematic diagram of an embodiment of the chip random test case regression device provided by the present invention. As Figure 2 shown, the chip random test case regression device of the embodiments of the present invention includes the following modules: a first module 011 configured to set the random number of times for each test case and generate the corresponding number of seed test cases for each test case; a second module 012 configured to sequentially submit all the seed test cases of each test case for testing based on a preset maximum number of runs; a third module 013 configured to stop submitting the other unsubmitted seed test cases generated by the corresponding test case in response to detecting that a certain seed test case fails in testing; and a fourth module 014 configured to obtain the failure reason of the failed seed test case and retest the failed seed test case based on a preset policy.

[0067] Based on the above purpose, the third aspect of the embodiments of the present invention proposes a computer device. Figure 3 Shown is a schematic diagram of an embodiment of the computer device provided by the present invention. As Figure 3As shown in the figure, the computer device according to the embodiment of the present invention includes the following devices: at least one processor 021; and a memory 022, where the memory 022 stores computer instructions 023 that can run on the processor. When the instructions are executed by the processor, the steps of the implementation method include: setting the random number of times for each test case, and generating the corresponding random number of seed cases for each test case; submitting all the seed cases of each test case for testing in sequence based on a preset maximum number of runs; in response to detecting that a certain seed case fails the test, stopping submitting the other unsubmitted seed cases generated by its corresponding test case for testing; and obtaining the failure reason of the failed seed case and retesting the failed seed case based on a preset policy.

[0068] In some embodiments of the present invention, setting the random number of times for each test case and generating the corresponding random number of seed cases for each test case includes: setting the random number of times corresponding to different types of test cases; obtaining the type of each test case, and generating the corresponding random number of seed cases for each test case according to its type.

[0069] In some embodiments of the present invention, submitting all the seed cases of each test case for testing in sequence based on a preset maximum number of runs includes: submitting the preset maximum number of seed cases for testing; in response to detecting that a seed case has completed the test, submitting a seed case to be submitted.

[0070] In some embodiments of the present invention, the method further includes: saving the status after the seed case test to a log; if the seed case test is successful, saving it directly; if the seed case test fails, extracting the value of the seed case and then saving it.

[0071] In some embodiments of the present invention, in response to detecting that a certain seed case fails the test, stopping submitting the other unsubmitted seed cases generated by its corresponding test case for testing includes: in response to detecting that a certain seed case fails the test, deleting the other unsubmitted seed cases generated by its corresponding test case from the seed cases to be submitted, and submitting the unsubmitted seed cases generated by other test cases for testing.

[0072] In some embodiments of the present invention, obtaining the failure reason of the failed seed case includes: obtaining the failure reason of the failed seed case and recording the value of the seed case.

[0073] In some embodiments of the present invention, retesting the failed seed case based on a preset policy includes: retesting all the failed seed cases; or retesting the seed cases with a specified failure reason.

[0074] The present invention also provides a computer-readable storage medium. Figure 4Shown is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. As Figure 4 shown, the computer-readable storage medium 031 stores a computer program 032 that, when executed by a processor, executes the above method.

[0075] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the above-described embodiment methods can be completed by instructing relevant hardware through a computer program. The program for the chip random test case regression method can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above-described method embodiments. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The above-described embodiments of the computer program can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

[0076] In addition, the method disclosed according to the embodiments of the present invention can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the above-described functions defined in the method disclosed in the embodiments of the present invention are executed.

[0077] In addition, the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above step or unit functions.

[0078] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, a general description of the functions of various illustrative components, blocks, modules, circuits, and steps has been presented. Whether this function is implemented as software or hardware depends on the particular application and the design constraints imposed on the overall system. The functions that those skilled in the art can implement in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0079] In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, the computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Additionally, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0080] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements disclosed by the embodiments of the present invention may be described or claimed in individual form, they may also be understood as plural unless explicitly limited to the singular.

[0081] It should be understood that, as used herein, unless the context clearly supports the contrary, the singular forms "a" are also intended to include the plural forms. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0082] The serial numbers of the disclosed embodiments of the present invention above are merely for description and do not represent the superiority or inferiority of the embodiments.

[0083] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware or by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a disk, an optical disc, or the like.

[0084] Those of ordinary skill in the art should understand that the discussion of any above embodiment is only exemplary and is not intended to imply that the scope (including the claims) disclosed by the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as described above, and they are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A regression method for chip random test cases, characterized in that, It includes the following steps: Set the random number of times for each test case, and generate the corresponding random number of seed cases for each test case; Based on the preset maximum number of runs, submit all the seed cases of each test case for testing in sequence; In response to detecting that a certain seed case fails the test, stop submitting the other unsubmitted seed cases generated by its corresponding test case for testing; And Obtain the failure reason of the failed test seed case, and retest the failed test seed case based on the preset policy.

2. The chip random test case regression method according to claim 1, wherein Setting the random number of times for each test case and generating the corresponding random number of seed cases for each test case includes: Set the random number of times corresponding to different types of test cases; Obtain the type of each test case, and generate the corresponding random number of seed cases for each test case according to its type.

3. The chip random test case regression method according to claim 1, wherein Based on the preset maximum number of runs, submitting all the seed cases of each test case for testing in sequence includes: Submit the preset maximum number of seed cases for testing; In response to detecting that a seed case has completed the test, submit a seed case to be submitted.

4. The chip random test case regression method according to claim 3, wherein It also includes: Save the status of the seed case after testing to the log; If the seed case passes the test, save it directly; If the seed case fails the test, extract and save the value of the seed case.

5. The chip random test case regression method according to claim 1, characterized in that In response to detecting that a certain seed case fails the test, stopping to submit the other unsubmitted seed cases generated by its corresponding test case for testing includes: In response to detecting that a certain seed case fails the test, delete the other unsubmitted seed cases generated by its corresponding test case from the seed cases to be submitted, and submit the unsubmitted seed cases generated by other test cases for testing.

6. The chip random test case regression method according to claim 1, wherein Obtaining the failure reason of the failed test seed case includes: Obtain the failure reason of the failed test seed case, and record the value of the seed case.

7. The chip random test case regression method according to claim 1, wherein Retesting the failed test seed case based on the preset policy includes: Retest all the failed test seed cases; or Retest the seed cases with specified failure reasons.

8. A regression device for chip random test cases, characterized in that, It includes: The first module is configured to set the random number of times for each test case, and generate the corresponding random number of seed cases for each test case; The second module is configured to submit all the seed cases of each test case for testing in sequence based on the preset maximum number of runs; The third module is configured to, in response to detecting that a certain seed case fails the test, stop submitting the other unsubmitted seed cases generated by its corresponding test case for testing; And The fourth module is configured to obtain the failure reason of the failed test seed case, and retest the failed test seed case based on the preset policy.

9. A computer device, characterized in that, It includes: At least one processor; And A memory, the memory stores computer instructions that can run on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of claims 1-7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1-7 are implemented.

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