System for adaptively determining a read threshold voltage using meta-information

Abstract

The present application relates to a system for adaptively determining a read threshold voltage using meta information. Embodiments of the present application adaptively determine a read retry threshold voltage for a next read operation using meta information collected from a previous failed read data. A controller obtains meta information associated with a read operation on a selected page, the meta information including a set of read threshold voltages. The controller determines a mathematical model for estimating a checksum value associated with data of a next read operation using a set function of the set of read threshold voltages and a set checksum value. The controller determines a set of parameters by performing a polynomial regression on the mathematical model. The controller estimates a next read threshold voltage for the next read operation based on the set of parameters.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a scheme for adaptively determining a read threshold voltage in a memory system. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either the main memory or secondary memory devices in portable electronic devices.

[0003] Because memory systems using memory devices have no moving parts, they offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs). Memory systems can use various read threshold voltages to perform read operations or read retry operations. Summary of the Invention

[0004] Aspects of the present invention include a system and method for adaptively determining a read threshold voltage using metadata collected from previously failed read data.

[0005] On one hand, a memory system includes a memory device having multiple pages and a controller. The controller obtains metadata associated with a read operation on a selected page among the multiple pages, the metadata including a set of read threshold voltages; determines a mathematical model for estimating a checksum value for data associated with the next read operation using a setting function for the set of read threshold voltages and a setting checksum value; determines a set of parameters by performing polynomial regression on the mathematical model; and estimates a next read threshold voltage for the next read operation based on the set of parameters.

[0006] On the other hand, a memory system includes a memory device having multiple pages and a controller. The controller obtains metadata associated with a read operation on a selected page among the multiple pages, the metadata including multiple read threshold voltage groups, multiple checksum values, and a bit percentage of a specific value in the data; determines a mathematical model for estimating the bit percentage of the specific value in the data for the next read operation using a setting function of the read threshold voltage groups of the current read operation; determines a set of parameters by performing linear regression on the mathematical model; determines a surface formed by each of the multiple read threshold voltage groups; determines a line of the surface based on the set of parameters; determines the optimal previous read threshold voltage group among the multiple read threshold voltage groups based on the multiple checksum values; determines a point in the surface corresponding to the optimal previous read threshold voltage group; and estimates the next read threshold voltage for the next read operation by projecting the point onto the line.

[0007] In another aspect, a memory system includes a memory device having multiple pages and a controller. The controller obtains metadata associated with a read operation on a selected page among the multiple pages, the metadata including multiple read threshold voltage groups, multiple checksum values, and a bit percentage of a specific value in the data; determines a first mathematical model for estimating the checksum value of the data associated with the next read operation using a setting function for the read threshold voltage groups and a setting checksum value; determines a first set of parameters by performing polynomial regression on the first mathematical model; estimates a first next read threshold voltage for the next read operation based on the first set of parameters; determines a second mathematical model for estimating the bit percentage of a specific value in the data for the next read operation using a setting function for the read threshold voltage groups for the current read operation; determines a second set of parameters by performing linear regression on the second mathematical model; determines a surface formed by each of the multiple read threshold voltage groups; determines a line of the surface based on the second set of parameters; determines an optimal previous read threshold voltage group among the multiple read threshold voltage groups based on the multiple checksum values; determines a point in the surface corresponding to the optimal previous read threshold voltage group; and estimates a second next read threshold voltage for the next read operation by projecting the point onto the line.

[0008] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0009] Figure 1 This is a block diagram showing the data processing system.

[0010] Figure 2 This is a block diagram showing the memory system.

[0011] Figure 3 This is a circuit diagram showing the memory blocks of a memory device.

[0012] Figure 4 It is a diagram showing the state distribution of different types of cells in a memory device.

[0013] Figure 5A This is a diagram illustrating an example of Gray coding for a multilayer cell (MLC).

[0014] Figure 5B This is a diagram showing the state distribution of pages in a multi-layer cell (MLC).

[0015] Figure 6A This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC).

[0016] Figure 6B This is a diagram showing the state distribution of pages in a three-layer cell (TLC).

[0017] Figure 7 This is a diagram illustrating the flow of an error recovery algorithm in a memory system.

[0018] Figure 8 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0019] Figure 9 This is a diagram illustrating a read threshold determiner according to an embodiment of the present invention.

[0020] Figure 10A and Figure 10B This is a diagram illustrating metadata according to an embodiment of the present invention.

[0021] Figure 11 This is a flowchart illustrating the operation for determining the read retry threshold voltage according to an embodiment of the present invention.

[0022] Figures 12A to 12D An example of an operation for determining a read retry threshold voltage according to an embodiment of the present invention is shown.

[0023] Figure 13 This is a graph illustrating the performance of the adaptive read retry operation according to an embodiment of the present invention. Detailed Implementation

[0024] Various embodiments are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references to “embodiment,” “another embodiment,” etc., herein are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals in the drawings and embodiments of the invention refer to the same parts.

[0025] This invention can be embodied in a variety of ways, including as a process, apparatus, system, computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided thereto in memory coupled to the processor. In this specification, these embodiments or any other form in which the invention may take may be referred to as technology. Generally, the order of steps of the disclosed process can be varied within the scope of this invention. Unless otherwise stated, components described as suitable for performing a task, such as processors or memory, may be implemented as general components temporarily configured to perform a task at a given time or manufactured as specific components for performing a task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data (e.g., computer program instructions).

[0026] The following provides a detailed description of embodiments of the present invention, along with accompanying drawings illustrating aspects of the invention. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims. The invention covers many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes only; the invention may be practiced without some or all of these specific details, as claimed. For clarity, known technical materials in the art related to the invention have not been described in detail, so as not to unnecessarily obscure the invention.

[0027] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0028] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0029] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, and / or digital video recorders and digital video players. In various embodiments, the host device 5 may include portable electronic devices such as mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and / or portable game consoles.

[0030] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as a component of a variety of electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, a variety of electronic devices for computer networks, a variety of electronic devices for telematics networks, or a component of a computing system.

[0031] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control all operations of the semiconductor memory device 200.

[0032] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, read enable signals, and other operation signals.

[0033] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the semiconductor memory system 10 is used with an SSD, the performance of host devices connected to the memory system 10 (e.g., Figure 1 The operating speed of the main unit 5).

[0034] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), miniaturized multimedia cards (RS-MMC), micro-versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), secure digital high capacity (SDHC) and / or universal flash memory (UFS).

[0035] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0036] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 It operates upon the request of the host device 5) and specifically stores data to be accessed by the host device.

[0037] The memory device 200 can store data to be accessed by the host device.

[0038] The memory device 200 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0039] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device, and can store data provided from the host device into the memory device 200.

[0040] The controller 100 may include a storage device 110, a control component 120 (which may be implemented as a processor such as a central processing unit (CPU)), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150, which are connected via a bus 160.

[0041] Storage device 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data used by controller 100 and memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0042] Storage device 110 may be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in storage device 200 for read and write operations. To store data, storage device 110 may include programming memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0043] Control component 120 can control the general operation of memory system 10 and control write or read operations of memory device 200 in response to write or read requests from host device. Control component 120 can drive firmware called Flash Translation Layer (FTL) to control the general operation of memory system 10. For example, FTL can perform operations such as logical-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block disposal. L2P mapping is called logical block addressing (LBA).

[0044] ECC component 130 can detect and correct errors in data read from memory device 200 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC component 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0045] In various embodiments, ECC component 130 may perform error correction operations based on coding modulations such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or means for appropriate error correction operations.

[0046] The host interface 140 can communicate with the host device through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0047] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for that flash memory and process data under the control of control component 120.

[0048] Memory device 200 may include memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (I / O) circuitry 270. Memory cell array 210 may include multiple memory blocks 211 capable of storing data. Voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for memory cell array 210. Peripheral circuitry may perform programming, reading, or erasing operations on memory cell array 210. Control circuitry 220 may control peripheral circuitry.

[0049] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0050] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. In response to a line address generated by the control circuit 220, the line decoder 240 can select at least one memory block among the plurality of memory blocks 211 and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0051] Page buffer 250 can be accessed via bit line BL ( Figure 3 (As shown) is connected to the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage, transfer data to and from the selected memory block during programming and reading operations, or temporarily store the transferred data in response to a page buffer control signal generated by the control circuit 220.

[0052] The column decoder 260 can transmit data to and receive data from the page buffer 250, or transmit data to and receive data from the input / output circuit 270.

[0053] Input / output circuit 270 can input from external devices (e.g., Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from the external device to the column decoder 260, or outputs data from the column decoder 260 to the external device via the input / output circuit 270.

[0054] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0055] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0056] Reference Figure 3 The exemplary storage block 211 may include multiple word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL connected to the line decoder 240. These lines may be arranged in parallel and have multiple word lines between DSL and SSL.

[0057] The exemplary memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be formed as a multi-level cell. For example, each of the memory cells may be formed as a single-level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-level cell (QLC) storing 4 bits of data.

[0058] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells in different cell strings can be connected to their respective word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0059] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0060] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded within the memory chip.

[0061] Figure 4 It is a diagram showing the state or programming voltage (PV) level distribution of different types of cells in a memory device.

[0062] Reference Figure 4Each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) for storing 1 bit of data, a multi-level cell (MLC) for storing 2 bits of data, a three-level cell (TLC) for storing 3 bits of data, or a four-level cell (QLC) for storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required.

[0063] An SLC can include two states, P0 and P1. P0 can represent the erase state, and P1 can represent the programmable state. Since an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to a set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can represent the erase state, and P1 through P3 can represent the programmable state. Since an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to a set encoding method. A TLC can include eight states, P0 through P7. Among these states, P0 can represent the erase state, and P1 through P7 can represent the programmable state. Since a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to a set encoding method. A QLC can include sixteen states, P0 through P15. Among these states, P0 can represent the erase state, and P1 through P15 can represent the programmable state. Since a QLC can be set to one of sixteen different states, each QLC can be programmed or store four bits according to a set encoding method.

[0064] Return to reference Figure 2 and Figure 3 The memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, such as... Figure 3As shown. Cells in each row are connected to word lines (e.g., WL0), and cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided on the bit line when the word line is asserted. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0065] Figure 5A This is a diagram illustrating an example of encoding a multilayer cell (MLC).

[0066] Reference Figure 5A The MLC can be programmed using a specified type of encoding. The MLC can have four programming states: erase state E (or PV0) and first programming states PV1 through third programming states PV3. Erase state E (or PV0) can correspond to "11". First programming state PV1 can correspond to "10". Second programming state PV2 can correspond to "00". Third programming state PV3 can correspond to "01".

[0067] In MLC, such as Figure 5B As shown, there are two types of pages: LSB pages and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For MSB pages, the single threshold is VT1. VT1 distinguishes between the first programming state PV1 and the second programming state PV2. For LSB pages, the two thresholds are threshold VT0 and threshold VT2. VT0 distinguishes between the erase state E and the first programming state PV1. VT2 distinguishes between the second programming state PV2 and the third programming state PV3.

[0068] Figure 6A This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC).

[0069] Reference Figure 6ATLCs can be programmed using Gray code. A TLC can have eight programming states, including an erase state E (or PV0) and first programming states PV1 through seventh programming states PV7. Eraser state E (or PV0) can correspond to "111". First programming state PV1 can correspond to "011". Second programming state PV2 can correspond to "001". Third programming state PV3 can correspond to "000". Fourth programming state PV4 can correspond to "010". Fifth programming state PV5 can correspond to "110". Sixth programming state PV6 can correspond to "100". Seventh programming state PV7 can correspond to "101".

[0070] In TLC, such as Figure 6B As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds include threshold VT0, which distinguishes between erase state E and first programming state PV1, and threshold VT4, which distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between first programming state PV1 and second programming state PV2. VT3 distinguishes between third programming state PV3 and fourth programming state PV4. VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds include VT2 and VT6. VT2 distinguishes between second programming state PV2 and third programming state PV3. VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0071] In such Figure 5A and Figure 6A After programming the memory array comprising multiple memory cells, when a read operation is performed on the memory array using a reference voltage such as a read threshold voltage (also referred to as a "read voltage level" or "read threshold"), the charge level of the memory cell (e.g., the threshold voltage level of the memory cell's transistor) is compared with one or more reference voltages to determine the state of an individual memory cell. For example, when a read threshold is applied to the memory array, memory cells with threshold voltage levels higher than the reference voltage are turned on and detected as "on" cells, while memory cells with threshold voltage levels lower than the reference voltage are turned off and detected as "off" cells. Therefore, each read threshold is set between adjacent threshold voltage distribution windows corresponding to different programming states, such that each read threshold can distinguish these programming states by turning the memory cell transistors on or off.

[0072] When performing a read operation on a memory cell in a data storage device using MLC technology, the threshold voltage level of the memory cell is compared with more than one read threshold level to determine the state of an individual memory cell. Read errors can be caused by distorted or overlapping threshold voltage distributions. Ideal memory cell threshold voltage distributions can be severely distorted or overlapping due to factors such as program / erase (P / E) cycles, inter-cell interference, and / or data retention errors. For example, as program / erase cycles increase, the margin between adjacent threshold voltage distributions of different programming states decreases, and eventually the distributions overlap. Therefore, a memory cell whose threshold voltage falls within the overlapping region of adjacent distributions may be read as having been programmed to a value different from the original target value, thus causing a read error. In most cases, such read errors can be managed by using error correction codes (ECC). The read operation fails when the number of bit errors in the read operation exceeds the ECC error correction capability of the data storage device. When a read operation fails, the controller 120 can control an error recovery algorithm, such as... Figure 7 As shown.

[0073] Reference Figure 7 The controller 120 may perform one or more read retry operations on memory cells using one or more read threshold voltages applied in a set order (S100). For example, the read threshold voltages may include N (e.g., N is 50) read threshold voltages (or read voltage levels), including a first read threshold voltage to an Nth read threshold voltage. The first read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). A historical read threshold voltage may be the read threshold voltage used in the last successful decoding, i.e., the read voltage used in a read operation that passed before the read retry operation. The controller 120 may perform read retry operations until a successful decoding associated with the corresponding read retry operation is determined.

[0074] When all read retry operations using the read threshold voltage fail, the controller 120 may perform additional recovery operations. For example, additional recovery operations may include optimal read threshold voltage search (S200), soft decoding using error correction codes (ECC) (S300), and independent disk redundant array (RAID) recovery (S400).

[0075] In memory systems such as NAND-based storage systems, if several read attempts on a particular page fail, further read attempts on that page will not be effective. However, to meet the Quality of Service (QoS) requirements of memory systems (e.g., enterprise solid-state drives (SSDs)), it is necessary to read pages with fewer bit errors than the error correction capability of the error correction code (ECC) scheme used in decoding read data. Furthermore, individual read operations may have relatively long latency (e.g., 60 μs or longer). Therefore, it is desirable to provide a scheme for determining the read retry threshold voltage that does not cause an unreasonably large number of bit errors within a small latency.

[0076] This embodiment provides a scheme for adaptively determining the read retry threshold voltage for the next read operation using metadata collected from data from previous failed read attempts and performing read retry operations using an adaptive read retry threshold voltage. This scheme may be referred to as an "adaptive read retry (RR) scheme." The adaptive RR scheme i) adapts to the cell level distribution of any failed page, ii) is independent of NAND condition information (e.g., PEC, SPRD, etc.) utilized in historical reads and other read mechanisms, and iii) is independent of NAND generation. The performance of the adaptive RR scheme may depend on the number of previous reads available and the quality of the metadata provided by previous failed read attempts.

[0077] Figure 8 This is a diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0078] Reference Figure 8 The memory system 10 may include a controller 100 and a memory device 200. The memory device 200 may include a plurality of memory cells 210 (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, such as... Figure 3As shown. Cells in each row are connected to word lines (e.g., WL0), and cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided on the bit line when the word line is specified. During a read operation, the word line is specified again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0079] Controller 100 may include a read processor 810, a decoder 820, and a read threshold determiner 830. Although the components of controller 100 are shown to be implemented separately, these components may be integrated into a single component of controller 100 (i.e., firmware (FW)) or Figure 2 In the control component 120. Although in Figure 8 Not shown, but the controller 100 and memory device 200 may include, for example... Figure 2 The various other components shown.

[0080] The read processor 810 can respond to data from the host (e.g., Figure 1 The host device 5) controls one or more read operations performed on the memory device 200 based on read requests. The read processor 810 can use various read thresholds to control the read operations. The decoder 820 can decode the data associated with the read operations.

[0081] In some embodiments, the read processor 810 can use a read threshold selected from a set read level table to control read operations on memory cells. In some embodiments, the read level table may include multiple read thresholds, one of which is a default read threshold. When performing a read operation on an MSB page of a TLC, a pair of first and second read thresholds [VT0, VT4] can be selected, such as... Figure 6BAs shown. The first read threshold VT0 is used to distinguish between the erase state (i.e., E) and the first programming state (i.e., PV1), and the second read threshold VT4 is used to distinguish between the fourth programming state (i.e., PV4) and the fifth programming state (i.e., PV5). When performing a read operation on the LSB page of the TLC, a pair of first and second read thresholds [VT2, VT6] can be selected, as follows. Figure 6B As shown. The first read threshold VT2 is used to distinguish between the second programming state (i.e., PV2) and the third programming state (i.e., PV3), and the second read threshold VT6 is used to distinguish between the sixth programming state (i.e., PV6) and the seventh programming state (i.e., PV7).

[0082] Based on the decoding result of decoder 820, it can be determined whether a read operation performed using one or more read thresholds selected from the read threshold group was successful or failed. When a read operation using the selected read threshold fails, read processor 810 can use a read retry voltage (read retry entry) to control the execution of one or more read retry operations on the memory cell, such as... Figure 7 As shown.

[0083] The read threshold determiner 830 can estimate the read threshold voltage Vt using P1 estimation and CS estimation.

[0084] For P1 estimation, the read threshold determiner 830 can obtain metadata associated with a read operation performed on a selected page among a plurality of pages. For a given read operation, the metadata includes a plurality of read threshold voltages (i.e., read threshold voltage groups), a checksum value, and the percentage of bits of a specific value (i.e., 0 or 1) in the data associated with the read operation. The read threshold determiner 830 can use a setting function for the read threshold voltage group for the current read operation to determine a mathematical model for estimating the percentage of bits of a specific value in the data associated with the next read operation. The read threshold determiner 830 can determine a set of parameters by performing a linear regression on the mathematical model. The read threshold determiner 830 can determine the optimal previous read threshold voltage group among a plurality of read threshold voltage groups for a plurality of past reads based on a plurality of checksum values. The read threshold determiner 830 can determine a point corresponding to the optimal previous read threshold voltage group on a surface defined by the voltage of the optimal previous read threshold voltage group. In some embodiments, the surface of the LSB page of the TLC can be formed by a set [VT2, VT6] of a plurality of read threshold voltage groups (e.g., VT0 to VT7), such as Figure 12A and Figure 12B As shown. The read threshold determiner 830 can determine the line on the surface pointing to the next read threshold voltage for the next read operation based on this set of parameters.

[0085] For CS estimation, the read threshold determiner 830 can obtain metadata associated with a read operation on a selected page among multiple pages, including a set of read threshold voltages associated with the read operation. The read threshold determiner 830 can use a setting function for the read threshold voltage set and the largest possible checksum value to determine a mathematical model for estimating the checksum value of the data associated with the next read operation. The read threshold determiner 830 can determine a set of parameters by performing a polynomial regression on the mathematical model. The read threshold determiner 830 can estimate the next read threshold voltage for the next read operation based on this set of parameters.

[0086] Furthermore, the read threshold determiner 830 can determine whether the estimated read threshold voltage is valid. In some embodiments, the read threshold determiner 830 can determine whether the estimated next read threshold voltage is within a set threshold range.

[0087] When at least one of the estimated read threshold voltages is determined to be valid (passed), the read threshold determiner 830 can determine all estimated read threshold voltages or only the estimated read threshold voltage determined to be valid as the new read threshold voltage V for the next read operation. (n) .

[0088] When all estimated read threshold voltages are determined to be invalid (failed), the read threshold determiner 830 can perform an exploratory read to estimate a new read threshold voltage V for the next read operation. (n) In some embodiments, when it is determined that none of the estimated read threshold voltages are within a set threshold range, the read threshold determiner 830 can divide the set threshold range into multiple regions. The read threshold determiner 830 can find the region with the fewest previously read threshold voltages among the multiple regions. The read threshold determiner 830 can randomly determine any read threshold voltage in the region as the new read threshold voltage V. (n) .

[0089] Figure 9 This is a diagram illustrating a read threshold determiner 830 according to an embodiment of the present invention.

[0090] Reference Figure 9 For the adaptive RR scheme, the read threshold determiner 830 can use and process metadata to determine and output the read threshold voltage V for the next read operation. (n) In some embodiments, metadata can be collected from decoder 820 even if the read fails, i.e., the read data is not successfully decoded. Metadata for CS and P1 estimation as described above can be used. Metadata is input to each of CS estimator 832 and P1 estimator 834. For the LSB page of a TLC memory cell, the metadata includes... Figure 6BThe read threshold voltage (v2, v6) or (VT2, VT6) and the percentage of 1s in the read data or the decoded result of the read data (i.e., P1). For pages where random data is written, P1 is close to 50%, and the checksum represents the initial checksum weight of the codeword (e.g., a low-density parity-check (LDPC) codeword) corresponding to the decoded result of the read data. Although the features of the invention are described in the case of LSB pages of TLC memory cells, these features can also be applied to any page of various memory cells, such as MSB or CSB pages of TLC memory cells, or MSB, CMSB, CLSB, or LSB pages of QLC memory cells.

[0091] Figure 10A and Figure 10B This is a diagram illustrating metadata about the level distribution of TLC memory cells according to an embodiment of the present invention. Figure 10A and Figure 10B In the diagram, the horizontal axis (i.e., the x-axis) represents the read threshold voltage, and the vertical axis (i.e., the y-axis) represents the distribution, which is the probability density function (PDF) of the programmed TLC memory cells.

[0092] Reference Figure 10A When randomized data is programmed into the LSB pages of a TLC memory cell, P1 (percentage of 1) is close to 50% in the shaded area.

[0093] Ideally, if these distributions do not intersect, error-free data can be recovered by applying a read threshold. However, these distributions may intersect or overlap. In such cases, by applying a read threshold (e.g., VT2 & VT6 of the LSB page), some information can be observed even if decoding fails. Figure 10A In the diagram, the shaded area represents the probability of observing the binary value 1. Figure 10B The shaded area represents the probability of a read failure. After each read, the number of cells read as 1 can be found. However, the probability of a read failure cannot be observed. Instead, the checksum can be observed, which is a mapping of the read failure probability.

[0094] Reference Figure 10B The checksum or checksum weight of the codewords from the decoded data can be used to estimate the bit error rate (BER), i.e., read failure.

[0095] Return to reference Figure 9 The read threshold determiner 830 can receive metadata associated with previously failed read data as input. In some embodiments, the metadata may include data from... Figure 8 The information V collected by the read processor 810 and / or decoder 820 in the middle r and O r. It can be a set of previous read thresholds (i.e., failed reads) of the LSB pages of a TLC memory cell. It can be achieved by applying V r The resulting set of observations is CS,P1. CS represents the checksum value, and P1 represents the percentage of 1s in the decoded data.

[0096] The CS estimator 832 can estimate the checksum value of the next potential read threshold voltage to be used in the next read operation. This represents the estimated checksum (CS). Although the actual CS value can be obtained after each read operation, the CS estimator 832 can use a mathematical model to estimate the checksum value. The CS estimator 832 can find... This makes it as close as possible to the CS. In some embodiments, the CS estimator 832 can use a mathematical model (i.e., a quadratic model) as shown in equation (1) to estimate the checksum value of the next potential read threshold voltage:

[0097]

[0098] In equation (1), S(·) represents the sigmoid function, and cs max Represents the maximum possible checksum value, where (v2, v6) represents a set of previously read thresholds for the LSB pages of a TLC memory cell. CS max This can be the size of the parity check unit or the number of rows in the parity check matrix, which are associated with the decoding of the read data. In some embodiments, when the number of rows in the parity check matrix is ​​m, CS max It can be determined to be m / 2. In other embodiments, CS max It can be determined as m.

[0099] The CS estimator 832 can find a set of parameters θs using equation (1) and can provide... Minimize a set of read threshold voltages. One of the provided set of read threshold voltages can be used as the next potential read threshold voltage. For this purpose, according to equation (1), the CS estimator 832 can derive the following equation (2):

[0100]

[0101] Next, the CS estimator 832 can perform a multinomial regression on equation (2) to obtain a set of parameters Θs={θ0,θ1,…,θ4}.

[0102] Finally, as shown in equation (3) below, the CS estimator 832 can calculate a set of read threshold voltages based on this set of parameters, one of which can be used as the next read threshold voltage:

[0103]

[0104] As mentioned above, in order to optimize The CS estimator 832 can make The partial derivatives with respect to v2 and v2 are equal to 0, and then the result is obtained.

[0105] The P1 estimator 834 can use a mathematical model (i.e., a linear model) as shown in equation (4) to estimate the percentage of 1 in the data associated with the next potential read threshold voltage to be used in the next read operation:

[0106]

[0107] The P1 estimator 834 can find a set of parameters φs using equation (4) and can provide a set of read threshold voltages that map the best previous reads to the surface formed by the read threshold voltages (e.g., Figure 12A A set of lines on the plane of coordinates in the image, where each of the read threshold voltages in the set is a potential read threshold voltage for the next read operation. For this operation, according to equation (4), the P1 estimator 834 can derive the following equation (5):

[0108]

[0109] Next, the P1 estimator 834 can perform linear regression on equation (5) to obtain a set of parameters Φs={φ0,φ1,φ2}.

[0110] Then, the P1 estimator 834 can be obtained through equation k. * =arg min 1≤k≤m cs (k) Find the best previously read index.

[0111] Finally, the P1 estimator 834 can calculate the next potential read threshold voltage based on this set of parameters, as shown in the following equation (6):

[0112]

[0113] In equation (6), “line” refers to a line in the two-dimensional space of (v2, v6).

[0114] During the reading process, the goal is to make P1 as close to 0.5 as possible. Therefore, the P1 estimator 834 can choose to provide... The threshold voltage. Based on the above equation (4), it can be derived that... And φ0+φ1v2+φ2v6=0. In other words, the P1 estimator 834 can indicate that any point on the line (φ0+φ1v2+φ2v6=0) has approximately the same number of 1s and 0s (P1=50%).

[0115] The P1 estimator 834 can select only one point from those points provided by P1 as the next read threshold voltage. In other words, the P1 estimator 834 can find a point on the line (φ0+φ1v2+φ2v6=0) as the optimal previous read threshold voltage. The optimal previous read threshold voltage can be one with the lowest checksum, as in equation (6). As shown. The goal is to find a point on the line (φ0 + φ1v2 + φ2v6 = 0) as the optimal preceding point. Need to start from point Draw another line perpendicular to the line (φ0 + φ1v2 + φ2v6 = 0). The P1 estimator 834 can find the intersection of these two lines as the next suggested reading threshold voltage. This operation can be called point... Projected onto the line (φ0+φ1v2+φ2v6=0).

[0116] Estimators 832 and 834 suggest (or anticipate) read threshold voltages for the next potential read threshold voltage. This can depend on how much data is available from previous reads. Based on previous read data, it is recommended to read the threshold voltage. Both or one of them may be within the acceptable threshold range R v In addition, in some embodiments, the acceptable threshold range R for the read threshold voltage (v2) of reading the LSB page of a TLC memory cell is... v This can be obtained from the read retry table, i.e. And the acceptable threshold range R for the read threshold voltage (v6) of the LSB page of the TLC memory cell. v This can be obtained from the read retry table, i.e. In this article, This indicates that the minimum value among all v2 thresholds in the retry table should be read. This indicates that the maximum value among all v2 thresholds in the retry table should be read. This indicates that the minimum value among all v6 thresholds in the retry table should be read. This indicates that the maximum value among all v6 thresholds in the retry table is read.

[0117] A potential read threshold voltage may occur when all previous reads are very close to each other and do not contain enough information to identify the face, or when many previous reads are affected by excessive noise. The validity checker 836 can check for incorrect estimates of the suggested read threshold voltage. Whether at least one of them is within the set acceptable threshold range R v In addition, the validity checker 836 can perform check operations and perform corresponding operations based on the check results, as shown in List (1):

[0118] List (1)

[0119]

[0120] Refer to List 1, when it is recommended to read the threshold voltage. Not within the set acceptable threshold range R v In addition, the validity checker 836 can determine the average of the two read threshold voltages as the read threshold voltage for the next read operation. When a read threshold voltage is recommended... One of them is in the set acceptable threshold range R v Within this range, the validity checker 836 can determine whether the value is within the set acceptable threshold range R. v The read threshold voltage within a certain range is used as the read threshold voltage for the next read operation. When a read threshold voltage is recommended... Both are within the set acceptable threshold range R. v In other cases, the validity checker 836 can control the exploratory read module (not shown) to handle situations where the suggested read threshold voltage is unreliable. The exploratory read module can set an acceptable threshold range R. v Divide the data into multiple regions, and find the region with the fewest previous reads among these regions. Then, the validity checker 836 can check the area The random point in the data is determined as the read threshold voltage for the next read operation. Out-of-bounds checks or other similar heuristic methods can be used to check the set acceptable threshold range R. v .

[0121] In some embodiments, the validity checker 836 can determine the acceptable threshold range R. v It is divided into four zones: Zone 1 to Zone 4. For example, in... In this case, the range of each of Zones 1 to 4 is shown in List (2):

[0122] List (2)

[0123]

[0124] Figure 11This is a flowchart illustrating an operation for determining a read retry threshold voltage according to an embodiment of the present invention. Operation 1100 may be performed by including Figure 8 and Figure 9 The firmware of the controller 100 is used to execute the read threshold determiner 830.

[0125] Reference Figure 11 In operation 1110, controller 100 can estimate the read threshold voltage Vt using P1 estimation. In some embodiments, as previously described, controller 100 can obtain metadata associated with a read operation on a selected page among a plurality of pages. Controller 100 can use a setting function for the set of read threshold voltages for the current read operation to determine a mathematical model for estimating the bit percentage of a specific value (e.g., 1) in the data for the next read operation. Controller 100 can determine a set of parameters by performing linear regression on the mathematical model. Controller 100 can determine the optimal previous read threshold voltage set among the plurality of read threshold voltage sets based on a plurality of checksum values. Controller 100 can determine points in a surface formed by each of the plurality of read threshold voltage sets corresponding to the optimal previous read threshold voltage set. Controller 100 can determine a line of the surface based on this set of parameters. Controller 100 can estimate the next read threshold voltage for the next read operation by projecting the points onto the line.

[0126] In operation 1120, controller 100 can estimate the read threshold voltage Vt using CS estimation. In some embodiments, as previously described, controller 100 can obtain metadata associated with a read operation on a selected page among a plurality of pages. Controller 100 can use a setting function for the set of read threshold voltages and a setting checksum value to determine a mathematical model for estimating the checksum value of the data associated with the next read operation. Controller 100 can determine a set of parameters by performing a polynomial regression on the mathematical model. Controller 100 can estimate the next read threshold voltage for the next read operation based on this set of parameters.

[0127] In operation 1130, controller 100 may determine whether the read threshold voltage estimated in operations 1110, 1120 is valid. In some embodiments, controller 100 may determine whether the estimated next read threshold voltage is within an acceptable threshold range.

[0128] When at least one of the estimated read threshold voltages is determined to be valid (passed), the controller 100 may determine either or both of the estimated read threshold voltages as the new read threshold voltage V for the next read operation. (n) .

[0129] When it is determined that all estimated read threshold voltages are invalid (failed), in operation 1140, controller 100 may perform an exploratory read to estimate a new read threshold voltage V for the next read operation. (n) In some embodiments, when it is determined that neither the first nor the second next read threshold voltage is within an acceptable threshold range, the controller 100 may divide the set threshold range into multiple regions. The controller 100 may find the region among the multiple regions corresponding to the fewest read operations. The controller 100 may randomly determine any read threshold voltage within the region as the new read threshold voltage V. (n) .

[0130] Figures 12A to 12D This is a diagram illustrating an example of an operation for determining a read retry threshold voltage according to an embodiment of the present invention.

[0131] Figure 12A and Figure 12B The final suggested read r5 of the adaptive read retry (RR) is shown, and the fact that this suggested read leads to successful decoding.

[0132] Figure 12C and Figure 12D The suggested reads of CS estimator 832 and P1 estimator 834 are shown respectively.

[0133] Reference Figure 12C Real contour lines represent the actual contour lines of the CS surface, which are actually unknown to the decoder. The symbol “◎” indicates information previously read. Imaginary contour lines represent the estimated CS surface obtained by the CS estimator only by looking at the information indicated by the symbol “◎”. A point represents the suggested read of the CS estimator, which is the lowest point of the CS surface (see Equation (3)). A point “●” represents the suggested read described in Equation (3).

[0134] Reference Figure 12D The symbol “◎” indicates previously read information. The solid line represents the actual P1 surface unknown to the decoder and the adaptive RR model. The dashed line 1210 represents the linear estimate of P_1 = 0.5 (i.e., the line (φ0 + φ1v2 + φ2v6 = 0) in paragraph

[00108] . Line 1210 is the projection of the best previous read (i.e., ◎ on line 1210) onto line 1210. The dot “●” indicates the suggested read described in equation (6).

[0135] The final output of adaptive RR is Figure 12C The dot "●" and Figure 12D The combination of dots "●" in the text.

[0136] Figure 13 This is a graph illustrating the performance of the adaptive read retry (RR) scheme according to an embodiment of the present invention.

[0137] Reference Figure 13 The horizontal axis (x-axis) represents the number of reads, and the vertical axis (y-axis) represents the probability of a successful read, which is the cumulative distribution function (CDF) of the success rate of the decoder in decoding the read data. The performance of the adaptive read retry scheme depends on the number of previous reads available.

[0138] There are three cases, each with a different number of prior reads |R Pre |: 3, 4, and 5. In the three previous reads (i.e., |R) Pre With |=3), when a second read attempt is performed using the read threshold voltage determined by the adaptive RR scheme, the decoder success rate is approximately 65% ​​(1310). In four previous reads (i.e., |R=3), the decoder success rate is approximately 65% ​​(1310). Pre With |=4), when a second read attempt is performed using the read threshold voltage determined by the adaptive RR scheme, the decoder success rate is approximately 71% (1320). In five previous reads (i.e., |R)... Pre When |=5), the decoder success rate increases to 85% (1330) when a second read attempt is performed using the read threshold voltage determined by the adaptive RR scheme. In |R Pre When |=5, the decoder success rate increases to 95% (1330) when two more read attempts are performed using the read threshold voltage determined by the adaptive RR scheme. As mentioned above, the latency of a single read can be approximately 60 μs. For pages that fail to read after a retry, an algorithm called E-Boost is executed to find the optimal read threshold. Typically, the algorithm requires approximately 500 μs (a very long latency) to suggest a new read. However, the inventors observed that the embodiment suggests a new read in less than 10 μs and achieves a success rate of over 75% after two read attempts, such as Figure 13 As shown. In other words, the embodiment reduces read latency and thus improves Quality of Service (QoS).

[0139] As described above, the embodiments provide a scheme for adaptively determining a read retry threshold voltage for the next read operation using metadata collected from previously failed read data. The embodiments can improve the Quality of Service (QoS) requirements of enterprise customers for solid-state drives.

[0140] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are exemplary and not restrictive. The invention is intended to cover all modifications and substitutions falling within the scope of the claims.

Claims

1. A memory system comprising: a memory device including a plurality of pages; and a controller, obtains meta-information associated with a read operation on a selected page among the plurality of pages, the meta-information including a set of read threshold voltages; determines a mathematical model for estimating a checksum value associated with a next read operation using a setting function of the set of read threshold voltages and a setting checksum value; determines a set of parameters by performing a polynomial regression on the mathematical model; and estimates a next read threshold voltage of the next read operation based on the set of parameters.

2. The memory system of claim 1, wherein the setting function includes a sigmoid function, and wherein the selected page includes a least significant bit (LSB) page of triple level cell (TLC).

3. The memory system of claim 2, wherein the mathematical model is a quadratic model, expressed as: where S(·) denotes a sigmoid function, (v2, v6) denotes a set of read threshold voltages of the LSB page, denotes an estimated checksum value of data associated with the next read operation, cs max denotes the set checksum value, Θ = {θ0, θ1,..., θ4} denotes the set of parameters.

4. The memory system of claim 3, wherein the setting checksum value is determined based on a number of rows of a parity check matrix used to decode data associated with the read operation.

5. The memory system of claim 3, wherein the controller determines the set of parameters by performing the polynomial regression on an inverse sigmoid function of the mathematical model according to the following equation: wherein CS denotes the checksum value.

6. A memory system comprising: a memory device including a plurality of pages; and a controller: obtains meta-information associated with a read operation on a selected page among the plurality of pages, the meta-information including a plurality of sets of read threshold voltages, a plurality of checksum values, and a bit percentage of a specific value in data; determines a mathematical model for estimating the bit percentage of the specific value in data of a next read operation using a setting function of a set of read threshold voltages of a current read operation; determines a set of parameters by performing a linear regression on the mathematical model; determines a plane formed by each of the plurality of sets of read threshold voltages; determines a line of the plane based on the set of parameters; determines a best previous set of read threshold voltages among the plurality of sets of read threshold voltages based on the plurality of checksum values; determines a point in the plane corresponding to the best previous set of read threshold voltages; and estimates a next read threshold voltage of the next read operation by projecting the point onto the line.

7. The memory system of claim 6, wherein the setting function includes a sigmoid function, and wherein the selected page includes a least significant bit (LSB) page of triple level cell (TLC).

8. The memory system of claim 7, wherein the mathematical model is a quadratic model, expressed as the following equation: where S( ) denotes a sigmoid function, (v2, v6) denotes a set of read threshold voltages of the LSB page, denotes a percentage of bits representing a particular value, and Φ = {φ0, φ1, φ2} denotes the set of parameters.

9. The memory system of claim 8, wherein the controller determines the set of parameters by performing the linear regression on an inverse sigmoid function of the mathematical model according to the following equation:

10. The memory system of claim 8, wherein the specific value is 1. 11.The memory system of claim 8, wherein the controller estimates the next read threshold voltage according to φ 0 + φ 1 v 2 + φ 2 v 6 = 0. 12.A memory system comprising: a memory device including a plurality of pages; and a controller: obtains meta information associated with a read operation on a selected page among the plurality of pages, the meta information including a plurality of read threshold voltage sets, a plurality of checksum values, and a bit percentage of a specific value in data; determines a first mathematical model for estimating a checksum value of data associated with a next read operation using a set checksum value and a set function of the read threshold voltage sets; determines a first set of parameters by performing a polynomial regression on the first mathematical model; estimates a first next read threshold voltage of the next read operation based on the first set of parameters; determines a second mathematical model for estimating a bit percentage of a specific value in data of the next read operation using a set function of a read threshold voltage set for a current read operation; determines a second set of parameters by performing a linear regression on the second mathematical model; determines a plane formed by each of the plurality of read threshold voltage sets; determines a line of the plane based on the second set of parameters; determines a best previous read threshold voltage set among the plurality of read threshold voltage sets based on the plurality of checksum values; determines a point in the plane corresponding to the best previous read threshold voltage set; and estimates a second next read threshold voltage of the next read operation by projecting the point onto the line. 13.The memory system of claim 12, wherein the set function includes a sigmoid function, and wherein the selected page includes a least significant bit (LSB) page of triple level cell (TLC). 14.The memory system of claim 13, wherein the first mathematical model is a quadratic model, expressed as: 15.The memory system of claim 14, wherein the set checksum value is determined based on a number of rows of a parity check matrix used to decode data associated with the read operation. where S( ) denotes a sigmoid function, (v2, v6) denotes a read threshold voltage set of the LSB page, denotes an estimated checksum value of the next read operation, cs max denotes the set checksum value, Θ = {θ0, θ1,..., θ4} denotes the first set of parameters. 16.The memory system of claim 14, wherein the controller determines the first set of parameters by performing the polynomial regression on an inverse sigmoid function of the first mathematical model according to the following equation: CS denotes the checksum value. wherein 17.The memory system of claim 13, wherein the second mathematical model is a quadratic model, expressed as the following equation: 18.The memory system of claim 17, wherein the controller determines the second set of parameters by performing the linear regression on an inverse sigmoid function of the mathematical model according to the following equation: where S(·) denotes a sigmoid function, (v2, v6) denotes a read threshold voltage set of the LSB page, denotes a bit percentage of a particular value, Φ = {φ0, φ1, φ2} denotes the second set of parameters. 19.The memory system of claim 17, wherein the specific value is 1, and wherein the controller estimates the second next read threshold voltage according to φ 0 + φ 1 v 2 + φ 2 v 6 = 0. ​ 20. The memory system of claim 13, wherein the controller further determines whether the first next read threshold voltage and the second next read threshold voltage are within a set threshold range; when it is determined that neither the first next read threshold voltage nor the second next read threshold voltage is within the set threshold range, the controller: divides the set threshold range into a plurality of regions, finds a region corresponding to the least number of read operations among the plurality of regions, and randomly determines any read threshold voltage in the region as a next read threshold voltage.

21. The memory system of claim 20, wherein the controller: when it is determined that the first next read threshold voltage is within the set threshold range, determines the first next read threshold voltage as the next read threshold voltage.

22. The memory system of claim 20, wherein the controller: when it is determined that the second next read threshold voltage is within the set threshold range, determines the second next read threshold voltage as the next read threshold voltage.

23. The memory system of claim 20, wherein the controller: when it is determined that neither the first next read threshold voltage nor the second next read threshold voltage is within the set threshold range, randomly selects one of the first next read threshold voltage and the second next read threshold voltage as the next read threshold voltage.

24. The memory system of claim 20, wherein the controller: when it is determined that neither the first next read threshold voltage nor the second next read threshold voltage is within the set threshold range, randomly selects one of the first next read threshold voltage and the second next read threshold voltage as the next read threshold voltage.

25. The memory system of claim 20, wherein the controller:

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