Etching method of silicon carbide trench and preparation method of silicon carbide device

Abstract

The application provides a silicon carbide trench etching method and a silicon carbide device preparation method. The etching method comprises the following steps: forming a first dielectric layer on a silicon carbide substrate; forming a second dielectric layer on the first dielectric layer; forming a photoresist pattern on the second dielectric layer; etching the second dielectric layer based on the photoresist pattern, and stopping the etching at the surface of the first dielectric layer to form a window; removing the photoresist pattern, wet etching the first dielectric layer through the window to remove the first dielectric layer in the window, and simultaneously removing the rough structure of the sidewall of the window to reduce the roughness of the sidewall of the window; taking the first dielectric layer and the second dielectric layer as masks, etching the silicon carbide substrate to form a trench; and removing the first dielectric layer and the second dielectric layer and performing damage repair treatment on the trench. The application can effectively reduce the surface roughness of the silicon carbide trench, improve the quality of the trench gate oxide layer of the silicon carbide device, and greatly reduce the influence of the trench roughness on the channel carrier mobility.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and in particular relates to a method for etching silicon carbide trenches and a method for fabricating silicon carbide devices. Background Technology

[0002] Silicon carbide (SiC) is widely recognized as a promising semiconductor material due to its unique physical properties and material characteristics. As a wide-bandgap semiconductor, SiC possesses high critical electric field strength, high saturated electron mobility, and high thermal conductivity, making it promising for high-power, high-temperature, high-frequency, and radiation-resistant electronic power applications. SiC's ability to form its native oxide, silicon dioxide (SiO2), provides it with a significant material advantage in device fabrication.

[0003] Silicon carbide trench MOSFETs (UMOSFETs) exhibit high channel mobility along the C-axis, high channel density, and the absence of additional JFET resistance, resulting in lower characteristic on-resistance compared to silicon carbide planar DMOSFETs. These superior characteristics give silicon carbide UMOSFETs a promising future in various applications. High-performance silicon carbide trench devices require smooth, trench-free bottoms and steep, smooth sidewalls. In the fabrication of silicon carbide trench UMOSFETs, the morphology and roughness of the trench etching significantly impact reverse breakdown, leakage current performance, and reliability. During reverse operation, severe electric field concentration occurs at trench corners. Unsmooth trench bottoms or micro-trenches at trench corners can easily lead to gate oxide breakdown, causing device damage. Damaged or highly rough trench sidewalls also affect the quality of the gate oxide layer, thus impacting device reliability and lifespan. This significant gate oxide reliability issue is a key factor hindering the commercial mass production of UMOSFETs. In addition, rough trench sidewalls can also affect the channel electron mobility, so improving the process of roughening the sidewalls of silicon carbide trench etching is an urgent problem to be solved.

[0004] The strong chemical bonds between silicon (Si) and carbon (C) atoms result in the high chemical inertness of silicon carbide, making room-temperature wet etching extremely difficult. Therefore, the fabrication of mesa and trench silicon carbide devices relies on dry etching. Fluorine-based gases have become the mainstream etching gases due to their faster etching rates compared to chlorine-based and bromine-based gases. O2 is typically added to the reactants to enhance C atom removal and increase the concentration of active reactants. Because of the process atmosphere used in silicon carbide etching, photoresist (PR) is unsuitable as a mask due to its low selectivity (<0.5, fluorine-based gases) for etching deep trenches in silicon carbide. The commonly used mask material for silicon carbide device fabrication is SiO2 deposited by chemical vapor deposition (CVD). There are several reasons for the roughness and damage of the sidewalls caused by silicon carbide trench etching: (1) During the silicon carbide etching process, the rough sidewall stripes formed by the etching of the SiO2 hard mask are continuously replicated. In particular, the roughness near the bottom of the SiO2 hard mask sidewall has a great influence on the roughness of the sidewall of the silicon carbide trench. In addition, the step formed by the bottom corner of the silicon carbide caused by the SiO2 etching is also not conducive to obtaining a steep trench morphology; (2) The physical bombardment of the silicon carbide sidewall and bottom by the high density and high energy plasma during the silicon carbide trench etching process inevitably causes etching damage; (3) During the silicon carbide trench etching process, the fluorine-based gas will not only etch silicon carbide but also etch SiO2. The byproducts generated by the reaction of the fluorine-based gas with SiO2 that are not removed are deposited on the surface of the silicon carbide trench. These byproducts act as "micromasks" to affect the local etching rate and cause a considerable degree of surface roughness.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for etching silicon carbide trenches and a method for fabricating silicon carbide devices, so as to solve the problem of high surface roughness of silicon carbide trenches in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides an etching method for silicon carbide trenches. The etching method includes: providing a silicon carbide substrate; forming a first dielectric layer on the silicon carbide substrate; forming a second dielectric layer on the first dielectric layer, wherein the thickness of the first dielectric layer is less than the thickness of the second dielectric layer; forming a photoresist pattern on the second dielectric layer; etching the second dielectric layer based on the photoresist pattern, stopping the etching at the surface of the first dielectric layer to form a window; removing the photoresist pattern; wet etching the first dielectric layer through the window to remove the first dielectric layer in the window, wherein the wet etching simultaneously removes the rough structure of the window sidewalls to reduce the roughness of the window sidewalls; using the first and second dielectric layers as masks, etching the silicon carbide substrate to form a trench; removing the first and second dielectric layers and performing damage repair treatment on the trench.

[0008] Optionally, the thickness of the first dielectric layer ranges from 0.01 micrometers to 10 micrometers, and the thickness of the second dielectric layer ranges from 0.1 micrometers to 50 micrometers.

[0009] Optionally, the first dielectric layer is a silicon nitride layer, and the second dielectric layer is a silicon dioxide layer.

[0010] Optionally, the etching solution used for wet etching of the first dielectric layer through the window includes a mixed acidic solution of H3PO4 and HF.

[0011] Optionally, in the mixed acidic solution, the volume ratio of HF to H3PO4 is 0:1 to 1:0.

[0012] Optionally, the etching process used to etch the silicon carbide substrate to form the trench includes reactive ion etching.

[0013] Optionally, when the first dielectric layer is wet-etched through the window to remove the first dielectric layer in the window, the first dielectric layer is also laterally recessed into the window by a width to form a lateral groove, so as to expose the corner between the trench and the top surface of the silicon carbide substrate, and at the same time repair the damage generated on the sidewall during the etching of the second dielectric layer.

[0014] Optionally, removing the first dielectric layer and the second dielectric layer and performing damage repair treatment on the trench includes: performing a first damage repair treatment on the trench using chemical dry etching before removing the first dielectric layer and the second dielectric layer.

[0015] Optionally, removing the first dielectric layer and the second dielectric layer and performing damage repair treatment on the trench further includes: after removing the first dielectric layer and the second dielectric layer, oxidizing the surface of the trench to form a sacrificial oxide layer, and removing the sacrificial oxide layer to perform a second damage repair treatment on the trench.

[0016] The present invention also provides a method for fabricating a silicon carbide device, the method comprising the steps of: forming a trench in the silicon carbide substrate by means of the silicon carbide trench etching method described in any of the above embodiments; and fabricating a trench gate structure of the silicon carbide device based on the trench.

[0017] As described above, the etching method for silicon carbide trenches and the fabrication method for silicon carbide devices of the present invention have the following beneficial effects:

[0018] The silicon carbide trenches obtained by the etching method of this invention have relatively steep and smooth sidewalls and rounded corners.

[0019] This invention uses a stack of silicon nitride and silicon dioxide layers as a hard mask. When dry etching the silicon dioxide layer with photoresist as a mask, the etching can automatically stop on the surface of the silicon nitride layer below it, so that the dry etching process will not damage the silicon carbide substrate and can effectively expand the process window.

[0020] This invention uses mixed acid treatment to improve the sidewall roughness of the hard mask layer (silicon dioxide layer), making the surface of the etched hard mask smooth, interrupting the replication of rough stripes on the hard mask layer during the silicon carbide trench etching process, and ultimately greatly improving the sidewall roughness of the silicon carbide trench.

[0021] This invention repairs damage to the sidewalls and bottom of silicon carbide trenches, thereby further improving the roughness of the sidewalls of the silicon carbide trenches.

[0022] This invention is applicable to the fabrication of trenches for silicon carbide UMOSFETs and trench-type JFET devices. Due to the low surface roughness of silicon carbide trenches, the quality of the trench gate oxide layer of silicon carbide devices is effectively improved, and the influence of trench roughness on channel carrier mobility is greatly reduced. Attached Figure Description

[0023] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0024] Figures 1-10 The diagram shows the structural schematics of each step in the etching method for silicon carbide trenches according to an embodiment of the present invention.

[0025] Figure 11 and Figure 12 The images shown are SEM images of the second dielectric layer before wet etching and the second dielectric layer after wet etching, respectively, according to an embodiment of the present invention.

[0026] Figure 13 and Figure 14 The images shown are SEM images of the silicon carbide trenches before and after the damage repair treatment, respectively, according to an embodiment of the present invention.

[0027] Component designation explanation

[0028] 101 Silicon Carbide Substrate

[0029] 102 Silicon carbide epitaxial layer

[0030] 103 First Dielectric Layer

[0031] 104 Second dielectric layer

[0032] 105 photoresist layer

[0033] 106 Photoresist Pattern

[0034] 107 windows

[0035] 108 Rough Structure

[0036] 109 Horizontal Groove

[0037] 110 Silicon carbide trench

[0038] 111 Rough Structure

[0039] 112 Sacrificial Oxide Layer Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0042] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0043] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0045] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] The mainstream process for improving the roughness of silicon carbide trench etching can be to perform etching damage repair treatment after the silicon carbide trench etching. Post-etching treatment methods include, for example, chemical dry etching (CDE), high-temperature annealing in a silicon atmosphere (SiH4 / AR), and sacrificial oxidation. This invention improves the roughness of silicon carbide trench etching by optimizing the pretreatment process of hard mask etching and combining it with etching damage repair treatment after silicon carbide trench etching.

[0048] Based on the above, such as Figures 1 to 14 As shown, this embodiment provides a method for etching silicon carbide trenches, the etching method comprising:

[0049] like Figure 1 As shown, step 1) is performed first, a silicon carbide substrate is provided, and a first dielectric layer 103 is formed on the silicon carbide substrate.

[0050] In one embodiment, the silicon carbide substrate may include a silicon carbide substrate 101 and a silicon carbide epitaxial layer 102 formed on the silicon carbide substrate 101 by processes such as vapor phase epitaxy. Specifically, the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are 4H-SiC. The silicon carbide epitaxial layer 102 may be doped or undoped. The thickness of the silicon carbide epitaxial layer 102 can be set according to different device requirements, for example, it may be 500 nanometers to 100 micrometers.

[0051] In one embodiment, the first dielectric layer 103 is selected as a silicon nitride layer, which can be formed by a process such as chemical vapor deposition (CVD). The thickness of the first dielectric layer 103 ranges from 0.01 micrometers to 10 micrometers. In a specific implementation, the thickness of the first dielectric layer 103 is 0.05 micrometers. The first dielectric layer 103 can serve as a stop layer during the subsequent etching of the second dielectric layer 104, protecting the silicon carbide epitaxial layer 102 from etching damage during the etching of the second dielectric layer 104. This avoids the formation of steps in the silicon carbide epitaxial layer 102 during the etching of the second dielectric layer, which would be detrimental to obtaining a steep trench morphology.

[0052] like Figure 2 As shown, then step 2) is performed to form a second dielectric layer 104 on the silicon nitride layer, wherein the thickness of the first dielectric layer 103 is less than the thickness of the second dielectric layer 104.

[0053] The first dielectric layer 103 and the second dielectric layer 104 are made of different materials. In one embodiment, the second dielectric layer 104 is selected as a silicon dioxide layer, which can be formed by a process such as chemical vapor deposition (CVD). The thickness of the second dielectric layer 104 ranges from 0.1 micrometers to 50 micrometers.

[0054] like Figures 3-4 As shown, step 3) is then performed to form a photoresist pattern 106 on the second dielectric layer 104.

[0055] In one embodiment, forming a photoresist pattern 106 on the second dielectric layer 104 includes the following steps:

[0056] Step 3-1): A photoresist layer 105 is formed on the second dielectric layer 104 by spin coating, such as... Figure 3 As shown;

[0057] Step 3-2): The photoresist layer 105 is processed by exposure and development processes to form a photoresist pattern 106, such as... Figure 4 As shown.

[0058] like Figure 5As shown, step 4) is then performed, where the second dielectric layer 104 is dry-etched based on the photoresist pattern 106. By selecting an appropriate etching selectivity, the etching stops on the surface of the first dielectric layer 103 to form a window 107. Due to the spacing of the first dielectric layers 103, the etching of the second dielectric layer will not damage the silicon carbide substrate and will not adversely affect subsequent silicon carbide etching.

[0059] like Figure 6 As shown, then step 5) is performed to remove the photoresist pattern 106 and wet-etch the first dielectric layer 103 through the window 107 to remove the first dielectric layer 103 in the window 107. The wet etching also removes the rough structure 108 of the sidewall of the window 107 to reduce the roughness of the sidewall of the window 107.

[0060] In one embodiment, the etching solution used for wet etching of the first dielectric layer 103 through the window 107 includes a mixed acidic solution of H3PO4 and HF. Specifically, in the mixed acidic solution, the volume ratio of HF to H3PO4 is 0:1 to 1:0, for example, the volume ratio of HF to H3PO4 can be 0.1:0.9.

[0061] Since dry etching typically forms a rough structure 108 on the sidewalls of the second dielectric layer 104 in the window 107, in this embodiment of wet etching, the HF in the mixed acid can remove the rough structure 108 on the sidewalls of the second dielectric layer 104, thereby achieving a certain degree of planarization. Figure 11 and Figure 12 The images shown are SEM images of the second dielectric layer 104 before wet etching and SEM images of the second dielectric layer 104 after wet etching, respectively. Figure 11 and Figure 12 The before-and-after comparison shows that the sidewall roughness of the second dielectric layer 104 was significantly improved after treatment with the mixed acid solution. This invention uses mixed acid treatment to improve the sidewall roughness of the hard mask layer (silicon dioxide layer), making the surface of the etched hard mask smooth and interrupting the replication of rough stripes on the hard mask layer during the etching process of the silicon carbide trench 110. Ultimately, this greatly improves the sidewall roughness of the silicon carbide trench 110.

[0062] Furthermore, when the first dielectric layer 103 is wet-etched through the window 107 to remove it, the first dielectric layer 103 is also laterally recessed into the window 107 by a width to form a lateral groove 109, thereby exposing the corner between the trench and the top surface of the silicon carbide substrate. This lateral groove 109 can expose the corner between the trench and the top surface of the silicon carbide substrate during the subsequent etching of the silicon carbide trench 110, resulting in a smooth corner in the subsequent silicon carbide trench 110 etching. Simultaneously, it repairs damage to the sidewalls caused during the etching of the second dielectric layer, thereby improving the withstand voltage performance of the silicon carbide device.

[0063] like Figure 7 As shown, the silicon carbide substrate is etched to form trenches using the first dielectric layer 103 and the second dielectric layer 104 as masks.

[0064] In one embodiment, the etching process used to etch the silicon carbide substrate to form the trench includes reactive ion etching (RIE). RIE typically forms a roughened structure 111 on the sidewalls and bottom of the silicon carbide trench 110.

[0065] like Figures 8-10 As shown, step 6) is performed last to remove the first dielectric layer 103 and the second dielectric layer 104 and to repair the damage to the trench.

[0066] In one embodiment, removing the first dielectric layer 103 and the second dielectric layer 104 and performing damage repair treatment on the trench includes: before removing the first dielectric layer 103 and the second dielectric layer 104, performing a first damage repair treatment on the trench using chemical dry etching to remove the rough structure 111 on the sidewalls and bottom of the silicon carbide trench 110, such as... Figure 8 As shown.

[0067] In one embodiment, removing the first dielectric layer 103 and the second dielectric layer 104 and performing damage repair treatment on the trench further includes: after removing the first dielectric layer 103 and the second dielectric layer 104, oxidizing the surface of the trench to form a sacrificial oxide layer 112, such as through thermal oxidation, and removing the sacrificial oxide layer 112 to perform a second damage repair treatment on the trench. Figure 9 and Figure 10 As shown.

[0068] Figure 13 and Figure 14 The images show SEM images of the silicon carbide trench 110 before and after damage repair treatment. As can be seen from the images, the silicon carbide trench 110 after damage repair treatment in this embodiment has relatively smooth sidewalls.

[0069] This embodiment also provides a method for fabricating a silicon carbide device, the method comprising the steps of: forming trenches in the silicon carbide substrate by etching the silicon carbide trench 110 as described in the above embodiment; and fabricating the trench gate structure of the silicon carbide device based on the trenches. In this embodiment, due to the low surface roughness of the silicon carbide trench 110, the quality of the trench gate oxide layer of the silicon carbide device is effectively improved, and the influence of trench roughness on the channel carrier mobility is greatly reduced.

[0070] As described above, the etching method for silicon carbide trenches and the fabrication method for silicon carbide devices of the present invention have the following beneficial effects:

[0071] The silicon carbide trenches obtained by the etching method of this invention have relatively steep sidewalls and smooth corners.

[0072] This invention uses a stack of silicon nitride and silicon dioxide layers as a hard mask. When dry etching the silicon dioxide layer with photoresist as a mask, the etching can automatically stop on the surface of the silicon nitride layer below it, so that the dry etching process will not damage the silicon carbide substrate and can effectively expand the process window.

[0073] This invention uses mixed acid treatment to improve the sidewall roughness of the hard mask layer (silicon dioxide layer), making the surface of the etched hard mask smooth, interrupting the replication of rough stripes on the hard mask layer during the silicon carbide trench etching process, and ultimately greatly improving the sidewall roughness of the silicon carbide trench.

[0074] This invention repairs damage to the sidewalls and bottom of silicon carbide trenches, thereby further improving the roughness of the sidewalls of the silicon carbide trenches.

[0075] This invention is applicable to the fabrication of silicon carbide UMOSFETs and trench-type JFET trenches. Due to the low surface roughness of silicon carbide trenches, the quality of the trench gate oxide layer of silicon carbide devices is effectively improved, and the influence of trench roughness on channel carrier mobility is greatly reduced.

[0076] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of etching a silicon carbide trench, comprising: The etching method comprises: providing a silicon carbide substrate; forming a first dielectric layer on the silicon carbide substrate; forming a second dielectric layer on the first dielectric layer, the thickness of the first dielectric layer being less than the thickness of the second dielectric layer; forming a photoresist pattern on the second dielectric layer; etching the second dielectric layer based on the photoresist pattern, the etching stopping at the surface of the first dielectric layer to form a window; removing the photoresist pattern and wet-etching the first dielectric layer through the window to remove the first dielectric layer in the window, the wet-etching simultaneously removing the rough structure of the sidewall of the window to reduce the roughness of the sidewall of the window; etching the silicon carbide substrate to form a trench using the first dielectric layer and the second dielectric layer as masks; removing the first dielectric layer and the second dielectric layer and performing damage repair treatment on the trench; when the first dielectric layer is wet-etched through the window to remove the first dielectric layer in the window, the first dielectric layer is also laterally recessed by a width of the window to form a lateral recess, so as to expose the corner between the trench and the top surface of the silicon carbide substrate, and simultaneously repair the damage generated on the sidewall during the etching of the second dielectric layer.

2. The method of claim 1, wherein: The thickness of the first dielectric layer ranges from 0.01 microns to 10 microns, and the thickness of the second dielectric layer ranges from 0.1 microns to 50 microns.

3. The method of claim 1, wherein: The first dielectric layer is a silicon nitride layer, and the second dielectric layer is a silicon dioxide layer.

4. The method of claim 3, wherein: The etching solution used for wet-etching the first dielectric layer through the window comprises a mixed acidic solution of H3PO4 and HF.

5. The method of claim 4, wherein: In the mixed acidic solution, the volume ratio of HF to H3PO4 ranges from 0:1 to 1:

0.

6. The method of claim 1, wherein: The etching process used for etching the silicon carbide substrate to form a trench comprises a reactive ion etching process.

7. The method of claim 1, wherein: The removal of the first dielectric layer and the second dielectric layer and the damage repair treatment on the trench further comprise: before the removal of the first dielectric layer and the second dielectric layer, performing a first damage repair treatment on the trench using a chemical dry etching process.

8. The method of claim 1, wherein: The removal of the first dielectric layer and the second dielectric layer and the damage repair treatment on the trench further comprise: after the removal of the first dielectric layer and the second dielectric layer, performing a second damage repair treatment on the trench by oxidizing the surface of the trench to form a sacrificial oxide layer and removing the sacrificial oxide layer.

9. A method of fabricating a silicon carbide device, comprising: The preparation method comprises the steps of: forming a trench in the silicon carbide substrate by the etching method of the silicon carbide trench according to any one of claims 1 to 8; and manufacturing a trench gate structure of the silicon carbide device based on the trench.

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