Detection structure and formation method thereof, and detection method

Abstract

A detection structure, a formation method thereof, and a detection method thereof include: a substrate, the substrate including a test area, the test area including a plurality of first active areas; a first gate structure and a second gate structure located on the plurality of first active areas; a first source-drain doped layer, a second source-drain doped layer, and a third source-drain doped layer located within the first active area; a first conductive structure located on the first source-drain doped layer; and a third conductive structure located on the third source-drain doped layer. A first voltage is applied to the first conductive structure and the first gate structure; and a second voltage is applied to the third conductive structure and the substrate, the second voltage being less than the first voltage. When the first gate structure and the second gate structure are short-circuited, the first voltage applied to the first gate structure is also equivalently applied to the second gate structure, connecting the first source-drain doped layer and the third source-drain doped layer. At this time, current is detected on the third conductive structure, thereby determining that the first gate structure and the second gate structure are short-circuited.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a detection structure and a forming method and a detection method thereof. Background Art

[0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing and are widely used in various integrated circuits. They are divided into NMOS and PMOS transistors based on the main carriers and the doping type during manufacturing.

[0003] The prior art provides a method for manufacturing a MOS transistor, comprising: providing a semiconductor substrate, forming a shallow trench isolation structure on the semiconductor substrate, wherein the semiconductor substrate between the shallow trench isolation structures serves as an active region, and forming a well region within the active region; doping the surface of the well region with impurity ions by first ion implantation to adjust the threshold voltage of a subsequently formed transistor; sequentially forming a gate dielectric layer and a gate electrode on the semiconductor substrate between the isolation structures, wherein the gate dielectric layer and the gate electrode constitute a gate structure; performing an oxidation process to form an oxide layer covering the gate structure; performing shallow dopant ion implantation to form source / drain extension regions within the semiconductor substrate on both sides of the gate structure; and performing deep dopant ion implantation on the well regions on both sides of the gate structure using the gate structure as a mask, wherein the energy and dose of the deep dopant ion implantation are greater than those of the shallow dopant ion implantation, thereby forming source and drain regions within the well regions on both sides of the gate structure, wherein the depth of the source and drain regions is greater than that of the source / drain extension regions.

[0004] However, the performance of transistors formed using existing technologies still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a detection structure and a forming method and a detection method thereof, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a detection structure, comprising: a substrate, the substrate including a test area, the test area including a plurality of mutually separated first active areas, and a first isolation structure located between adjacent first active areas; a first gate structure and a second gate structure located on the plurality of first active areas and arranged in parallel, the first gate structure and the second gate structure covering a portion of the top surface of the first active area; a first source-drain doping layer, a second source-drain doping layer and a third source-drain doping layer located in the first active area, the second source-drain doping layer being located between the first gate structure and the second gate structure, the first source-drain doping layer and the second source-drain doping layer being respectively located on both sides of the first gate structure, the third source-drain doping layer and the second source-drain doping layer being respectively located on both sides of the second gate structure; a first conductive structure located on the plurality of first source-drain doping layers, the first conductive structure electrically interconnecting the plurality of first source-drain doping layers; a third conductive structure located on the plurality of third source-drain doping layers, the third conductive structure electrically interconnecting the plurality of third source-drain doping layers.

[0007] Optionally, the substrate also includes an effective area, which includes several mutually separate second active areas and a second isolation structure located between adjacent second active areas; several parallel arranged third gate structures located on several second active areas, and the third gate structures cover part of the top surface of the second active areas; and fourth source-drain doped layers located in the second active areas on both sides of the third gate structures.

[0008] Optionally, a top surface of the first isolation structure is higher than a top surface of the first active region.

[0009] Optionally, it further includes: a first sidewall spacer located on the sidewall of the first gate structure.

[0010] Optionally, the method further includes: a second sidewall spacer located on the sidewall of the second gate structure.

[0011] Optionally, the first gate structure includes: a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0012] Optionally, the second gate structure includes: a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0013] Optionally, the material of the first gate layer includes: polysilicon.

[0014] Optionally, the material of the second gate layer includes polysilicon.

[0015] Optionally, it further includes: a second conductive structure located on the first gate structure.

[0016] Optionally, the first conductive structure includes: a first conductive layer located on several of the first source-drain doped layers and a first conductive plug located on the first conductive layer; the second conductive structure includes: a second conductive layer located on the first gate structure and a second conductive plug located on the second conductive layer; the third conductive structure includes: a third conductive layer located on several of the third source-drain doped layers and a third conductive plug located on the third conductive layer.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a detection structure, including: providing a substrate, the substrate including a test area, the test area including a plurality of mutually separated first active areas, and a first isolation structure located between adjacent first active areas; forming a first gate structure and a second gate structure arranged in parallel on the plurality of first active areas, the first gate structure and the second gate structure covering a portion of the top surface of the first active area; forming a first source-drain doping layer, a second source-drain doping layer and a third source-drain doping layer in the first active area, the second source-drain doping layer being located between the first gate structure and the second gate structure, the first source-drain doping layer and the second source-drain doping layer being located on both sides of the first gate structure, and the third source-drain doping layer and the second source-drain doping layer being located on both sides of the second gate structure; forming a first conductive structure on the plurality of first source-drain doping layers, the first conductive structure electrically interconnecting the plurality of first source-drain doping layers; forming a third conductive structure on the plurality of third source-drain doping layers, the third conductive structure electrically interconnecting the plurality of third source-drain doping layers.

[0018] Optionally, the substrate further includes an active region, wherein the active region includes a plurality of mutually separated second active regions and a second isolation structure located between adjacent second active regions.

[0019] Optionally, the process of forming the first gate structure and the second gate structure further includes: forming a plurality of third gate structures arranged in parallel on a plurality of the second active regions, wherein the third gate structures cover a portion of the top surface of the second active regions.

[0020] Optionally, the process of forming the first source-drain doped layer, the second source-drain doped layer and the third source-drain doped layer further includes: forming fourth source-drain doped layers in the second active region on both sides of the third gate structure.

[0021] Optionally, a top surface of the first isolation structure is higher than a top surface of the first active region.

[0022] Optionally, the first gate structure includes: a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure includes: a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0023] Optionally, the material of the first gate layer includes: polysilicon.

[0024] Optionally, the material of the second gate layer includes polysilicon.

[0025] Optionally, the method for forming the first gate structure and the second gate structure includes: forming a gate dielectric film on the substrate; forming a gate film on the gate dielectric film; forming a patterned layer on the gate film, wherein the patterned layer exposes a portion of the top surface of the gate film; etching the gate film and the gate dielectric film using the patterned layer as a mask until the top surfaces of the first active area and the first isolation structure are exposed, thereby forming the first gate structure and the second gate structure.

[0026] Optionally, after forming the first gate structure and the second gate structure, the method further includes: forming a first spacer on the sidewall of the first gate structure; and forming a second spacer on the sidewall of the second gate structure.

[0027] Optionally, the process of forming the first conductive structure and the second conductive structure further includes: forming the second conductive structure on the first gate structure.

[0028] Optionally, the first conductive structure includes: a first conductive layer located on several of the first source-drain doped layers and a first conductive plug located on the first conductive layer; the second conductive structure includes: a second conductive layer located on the first gate structure and a second conductive plug located on the second conductive layer; the third conductive structure includes: a third conductive layer located on several of the third source-drain doped layers and a third conductive plug located on the third conductive layer.

[0029] Correspondingly, the technical solution of the present invention also provides a detection method, comprising: providing a detection structure, the detection structure comprising: a substrate, the substrate including a test area, the test area including a plurality of mutually separated first active areas, and a first isolation structure located between adjacent first active areas; a first gate structure and a second gate structure located on the plurality of first active areas and arranged in parallel, the first gate structure and the second gate structure covering a portion of the top surface of the first active area; a first source-drain doped layer, a second source-drain doped layer, and a third source-drain doped layer located in the first active area, the second source-drain doped layer located between the first gate structure and the second gate structure, the first source-drain doped layer and the second source-drain doped layer being located on either side of the first gate structure, respectively, and the third source-drain doped layer and the second source-drain doped layer being located on either side of the second gate structure, respectively; a first conductive structure located on the plurality of first source-drain doped layers, the first conductive structure electrically interconnecting the plurality of first source-drain doped layers; a third conductive structure located on the plurality of third source-drain doped layers, the third conductive structure electrically interconnecting the plurality of third source-drain doped layers; applying a first voltage to the first conductive structure and the first gate structure; and applying a second voltage to the third conductive structure and the substrate, the second voltage being less than the first voltage.

[0030] Optionally, whether current exists on the third conductive structure is detected; when current is detected on the third conductive structure, a short circuit occurs between the first gate structure and the second gate structure.

[0031] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0032] In the detection method of the technical solution of the present invention, a first voltage is applied to the first conductive structure and the first gate structure; and a second voltage is applied to the third conductive structure and the substrate, the second voltage being less than the first voltage. When the first gate structure and the second gate structure are short-circuited, the first voltage applied to the first gate structure is also equivalently applied to the second gate structure. At this time, the MOS transistor device composed of the second gate structure is also in the on state, and the first source-drain doped layer and the third source-drain doped layer are connected. At this time, current is detected in the third conductive structure, and it is determined that the first gate structure and the second gate structure are short-circuited. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 2 It is a structural diagram of a semiconductor structure;

[0034] Figures 3 to 8 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0035] As described in the background art, the performance of transistors formed by existing technologies still needs to be improved, which will be described in detail below with reference to the accompanying drawings.

[0036] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 In the cross-sectional schematic diagram along line AA, a substrate 100 is provided, wherein the substrate 100 includes a plurality of mutually separated active areas 102, and an isolation structure 101 is provided between adjacent active areas 102; an initial gate structure (not shown) is formed on the substrate 100, wherein the initial gate structure covers the active areas 102 and the isolation structure 101; the initial gate structure is patterned to form a plurality of gate structures 103, wherein the gate structure 103 covers a portion of the top surface of the active area 102; and a source-drain doping layer 104 is formed in the active area on both sides of the gate structure 103.

[0037] In this embodiment, since the top surface of the isolation structure 101 is higher than the top surface of the active area 102, during the process of patterning the initial gate structure, gate structure material residue is easily formed at the junction of the isolation structure 102 and the active area 101. If the residue occurs in an area where the semiconductor device structure is relatively dense, it is easy for the adjacent gate structures 103 to be short-circuited, thereby reducing the performance of the ultimately formed semiconductor structure.

[0038] In the prior art, there is no effective electrical testing structure to detect the short circuit problem caused by the gate structure material residue at the interface between the active region 102 and the isolation structure 101 .

[0039] On this basis, the present invention provides a detection structure, a method for forming the same, and a detection method. By applying a first voltage to the first conductive structure and the first gate structure, and applying a second voltage to the third conductive structure and the substrate, the second voltage being less than the first voltage, when the first gate structure and the second gate structure are short-circuited, the first voltage applied to the first gate structure is also equivalently applied to the second gate structure. At this time, the MOS transistor device formed by the second gate structure is also in the on state, and the first source-drain doped layer and the third source-drain doped layer are connected. At this time, current is detected in the third conductive structure, thereby determining that the first gate structure and the second gate structure are short-circuited.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 8 It is a structural schematic diagram of the formation process of a detection structure according to an embodiment of the present invention.

[0042] Please refer to Figure 3 and Figure 4 , Figure 3 is a top view of the detection structure. Figure 4 yes Figure 3 In the cross-sectional view along line BB, a substrate 200 is provided. The substrate 200 includes a test area A1 . The test area A1 includes a plurality of mutually separated first active areas 201 and a first isolation structure 202 located between adjacent first active areas 201 .

[0043] In this embodiment, the method for forming the first active area 201 and the first isolation structure 202 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, wherein the patterned layer exposes a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form a plurality of first active areas 201 and a plurality of isolation trenches (not shown) in the initial substrate; and forming the first isolation structure 202 in the isolation trenches.

[0044] In this embodiment, the top surface of the first isolation structure 202 is higher than the top surface of the first active region 201. Since a large number of etching processes will be used in subsequent manufacturing processes, these etching processes will continuously damage the first isolation structure 202. To ensure the final height of the first isolation structure 202 and provide a better isolation effect, the top surface of the first isolation structure 202 is initially formed to be higher than the top surface of the first active region 201.

[0045] In this embodiment, the substrate 200 further includes an active region B1 , which includes a plurality of mutually separated second active regions 203 and a second isolation structure 204 located between adjacent second active regions 203 .

[0046] In this embodiment, the test area A1 is used to form a detection structure, and the effective area B1 is used to form a device structure with actual functions. The detection structure and the device structure are formed through the same process step. By testing whether there is a problem with the detection structure, it is verified whether there is a problem with the formed device structure.

[0047] Please refer to Figure 5 , Figure 5 and Figure 4In the same viewing direction, first gate structures 205 and second gate structures 206 arranged in parallel are formed on the first active regions 201 , and the first gate structures 205 and the second gate structures 206 cover part of the top surface of the first active region 201 .

[0048] In this embodiment, the first gate structure 205 includes: a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer; the second gate structure 206 includes: a second gate dielectric layer and a second gate layer (not labeled) located on the second gate dielectric layer.

[0049] In this embodiment, the material of the first gate layer includes polysilicon; the material of the second gate layer includes polysilicon.

[0050] In this embodiment, the method for forming the first gate structure and the second gate structure includes: forming a gate dielectric film (not shown) on the substrate 200; forming a gate film (not shown) on the gate dielectric film; forming a patterned layer (not shown) on the gate film, wherein the patterned layer exposes a portion of the top surface of the gate film; etching the gate film and the gate dielectric film using the patterned layer as a mask until the top surfaces of the first active area 201 and the first isolation structure 202 are exposed, thereby forming the first gate structure 205 and the second gate structure 206.

[0051] In this embodiment, the process of forming the first gate structure 205 and the second gate structure 206 further includes: forming a plurality of third gate structures 207 arranged in parallel on a plurality of the second active regions 203 , wherein the third gate structures 207 cover a portion of the top surface of the second active regions 203 .

[0052] In this embodiment, the first gate structure 205 , the second gate structure 206 and the third gate structure 207 are formed simultaneously through a global process, which can effectively save process steps and improve production efficiency.

[0053] Please continue to refer to Figure 5 After forming the first gate structure 205 and the second gate structure 206, it also includes: forming a first sidewall 208 on the sidewall of the first gate structure 205; forming a second sidewall 209 on the sidewall of the second gate structure 206; and forming a third sidewall 210 on the sidewall of the third gate structure 207.

[0054] In this embodiment, the method for forming the first sidewall spacer 208, the second sidewall spacer 209 and the third sidewall spacer 210 includes: forming a sidewall material film (not shown) on the sidewalls and top surfaces of the first gate structure 205, the second gate structure 206 and the third gate structure 207, and the top surface of the substrate 200; and etching back the sidewall material film until the first gate structure 205, the second gate structure 206, the third gate structure 207 and the top surface of the substrate 200 are exposed, thereby forming the first sidewall spacer 208, the second sidewall spacer 209 and the third sidewall spacer 210.

[0055] In this embodiment, the material of the first spacer 208 , the second spacer 209 , and the third spacer 210 includes silicon nitride.

[0056] Please refer to Figure 6 A first source-drain doped layer 211, a second source-drain doped layer 212 and a third source-drain doped layer 213 are formed in the first active area 201, the second source-drain doped layer 212 is located between the first gate structure 205 and the second gate structure 206, the first source-drain doped layer 211 and the second source-drain doped layer 212 are respectively located on both sides of the first gate structure 205, and the third source-drain doped layer 213 and the second source-drain doped layer 212 are respectively located on both sides of the second gate structure 206.

[0057] In this embodiment, the method for forming the first source-drain doped layer 211, the second source-drain doped layer 212 and the third source-drain doped layer 213 includes: etching the first active area 201 using the first gate structure 205 and the second gate structure 206 as masks to form a first source-drain opening, a second source-drain opening and a third source-drain opening (not shown) in the first active area 201; forming the first source-drain doped layer 211 in the first source-drain opening; forming the second source-drain doped layer 212 in the second source-drain opening; and forming the third source-drain doped layer 213 in the third source-drain opening.

[0058] In this embodiment, the process of forming the first source-drain doped layer 211 , the second source-drain doped layer 212 and the third source-drain doped layer 213 further includes: forming fourth source-drain doped layers 214 in the second active region 203 on both sides of the third gate structure 207 .

[0059] Please refer to Figure 7 After forming the first source-drain doping layer 211 , the second source-drain doping layer 212 and the third source-drain doping layer 213 , a dielectric layer 215 is formed on the substrate 200 , and the dielectric layer 215 covers the first gate structure 205 and the second gate structure 206 .

[0060] In this embodiment, the material of the dielectric layer 215 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0061] In this embodiment, the dielectric layer 215 also covers the third gate structure 207 .

[0062] Please refer to Figure 8 After forming the dielectric layer 215, a first conductive structure 216 is formed on the first source-drain doped layers 211, and the first conductive structure 216 electrically interconnects the first source-drain doped layers 211; a third conductive structure 217 is formed on the third source-drain doped layers 213, and the third conductive structure 217 electrically interconnects the third source-drain doped layers 213.

[0063] In this embodiment, a second conductive structure 218 is formed on the first gate structure 205 .

[0064] In this embodiment, the first conductive structure 216 includes: a first conductive layer located on several of the first source-drain doped layers 211 and a first conductive plug (not labeled) located on the first conductive layer; the second conductive structure 218 includes: a second conductive layer located on the first gate structure 205 and a second conductive plug (not labeled) located on the second conductive layer; the third conductive structure 217 includes: a third conductive layer located on several of the third source-drain doped layers 213 and a third conductive plug (not labeled) located on the third conductive layer.

[0065] Correspondingly, a detection structure is also provided in the embodiment of the present invention, please continue to refer to Figure 8, comprising: a substrate 200, the substrate 200 including a test area A1, the test area A1 including a plurality of mutually separated first active areas 201, and a first isolation structure 202 located between adjacent first active areas 201; a first gate structure 205 and a second gate structure 206 located on the plurality of first active areas 201 and arranged in parallel, the first gate structure 205 and the second gate structure 206 covering a portion of the top surface of the first active area 201; a first source-drain doped layer 211, a second source-drain doped layer 212, and a third source-drain doped layer 213 located in the first active area 201, the second source-drain doped layer 21 2 is located between the first gate structure 205 and the second gate structure 206, the first source-drain doped layer 211 and the second source-drain doped layer 212 are respectively located on both sides of the first gate structure 205, and the third source-drain doped layer 213 and the second source-drain doped layer 212 are respectively located on both sides of the second gate structure 206; a first conductive structure 216 is located on a plurality of the first source-drain doped layers 211, and the first conductive structure 216 electrically interconnects the plurality of first source-drain doped layers 211; a third conductive structure 217 is located on a plurality of the third source-drain doped layers 213, and the third conductive structure 217 electrically interconnects the plurality of third source-drain doped layers 213.

[0066] In this embodiment, the substrate 200 also includes an active area B1, which includes a number of mutually separate second active areas 203 and a second isolation structure 204 located between adjacent second active areas 203; a number of parallel arranged third gate structures 207 located on the number of second active areas 203, and the third gate structures 207 cover part of the top surface of the second active area 203; and a fourth source-drain doped layer 214 located in the second active area 203 on both sides of the third gate structure 207.

[0067] In this embodiment, a top surface of the first isolation structure 202 is higher than a top surface of the first active region 201 .

[0068] In this embodiment, the present invention further includes: a first spacer 208 located on the sidewall of the first gate structure 205 .

[0069] In this embodiment, the present invention further includes: a second spacer 209 located on the sidewall of the second gate structure 206 .

[0070] In this embodiment, the first gate structure 205 includes: a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0071] In this embodiment, the second gate structure 206 includes: a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0072] In this embodiment, the material of the first gate layer includes polysilicon.

[0073] In this embodiment, the material of the second gate layer includes polysilicon.

[0074] In this embodiment, the present invention further includes: a second conductive structure 218 located on the first gate structure 205 .

[0075] In this embodiment, the first conductive structure 216 includes: a first conductive layer located on several of the first source-drain doped layers 211 and a first conductive plug located on the first conductive layer; the second conductive structure 218 includes: a second conductive layer located on the first gate structure 205 and a second conductive plug located on the second conductive layer; the third conductive structure 217 includes: a third conductive layer located on several of the third source-drain doped layers 213 and a third conductive plug located on the third conductive layer.

[0076] Accordingly, a detection method is also provided in the embodiment of the present invention, please continue to refer to Figure 8 , including: providing a detection structure, a substrate 200, the substrate 200 including a test area A1, the test area A1 including a plurality of mutually separated first active areas 201, and a first isolation structure 202 located between adjacent first active areas 201; a first gate structure 205 and a second gate structure 206 located on the plurality of first active areas 201 and arranged in parallel, the first gate structure 205 and the second gate structure 206 covering a portion of the top surface of the first active area 201; a first source-drain doped layer 211, a second source-drain doped layer 212 and a third source-drain doped layer 213 located in the first active area 201, the second source-drain doped layer 212 located between the first gate structure 205 and the second gate structure 206, the first The source-drain doped layer 211 and the second source-drain doped layer 212 are respectively located on both sides of the first gate structure 205, and the third source-drain doped layer 213 and the second source-drain doped layer 212 are respectively located on both sides of the second gate structure 206; a first conductive structure 216 is located on several of the first source-drain doped layers 211, and the first conductive structure 216 electrically interconnects the several first source-drain doped layers 211; a third conductive structure 217 is located on several of the third source-drain doped layers 213, and the third conductive structure 217 electrically interconnects the several third source-drain doped layers 213; a first voltage is applied to the first conductive structure 216 and the first gate structure 205; a second voltage is applied to the third conductive structure 217 and the substrate, and the second voltage is less than the first voltage.

[0077] In this embodiment, whether there is current on the third conductive structure 217 is detected; when current is detected on the third conductive structure 217 , a short circuit occurs between the first gate structure 205 and the second gate structure 206 .

[0078] In the detection method of this embodiment, a first voltage is applied to the first conductive structure 216 and the first gate structure 205; and a second voltage is applied to the third conductive structure 217 and the substrate, where the second voltage is less than the first voltage. When the first gate structure 205 and the second gate structure 206 are short-circuited, the first voltage applied to the first gate structure 205 is also equivalently applied to the second gate structure 206. At this time, the MOS transistor device formed by the second gate structure 206 is also in the on state, and the first source-drain doped layer 211 and the third source-drain doped layer 213 are connected. At this time, current is detected in the third conductive structure 217, and it is determined that the first gate structure 205 and the second gate structure 206 are short-circuited.

[0079] In addition, in this embodiment, the detection structure includes several first active areas 201 arranged in parallel, which can increase the probability of short circuit between the subsequent first gate structure 205 and the second gate structure 206, making the detection structure more reliable; in addition, the total current of the final detection can be increased, that is, the tested current is the sum of the currents of multiple MOS, thereby reducing the test error.

[0080] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A detection structure, characterized in that: include: A substrate comprising a test area, wherein the test area comprises a plurality of mutually separated first active areas and a first isolation structure located between adjacent first active areas; a first gate structure and a second gate structure located on the plurality of first active regions and arranged in parallel, the first gate structure and the second gate structure covering a portion of a top surface of the first active region, and an extension direction of the first gate structure and the second gate structure intersecting with an extension direction of the plurality of first active regions; a first source-drain doped layer, a second source-drain doped layer, and a third source-drain doped layer located in the first active region, the second source-drain doped layer located between the first gate structure and the second gate structure, the first source-drain doped layer and the second source-drain doped layer located on either side of the first gate structure, respectively, and the third source-drain doped layer and the second source-drain doped layer located on either side of the second gate structure, respectively; a first conductive structure located on the plurality of first source-drain doped layers, wherein the first conductive structure electrically interconnects the plurality of first source-drain doped layers; A third conductive structure is located on the plurality of third source / drain doped layers, and the third conductive structure electrically interconnects the plurality of third source / drain doped layers.

2. The detection structure according to claim 1, wherein: The substrate further includes an active region, the active region including a plurality of mutually separated second active regions and a second isolation structure located between adjacent second active regions; a plurality of third gate structures arranged in parallel on the plurality of second active regions, the third gate structures covering portions of top surfaces of the second active regions, and an extension direction of the third gate structures intersecting with an extension direction of the plurality of second active regions; Fourth source-drain doped layers are respectively located in the second active region on both sides of the third gate structure.

3. The detection structure according to claim 1, wherein: A top surface of the first isolation structure is higher than a top surface of the first active region.

4. The detection structure according to claim 1, wherein: Also includes: A first spacer is located on the sidewall of the first gate structure.

5. The detection structure according to claim 1, wherein: Also includes: A second spacer is located on the sidewall of the second gate structure.

6. The detection structure according to claim 1, wherein: The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

7. The method for forming a detection structure according to claim 1, wherein: The second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

8. The detection structure according to claim 6, characterized in that: The material of the first gate layer includes polysilicon.

9. The detection structure according to claim 7, characterized in that: The material of the second gate layer includes polysilicon.

10. The detection structure according to claim 1, wherein: Also includes: A second conductive structure is located on the first gate structure.

11. The detection structure according to claim 10, characterized in that: The first conductive structure includes: a first conductive layer located on several of the first source-drain doped layers and a first conductive plug located on the first conductive layer; the second conductive structure includes: a second conductive layer located on the first gate structure and a second conductive plug located on the second conductive layer; the third conductive structure includes: a third conductive layer located on several of the third source-drain doped layers and a third conductive plug located on the third conductive layer.

12. A method for forming a detection structure, characterized in that: include: Providing a substrate, the substrate comprising a test area, the test area comprising a plurality of mutually separated first active areas and a first isolation structure located between adjacent first active areas; forming first and second gate structures arranged in parallel on the plurality of first active regions, wherein the first and second gate structures cover portions of top surfaces of the first active regions, and extension directions of the first and second gate structures intersect with extension directions of the plurality of first active regions; a first source-drain doped layer, a second source-drain doped layer, and a third source-drain doped layer formed in the first active region, the second source-drain doped layer being located between the first gate structure and the second gate structure, the first source-drain doped layer and the second source-drain doped layer being located on either side of the first gate structure, and the third source-drain doped layer and the second source-drain doped layer being located on either side of the second gate structure; forming a first conductive structure on the plurality of first source / drain doped layers, wherein the first conductive structure electrically interconnects the plurality of first source / drain doped layers; A third conductive structure is formed on the plurality of third source / drain doped layers, wherein the third conductive structure electrically interconnects the plurality of third source / drain doped layers.

13. The method for forming a detection structure according to claim 12, wherein: The substrate further includes an active region including a plurality of mutually separated second active regions and a second isolation structure located between adjacent second active regions.

14. The method for forming a detection structure according to claim 13, wherein: The process of forming the first gate structure and the second gate structure also includes: forming a plurality of third gate structures arranged in parallel on the plurality of second active regions, the third gate structure covering a portion of the top surface of the second active region, and the extension direction of the third gate structure intersecting with the extension direction of the plurality of second active regions.

15. The method for forming a detection structure according to claim 14, wherein: The process of forming the first source-drain doped layer, the second source-drain doped layer and the third source-drain doped layer further includes: forming fourth source-drain doped layers in the second active region on both sides of the third gate structure.

16. The method for forming a detection structure according to claim 12, wherein: A top surface of the first isolation structure is higher than a top surface of the first active region.

17. The method for forming a detection structure according to claim 12, wherein: The first gate structure includes: a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure includes: a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

18. The method for forming a detection structure according to claim 17, wherein: The material of the first gate layer includes polysilicon.

19. The method for forming a detection structure according to claim 17, wherein: The material of the second gate layer includes polysilicon.

20. The method for forming a detection structure according to claim 17, wherein: The method for forming the first gate structure and the second gate structure includes: forming a gate dielectric film on the substrate; forming a gate film on the gate dielectric film; forming a patterned layer on the gate film, wherein the patterned layer exposes a portion of the top surface of the gate film; etching the gate film and the gate dielectric film using the patterned layer as a mask until the top surfaces of the first active area and the first isolation structure are exposed, thereby forming the first gate structure and the second gate structure.

21. The method for forming a detection structure according to claim 12, wherein: After forming the first gate structure and the second gate structure, the method further includes: forming a first spacer on the sidewall of the first gate structure; and forming a second spacer on the sidewall of the second gate structure.

22. The method for forming a detection structure according to claim 12, wherein: The process of forming the first conductive structure further includes: forming a second conductive structure on the first gate structure.

23. The method for forming a detection structure according to claim 22, wherein: The first conductive structure includes: a first conductive layer located on several of the first source-drain doped layers and a first conductive plug located on the first conductive layer; the second conductive structure includes: a second conductive layer located on the first gate structure and a second conductive plug located on the second conductive layer; the third conductive structure includes: a third conductive layer located on several of the third source-drain doped layers and a third conductive plug located on the third conductive layer.

24. A detection method, characterized in that: include: A detection structure is provided, the detection structure comprising: a substrate, the substrate comprising a test area, the test area comprising a plurality of mutually separated first active areas, and a first isolation structure located between adjacent first active areas; a first gate structure and a second gate structure located on the plurality of first active regions and arranged in parallel, the first gate structure and the second gate structure covering a portion of the top surface of the first active region, the first gate structure and the second gate structure extending in a direction that intersects with the extending direction of the plurality of first active regions; a first source-drain doped layer, a second source-drain doped layer, and a third source-drain doped layer located within the first active region, the second source-drain doped layer located between the first gate structure and the second gate structure, the first source-drain doped layer and the second source-drain doped layer being located on either side of the first gate structure, and the third source-drain doped layer and the second source-drain doped layer being located on either side of the second gate structure; a first conductive structure located on the plurality of first source-drain doped layers, the first conductive structure electrically interconnecting the plurality of first source-drain doped layers; and a third conductive structure located on the plurality of third source-drain doped layers, the third conductive structure electrically interconnecting the plurality of third source-drain doped layers. applying a first voltage to the first conductive structure and the first gate structure; A second voltage is applied to the third conductive structure and the substrate, where the second voltage is lower than the first voltage.

25. The detection method according to claim 24, wherein: detecting whether current exists on the third conductive structure; and when current is detected on the third conductive structure, short circuit occurs between the first gate structure and the second gate structure.

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