Oscillator circuit with low jitter and insensitivity to temperature variations

Abstract

An oscillator circuit includes an initial level setting circuit, a switch circuit, a signal generating circuit, and an inverter circuit, wherein the initial level setting circuit is configured to operate in an on state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node; the switch circuit is configured to connect a power supply voltage terminal and a ground terminal to a first node or a second node in response to a first clock signal and a second clock signal with different phases after the initial operation; the signal generating circuit is connected between the first node and the second node, and is configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and to generate a first voltage and a second voltage determined by the charging operation and the discharging operation; and the inverter circuit is configured to generate a first clock signal based on the first voltage, and to generate a second clock signal based on the second voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0160363 filed in the Korean Intellectual Property Office on November 25, 2020, the disclosure of which is incorporated herein in its entirety by reference for all purposes. Technical Field

[0003] The present application relates to an oscillator circuit having low jitter and insensitivity to temperature variations. Background Art

[0004] As the performance of mobile phone cameras improves, high-resolution camera modules with high performance and optical image stabilization technology are needed. To this end, a high-resolution analog-to-digital converter (ADC) is required. Generally, to obtain an ADC with a resolution of 16 bits or higher, the jitter performance of the ADC's oscillator should be improved.

[0005] Larger image sensors result in larger actuator driving forces, and ambient temperature changes due to heat from the driver IC are significant. Therefore, the oscillator frequency characteristics need to be less sensitive to temperature changes.

[0006] In the inductor sensing method, contrary to the Hall sensor IC sensing method, the jitter performance and temperature characteristics of the system clock have a great influence on the actuator performance. In addition, in a system using a high-resolution ADC, the jitter performance may affect the ADC performance.

[0007] The related art oscillator includes a separate temperature compensation block to compensate for temperature variation, and additionally includes a voltage source to improve jitter performance.

[0008] In such a related art oscillator, the area of ​​the oscillator increases, and a compensator capable of compensating for the temperature characteristics of the oscillator core should be additionally designed.

[0009] For example, in an oscillator of the related art, when the frequency characteristic of the oscillator has a positive direction characteristic in response to temperature changes, temperature compensation is performed by designing the oscillator so that the bias current has a negative direction characteristic in response to temperature changes using an additional temperature compensation circuit.

[0010] However, the problem with the oscillator of the related art is that it may be difficult to obtain accurate compensation characteristics because there is a difference between the design change rate and the actual product change rate. Therefore, there is a disadvantage that a voltage source for improving jitter performance needs to be additionally provided, which increases the area of ​​the oscillator. Summary of the invention

[0011] The purpose of providing this summary is to introduce a selection of inventive concepts in a concise form, and these inventive concepts will be further described in the following detailed description. This summary is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0012] In a general aspect, an oscillator circuit includes an initial level setting circuit, a switch circuit, a signal generating circuit, and an inverter circuit, wherein the initial level setting circuit is configured to operate in an on state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node; the switch circuit is configured to connect a power supply voltage terminal and a ground terminal to a first node or a second node in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillator circuit; the signal generating circuit is connected between the first node and the second node, and is configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and to generate a first voltage and a second voltage determined by the charging operation and the discharging operation; and the inverter circuit is configured to generate a first clock signal based on the first voltage, and to generate a second clock signal based on the second voltage.

[0013] The initial level setting circuit may also be configured to operate in an off state after an initial operation of the oscillator circuit so as not to supply the first level voltage to the first node and not to supply the second level voltage to the second node.

[0014] The initial level setting circuit may include a first initial level setting unit and a second initial level setting unit, wherein the first initial level setting unit is configured to operate in an on state during the initial operation of the oscillator circuit to supply a first level voltage to the first node; and the second initial level setting unit is configured to operate in an on state during the initial operation of the oscillator circuit to supply a second level voltage to the second node.

[0015] The switching circuit may include a first switch and a second switch, wherein the first switch is configured to alternately connect the power supply voltage terminal to the first node and the second node in response to a first clock signal; and the second switch is configured to alternately connect the ground terminal to the second node and the first node in response to a second clock signal.

[0016] The first switch and the second switch may also be configured such that the first switch connects the power supply voltage terminal to the first node while the second switch connects the ground terminal to the second node, or such that the first switch connects the power supply voltage terminal to the second node while the second switch connects the ground terminal to the first node.

[0017] The signal generating circuit may include a first RC circuit and a second RC circuit, wherein the first RC circuit includes a first resistor and a first capacitor connected in series between a first node and a second node to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and output a first voltage from an intermediate connection node between the first resistor and the first capacitor; and the second RC circuit includes a second capacitor and a second resistor connected in series between the first node and the second node to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and output a second voltage from an intermediate connection node between the second capacitor and the second resistor.

[0018] A time constant of the first resistor and the first capacitor of the first RC circuit may determine an oscillation frequency of the first clock signal, and a time constant of the second capacitor and the second resistor of the second RC circuit may determine an oscillation frequency of the second clock signal.

[0019] The inverter circuit may include a first inverter configured to generate a first clock signal by inverting a first voltage and a second inverter configured to generate a second clock signal by inverting a second voltage.

[0020] The first inverter may also be configured to generate a first clock signal by inverting a first voltage based on a first threshold voltage, and the second inverter may also be configured to generate a second clock signal by inverting a second voltage based on a second threshold voltage different from the first threshold voltage, wherein the first threshold voltage may cause the first clock signal to have a duty cycle less than 50%, and the second threshold voltage may cause the second clock signal to have a duty cycle greater than 50%.

[0021] In another general aspect, an oscillator circuit includes an initial level setting circuit, a switch circuit, a signal generating circuit, an inverter circuit, and a control circuit, wherein the initial level setting circuit is configured to operate in an on state in response to a control signal during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node; the switch circuit is configured to connect a power supply voltage terminal and a ground terminal to a first node or a second node in response to a first clock signal and a second clock signal with different phases after the initial operation of the oscillator circuit; the signal generating circuit is connected between the first node and the second node, and is configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and generate a first voltage and a second voltage determined by the charging operation and the discharging operation; the inverter circuit is configured to generate a first clock signal based on the first voltage, and to generate a second clock signal based on the second voltage; and the control circuit is configured to generate a control signal to control the initial level setting circuit to operate in an on state during the initial operation of the oscillator circuit.

[0022] The initial level setting circuit can also be configured to operate in an off state in response to a control signal after the initial operation of the oscillator circuit so as not to supply the first level voltage to the first node and not to supply the second level voltage to the second node, and the control circuit can also be configured to generate a control signal after the initial operation of the oscillator circuit to control the initial level setting circuit to operate in the off state.

[0023] The initial level setting circuit may include a first initial level setting unit and a second initial level setting unit, wherein the first initial level setting unit is configured to operate in an on state during the initial operation of the oscillator circuit to supply a first level voltage to a first node; and the second initial level setting unit is configured to operate in an on state during the initial operation of the oscillator circuit to supply a second level voltage to a second node.

[0024] The switching circuit may include a first switch and a second switch, wherein the first switch is configured to alternately connect the power supply voltage terminal to the first node and the second node in response to a first clock signal; and the second switch is configured to alternately connect the ground terminal to the second node and the first node in response to a second clock signal.

[0025] The first switch and the second switch may also be configured such that the first switch connects the power supply voltage terminal to the first node while the second switch connects the ground terminal to the second node, or such that the first switch connects the power supply voltage terminal to the second node while the second switch connects the ground terminal to the first node.

[0026] The signal generating circuit may include a first RC circuit and a second RC circuit, wherein the first RC circuit includes a first resistor and a first capacitor connected in series between a first node and a second node to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and output a first voltage from an intermediate connection node between the first resistor and the first capacitor; and the second RC circuit includes a second capacitor and a second resistor connected in series between the first node and the second node to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and output a second voltage from an intermediate connection node between the second capacitor and the second resistor.

[0027] A time constant of the first resistor and the first capacitor of the first RC circuit may determine an oscillation frequency of the first clock signal, and a time constant of the second capacitor and the second resistor of the second RC circuit may determine an oscillation frequency of the second clock signal.

[0028] The inverter circuit may include a first inverter configured to generate a first clock signal by inverting a first voltage and a second inverter configured to generate a second clock signal by inverting a second voltage.

[0029] The first inverter may also be configured to generate a first clock signal by inverting a first voltage based on a first threshold voltage, and the second inverter may also be configured to generate a second clock signal by inverting a second voltage based on a second threshold voltage different from the first threshold voltage, wherein the first threshold voltage may cause the first clock signal to have a duty cycle less than 50%, and the second threshold voltage may cause the second clock signal to have a duty cycle greater than 50%.

[0030] In another general aspect, an oscillator circuit includes an initial level setting circuit, a switch circuit, a signal generating circuit, and an inverter circuit, wherein the initial level setting circuit is configured to supply a first level voltage to a first node and a second level voltage to a second node during an initial operation of the oscillator circuit; the switch circuit is configured to periodically switch between a first configuration and a second configuration in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillator circuit, in which the power supply voltage terminal is connected to the first node and the ground terminal is connected to the second node, and in the second configuration, the power supply voltage terminal is connected to the second node and the ground terminal is connected to the first node; the signal generating circuit is connected between the first node and the second node, and is configured to generate a first voltage and a second voltage that vary with time based on a potential difference between the first node and the second node; and the inverter circuit is configured to generate a first clock signal based on the first voltage, and a second clock signal based on the second voltage.

[0031] The initial level setting circuit may also be configured to not supply any voltage to the first node and the second node after the initial operation of the oscillator circuit, and the switching circuit may include a first switch and a second switch, the first switch being configured to alternate between connecting the power supply voltage terminal to the first node and connecting the power supply voltage terminal to the second node in response to a first clock signal after the initial operation of the oscillator circuit, and the second switch being configured to alternate between the following operations in response to a second clock signal after the initial operation of the oscillator circuit: connecting the ground terminal to the second node while the first switch connects the power supply voltage terminal to the first node; connecting the ground terminal to the first node while the first switch connects the power supply voltage terminal to the second node.

[0032] The signal generating circuit may also be configured to generate the first voltage and the second voltage such that the first voltage and the second voltage vary with time in opposite directions.

[0033] The signal generating circuit may include a first RC circuit and a second RC circuit, wherein the first RC circuit includes a first resistor and a first capacitor connected in series between a first node and a second node, wherein a first voltage is output from a first intermediate connection node between the first node and the second node, the first resistor is connected to the first node, and the first capacitor is connected to the second node, so that when the switch circuit is in a first configuration, the first voltage increases over time based on the potential difference between the first node and the second node, and when the switch circuit is in a second configuration, the first voltage decreases over time based on the potential difference between the first node and the second node; and the second RC circuit includes a second capacitor and a second resistor connected in series between the first node and the second node, wherein a second voltage is output from a second intermediate connection node between the first node and the second node, the second capacitor is connected to the first node, and the second resistor is connected to the second node, so that when the switch circuit is in the first configuration, the second voltage decreases over time based on the potential difference between the first node and the second node, and when the switch circuit is in the second configuration, the second voltage increases over time based on the potential difference between the first node and the second node.

[0034] The inverter circuit may include a first inverter configured to generate a first clock signal by inverting a first voltage based on a threshold voltage Vth, and a second inverter configured to generate a second clock signal by inverting a second voltage based on the threshold voltage Vth.

[0035] The threshold voltage Vth may allow the first clock signal and the second clock signal to have a duty cycle of 50%.

[0036] The inverter circuit may include a first inverter and a second inverter, the first inverter having a threshold voltage Vth and configured to generate a first clock signal by inverting a first voltage based on a first threshold voltage Vth-(Vos / 2), where Vos is an offset voltage of the inverter circuit; and the second inverter having a threshold voltage Vth and configured to generate a second clock signal by inverting a second voltage based on a second threshold voltage Vth+(Vos / 2).

[0037] The first threshold voltage Vth-(Vos / 2) may cause the first clock signal to have a duty cycle less than 50%, and the second threshold voltage Vth+(Vos / 2) may cause the second clock signal to have a duty cycle greater than 50%.

[0038] In another general aspect, an oscillator circuit includes an initial level setting circuit, a switch circuit, a signal generating circuit, and an inverter circuit, wherein the initial level setting circuit is configured to supply a first level voltage to a first node and a second level voltage to a second node during an initial operation of the oscillator circuit; the switch circuit is configured to periodically switch between a first configuration and a second configuration in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillator circuit, in which the power supply voltage terminal is connected to the first node and the ground terminal is connected to the second node, and in the second configuration, the power supply voltage terminal is connected to the second node and the ground terminal is connected to the first node; the signal generating circuit is connected between the first node and the second node, and is configured to generate a first voltage and a second voltage based on a potential difference between the first node and the second node; and the inverter circuit is configured to generate a first clock signal based on the first voltage, and a second clock signal based on the second voltage, wherein the first voltage and the second voltage vary over time by a fixed amount regardless of whether the inverter circuit has an offset voltage.

[0039] The inverter circuit may not have an offset voltage, and may include a first inverter configured to generate a first clock signal by inverting a first voltage based on a threshold voltage Vth and a second inverter configured to generate a second clock signal by inverting a second voltage based on the threshold voltage Vth.

[0040] The inverter circuit may have an offset voltage Vos and may include a first inverter and a second inverter, wherein the first inverter has a threshold voltage Vth and is configured to generate a first clock signal by inverting the first voltage based on a first threshold voltage Vth-(Vos / 2), and the second inverter has a threshold voltage Vth and is configured to generate a second clock signal by inverting the second voltage based on a second threshold voltage Vth+(Vos / 2).

[0041] The power supply voltage terminal may be configured to receive a power supply voltage, the ground terminal may be configured to receive a ground potential, and the first voltage and the second voltage may vary over time by a fixed amount equal to twice the power supply voltage regardless of whether the inverter circuit has an offset voltage.

[0042] Other features and aspects will become apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a diagram showing an example of an oscillator circuit.

[0044] Figure 2 is a diagram showing another example of an oscillator circuit.

[0045] Figure 3 It is shown Figure 2A diagram of an example of an internal circuit of an oscillator circuit in which an inverter circuit does not have an offset voltage.

[0046] Figure 4 It is shown Figure 2 A diagram of another example of an internal circuit of an oscillator circuit in which an inverter circuit has an offset voltage.

[0047] Figure 5A and Figure 5B It is shown Figure 3 and Figure 4 A diagram of the operating state of the initial level setting circuit.

[0048] Figure 6 It is shown Figure 3 and Figure 4 FIG. 1 is a diagram of an example of a change in the amplitude of the first voltage or the second voltage.

[0049] Fig. 7A and Figure 7B It is shown Figure 3 and Figure 4 Diagram of the operating state of the switching circuit.

[0050] Figure 8 It is shown Figure 3 A diagram of the operation of a signal generating circuit in which the inverter circuit does not have an offset voltage.

[0051] Fig. 9 It is shown Figure 4 A diagram of the operation of a signal generating circuit in which an inverter circuit has an offset voltage.

[0052] Fig.10 It is shown Figures 2 to 4 A block diagram of an example of a control circuit.

[0053] In all drawings and detailed description, the same reference numerals refer to the same elements. For the purpose of clarity, illustration and convenience, the drawings may not be drawn to scale, and the relative sizes, proportions and depictions of elements in the drawings may be exaggerated. DETAILED DESCRIPTION

[0054] The following specific embodiments are provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent after understanding the disclosure of the application. Except for the operations that must occur in a specific order, the order of the operations described herein is merely an example, and is not limited to the order set forth in this article, but can be made to be apparent after obtaining an understanding of the disclosure of the application. In addition, for greater clarity and brevity, the description of features known in the art may be omitted.

[0055] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein that will be apparent after understanding the disclosure of the present application.

[0056] The word "may" used herein to describe various examples (eg, with respect to what an implementation or example may include or implement) means that there is at least one example in which such feature is included or implemented, and all examples are not limited thereto.

[0057] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “on,” “connected to,” or “coupled to” another element, the element may be directly “on,” “connected to,” or “coupled to” another element, or one or more other elements may be present between the element and the other element. Conversely, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, no other elements may be present between the element and the other element.

[0058] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more items.

[0059] Although terms such as "first", "second" and "third" may be used herein to describe various components, parts, regions, layers or portions, these components, parts, regions, layers or portions are not limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer or portion from another component, part, region, layer or portion. Therefore, without departing from the teachings of the examples described herein, the first component, first component, first region, first layer or first portion mentioned in the examples may also be referred to as the second component, second component, second region, second layer or second portion.

[0060] Spatially relative terms such as "above", "higher", "below", and "lower" may be used herein for descriptive convenience to describe the relationship of one element relative to another element as shown in the accompanying drawings. In addition to covering the orientations depicted in the accompanying drawings, these spatially relative terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as being "above" or "higher" relative to another element will be "below" or "lower" relative to the other element. Therefore, depending on the spatial orientation of the device, the term "above" covers both "above" and "below" orientations. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0061] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include plural forms as well. The words "include", "comprise" and "have" illustrate the presence of stated features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof.

[0062] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include shape variations that occur during manufacturing.

[0063] The features of the examples described herein can be combined in various ways, which will be apparent after understanding the disclosure of the present application. In addition, although the examples described herein have multiple configurations, it will be apparent after understanding the disclosure of the present application that other configurations are also possible.

[0064] Figure 1 is a diagram showing an example of an oscillator circuit, and Figure 2 is a diagram showing another example of an oscillator circuit.

[0065] refer to Figure 1 and Figure 2 , the oscillator circuit 10 may include a switch circuit 100 , an initial level setting circuit 200 , a signal generating circuit 300 , and an inverter circuit 400 .

[0066] The switch circuit 100 may connect the power supply voltage terminal TVdd and the ground terminal TGND to the first node N1 or the second node N2 based on the first clock signal CLK and the second clock signal CLKB having different phases. For example, the switch circuit 100 may alternately connect the power supply voltage terminal TVdd to the first node N1 and the second node N2 in response to the first clock signal CLK, and may alternately connect the ground terminal TGND to the second node N2 and the first node N1 in response to the second clock signal CLKB. The switch circuit 100 may connect the power supply voltage terminal TVdd to the first node N1 while the switch circuit 100 connects the ground terminal TGND to the second node N2, and the switch circuit 100 may connect the power supply voltage terminal TVdd to the second node N2 while the switch circuit 100 connects the ground terminal TGND to the first node N1.

[0067] The initial level setting circuit 200 operates in response to the control signal SC.

[0068] Specifically, the initial level setting circuit 200 operates in an on state in response to the control signal SC during the initial operation of the oscillator circuit 10. When operating in the on state, the initial level setting circuit 200 supplies a first level voltage (e.g., a power supply voltage Vdd) to the first node N1, and supplies a second level voltage (e.g., a ground potential GND) to the second node N2.

[0069] Furthermore, the initial level setting circuit 200 operates in the off state in response to the control signal SC after the initial operation of the oscillator circuit 10. When operating in the off state, the initial level setting circuit 200 does not supply the first level voltage to the first node N1 and does not supply the second level voltage to the second node N2.

[0070] The signal generating circuit 300 may be connected between the first node N1 and the second node N2, may perform charging and discharging operations based on a potential difference between the first node N1 and the second node N2, and may generate first and second voltages Vc1 and Vc2 determined by the charging and discharging operations.

[0071] Furthermore, the inverter circuit 400 may generate a first clock signal CLK based on the first voltage Vc1 , generate a second clock signal CLKB based on the second voltage Vc2 , and output an oscillation signal Sosc including one or both of the first clock signal CLK and the second clock signal CLKB.

[0072] For example, the inverter circuit 400 may invert the first voltage Vc1 to generate the first clock signal CLK, and may invert the second voltage Vc2 to generate the second clock signal CLKB.

[0073] refer to Figure 2, the oscillator circuit 10 may further include a control circuit 500 .

[0074] For example, during the initial operation of the oscillator circuit 10, the control circuit 500 may output a control signal SC to the initial level setting circuit 200 for controlling the initial level setting circuit 200 to operate in the on state, and after the initial operation of the oscillator circuit 10, the control circuit 500 may output a control signal SC to the initial level setting circuit 200 for controlling the initial level setting circuit 200 to operate in the off state.

[0075] For example, the control signal SC may have a high level during the initial operation of the oscillator circuit 10 , and may have a low level after the initial operation of the oscillator circuit 10 , but the configuration of the control signal SC is not limited thereto.

[0076] In the following description, redundant descriptions of components having the same reference numerals and the same functions in the drawings may be omitted, and only differences between the drawings may be described.

[0077] Figure 3 It is shown Figure 2 A diagram of an example of an internal circuit of an oscillator circuit in which an inverter circuit does not have an offset voltage, and Figure 4 It is shown Figure 2 A diagram of another example of an internal circuit of an oscillator circuit in which an inverter circuit has an offset voltage.

[0078] refer to Figure 3 and Figure 4 , the switch circuit 100 may include a first switch 110 and a second switch 120 .

[0079] The first switch 110 may alternately connect the power supply voltage terminal TVdd to the first node N1 and the second node N2 based on the first clock signal CLK.

[0080] For example, the first switch 110 may connect the common terminal TC of the first switch 110 connected to the power supply voltage terminal TVdd to one of the first terminal T1 of the first switch 110 connected to the first node N1 and the second terminal T2 of the first switch 110 connected to the second node N2. For example, when the first clock signal CLK has a high level, the first switch 110 may connect the common terminal TC of the first switch 110 to the first node N1, and when the first clock signal CLK has a low level, the first switch 110 may connect the common terminal TC of the first switch 110 to the second node N2, but the configuration of the first switch 110 is not limited thereto.

[0081] The second switch 120 may alternately connect the ground terminal TGND to the first node N1 and the second node N2 based on the second clock signal CLKB.

[0082] For example, the second switch 120 may connect the common terminal TC of the second switch 120 connected to the ground terminal TGND to one of the second terminal T2 of the second switch 120 connected to the first node N1 and the first terminal T1 of the second switch 120 connected to the second node N2. For example, when the second clock signal CLKB has a high level, the second switch 120 may connect the common terminal TC of the second switch 120 to the first node N1, and when the second clock signal CLKB has a low level, the second switch 120 may connect the common terminal TC of the second switch 120 to the second node N2, but the configuration of the second switch 120 is not limited thereto.

[0083] The initial level setting circuit 200 may include a first initial level setting unit 210 and a second initial level setting unit 220 .

[0084] The first initial level setting unit 210 may operate in an on state in response to the control signal SC during an initial operation to supply a first level voltage to the first node N1. The second initial level setting unit 220 may operate in an on state in response to the control signal SC during an initial operation to supply a second level voltage to the second node N2.

[0085] For example, during the initial operation of the oscillator circuit 10, when the control signal SC has a high level, the first initial level setting unit 210 and the second initial level setting unit 220 may operate in an on state, and after the initial operation of the oscillator circuit 10, when the control signal SC has a low level, the first initial level setting unit 210 and the second initial level setting unit 220 may operate in an off state.

[0086] For example, the control signal SC may be set to a high level during an initial operation of the oscillator circuit 10 , and may be set to a low level after the initial operation of the oscillator circuit 10 , but the configuration of the control signal SC is not limited thereto.

[0087] The signal generating circuit 300 may include a first RC circuit 310 and a second RC circuit 320 .

[0088] The first RC circuit 310 includes a first resistor R1 and a first capacitor C1 connected in series between a first node N1 and a second node N2, and can output a first voltage Vc1 from an intermediate connection node NM1 between the first resistor R1 and the first capacitor C1 by performing a charging operation or a discharging operation based on a potential difference between the first node N1 and the second node N2.

[0089] The second RC circuit 320 may include a second capacitor C2 and a second resistor R2 connected in series between the first node N1 and the second node N2, and may output a second voltage Vc2 from an intermediate connection node NM2 between the second capacitor C2 and the second resistor R2 by performing a charging operation or a discharging operation based on a potential difference between the first node N1 and the second node N2.

[0090] The first RC circuit 310 and the second RC circuit 320 are different from each other in the manner in which the first resistor R1, the first capacitor C1, the second capacitor C2, and the second resistor R2 are connected to the first node N1 and the second node N2. Specifically, in the first RC circuit 310, the first resistor R1 is connected to the first node N1 and the first capacitor C1 is connected to the second node N2, while in the second RC circuit 320, the second capacitor C2 is connected to the first node N1 and the second resistor R2 is connected to the second node N2. Therefore, the first voltage Vc1 and the second voltage Vc2 vary differently.

[0091] For example, the first RC circuit 310 may determine the oscillation frequency of the first clock signal CLK according to the time constant of the first resistor R1 and the first capacitor C1. For example, at least one of the first resistor R1 and the first capacitor C1 may be a variable element for changing the oscillation frequency of the first clock signal CLK. Figure 3 In the example shown, the first capacitor C1 is a variable element.

[0092] The second RC circuit 320 may determine the oscillation frequency of the second clock signal CLKB according to the time constant of the second resistor R2 and the second capacitor C2. For example, at least one of the second resistor R2 and the second capacitor C2 may be a variable element for changing the oscillation frequency of the second clock signal CLKB. Figure 3 In the example shown, the second capacitor C2 is a variable element.

[0093] For example, the first capacitor C1 and the second capacitor C2 may have the same capacitor value, but are not limited thereto.

[0094] The inverter circuit 400 may include a first inverter 410 and a second inverter 420 .

[0095] refer to Figure 3 The first inverter 410 may generate the first clock signal CLK by inverting the first voltage Vc1. For example, the first inverter 410 may include a first inverter element INT1, and the first inverter element INT1 may generate the first clock signal CLK by inverting the first voltage Vc1 based on the threshold voltage Vth.

[0096] The second inverter 420 may generate the second clock signal CLKB by inverting the second voltage Vc2. For example, the second inverter 420 may include a second inverter element INT2 that may generate the second clock signal CLKB by inverting the second voltage Vc2 based on the threshold voltage Vth.

[0097] Therefore, the first inverter 410 and the second inverter 420 may have the same threshold voltage Vth. Therefore, the threshold voltage Vth may allow the first clock signal CLK and the second clock signal CLKB to each have a duty ratio of 50%.

[0098] Figure 3 4 represents a case where the inverter circuit 400 does not have an offset voltage Vos between the threshold voltage Vth of the first inverter 410 and the threshold voltage Vth of the second inverter 420. On the other hand, when the inverter circuit 400 has an offset voltage Vos, the inverter circuit 400 may be as follows: Figure 4 As shown, the influence of offset voltage Vos is taken into account.

[0099] refer to Figure 4 , Vos is the offset voltage of the inverter circuit 400. The first inverter 410 may include a first inverter element INT1 having a threshold voltage Vth and a first virtual voltage source generating a voltage of -(Vos / 2). The second inverter 420 may include a second inverter element INT2 having a threshold voltage Vth and a second virtual voltage source generating a voltage of +(Vos / 2). The first virtual voltage source and the second virtual voltage source take into account the influence of the offset voltage Vos.

[0100] The first inverter 410 may generate the first clock signal CLK by inverting the first voltage Vc1 based on a first threshold voltage Vth−(Vos / 2) equal to the threshold voltage Vth minus half of the offset voltage Vos of the inverter circuit 400 .

[0101] The second inverter 420 may generate the second clock signal CLKB by inverting the second voltage Vc2 based on a second threshold voltage Vth+(Vos / 2) equal to the threshold voltage Vth plus half of the offset voltage Vos of the inverter circuit 400 .

[0102] Therefore, the first threshold voltage Vth-(Vos / 2) and the second threshold voltage Vth+(Vos / 2) are separated by the offset voltage Vos of the inverter circuit 400, and the first threshold voltage Vth-(Vos / 2) can cause the first clock signal CLK to have a duty cycle less than 50%, and the second threshold voltage Vth+(Vos / 2) can cause the second clock signal CLKB to have a duty cycle greater than 50%.

[0103] In the above description, the threshold voltage Vth is the threshold voltage of the first inverter element INT1 and the second inverter element INT2 itself, and the first threshold voltage Vth-(Vos / 2) and the second threshold voltage Vth+(Vos / 2) are the threshold voltages of the first inverter 410 and the second inverter 420.

[0104] Figure 5A and Figure 5B It is shown Figure 3 and Figure 4 A diagram of the operating state of the initial level setting circuit.

[0105] Figure 5A is a diagram showing a first initial level setting unit 210 and a second initial level setting unit 220 of the initial level setting circuit 200 in an on state, and Figure 5B is a diagram showing the first initial level setting unit 210 and the second initial level setting unit 220 of the initial level setting circuit 200 in an off state.

[0106] refer to Figure 5A , when the first initial level setting unit 210 and the second initial level setting unit 220 operate in an on state in response to the control signal SC during the initial operation of the oscillator circuit 10, the potential of the first node N1 may be the power supply voltage Vdd, and the potential of the second node N2 may be the ground potential TGND.

[0107] Therefore, the potentials of the first node N1 and the second node N2 can be set during the initial operation of the oscillator circuit 10 , and thus, a stable operation can be started when the operation starts.

[0108] refer to Figure 5B When the first initial level setting unit 210 and the second initial level setting unit 220 operate in the off state in response to the control signal SC after the initial operation of the oscillator circuit 10, the potential of the first node N1 and the potential of the second node N2 can be determined according to the operation of the first switch 110 and the second switch 120 of the switching circuit 100.

[0109] Figure 6 It is shown Figure 3 and Figure 4 FIG. 1 is a diagram of an example of a change in the amplitude of the first voltage or the second voltage.

[0110] refer to Figure 6 , when the first voltage Vc1 or the second voltage Vc2 is Figure 6 When the change ΔV is shown, the jitter amount can be expressed by the following equation 1.

[0111] Jitter ∝ (fixed circuit noise / ΔV) (1)

[0112] Referring to Equation 1, it can be seen that the jitter amount is proportional to the fixed circuit noise (such as input offset noise or other noise), and is inversely proportional to the change ΔV in the voltage Vc1 or Vc2. Therefore, when the change ΔV in the voltage Vc1 or Vc2 decreases, the problem of an increase in the jitter amount may occur. Therefore, it can be seen that preventing a decrease in the change ΔV will prevent an increase in the jitter amount.

[0113] In view of this, in order to prevent the change ΔV in the voltage Vc1 or Vc2 from decreasing, a signal generating circuit including an RC oscillator circuit may be implemented, and an increase in the jitter amount may be prevented by adopting a concept of switching the power supply voltage of the signal generating circuit as described below.

[0114] Fig. 7A and Figure 7B It is shown Figure 3 and Figure 4 Diagram of the operating state of the switching circuit.

[0115] Fig. 7A is a diagram showing a state in which the power supply voltage terminal TVdd is connected to the first node N1 through the first switch 110 of the switch circuit 100 , and the ground terminal TGND is connected to the second node N2 through the second switch 120 of the switch circuit 100 .

[0116] refer to Fig. 7A , the potential of the first node N1 becomes the power supply voltage Vdd and the potential of the second node N2 becomes the ground potential GND, and therefore, the first RC circuit 310 can output a voltage increased to the threshold voltage Vth (such as Fig. 7A ) or a first voltage Vc1 increased to a first threshold voltage Vth-(Vos / 2) (not shown), wherein the first RC circuit 310 includes a first resistor R1 and a first capacitor C1 connected in series between the first node N1 and the second node N2.

[0117] In addition, the second RC circuit 320 can output a voltage reduced to a threshold voltage Vth (eg, Fig. 7A The second RC circuit 320 includes a second capacitor C2 and a second resistor R2 connected in series between the first node N1 and the second node N2.

[0118] Figure 7Bis a diagram showing a state in which the power supply voltage terminal TVdd is connected to the second node N2 through the first switch 110 of the switch circuit 100 , and the ground terminal TGND is connected to the first node N1 through the second switch 120 of the switch circuit 100 .

[0119] refer to Figure 7B , the potential of the first node N1 becomes the ground potential GND and the potential of the second node N2 becomes the power supply voltage Vdd, and therefore, the first RC circuit 310 can output a voltage reduced to the threshold voltage Vth (such as Figure 7B ) or a first voltage Vc1 that is reduced to a first threshold voltage Vth-(Vos / 2) (not shown).

[0120] In addition, the second RC circuit 320 can output a voltage increased to a threshold voltage Vth (eg, Fig. 7A ) or a second voltage Vc2 increased to a second threshold voltage Vth+(Vos / 2) (not shown).

[0121] Figure 8 It is shown Figure 3 A diagram of the operation of a signal generating circuit in which the inverter circuit does not have an offset voltage.

[0122] refer to Figure 8 , in the case where the inverter circuit 400 does not have the offset voltage Vos, level conversion to a high level or to a low level based on the threshold voltage Vth may occur in the first inverter 410 and the second inverter 420 .

[0123] Therefore, when the first clock signal CLK has a high level, the first voltage Vc1 gradually increases to the threshold voltage Vth, and when the first clock signal CLK switches to a low level, the first voltage Vc1 immediately rises to "power supply voltage + threshold voltage" (Vdd + Vth), and then gradually decreases to the threshold voltage Vth during the first half cycle period T1.

[0124] Subsequently, when the first clock signal CLK transitions to a high level, the first voltage Vc1 immediately drops to “negative power supply voltage+threshold voltage” (−Vdd+Vth), and then gradually increases to the threshold voltage Vth during the second half cycle period T2 .

[0125] In addition, when the first clock signal CLK has a high level, the second voltage Vc2 gradually decreases to the threshold voltage Vth, and when the first clock signal CLK switches to a low level, the second voltage Vc2 immediately drops to the "negative power supply voltage + threshold voltage" (-Vdd + Vth), and then gradually increases to the threshold voltage Vth during the first half cycle period T1.

[0126] Subsequently, when the first clock signal CLK transitions to a high level, the second voltage Vc2 immediately rises to “power supply voltage+threshold voltage” (Vdd+Vth), and then gradually decreases to the threshold voltage Vth during the second half cycle period T2.

[0127] The operation of one cycle (T= T1 + T2 ) as described above may be repeatedly performed, and in this case, a change ΔV in each of the first voltage Vc1 and the second voltage Vc2 is 2Vdd.

[0128] Fig. 9 It is shown Figure 4 A diagram of the operation of a signal generating circuit in which an inverter circuit has an offset voltage.

[0129] refer to Fig. 9 , Fig. 9 The situation and Figure 8 The difference between the cases above is that, in the case where the inverter circuit 400 has an offset voltage Vos, a level transition to a high level or a low level based on a first threshold voltage Vth-(Vos / 2) may occur in the first inverter 410, and a level transition to a high level or a low level based on a second threshold voltage Vth+(Vos / 2) may occur in the second inverter 420.

[0130] Therefore, when the first clock signal CLK has a high level, the first voltage Vc1 gradually increases to the first threshold voltage Vth-(Vos / 2), and when the first clock signal CLK switches to a low level, the first voltage Vc1 immediately rises to "power supply voltage+threshold voltage-(Vos / 2)" (Vdd+Vth-(Vos / 2)), and then gradually decreases to the first threshold voltage Vth-(Vos / 2) during the first period T1+ΔTe.

[0131] Subsequently, when the first clock signal CLK switches to a high level, the first voltage Vc1 immediately drops to "negative power supply voltage + threshold voltage - (Vos / 2)" (-Vdd + Vth - (Vos / 2)), and then gradually increases to the first threshold voltage Vth - (Vos / 2) during the second period T2 - ΔTe.

[0132] In addition, when the first clock signal CLK has a high level, the second voltage Vc2 gradually decreases to the second threshold voltage Vth+(Vos / 2), and when the first clock signal CLK switches to a low level, the second voltage Vc2 immediately drops to "negative power supply voltage+threshold voltage+(Vos / 2)" (-Vdd+Vth+(Vos / 2)), and then gradually increases to the second threshold voltage Vth+(Vos / 2) during the first period T1+ΔTe.

[0133] Subsequently, when the first clock signal CLK switches to a high level, the second voltage Vc2 immediately rises to "power supply voltage + threshold voltage + (Vos / 2)" (Vdd + Vth + (Vos / 2)), and then gradually decreases to the second threshold voltage Vth + (Vos / 2) during the second period T2-ΔTe.

[0134] The operation of one cycle (T=(T1+ΔTe+(T2-ΔTe)) as described above may be repeatedly performed, and in this case, a change ΔV in each of the first voltage Vc1 and the second voltage Vc2 is 2Vdd.

[0135] Therefore, it can be seen that even when the inverter circuit 400 has the offset voltage Vos, the change ΔV of each of the first voltage Vc1 and the second voltage Vc2 is the same as when the inverter circuit 400 does not have the offset voltage Vos, and thus it can be seen that an increase in the jitter amount can be prevented.

[0136] For example, one cycle when the inverter circuit 400 does not have the offset voltage Vos may be the same as one cycle when the inverter circuit 400 has the offset voltage Vos, but the configuration of one cycle is not limited thereto.

[0137] Fig.10 It is shown Figures 2 to 4 A block diagram of an example of a control circuit.

[0138] refer to Fig.10 , the memory 1010 stores instructions, which, when executed by the processor 1020, cause the processor 1020 to execute Figures 2 to 4 Therefore, the processor 1020 includes the control circuit 500.

[0139] Figures 2 to 4The control circuit 500 for performing the operation described in the present application is implemented by a hardware component configured to perform the operation performed by the hardware component described in the present application. Where appropriate, examples of hardware components that can be used to perform the operation described in the present application include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, transistors, and any other electronic components configured to perform the operation described in the present application. In other examples, one or more hardware components for performing the operation described in the present application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers, and arithmetic logic units), digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a limited manner to achieve a desired result. In one example, a processor or computer includes one or more memories storing instructions or software executed by a processor or computer, or is connected to one or more memories storing instructions or software executed by a processor or computer. The hardware components implemented by a processor or a computer can execute instructions or software, such as an operating system (OS) and one or more software applications running on the OS to perform the operations described in this application. The hardware components can also access, manipulate, process, create and store data in response to executing instructions or software. For simplicity, the singular wording "processor" or "computer" can be used to describe the examples described in this application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements or multiple types of processing elements or multiple processing elements and multiple types of processing elements. For example, a single hardware component or two or more hardware components can be implemented by a single processor or two or more processors or a processor and a controller. One or more hardware components can be implemented by one or more processors or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors or another processor and another controller. One or more processors or a processor and a controller can implement a single hardware component or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0140] The instructions or software that control computing hardware (e.g., one or more processors or computers) to implement the hardware components as described above can be written as a computer program, code segment, instruction, or any combination thereof, for individually or collectively instructing or configuring one or more processors or computers to work as a machine or special-purpose computer to perform the operations performed by the hardware components as described above. In one example, the instructions or software include machine code directly executed by one or more processors or computers, such as machine code generated by a compiler. In another example, the instructions or software include high-level code executed by one or more processors or computers using an interpreter. The instructions or software can be written in any programming language based on the description of the operations performed by the hardware components as described above.

[0141] The instructions or software that controls computing hardware (e.g., one or more processors or computers) to implement the hardware components described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), flash memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state disk, and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that one or more processors or computers can execute the instructions. In one example, instructions or software and any associated data, data files, and data structures are distributed over a network-connected computer system so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0142] The above-described example of an oscillator circuit is insensitive to temperature variations without the need for a separate temperature compensation circuit, is conducive to miniaturization, and is therefore suitable for use in an autofocus (AF) or optical image stabilization (OIS) circuit of a mobile phone camera module, and also has improved jitter performance.

[0143] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the appended claims and their equivalents. The examples described herein should be interpreted in a descriptive sense only, and not for limiting purposes. The description of the features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may also be obtained if the described techniques are performed in a different order, and / or if the components in the described system, architecture, device or circuit are replaced or supplemented in a different manner and / or with other components or their equivalents. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents should be understood to be included in the present disclosure.

Claims

1. An oscillator circuit, comprising: an initial level setting circuit configured to operate in an on state during an initial operation of the oscillator circuit to supply a first level voltage to the first node and a second level voltage to the second node; a switch circuit configured to connect a power supply voltage terminal and a ground terminal to the first node or the second node in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillator circuit; a signal generating circuit connected between the first node and the second node and configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and to generate a first voltage and a second voltage determined by the charging operation and the discharging operation; as well as The inverter circuit is configured to generate the first clock signal based on the first voltage and to generate the second clock signal based on the second voltage.

2. The oscillator circuit according to claim 1, wherein: The initial level setting circuit is further configured to operate in an off state after the initial operation of the oscillator circuit so as not to supply the first level voltage to the first node and not to supply the second level voltage to the second node.

3. The oscillator circuit according to claim 1, wherein: The initial level setting circuit comprises: a first initial level setting unit configured to operate in an on state during the initial operation of the oscillator circuit to supply the first level voltage to the first node; and A second initial level setting unit is configured to operate in an on state during the initial operation of the oscillator circuit to supply the second level voltage to the second node.

4. The oscillator circuit according to claim 1, wherein: The switch circuit comprises: a first switch configured to alternately connect the power supply voltage terminal to the first node and the second node in response to the first clock signal; and A second switch is configured to connect the ground terminal to the second node and the first node alternately in response to the second clock signal.

5. The oscillator circuit according to claim 4, wherein: The first switch and the second switch are further configured such that the first switch connects the power supply voltage terminal to the first node while the second switch connects the ground terminal to the second node, or the first switch connects the power supply voltage terminal to the second node while the second switch connects the ground terminal to the first node.

6. The oscillator circuit according to claim 1, wherein: The signal generating circuit comprises: a first RC circuit including a first resistor and a first capacitor connected in series between the first node and the second node to perform a charging operation and a discharging operation based on the potential difference between the first node and the second node, and output the first voltage from an intermediate connection node between the first resistor and the first capacitor; and A second RC circuit includes a second capacitor and a second resistor connected in series between the first node and the second node to perform charging and discharging operations based on the potential difference between the first node and the second node, and output the second voltage from an intermediate connection node between the second capacitor and the second resistor.

7. The oscillator circuit according to claim 6, wherein: A time constant of the first resistor and the first capacitor of the first RC circuit determines an oscillation frequency of the first clock signal, and A time constant of the second capacitor and the second resistor of the second RC circuit determines an oscillation frequency of the second clock signal.

8. The oscillator circuit according to claim 1, wherein: The inverter circuit comprises: a first inverter configured to generate the first clock signal by inverting the first voltage; and The second inverter is configured to generate the second clock signal by inverting the second voltage.

9. The oscillator circuit according to claim 8, wherein: The first inverter is further configured to generate the first clock signal by inverting the first voltage based on a first threshold voltage, The second inverter is further configured to generate the second clock signal by inverting the second voltage based on a second threshold voltage different from the first threshold voltage, The first threshold voltage causes the first clock signal to have a duty cycle less than 50%, and The second threshold voltage enables the second clock signal to have a duty cycle greater than 50%.

10. An oscillator circuit comprising: an initial level setting circuit configured to operate in an on state in response to a control signal during an initial operation of the oscillator circuit to supply a first level voltage to the first node and a second level voltage to the second node; a switch circuit configured to connect a power supply voltage terminal and a ground terminal to the first node or the second node in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillator circuit; a signal generating circuit connected between the first node and the second node and configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and to generate a first voltage and a second voltage determined by the charging operation and the discharging operation; an inverter circuit configured to generate the first clock signal based on the first voltage and to generate the second clock signal based on the second voltage; as well as A control circuit is configured to generate the control signal to control the initial level setting circuit to operate in the on state during the initial operation of the oscillator circuit.

11. The oscillator circuit according to claim 10, wherein: The initial level setting circuit is further configured to operate in an off state in response to the control signal after the initial operation of the oscillator circuit so as not to supply the first level voltage to the first node and not to supply the second level voltage to the second node, and The control circuit is further configured to generate the control signal to control the initial level setting circuit to operate in the off state after the initial operation of the oscillator circuit.

12. The oscillator circuit according to claim 10, wherein: The initial level setting circuit comprises: a first initial level setting unit configured to operate in an on state during the initial operation of the oscillator circuit to supply the first level voltage to the first node; and A second initial level setting unit is configured to operate in an on state during the initial operation of the oscillator circuit to supply the second level voltage to the second node.

13. The oscillator circuit according to claim 10, wherein: The switch circuit comprises: a first switch configured to alternately connect the power supply voltage terminal to the first node and the second node in response to the first clock signal; and A second switch is configured to connect the ground terminal to the second node and the first node alternately in response to the second clock signal.

14. The oscillator circuit according to claim 13, wherein: The first switch and the second switch are further configured such that the first switch connects the power supply voltage terminal to the first node while the second switch connects the ground terminal to the second node, or the first switch connects the power supply voltage terminal to the second node while the second switch connects the ground terminal to the first node.

15. The oscillator circuit according to claim 10, wherein: The signal generating circuit comprises: a first RC circuit including a first resistor and a first capacitor connected in series between the first node and the second node to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and output the first voltage from an intermediate connection node between the first resistor and the first capacitor; and A second RC circuit includes a second capacitor and a second resistor connected in series between the first node and the second node to perform charging and discharging operations based on the potential difference between the first node and the second node, and output the second voltage from an intermediate connection node between the second capacitor and the second resistor.

16. The oscillator circuit according to claim 15, wherein: A time constant of the first resistor and the first capacitor of the first RC circuit determines an oscillation frequency of the first clock signal, and A time constant of the second capacitor and the second resistor of the second RC circuit determines an oscillation frequency of the second clock signal.

17. The oscillator circuit according to claim 10, wherein: The inverter circuit comprises: a first inverter configured to generate the first clock signal by inverting the first voltage; and The second inverter is configured to generate the second clock signal by inverting the second voltage.

18. The oscillator circuit according to claim 17, wherein: The first inverter is further configured to generate the first clock signal by inverting the first voltage based on a first threshold voltage, The second inverter is further configured to generate the second clock signal by inverting the second voltage based on a second threshold voltage different from the first threshold voltage, The first threshold voltage causes the first clock signal to have a duty cycle less than 50%, and The second threshold voltage enables the second clock signal to have a duty cycle greater than 50%.

19. An oscillator circuit comprising: an initial level setting circuit configured to supply a first level voltage to the first node and a second level voltage to the second node during an initial operation of the oscillator circuit; a switch circuit configured to periodically switch between a first configuration in which a power supply voltage terminal is connected to the first node and a ground terminal is connected to the second node and a second configuration in which the power supply voltage terminal is connected to the second node and the ground terminal is connected to the first node in response to first and second clock signals having different phases after the initial operation of the oscillator circuit; a signal generating circuit connected between the first node and the second node and configured to generate a first voltage and a second voltage that vary with time based on a potential difference between the first node and the second node; as well as The inverter circuit is configured to generate the first clock signal based on the first voltage and to generate the second clock signal based on the second voltage.

20. The oscillator circuit of claim 19, wherein: The initial level setting circuit is further configured not to supply any voltage to the first node and the second node after the initial operation of the oscillator circuit, and The switch circuit comprises: a first switch configured to alternate between the following operations in response to the first clock signal after the initial operation of the oscillator circuit: connecting the supply voltage terminal to the first node, and connecting the supply voltage terminal to the second node; and a second switch configured to alternate between the following operations in response to the second clock signal after the initial operation of the oscillator circuit: connecting the ground terminal to the second node while the first switch connects the power supply voltage terminal to the first node, and The first switch connects the ground terminal to the first node while the first switch connects the power supply voltage terminal to the second node.

21. The oscillator circuit of claim 19, wherein: The signal generating circuit is further configured to generate the first voltage and the second voltage such that the first voltage and the second voltage vary with time in opposite directions.

22. The oscillator circuit of claim 19, wherein: The signal generating circuit comprises: a first RC circuit including a first resistor and a first capacitor connected in series between the first node and the second node, wherein the first voltage is output from a first intermediate connection node between the first node and the second node, the first resistor is connected to the first node and the first capacitor is connected to the second node, so that when the switch circuit is in the first configuration, the first voltage increases over time based on the potential difference between the first node and the second node, and when the switch circuit is in the second configuration, the first voltage decreases over time based on the potential difference between the first node and the second node; and A second RC circuit includes a second capacitor and a second resistor connected in series between the first node and the second node, wherein the second voltage is output from a second intermediate connection node between the first node and the second node, the second capacitor is connected to the first node and the second resistor is connected to the second node, so that when the switch circuit is in the first configuration, the second voltage decreases over time based on the potential difference between the first node and the second node, and when the switch circuit is in the second configuration, the second voltage increases over time based on the potential difference between the first node and the second node.

23. The oscillator circuit of claim 19, wherein: The inverter circuit comprises: a first inverter configured to generate the first clock signal by inverting the first voltage based on a threshold voltage Vth, and The second inverter is configured to generate the second clock signal by inverting the second voltage based on the threshold voltage Vth.

24. The oscillator circuit of claim 23, wherein: The threshold voltage Vth allows the first clock signal and the second clock signal to have a duty ratio of 50%.

25. The oscillator circuit of claim 19, wherein: The inverter circuit comprises: a first inverter having a threshold voltage Vth and configured to generate the first clock signal by inverting the first voltage based on a first threshold voltage Vth-(Vos / 2), wherein Vos is an offset voltage of the inverter circuit; and The second inverter has the threshold voltage Vth and is configured to generate the second clock signal by inverting the second voltage based on a second threshold voltage Vth+(Vos / 2).

26. The oscillator circuit of claim 25, wherein: The first threshold voltage Vth-(Vos / 2) enables the first clock signal to have a duty cycle less than 50%, and The second threshold voltage Vth+(Vos / 2) enables the second clock signal to have a duty cycle greater than 50%.

27. An oscillator circuit comprising: an initial level setting circuit configured to supply a first level voltage to the first node and a second level voltage to the second node during an initial operation of the oscillator circuit; a switch circuit configured to periodically switch between a first configuration in which a power supply voltage terminal is connected to the first node and a ground terminal is connected to the second node and a second configuration in which the power supply voltage terminal is connected to the second node and the ground terminal is connected to the first node in response to first and second clock signals having different phases after the initial operation of the oscillator circuit; a signal generating circuit connected between the first node and the second node and configured to generate a first voltage and a second voltage based on a potential difference between the first node and the second node; as well as an inverter circuit configured to generate the first clock signal based on the first voltage and to generate the second clock signal based on the second voltage; The first voltage and the second voltage vary with time by a fixed amount regardless of whether the inverter circuit has an offset voltage.

28. The oscillator circuit of claim 27, wherein: The inverter circuit has no offset voltage and comprises: a first inverter configured to generate the first clock signal by inverting the first voltage based on a threshold voltage Vth, and The second inverter is configured to generate the second clock signal by inverting the second voltage based on the threshold voltage Vth.

29. The oscillator circuit of claim 27, wherein: The inverter circuit has an offset voltage Vos and comprises: a first inverter having a threshold voltage Vth and configured to generate the first clock signal by inverting the first voltage based on a first threshold voltage Vth-(Vos / 2); and The second inverter has the threshold voltage Vth and is configured to generate the second clock signal by inverting the second voltage based on a second threshold voltage Vth+(Vos / 2).

30. The oscillator circuit of claim 27, wherein: The power supply voltage terminal is configured to receive a power supply voltage, The ground terminal is configured to receive a ground potential, and Regardless of whether the inverter circuit has the offset voltage, the first voltage and the second voltage vary with time by a fixed amount equal to twice the power supply voltage.

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