oscillator

Abstract

Embodiments of the present disclosure relate to an oscillator. A series of first ramps and second ramps are generated. A circuit delivers a first signal representing a comparison of each first ramp to a setpoint, and delivers a second signal representing a comparison of each second ramp to the setpoint. Based on the first and second signals: when a first ramp reaches the setpoint, the first ramp is stopped and a second ramp is started; and when a second ramp reaches the setpoint, the second ramp is stopped and a first ramp is started. The setpoint is modulated in response to a maximum of the first / second ramps compared to the setpoint.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2012048, filed on November 24, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates generally to electronic circuits, and more specifically to oscillators. Background Technology

[0004] Oscillators are known to be configured to generate binary periodic signals, such as clock signals. These oscillators use at least one voltage ramp to compare with a setpoint voltage to generate a periodic signal; the slope of the ramp and the setpoint voltage determine the frequency of the generated periodic signal. The comparison is implemented by one or more voltage comparators, typically by an operational amplifier assembled with comparators.

[0005] However, the propagation time in the comparator is sensitive to temperature changes in the oscillator. Therefore, modifications to the oscillator temperature will result in modifications to the frequency at which the periodic signal is generated, which is undesirable. Summary of the Invention

[0006] It is necessary to overcome all or part of the shortcomings of known oscillators, especially those previously described.

[0007] The embodiments overcome all or part of the disadvantages of known oscillators, especially those previously described.

[0008] For example, the embodiments overcome all or part of the known drawbacks of oscillators associated with temperature variations in these oscillators.

[0009] An embodiment provides an apparatus comprising: a first generator of a series of first voltage ramps and a second generator of a series of second voltage ramps; a first circuit configured to compare each of the first ramps in the series with a setpoint voltage, compare each of the second ramps in the series with the setpoint voltage, deliver a binary first signal representing a comparison of the first ramps with the setpoint voltage, and deliver a binary second signal representing a comparison of the second ramps with the setpoint voltage; a second circuit configured, based on the first and second signals, to: stop the first ramp and start the second ramp when the first ramp reaches the setpoint voltage, and stop the second ramp and start the first ramp when the second ramp reaches the setpoint voltage; and a third circuit configured to modulate the setpoint voltage based on the maximum value of at least the last of the first ramps compared with the setpoint voltage.

[0010] According to an embodiment, the second circuit is further configured to reset the first generator between every two first consecutive ramps in the series, and to reset the second generator between every two second consecutive ramps in the series.

[0011] According to an embodiment, the first generator includes: a first capacitor element, a first switch, and a first current source connected in series between a node applying a power supply voltage and a node applying a reference potential, and a second switch connected in parallel with the first capacitor element; and the second generator includes: a second capacitor element, a third switch, and a second current source connected in series between the node applying the power supply voltage and the node applying the reference potential, and a fourth switch connected in parallel with the second capacitor element; the second circuit is configured based on the first signal and the second signal to: turn on the first switch and turn off the third switch when the second ramp reaches the setpoint voltage; and turn on the third switch and turn off the first switch when the first ramp reaches the setpoint voltage.

[0012] According to an embodiment, the first generator is reset by turning on the second switch, the second generator is reset by turning on the fourth switch, and the second circuit is configured to control the second and fourth switches based on the first and second signals.

[0013] According to an embodiment, the third circuit is configured to: generate a third signal representing the difference between the reference voltage and the maximum value of at least the last of the first ramp, and deliver the setpoint voltage equal to the reference voltage minus the difference.

[0014] According to an embodiment, the third circuit includes a fourth circuit configured to update and subsequently store a first voltage representing the maximum value of each first ramp between the end of each first ramp and the next reset of the first generator, and the second circuit is configured to control the storage and the subsequent update based on the first signal and the second signal.

[0015] According to an embodiment: the fourth circuit includes a series combination of a capacitor element and a switch, the combination being connected in parallel with the first capacitor element, and the first voltage is obtainable across the capacitor element; the first voltage is updated by turning on the switch and stored by turning off the switch; and the second circuit is configured to control the switch of the third circuit based on the first signal and the second signal.

[0016] According to an embodiment, the third circuit includes an error amplifier having a first input configured to receive a signal representing the reference voltage, a second input configured to receive the first voltage, and an output configured to deliver the third signal.

[0017] According to an embodiment, the second circuit is configured to modulate the setpoint voltage based on the maximum value of at least the last first ramp compared with the setpoint voltage, and based on the maximum value of at least the last second ramp compared with the setpoint voltage.

[0018] According to an embodiment, the second circuit is configured to generate a third signal that alternately represents a first difference between a reference voltage and the maximum value of at least the last first ramp and a second difference between the reference voltage and the maximum value of at least the last second ramp, and delivers the setpoint voltage that alternately equals the reference voltage minus the first difference and the reference voltage minus the second difference.

[0019] According to an embodiment: the third circuit includes a fourth circuit configured to update and store a first voltage representing the maximum value of each first ramp between the end of each first ramp and the next reset of the first generator; the third circuit includes a fifth circuit configured to update and store a second voltage representing the maximum value of each second ramp between the end of each second ramp and the next reset of the second generator; the second circuit is configured to control the storage and the update based on a first signal and a second signal.

[0020] According to an embodiment: the fourth circuit includes a first series combination of a capacitor element and a switch, the first combination being connected in parallel with the first capacitor element, the first voltage being obtainable across the capacitor element of the fourth circuit, the first voltage being updated by the switching being turned on and stored by the switching being turned off; the fifth circuit includes a second series combination of a capacitor element and a switch, the second combination being connected in parallel with the second capacitor element, the second voltage being obtainable across the capacitor element of the fifth circuit, the second voltage being updated by the switching being turned on and stored by the switching being turned off; and the second circuit is configured to control the switches of the fourth circuit and the fifth circuit based on the first signal and the second signal.

[0021] According to an embodiment, the third circuit includes: a first commutator having an input terminal configured to receive the first voltage and another input terminal configured to receive the second voltage; and an error amplifier having a first input terminal configured to receive a reference voltage, a second input terminal coupled to an output terminal of the first commutator, and an output terminal configured to deliver the third signal, wherein the first commutator is controlled by the second circuit based on the first signal and the second signal.

[0022] According to an embodiment, the third circuit includes circuitry for storing a reference voltage. The circuitry includes: a capacitor element and a first switch, the first switch coupling a node for delivering the reference voltage to a terminal of the capacitor element, the other terminal of the capacitor element being coupled to a second node; a further capacitor element and a second switch, the second switch coupling a node connecting the capacitor element and the first switch to a terminal of the further capacitor element, the other terminal of the further capacitor element being coupled to the second node, and configured to deliver the signal representing the reference voltage; and a second circuit configured to control the first and second switches of the storage circuitry based on the first and second signals.

[0023] According to an embodiment, the other terminal of the additional capacitor element is coupled to the first input terminal of the error amplifier by a second commutator, and the second circuit is configured to control the second commutator in a manner similar to the first commutator.

[0024] According to an embodiment, the third circuit includes: a third current source and a resistor connected in series between the first and second nodes; and a transistor connected in parallel with the resistor, the control terminal of the transistor being configured to receive a third signal. Attached Figure Description

[0025] The above-described features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, in which:

[0026] Figure 1 An example of an oscillator circuit is shown;

[0027] Figure 2 Explanation is shown Figure 1 Timing diagram of ideal operation of the oscillator;

[0028] Figure 3 An embodiment of the oscillator is illustrated using functional blocks;

[0029] Figure 4 Explanation is shown Figure 3 Timing diagram of the operation of the oscillator;

[0030] Figure 5 Further details are shown Figure 3 An embodiment of a portion of an oscillator;

[0031] Figure 6 Further details are shown Figure 3 An embodiment of a portion of an oscillator;

[0032] Figure 7 Further details are shown Figure 3An embodiment of a portion of the oscillator; and

[0033] Figure 8 Further details are shown Figure 3 An example of an oscillator in [the text]. Detailed Implementation

[0034] In different figures, similar features are designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0035] For clarity, only the steps and elements useful for understanding the embodiments described herein are described in detail. In particular, various existing electronic circuits for generating clock signals, which may be provided, are not described in detail, and the described embodiments and variations are compatible with such existing electronic circuits.

[0036] Unless otherwise stated, when referring to two elements connected together, it means there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled by one or more other elements.

[0037] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative position qualifiers such as “above,” “below,” “higher,” “lower,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc., reference is made to the orientation shown in the figure.

[0038] Unless otherwise stated, the terms “about,” “approximately,” “basically,” and “on the order of magnitude of” indicate within 10%, and preferably within 5%.

[0039] Figure 1 An example of the circuitry for oscillator 1 is shown.

[0040] The oscillator 1 includes a voltage ramp Vc1 generator 100 (including a series of ramps) and a voltage ramp Vc2 generator 102 (including a series of ramps).

[0041] Generator 100 includes a current source 104, a switch SW1, and a capacitor element C1, these three elements preferably connected in series in this order between node 106, where the applied supply voltage Vdd is applied, and node 108, where the applied reference potential (here, ground GND) is applied. Switch SW1 couples the current source 104 to the capacitor element C1. In this example, the supply voltage Vdd is positive and referenced to node 108, which is set to ground potential GND. Generator 100 further includes a switch SW2 connected in parallel with the capacitor element C1. The current source 104 provides a constant current Ic1. In this example, when switch SW1 is on and switch SW2 is off, capacitor element C1 charges, which results in a voltage ramp Vc1 across capacitor element C1, as... Figure 2 As can be seen, when switch SW2 is turned on, generator 100 is reset, or in other words, in this example, voltage Vc1 is reset to 0V.

[0042] Similarly, generator 102 includes a current source 110, a switch SW2, and a capacitor C2, these three components preferably connected in series between the two nodes 106 and 108 in this order. Switch SW3 couples the current source 110 to the capacitor C2. Preferably, the value of capacitor C2 is the same as the value of capacitor C1. Generator 102 also includes a switch SW4 connected in parallel with capacitor C2. Current source 110 provides a constant current Ic2, preferably having the same value Ic as current Ic1. In this example, when switch SW3 is on and switch SW4 is off, capacitor C2 charges, which results in a voltage ramp Vc2 across capacitor C2, as... Figure 2 As can be seen, when switch SW4 is turned on, generator 102 is reset, or in other words, voltage Vc2 is reset, in this example to 0V.

[0043] The setpoint or reference voltage Vref is delivered by voltage generator 112. In this example, generator 112 includes a current source 114 that delivers a constant current Iref, and a resistor R connected in series with the source 114 between nodes 106 and 108. The voltage Vref corresponds to the voltage across the resistor R, and in this example, the voltage Vref is referenced to node 108, which has terminals of the resistor R coupled thereto.

[0044] Oscillator 1 also includes a comparator circuit COMP (by... Figure 1The circuit COMP (defined by dashed lines) is configured to compare voltage Vc1 with setpoint voltage Vref and voltage Vc2 with setpoint voltage Vref. The circuit COMP is also configured to deliver a binary signal out1 indicating a high or low state of the comparison between voltage Vc1 and voltage Vref, and a binary signal out2 indicating a high or low state of the comparison between voltage Vc2 and voltage Vref. The circuit COMP includes, for example, three inputs that receive the corresponding voltages Vref, Vc1, and Vc2.

[0045] exist Figure 1 In the example, the circuit COMP is implemented by comparators COMP1 and COMP2, which are preferably identical.

[0046] Comparator COMP1 is configured to compare voltage Vc1 with setpoint voltage Vref and deliver signal out1. In this example, the inverting input (-) of comparator COMP1 receives voltage Vc1, and the non-inverting input (+) of comparator COMP1 receives voltage Vref.

[0047] Similarly, comparator COMP2 is configured to compare voltage Vc2 with setpoint voltage Vref and deliver signal out2. In this example, the inverting input (-) of comparator COMP2 receives voltage Vc2, and the non-inverting input (+) of comparator COMP2 receives voltage Vref.

[0048] The oscillator 1 further includes a control circuit 116, which is configured based on signals out1 and out2 to: stop voltage ramp Vc1 and start voltage ramp Vc2 when voltage ramp Vc1 reaches voltage Vref; and stop voltage ramp Vc2 and start voltage ramp Vc1 when voltage ramp Vc2 reaches voltage Vref.

[0049] In this example, control unit 116 is an RS latch with an input nR for receiving signal out1, an input nS for receiving signal out2, an output nQ for delivering signal cmd2 to control switches SW2 and SW3, and a Q output for delivering signal cmd1 to control switches SW1 and SW4. In this example, the RS latch is configured to: set signal cmd1 to high and set signal cmd2 to low when signal out2 switches low and signal out1 is high; and set signal cmd2 to high and set signal cmd1 to low when signal out1 switches low and signal out2 is high. In this example, switches SW1, SW2, SW3, and SW4 are open when their respective control signals are low and closed when their respective control signals are high.

[0050] Figure 2 It shows Figure 1 The timing diagram of the ideal operation of the oscillator, specifically, Figure 2 The timing diagrams for voltages Vc1 and Vc2 (each showing a series of voltage ramps) and signals cmd1, cmd2, out1, and out2 are shown. Signals out1 and out2 correspond to the connections... Figure 1 The signals received at the corresponding nR and nS input terminals of the RS latch 116.

[0051] At time t0, signal cmd1 is in a high state and signal cmd2 is in a low state, with switches SW1 and SW4 on and switches SW2 and SW3 off. Therefore, generator 100 delivers a voltage ramp Vc1, while generator 102 is in its original state (voltage Vc2 is zero in this example).

[0052] At the next time t1, the ramp Vc1 reaches the voltage Vref, thereby signal out1 switches to a low state, and signals cmd1 and cmd2 switch to a low state and a high state, respectively.

[0053] Therefore, from time t1, switches SW1 and SW4 are turned off, while switches SW2 and SW3 are turned on, thereby generating 102 delivers a voltage ramp Vc2. Furthermore, the turning on of switch SW2 causes generator 100 to be set to its initial state (in this example, voltage Vc1 is zero), thereby causing signal out1 to switch to a high state shortly after time t1.

[0054] At the next time t2, the ramp Vc2 reaches the voltage Vref, which causes the signal out2 to switch to a low state, which causes the signals cmd and cmd2 to switch to a high state and a low state, respectively.

[0055] Therefore, from time t2, switches SW1 and SW4 are turned on, while switches SW2 and SW3 are turned off, thereby generator 100 delivers a voltage ramp Vc1. In addition, the turning on of switch SW4 causes generator 102 to be set to the initial state (in this example, voltage Vc2 is zero), thereby signal out2 switches to the high state shortly after time t2.

[0056] After time t2, the operation of oscillator 1 is performed similarly to that described above, so signals cmd1 and cmd2 are periodic signals.

[0057] Considering that the propagation time Tp in circuit COMP, or in other words, in comparators COMP1 and COMP2, is zero, the frequencies of signals cmd1 and cmd2 are equal to Ic / (2*C*Vref), where C is the value of capacitors C1 and C2, and Ic is the value of currents Ic1 and Ic2. In other words, when current Iref has the value Ic, the frequencies of signals cmd1 and cmd2 are equal to Ic / (2*C*R*Vref), which is half of 1 / (R*C). Therefore, oscillator 1 is currently called an RC oscillator because the voltage Vref can be obtained across resistor R, and the ramps Vc1 and Vc2 can be obtained across the corresponding capacitors C1 and C2, or in other words, because signals cmd1 and cmd2 are determined by the values ​​of resistor R and capacitors C1 and C2.

[0058] However, in reality, the propagation time Tp of the comparator is not zero. Therefore, the switching of cmd1 and cmd2 does not occur at times t1 and t2 respectively when signals Vc1 and Vc2 reach the value Vref, but rather at times t1+Tp and t2+Tp respectively when ramps Vc1 and Vc2 reach Vc1max and Vc2max, respectively, which are greater than the maximum value of voltage Vref. The frequencies of signals cmd1 and cmd2 are then equal to Ic / ((2*C)*(Vref+Ic*Tp / C)), or in other words, equal to half of 1 / (R*C*(Iref / Ic+Tp / (R*C))).

[0059] Now, the propagation time Tp of the comparator varies with the temperature of oscillator 1, which causes the frequencies of signals cmd1 and cmd2 to vary with the temperature of oscillator 1. For example, regarding frequencies at 30°C, the frequencies of signals cmd1 and cmd2 can vary by +0.3% at -40°C and by -1.4% at 125°C. This variation is not ideal, especially when signals cmd1 or cmd2 are used as clock signals or to generate clock signals.

[0060] This article provides a method with Figure 1 The related description of the type of oscillator, in one embodiment, involves a setpoint voltage Vref' being delivered to a circuit COMP, such as comparators COMP1 and COMP2, for modulation, modification, or control based on at least the maximum value of the last ramp Vc1 and / or from at least the maximum value of the last ramp Vc2. In this case, voltages Vc1 and Vc2 are compared with voltage Vref' rather than with voltage Vref.

[0061] In the following description, unless otherwise stated, the expression "at least the maximum value of the final slope Vc1" means the maximum value of the final slope of voltage Vc1, Vc1max, or the averaged, smoothed, or filtered maximum value of the multiple final slopes Vc1, Vc1maxmean. Similarly, the expression "at least the maximum value of the final slope Vc2" means the maximum value of the final slope of voltage Vc2, Vc2max, or the averaged, smoothed, or filtered maximum value of the multiple final slopes Vc2, Vc2maxmean. To avoid repetition, the maximum values ​​of at least the final slopes Vc1 and Vc2 will be referred to as the maximum values ​​Vc1m and Vc2m, respectively. In other words, the maximum values ​​Vc1m and Vc2m correspond to the maximum values ​​Vc1max and Vc2max of the final voltage ramps Vc1 and Vc2, respectively, or to the averaged, smoothed, or filtered maximum values ​​Vc1maxmean and Vc2maxmean of the multiple final voltage ramps Vc1 and Vc2.

[0062] Therefore, an increase in the value Vc1m and / or the value Vc2m reflects an increase in the propagation time Tp, and conversely, a decrease in the value Vc1m and / or the value Vc2m reflects a decrease in the propagation time Tp.

[0063] According to an embodiment, the value of the setpoint voltage Vref' decreases when the values ​​Vc1m and / or Vc2m increase, and conversely, the value of the setpoint voltage Vref' increases when the values ​​Vc2m and / or Vc1m decrease. Preferably, the voltage Vref' is less than the voltage Vref.

[0064] According to an embodiment, the setpoint voltage Vref' delivered to the circuit COMP, such as comparators COMP1 and COMP2, is equal to the reference voltage Vref minus the difference between the reference voltage Vref and the maximum value Vc1m. In other words, Vref' = Vref - (Vc1m - Vref).

[0065] According to another embodiment, the setpoint voltage Vref' delivered to the circuit COMP, such as comparators COMP1 and COMP2, is equal to the reference voltage Vref minus the difference between the reference voltage Vref and the maximum value Vc1m, and the difference between the reference voltage Vref and the maximum value Vc2m, respectively. In other words, voltage Vref' is equal to Vref-(Vc1m-Vref) and Vref-(Vc2m-Vref), respectively.

[0066] The advantage here lies in the fact that the maximum value of each ramp Vc1, Vc1max, and the maximum value of each ramp Vc2, Vc2max, depend on the propagation time Tp of the circuit COMP, i.e., for example, on the propagation time Tp of the comparators (the respective comparators COMP1 and COMP2). In other words, it is provided here that the setpoint voltage Vref' delivered to the circuit COMP, such as comparators COMP1 and COMP2, is controlled based on this propagation time Tp.

[0067] Figure 3 An embodiment of this oscillator 2 is illustrated schematically using function blocks. Oscillator 2 includes elements common to oscillator 1 and will not be described further.

[0068] Specifically, similar to oscillator 1, oscillator 2 includes: a generator 100 for voltage ramp Vc1, a generator 102 for voltage ramp Vc2, and a generator 112 for voltage ramp Vref, wherein generators 100, 102, and 112 are, for example, related to... Figure 1 The components described are the same.

[0069] However, unlike oscillator 1, where circuit COMP is configured to compare each voltage ramp Vc1, Vc2 with voltage Vref, in this embodiment, circuit COMP', for example, the same as circuit COMP, is configured to compare each voltage ramp Vc1, Vc2 with setpoint voltage Vref'. Like circuit COMP, circuit COMP' is configured to deliver a binary signal out1 indicating a high or low state of the comparison between voltage Vc1 and voltage Vref', and a binary signal out2 indicating a high or low state of the comparison between voltage Vc2 and voltage Vref'. Circuit COMP' includes, for example, three inputs for receiving the corresponding voltages Vref', Vc1, and Vc2.

[0070] The circuit COMP' includes, for example, comparators COMP1' (e.g., the same as comparator COMP1) and COMP2' (e.g., the same as comparator COMP2). Comparator COMP1' is configured to compare each voltage ramp Vc1 with the setpoint voltage Vref' and deliver a signal out1. Comparator COMP2' is configured to compare each voltage ramp Vc2 with the setpoint voltage Vref' and deliver a signal out2. In this example, the inverting input (-) of comparator COMP1' receives voltage Vc1, the non-inverting input (+) of comparator COMP1' receives voltage Vref', the inverting input (-) of comparator COMP2' receives voltage Vc2, and the non-inverting input (+) of comparator COMP2' receives voltage Vref'.

[0071] Furthermore, compared to oscillator 1, oscillator 2 includes a voltage generator circuit 200 configured to deliver or generate voltage Vref'.

[0072] exist Figure 3 In the embodiment shown, circuit 200 is configured to modulate voltage Vref' based on maximum values ​​Vc1m and Vc2m. Therefore, in this embodiment, circuit 200 includes: an input terminal 201 coupled, for example, to the output terminal of generator 100, on which voltage Vc1 is available; and an input terminal 202 coupled, for example, to the output terminal of generator 102, on which voltage Vc2 is available. Circuit 200 is then configured to determine the maximum values ​​Vc1m and Vc2m based on the corresponding values ​​Vc1 and Vc2.

[0073] In an optional embodiment (not shown), where circuit 200 is configured to modulate voltage Vref' based only on the maximum voltage Vc1m or only on the maximum voltage Vc2m, inputs 202 or 201 may be omitted respectively.

[0074] Circuit 200 further includes an input terminal 203, which is coupled, for example, to the output terminal of generator 112, on which a reference voltage Vref is available, for example.

[0075] Circuit 200 further includes an output terminal 204 on which a modulated voltage Vref' is available.

[0076] In this embodiment, circuit 200 is configured to generate a signal Δ based on voltages Vref, Vc1, and Vc2, which alternately represents the difference between voltage Vref and its maximum value Vc1m, and the difference between voltage Vref and its maximum voltage Vc2m. The function of circuit 200 is implemented by function block 206. Circuit 200 is further configured to deliver a voltage Vref' such that it is equal to voltage Vref alternately subtracted from the difference between voltage Vref and its maximum value Vc1m, and the difference between voltage Vref and its maximum value Vc2m. This function of circuit 200 is described by subtractor block 208, which takes the input signal Δ and voltage Vref as input signals and outputs voltage Vref'.

[0077] In an optional embodiment (not shown), circuit 200 is configured to modulate voltage Vref' based solely on the maximum value Vc1m or Vc2m. Block or circuit 206 is then configured to deliver a signal Δ such that it represents the difference between voltage Vref and the maximum value (Vc1m or Vc2m, respectively). Furthermore, circuit 200 is then configured to deliver voltage Vref' such that it is equal to voltage Vref minus this difference.

[0078] Preferably, in Figure 3 In the embodiment shown, the maximum values ​​Vc1m and Vc2m correspond to the values ​​Vc1maxmean and Vc2maxmean, respectively. In this case, block or circuit 206 is preferably configured to update and store a first signal Vc1-sig (representing the value Vc1maxmean). Figure 3 (not shown in the image), and update and store the second signal Vc2-sig (representing the maximum value Vc2maxmean). Figure 3 (Not shown in the image). Then, the signal Δ is determined based on these signals Vc1-sig and Vc2-sig. Preferably, the signal Δ is determined alternately based on the signals Vc1-sig and Vc2-sig.

[0079] The oscillator 2 further includes a control circuit 210, in Figure 3 The middle part is shown. Based on signals out1 and out2, control signal 210 is configured as follows:

[0080] When voltage ramp Vc1 reaches voltage Vref', voltage ramp Vc1 stops and voltage ramp Vc2 starts.

[0081] When voltage ramp Vc2 reaches voltage Vref', voltage ramp Vc2 stops and voltage ramp Vc1 starts.

[0082] According to an embodiment, voltage ramp Vc1 is stopped by switching switch SW1 to the off state, and voltage ramp Vc2 is stopped by switching voltage SW3 to the off state. Conversely, voltage ramp Vc1 starts when switch SW1 is switched to the on state, and voltage ramp Vc2 starts when switch SW3 is switched to the on state. As an example, control circuit 210 includes RS latch 212, which has an nS input for receiving signal out2, an nR input for receiving signal out1, an nQ output for delivering signal ctrl3 for controlling switch SW3, and a Q output for delivering signal ctrl1 for controlling switch SW1. In this example, the RS latch is configured as follows:

[0083] - When signal out1 switches to low and signal out2 is high, set signal ctrl3 to high and set signal ctrl1 to low.

[0084] - When signal out2 switches to low and signal out1 switches to high, signal ctrl1 is set to high and signal ctrl3 is set to low. In this example, switches SW1 and SW3 are off when their respective control signals are high, and on when their respective control signals are high.

[0085] According to an embodiment, control signal 210 is further configured, based on signals out1 and out2, to reset generator 100 between every two consecutive voltage ramps Vc1 and generator 102 between every two consecutive voltage ramps Vc2. The respective resets of generators 100 and 102 include setting voltages Vc1 and Vc2 back to their initial values, i.e., the values ​​of voltages Vc1 and Vc2 at the start of the ramp.

[0086] According to an embodiment, the control unit 210 is configured to reset the generators 100 and 102 respectively by turning on and then off switches SW2 and SW4 respectively.

[0087] According to an embodiment, control circuit 210 is configured such that the reset of generators 100 and 102 occurs at the end of a timing period Ttemp, which begins at the stop or end of ramps Vc1 and Vc2, respectively. The timing period Ttemp is short enough that generators 100 and 102 are reset before the end of the next ramp Vc1 and Vc2, respectively. Therefore, for each ramp Vc1 and Vc2, voltages Vc1 and Vc2 maintain their maximum values ​​Vc1max and Vc2max, respectively, throughout the timing period Ttemp. This enables circuit 200 to read this maximum value during the timing period Ttemp, thereby updating the signal Vc1-sig or Vc2-sig during the timing period Ttemp.

[0088] Based on the functional indications given above, it is within the capabilities of those skilled in the art to implement the control circuit 210 such that it generates control signals for resetting generators 110 and 102 from signals out1 and out2, or even from signals ctrl3 and ctrl1, for example.

[0089] Preferably, when block 206 is configured to update and store signal Vc1-sig and / or update and store signal Vc2-sig, control circuitry 210 is further configured to deliver signals for controlling these update and storage phases. In this case, although this is in Figure 3 As not shown, circuit 200 includes input terminals configured to receive these control signals originating from circuit 210.

[0090] Based on the functional indications given above, it is within the capabilities of those skilled in the art to implement the control circuit 210 such that it generates control signals for the circuit 200 from signals out1 and out2, or even, for example, from signals ctrl3 and ctrl1.

[0091] According to an embodiment, oscillator 2 is used to generate a clock signal. This clock signal may then correspond to signal out1, signal out2, signal ctrl3, or signal ctrl1. However, due to the pulse characteristics of signals out1 and out2, the clock signal is preferably obtained after shaping signals out1 and / or out2, such as signal ctrl1 or ctrl3.

[0092] Figure 4 Explanation is shown Figure 3 Timing diagram of the voltage ramp Vc1 for the operation of oscillator 2.

[0093] Before time t10, generator 100 can be reset and voltage Vc1 is the initial value, which is 0V in this example where the ramp Vc1 increases.

[0094] At time t10, the voltage ramp Vc1 begins.

[0095] At the next time t11, voltage Vc1 reaches (overtakes) voltage Vref'. However, comparator COMP1' ( Figure 3 The output terminal out1 () Figure 4 (Not shown) Switches only at the next time t12, which is equal to t11+Tp. In other words, the output out1 of comparator COMP1' switches with a delay Tp relative to time t11, which is in response to the propagation time in comparator COMP1'.

[0096] Because of the fact that between times t11 and t12, due to the propagation time Tp in comparator COMP1', the output of comparator COMP1' remains in a state indicating that the voltage ramp Vc1 has not yet reached the voltage Vref', and control circuit 210 does not control the stopping of the voltage ramp via generator 100. Therefore, in this example of ramp Vc1 increasing, ramp Vc1 continues to increase until time t12.

[0097] At time t12, the output out1 of comparator COMP1' switches, thereby controlling the stopping of voltage ramp Vc1 by circuit 210. Voltage ramp Vc1 thus reaches its maximum value Vc1max at time t12, and this maximum value Vc1max is then equal to voltage Vref. In other words, output out1 switches when voltage Vc1 reaches the set point Vref, as if comparator COMP1' had already compared voltage Vc1 with voltage Vref and had zero propagation time Tp.

[0098] Therefore, in the ideal case where the propagation time Tp in the circuit COMP (e.g., comparators COMP1 and COMP2) of oscillator 1 is zero, the frequencies of signals out1 and out2 of oscillator 2 are equal to the frequencies of signals out1 and out2 of oscillator 1.

[0099] exist Figure 4 In the example, after time t12, voltage Vc1 remains at its maximum value Vc1max until time t13 equals t12 + Ttemp. Therefore, between times t12 and t13, the maximum value Vc1Max of the voltage ramp Vc1 is available for circuit 200. At time t13, generator 100 is reset, for example under the control of circuit 210, and voltage Vc1 is set back to its initial value, thereby switching signal out1.

[0100] Although this is in Figure 4 It is not shown in the figure, but time t10 corresponds to the end of voltage ramp Vc2, while time t12 corresponds to the beginning of the new voltage ramp Vc2.

[0101] Although not shown, the operation of oscillator 2 during voltage ramp Vc2 can be deduced from the operation of oscillator 2 during voltage ramp Vc1, as per the information provided. Figure 4 As described. However, it should be noted that in an alternative embodiment not shown, where circuit 200 is configured to modulate voltage Vref' based solely on the maximum value Vc1m or Vc2m, the timing period Ttemp for resetting generator 102 or 100 may be zero.

[0102] Figure 5 Shown in a more detailed way Figure 3 An embodiment of a portion of the oscillator 2 is shown, and more specifically, an embodiment of the oscillator 2 is shown. Figure 3 An embodiment of circuit 200, which is herein labeled 200-1. It should be noted that, for... Figure 3 The contents indicated by circuit 200 are applicable to Figure 5 Circuit 200-1.

[0103] In this embodiment, circuit 200-1 is configured to modulate voltage Vref' based on maximum values ​​Vc1m and Vc2m. In other words, signal Δ is preferably determined alternately based on signals Vc1-sig and Vc2-sig.

[0104] More specifically, in this embodiment, circuit 200 is configured to update and store a first signal Vc1-sig representing the maximum value Vc1m, and to update and store a second signal Vc2-sig representing the maximum value Vc2m.

[0105] In this embodiment, circuit 200-1 includes circuit 500 configured to generate a signal Vc1-sig (actually a voltage) based on voltage Vc1. Circuit 500 therefore includes an input configured to receive voltage Vc1 and an output configured to deliver signal Vc1-sig. More specifically, at the end of each voltage ramp Vc1, during a timing period Ttemp, circuit 500 is configured to update signal Vc1-sig based on the maximum value Vc1max of the voltage ramp Vc1, and then store the updated signal Vc1-sig.

[0106] Similarly, circuit 200-1 includes circuit 502 configured to generate a signal Vc2-sig (actually a voltage) based on voltage Vc2. Circuit 502 therefore includes an input configured to receive voltage Vc2 and an output configured to deliver signal Vc2-sig. More specifically, at the end of each voltage ramp Vc2, during a timing period Ttemp, circuit 502 is configured to update signal Vc2-sig based on the maximum value Vc2max of the voltage ramp Vc2, and then store the updated signal Vc2-sig.

[0107] Preferably, the update and storage stages of signals Vc1-sig and Vc2-sig are derived from the control circuit 210 ( Figure 3 The circuits 500 and 502 then include input terminals configured to receive these control signals. Figure 5 Not shown in the image.

[0108] Circuit 200-1 further includes a commutator 504, which includes an input terminal 506 configured to receive a signal Vc1-sig, an input terminal 508 configured to receive a signal Vc2-sig, and an output terminal 510 configured to deliver a signal (e.g., voltage) Vcmax. When the signal (not shown) used to control the commutator 504 is in a first binary state, Vcmax is equal to the signal Vc1-sig, and when the signal (not shown) used to control the commutator 504 is in a second binary state, Vcmax is equal to the signal Vc2-sig. Therefore, the signal is alternately equal to Vc1-sig and Vc2-sig. Preferably, the signal used to control the commutator 504 is transmitted through a control circuit 210 (…). Figure 3 ) is delivered.

[0109] Circuit 200 further includes an error amplifier 512 (“ErrAmp”) configured to deliver a signal Δ. Error amplifier 512 includes an input configured to receive a signal Vcmax, this input coupled, for example, to the output 510 of commutator 504. Amplifier 512 further includes another input configured to receive a signal Vrefsample representing a voltage Vref, determined by the voltage Vref.

[0110] exist Figure 5 In one embodiment, circuit 200 includes optional circuitry 514 configured to generate a signal Vrefsample based on voltage Vref. Circuitry 514 therefore includes an input configured to receive voltage Vref and an output configured to deliver the signal Vrefsample. Preferably, at the end of each voltage ramp Vc1 or each ramp Vc2, during a time period Ttemp, circuitry 514 is configured to update the signal Vrefsample based on voltage Vref and then store the updated signal Vrefsample. The operation and implementation of circuitry 514 are, for example, similar to the operation and implementation of circuits 500 and 502.

[0111] exist Figure 5 In this embodiment, the output of circuit 514 is coupled to the input of error amplifier 512, which is configured to receive the signal Vrefsample via an optional commutator 516 (preferably the same as commutator 504). Commutator 516 includes two inputs coupled to, and preferably connected to, the output of circuit 514; and an output coupled to the input of error amplifier 512. Preferably, commutator 516 is controlled in the same way as commutator 504, for example, by the same control signal. As will be seen in more detail below, commutator 516 is provided to enable the same charge injection to occur on signals Vcmax and Vrefsample, such that these charge injections cancel each other out at the potential of error amplifier 512.

[0112] According to an embodiment, each circuit 500, 502, and 514 respectively spans signals Vc1-sig, Vc2-sig, and Vrefsample across a capacitor element coupled to the input of the circuit by a switch, as if combined Figure 6 as well as Figure 7Further detailed description. During their switching, these switches can inject charge into their coupled capacitive elements. The provision of circuit 514 enables the same charge injection to occur at the output signal of circuit 514 as well as in signals Vc1-sig and Vc2-sig. Therefore, the charge injected into circuits 500, 502, and 514 cancels out in signal Δ, since signal Δ is a differential signal representing the difference between signal Vcmax and Vrefsample. Similarly, switching of commutator 504 can inject charge into signal Vcmax. Commutator 516 is provided so that the same charge injection can occur in signals Vcmax and Vrefsample, and cancel out in signal Δ.

[0113] In an alternative embodiment not shown, commutator 516 and circuit 514 are omitted, and the signal Vrefsample is the same as or in other words confused with the signal Vref. In another alternative embodiment not shown, only rectifier 516 is omitted, and the output of circuit 514 then delivers the signal Vrefsample, and is connected, for example, to the corresponding input of error amplifier 512.

[0114] Circuits 500 and 502, optional circuit 514, commutator 504, preferred commutator 516, and error amplifier 512 implement the following: Figure 3 The function of the block or circuit 206 described.

[0115] exist Figure 5 In one embodiment, circuit 200 includes a voltage generator 518 configured to deliver a voltage Vref', the generator 518 being controlled by a signal Δ. The generator 518 implements... Figure 3 The function of the subtractor block 208 is described.

[0116] As an example, generator 518 includes: similar to the one about Figure 3 The described generator 112; current source 520, configured to deliver a constant current Tref', preferably in conjunction with a current Iref ( Figure 3 The same as; and resistor R', preferably the same as resistor R( Figure 3 The same applies. Current source 520 and resistor R' are connected in series between nodes 106 and 108. Generator 518 further includes a MOS ("Metal-Oxide-Semiconductor") transistor 522 connected in parallel with resistor R', the gate of which receives a signal Δ. Therefore, as the difference between voltage Vref and the maximum values ​​Vc1m and Vc2m increases, signal Δ increases, which reduces the equivalent resistance corresponding to the parallel combination of resistor R' and transistor 522, resulting in a decrease in voltage Vref'.

[0117] When circuit 200-1 is configured to modulate the voltage Vref' based on the maximum value Vc1m and the maximum value Vc2m, examples of embodiments of circuit 200-1 have already been described above. Figure 5 It has been described.

[0118] In an alternative embodiment (not shown), circuit 200-1 is configured to modulate voltage Vref' based solely on the maximum value Vc1m. In this variant, commutator 504, circuit 502, and optional commutator 516 are omitted. The signal Vcmax is thus identical to signal Vc1-sig, i.e., confused with signal Vc1-sig. In another alternative embodiment (not shown), circuit 200 is configured to modulate voltage Vref' based solely on the maximum value Vc2m. In this other variant, commutator 504, circuit 500, and optional commutator 516 are omitted. The signal Vcmax is thus identical to signal Vc2-sig, i.e., confused with signal Vc2-sig.

[0119] Figure 6 Shown in a more detailed way Figure 3 An embodiment of oscillator 2. More precisely, Figure 6 The information about each point is shown in more detail. Figure 5 The circuit 500 describes embodiments of circuits 500 and 502, which are connected here to generators 100 and 102 of oscillator 2, respectively.

[0120] Circuit 500 includes a series combination of circuit element C1' and switch SW5, which is connected in parallel with capacitor element C1. Switch SW5 is connected to a terminal of capacitor element C1, at which voltage Vc1 is available. In other words, switch SW5 couples the output of generator 100 to a first terminal of capacitor element C1', and a second terminal of capacitor element C1' is coupled, preferably, connected to node 108. Capacitor element C1' is preferably the same as capacitor element C1. Signal Vc1-sig corresponds to the voltage across capacitor element C1', or in other words, voltage Vc1-sig is available at the first terminal of capacitor element C1', which then forms the output of circuit 500. Voltage Vc1-sig is updated based on voltage Vc1 by the opening of switch SW5 and stored on capacitor element C1' by the opening of switch SW5. Preferably, the signal for controlling SW5 is transmitted through control circuit 210 (…). Figure 3 The voltage is delivered. Preferably, after each voltage ramp Vc1, switch SW5 switches to the ON state during a timing period Ttemp after the ramp stops, and then switches to the OFF state at the end of the period Ttemp.

[0121] Similarly, circuit 502 includes a series combination of capacitor element C2' and switch SW6, which is connected in parallel with capacitor element C2. Switch SW6 is connected to a terminal of capacitor element C2, at which voltage Vc2 is available. In other words, switch SW6 couples the output of generator 102 to a first terminal of capacitor element C2', and a second terminal of capacitor element C2' is coupled, preferably connected, to node 108. Capacitor element C2' is preferably the same as capacitor element C2. Signal Vc2-sig corresponds to the voltage across capacitor element C2', or in other words, voltage Vc2-sig is available at the first terminal of capacitor element C2', which thus forms the output of circuit 502. Voltage Vc2-sig is updated based on voltage Vc2 by the opening of switch SW5 and stored on capacitor element C2' by the opening of switch SW6. Preferably, the signal for controlling SW6 is transmitted through control circuit 210 ( Figure 3 The voltage is delivered. Preferably, after each voltage ramp Vc2, switch SW6 switches to the ON state during a timing period Ttemp after the ramp stops, and then switches to the OFF state at the end of the period Ttemp.

[0122] Based on the functional instructions given above, implement circuit 210 ( Figure 3 Based on signals out1 and out2 ( Figure 3 Delivering the control switches SW5 and SW6 is within the capabilities of those skilled in the art.

[0123] In an alternative embodiment (not shown), generator 100 includes an additional switch connected in parallel with a series combination of switch SW1 and capacitor element C1, which is controlled, for example, like switch SW2. When switch SW1 is open, this additional switch is capable of coupling current source 104 to node 108 to reduce or even suppress possible transients at the terminals of current source 104 coupled to switch SW1. Symmetrically, in this variant, generator 102 includes an additional switch connected in parallel with a series combination of switch SW3 and capacitor element C2, which is controlled, for example, like switch SW4.

[0124] Figure 7 Shown in a more detailed way Figure 3 An embodiment of oscillator 2. More precisely, Figure 7 Showing information in a more detailed manner Figure 5 An embodiment of circuit 514 is described, wherein circuit 514 is connected here to generator 112 of oscillator 2.

[0125] Circuit 514 includes a capacitor element C3 and a switch SW7, which couples the output of generator 112, i.e., the node used to deliver voltage Vref, to a first terminal of capacitor element C3. The second terminal of capacitor element C3 is coupled, preferably, to node 108. Circuit 514 also includes a capacitor element C3' (preferably the same as capacitor element C3) and a switch SW8, which couples the first terminal of capacitor element C3 (i.e., the node connecting capacitor element C3 and switch SW7) to the first terminal of capacitor element C3'. The second terminal of capacitor element C3' is coupled, preferably, to node 108. Voltage Vrefsample is available at the first terminal of capacitor element C3', which forms the output of circuit 514.

[0126] Preferably, the signals used to control switches SW7 and SW8 are based on signals out1 and out2 via control circuit 210 ( Figure 3 ) is delivered. As an example, switch SW7 is similar to switch SW1 ( Figure 6 ) is controlled in a similar manner, and switch SW8 is therefore similar to switch SW5 ( Figure 6 Therefore, the charge injection on capacitor C3' due to the switching of switches SW7 and SW8 is controlled by the same principle as the charge injection on capacitor C1' due to the switching of switches SW1 and SW5. Figure 6 The charge injection on them is the same. According to another example, switches SW7 and SW8 are controlled in the same way as their counterparts SW3 and SW6. Figure 6 Due to the switching of switches SW7 and SW8, charge is injected into capacitor element C3' and then onto capacitor element C2' due to the switching of switches SW3 and SW6. Figure 6 The charge injection on the surface is the same.

[0127] Figure 8 Shown in a more detailed way Figure 3 An embodiment of oscillator 2. More precisely, in Figure 8 In the middle, the circuit 200 of oscillator 2 consists of Figure 5 Circuit 200-1 is implemented, and circuits 500 and 502 are as follows: Figure 6 The implementation is described in the diagram, and circuit 514 is as follows. Figure 7 This is implemented as described in the text. Furthermore, in... Figure 8 In the present invention, an embodiment of circuit 210 is described in detail.

[0128] In this detailed embodiment, when the corresponding control signals of SW1, SW2, SW3, SW4, SW5, SW6, SW7 and SW8 are in high and low states respectively, they are considered to be on and off respectively.

[0129] Control circuit 210 includes, for example, regarding Figure 3 The latch 212 is described above. In this example, as... Figure 3 As explained, signal ctrl1 is used to control switch SW1, and signal ctrl3 is used to control switch SW3.

[0130] In this example, control circuit 210 also includes a D flip-flop 800. Flip-flop 800 includes a D data input that receives a potential Vdd, a C synchronization input that is active on the rising edge and receives a signal ctrl3, a Q output that copies and stores the potential Vdd on each rising edge of signal ctrl3, and an R input. When the signal applied to the R input of the flip-flop is high, the Q output of flip-flop 800 is set back to ground potential GND. The Q output of flip-flop 800 is coupled to the R input of flip-flop 800 via circuit D1 with a delay equal to the time period Ttemp. The signal ctrl5, used to control switch SW5, is available at the Q output of flip-flop 800 and is delivered to the R input of the flip-flop via circuit D1 with a delay Ttemp.

[0131] In this example, control circuit 210 also includes a D flip-flop 802, identical to flip-flop 800. The C input of flip-flop 800 is coupled to its Q output via an inverter. In other embodiments, the C input of flip-flop 802 receives the inverted signal ctrl5. The D input of flip-flop 802 receives a potential Vdd. The signal ctrl2, used to control switch SW2, is available at the Q output of flip-flop 802 and is delivered to its R input with a delay introduced by circuit D2, which couples the Q output and R input of flip-flop 802.

[0132] Therefore, when the voltage ramp Vc1 intersects with the voltage Vref' by causing signal out1 to switch low, signal ctrl3 switches high, causing switch SW3 to turn on and ramp Vc2 to begin. Then, signal ctrl1 switches low, causing switch SW1 to turn off and ramp Vc1 to end. A rising edge on signal ctrl3 also causes signal ctrl5 to switch high and switch SW5 to turn on (updating voltage Vc1max). Signal ctrl5 remains high for the entire time period Ttemp until a rising edge of signal ctrl5 is transmitted to the R input of flip-flop 800 via circuit D1, causing signal ctrl5 to switch low and switch SW5 to turn off (storing voltage Vc1max). Switching ctrl5 low causes a rising edge to be applied to the C input of flip-flop 802, causing signal ctrl2 to switch high and switch SW2 to turn on (resetting voltage Vc1). The signal ctrl2 remains high until its rising edge is sent to the R input of the flip-flop 802 by circuit D2, which causes the signal ctrl2 to switch low and the switch SW2 to open.

[0133] In this example, the control circuit 210 further includes a D flip-flop 804, identical to flip-flops 800 and 804. Flip-flop 804 includes a D data input for receiving a potential Vdd, a C synchronization input for receiving a signal ctrl1, and a Q output for delivering a signal ctrl6 to control switch SW6. The Q output of flip-flop 804 is coupled to its R input via a circuit D1 that introduces a delay equal to the time period Ttemp.

[0134] In this example, control circuit 210 further includes a D flip-flop 806, identical to flip-flop 800. The C input of flip-flop 806 is coupled to the Q output of flip-flop 804 by an inverter. In other words, the C input of flip-flop 806 receives the inverted signal ctrl6. The D input of flip-flop 806 receives the potential Vdd. The signal ctrl4, used to control switch SW4, is available at the Q output of flip-flop 806, and is delivered to the R input of flip-flop 806 with a delay introduced by circuit D2, which couples the Q output and R input of flip-flop 806.

[0135] Therefore, when the voltage ramp Vc2 intersects with the voltage Vref' by causing signal out2 to switch low, signal ctrl1 switches high, causing switch SW1 to turn on and ramp Vc1 to begin. Signal ctrl3 then switches low, causing switch SW3 to turn off and ramp Vc2 to end. A rising edge on signal ctrl1 also causes signal ctrl6 to switch high and switch SW6 to turn on (updating voltage Vc2max). Signal ctrl6 remains high throughout the entire Temp period until a rising edge of signal ctrl6 is sent to the R input of flip-flop 804 via circuit D1, causing signal ctrl6 to switch low and switch SW6 to turn off (storing voltage Vc2max). Switching ctrl6 low causes a rising edge to be applied to the C input of flip-flop 806, causing signal ctrl4 to switch high and switch SW4 to turn on (resetting voltage Vc2). The signal ctrl4 remains high until the rising edge of the signal ctrl4 is sent to the R input of the flip-flop 806 by circuit D2, which causes the signal ctrl4 to switch to low and SW4 to turn off.

[0136] Within the capabilities of those skilled in the art, the switching frequencies of commutator 504 and possibly commutator 516 can be selected, and control signals for these commutators can be generated via circuit 210. As an example, the signals used to control commutators 504 and 516 are switched at the beginning of each of each ramp Vc1 and Vc2, for example, such that during each voltage ramp Vc1, signal Vcmax is equal to signal Vc2max, and during each voltage ramp Vc2, signal Vcmax is equal to signal Vc1max. As another example, commutator 504 and possibly commutator 516 are switched at integral divisions of the clock signal obtained from oscillator 2, such that signal Vcmax represents the average value between signal Vc1-sig and signal Vc2-sig, which alternately take the values ​​of signal Vc1-sig and signal Vc2-sig during the frequency switching of commutators 504 and 516.

[0137] exist Figure 8 In the example, switches SW7 and SW8 are controlled in the same way as the corresponding switches SW1 and SW3. In other examples not shown, when commutator 504 is in a first state where signal Vcmax equals signal Vc1-sig, the switches can be controlled in the same way as the corresponding switches SW1 and SW5, and when commutator 504 is in a second state where signal Vcmax equals signal Vc2-sig, the switches can be controlled in the same way as the corresponding switches SW3 and SW6.

[0138] Within the capabilities of those skilled in the art, the value of the time period Ttemp and the value of the delay introduced by each circuit D2 can be selected so that while generators 102 and 100 provide voltage ramps Vc2 and VC1 respectively, the continuity of the stages of updating voltages Vc1max and Vc2max respectively, storing voltages Vc1max and Vc2max respectively, and resetting voltages Vc1 and Vc2 respectively can be achieved.

[0139] Although previously not combined Figures 1 to 8 While described, comparators COMP1' and COMP2' may each exhibit offsets between their inverting and non-inverting inputs. However, these offsets are typically reduced or even suppressed during the calibration phase of comparators COMP1' and COMP2'. Furthermore, although this offset may vary with the temperature of oscillator 2, its effect with temperature variation is negligible compared to the variation of the propagation time of comparators COMP1' and COMP2' with oscillator temperature. It can also be assumed that this input offset affects the propagation time Tp, and is therefore compensated for by the variation of voltage Vref' with propagation time Tp.

[0140] Furthermore, a first embodiment and its variants have been described, wherein circuit 200 is configured to modulate voltage Vref' based on maximum values ​​Vc1m and Vc2m; and a second embodiment and its variants, wherein circuit 200 is configured to modulate voltage Vref' based only on maximum value Vc1m or maximum value Vc2m. These first and second embodiments and variants are capable of obtaining periodic signals, such as signals ctrl3 and ctrl1, whose frequencies vary only slightly, for example, less than 1%, over a temperature range from -40°C to 130°C. However, the first embodiment and its variants have the additional advantage of having a duty cycle that also varies only slightly, for example, less than 1%, over the same periodic signals in the second embodiment and its variants, compared to the duty cycles of these periodic signals over the temperature range from -40°C to 130°C. Compared to the second embodiment and its variants, the first embodiment and its variants are also capable of correcting for possible offsets between the values ​​of capacitor element C1 and capacitor element C2, and / or between the values ​​of current IC1 and current IC2, and / or between the values ​​of comparator COMP'1 and comparator COMP'2.

[0141] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will conceive of by those skilled in the art. In particular, to the extent possible within the capabilities of those skilled in the art, the described embodiments and variations can be modified to suit:

[0142] The cases where ramps Vc1 and Vc2 are decreasing, and / or the cases where one or more switch control signals are high instead of low, causing these signals to turn on the corresponding switches, and / or the cases where voltage Vref' is delivered to the inverting inputs of comparators COMP1 and / or COMP2.

[0143] More generally, other implementations of circuits 200, 210, 500, 502, 514, 100, 102, 112 and / or 518 (instead of those described above as examples) are within the capabilities of those skilled in the art.

[0144] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. In particular, based on the functional indications given above, implementing circuits 200, 210, 500, 502, 514, 100, 102, 112 and / or 518 is within the capabilities of those skilled in the art.

Claims

1. An oscillator, comprising: The first generator is configured to generate a first series of first voltage ramps; The second generator is configured to generate a second series of second voltage ramps; A first circuit is configured to: compare each first voltage ramp with a setpoint voltage and deliver a binary first signal representing the comparison between the first voltage ramp and the setpoint voltage; compare each second voltage ramp with the setpoint voltage and deliver a binary second signal representing the comparison between the second voltage ramp and the setpoint voltage; The second circuit is configured based on the first signal and the second signal as follows: When the first voltage ramp reaches the set point voltage, the first voltage ramp stops and the second voltage ramp begins; and When the second voltage ramp reaches the set point voltage, the second voltage ramp stops and the first voltage ramp starts. as well as A third circuit is configured to modulate the setpoint voltage oscillator based on the maximum value of at least the last first voltage ramp in the first series of first voltage ramps compared with the setpoint voltage. The second circuit is further configured to reset the first generator between every two consecutive first voltage ramps in the first series, and to reset the second generator between every two consecutive second voltage ramps in the second series.

2. The oscillator according to claim 1, wherein: The first generator includes: a first capacitor element, a first switch, and a first current source connected in series between a node with the applied power supply voltage and a node with the applied reference potential; and a second switch connected in parallel with the first capacitor element; and The second generator includes: a second capacitor element connected in series between the node applying the power supply voltage and the node applying the reference potential, a third switch, and a second current source, and a fourth switch connected in parallel with the second capacitor element. The second circuit is configured based on the first signal and the second signal as follows: When the second voltage ramp reaches the set point voltage, the first switch is turned on and the third switch is turned off; and When the first voltage ramp reaches the set point voltage, the third switch is turned on and the first switch is turned off.

3. The oscillator of claim 2, wherein the first generator is reset by turning on the second switch, wherein the second generator is reset by turning on the fourth switch, and wherein the second circuit is configured to control the second switch and the fourth switch based on the first signal and the second signal.

4. The oscillator of claim 2, wherein the third circuit is configured to: generate a third signal representing the difference between a reference voltage and the maximum value of at least the last first voltage ramp in the first series, and deliver the setpoint voltage equal to the reference voltage minus the difference.

5. The oscillator of claim 4, wherein the third circuit comprises a third current source and a resistor connected in series between the node applying the power supply voltage and the node applying the reference potential, and a transistor connected in parallel with the resistor for controlling the terminals of the transistor to be configured to receive the third signal.

6. The oscillator of claim 5, wherein the third circuit includes a fourth circuit configured to update and subsequently store a first voltage representing the maximum value of each first voltage ramp between the end of each first voltage ramp and the next reset of the first generator, the second circuit being configured to control the storage and the subsequent update based on the first signal and the second signal.

7. The oscillator according to claim 6, wherein: The fourth circuit includes a series combination of a capacitor element and a switch, the series combination being connected in parallel with the first capacitor element, and the first voltage being obtainable across the capacitor element. The first voltage is updated when the switch is turned on and stored when the switch is turned off; as well as The second circuit is configured to control the switching of the fourth circuit based on the first signal and the second signal.

8. The oscillator of claim 6, wherein the third circuitry includes an error amplifier having a first input configured to receive a signal representing the reference voltage, a second input configured to receive the first voltage, and an output configured to deliver the third signal.

9. The oscillator of claim 8, wherein the third circuit includes circuitry for storing the reference voltage, the circuitry comprising: A capacitor element and a first switch, wherein the first switch couples a node for delivering the reference voltage to one terminal of the capacitor element, and the other terminal of the capacitor element is coupled to a node to which the reference potential is applied; An additional capacitor element and a second switch, wherein the second switch couples a node connecting the capacitor element and the first switch to one terminal of the additional capacitor element, and the other terminal of the additional capacitor element is coupled to a node where the reference potential is applied; and The third circuit is configured to control the first and second switches of the circuit used for storage based on the first and second signals.

10. The oscillator of claim 1, wherein the third circuit is configured to modulate the setpoint voltage based on the maximum value of at least the last of the first voltage ramps in the first series compared with the setpoint voltage, and the maximum value of at least the last of the second voltage ramps in the second series compared with the setpoint voltage.

11. The circuit of claim 10, wherein the third circuit is configured to generate a third signal that alternately represents a first difference between a reference voltage and the maximum value of at least the last first voltage ramp, and a second difference between the reference voltage and the maximum value of at least the last second voltage ramp, and the third circuit is configured to deliver the setpoint voltage that alternately equals the reference voltage minus the first difference and the reference voltage minus the second difference.

12. The oscillator according to claim 11, wherein: The third circuit includes a fourth circuit configured to update and store a first voltage representing the maximum value of each first voltage ramp between the end of each first voltage ramp and the next reset of the first generator. The third circuit includes a fifth circuit configured to update and store a second voltage representing the maximum value of each second voltage ramp between the end of each second voltage ramp and the next reset of the second generator. The second circuit is configured to control the storage and the update based on the first signal and the second signal.

13. The oscillator according to claim 12, wherein: The fourth circuit includes a first combination of a capacitor element and a switch connected in series, the first combination being connected in parallel with the first capacitor element of the first generator, the first voltage being obtainable across the capacitor element of the fourth circuit, the first voltage being updated by turning on the switch and stored by turning off the switch. The fifth circuit includes a second combination of a capacitor element and a switch connected in series, the second combination being connected in parallel with the second capacitor element of the second generator, the second voltage being obtainable across the capacitor element of the fifth circuit, the second voltage being updated by the switching on and stored by the switching off; as well as The second circuit is configured to control the switching of the fourth circuit and the fifth circuit based on the first signal and the second signal.

14. The oscillator of claim 12, wherein the third circuit comprises: The first commutator has an input terminal configured to receive the first voltage and another input terminal configured to receive the second voltage; as well as An error amplifier has a first input terminal configured to receive a reference voltage, a second input terminal coupled to an output terminal of the first commutator, and an output terminal configured to deliver the third signal, the first commutator being controlled by the second circuit based on the first signal and the second signal.

15. The oscillator of claim 14, wherein the third circuit includes circuitry for storing the reference voltage, the circuitry comprising: A capacitor element and a first switch, wherein the first switch couples a node for delivering the reference voltage to one terminal of the capacitor element, and the other terminal of the capacitor element is coupled to a node to which the reference potential is applied; An additional capacitor element and a second switch, wherein the second switch couples a node connecting the capacitor element and the first switch to one terminal of the additional capacitor element, the other terminal of the additional capacitor element being coupled to a node to which the reference potential is applied, and the second switch is configured to deliver the signal representing the reference voltage. as well as The second circuit is configured to control the first switch and the second switch of the storage circuit based on the first signal and the second signal.

16. The oscillator of claim 15, wherein the other terminal of the additional capacitive element is coupled to the first input of the error amplifier by a second commutator, and the second circuit is configured to control the second commutator in a manner similar to the first commutator.

17. The oscillator of claim 11, wherein the third circuit comprises: A third current source and a resistor are connected in series between the node where the applied power supply voltage is applied and the node where the applied reference potential is applied. And a transistor connected in parallel with the resistor, for controlling the terminals of the transistor to be configured to receive the third signal.

18. An oscillator, comprising: The first generator is configured to generate a first series of first voltage ramps; The second generator is configured to generate a second series of second voltage ramps; The comparator circuit is configured to: compare each first voltage ramp with a setpoint voltage and deliver a binary first signal representing the comparison between the first voltage ramp and the setpoint voltage; compare each second voltage ramp with the setpoint voltage and deliver a binary second signal representing the comparison between the second voltage ramp and the setpoint voltage; as well as A voltage generator circuit is configured to generate the setpoint voltage, the voltage generator circuit being configured to modulate the setpoint voltage to alternately have a first value and a second value, the first value being based on the maximum value of at least the last of a first voltage ramp in a first series compared with the setpoint voltage, and the second value being based on the maximum value of at least the last of a second voltage ramp in a second series compared with the setpoint voltage. The voltage generator circuit is configured to generate a first difference signal indicating the difference between the maximum value of at least the last first voltage ramp and a reference voltage, and then generate a first value of the setpoint voltage equal to the reference voltage minus the first difference signal; and is configured to generate a second difference signal indicating the difference between the maximum value of at least the last second voltage ramp and a reference voltage, and then generate a second value of the setpoint voltage equal to the reference voltage minus the second difference signal.

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