Processor management method, device, electronic device and storage medium

Abstract

The present application provides a processor management method, device, electronic device and storage medium, the method comprising: obtaining the current state information of each processor in the device to be managed; wherein the current state information represents the processor's own working state and load mounting situation; comparing the current state information of each processor to obtain the state difference between each processor; with the goal of reducing the state difference between each processor, according to the impact of the state difference between each processor on the bit error rate between processors, the state of each processor is adjusted accordingly. The processor management method provided by the above scheme adjusts the state of the processor with the goal of reducing the state difference between each processor, thereby fundamentally eliminating the factors that cause bit errors between processors, and can significantly reduce the bit error rate between processors in any application scenario.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor management method, device, electronic device and storage medium. Background Art

[0002] A high-density server is a server device with an optimized architecture launched for cloud computing, data centers, and Internet applications. It can integrate more processors and I / O expansion capabilities in a very small physical space, so that there will be a large amount of data communication between processors. If the bit error rate of the interconnection channel between processors increases, it will cause stability problems for the entire machine.

[0003] In the prior art, in order to reduce the bit error rate between processors, the signal quality of the physical path between processors is usually increased to reduce the interference between communication signals, or the negotiation parameters of the high-speed interconnect path in the CPU are adjusted to the best.

[0004] However, in a high-density server, even if the communication physical links between processors are adjusted to the best and the negotiation parameters are adjusted to the optimal, the bit error rate will still increase significantly in some application scenarios. Summary of the invention

[0005] The present application provides a processor management method, device, electronic device and storage medium to solve the defects of the prior art that the bit error rate between processors cannot be reduced in certain application scenarios.

[0006] The first aspect of the present application provides a processor management method, comprising:

[0007] Obtaining current status information of each processor in the device to be managed; wherein the current status information represents the working status and load mounting status of the processor itself;

[0008] Comparing the current status information of each of the processors to obtain the status difference between the processors;

[0009] With the goal of reducing the state difference between the processors, the state of each processor is adjusted accordingly according to the impact of the state difference between the processors on the bit error rate between the processors.

[0010] Optionally, adjusting the state of each processor accordingly according to the influence of the state difference between the processors on the bit error rate between the processors includes:

[0011] estimating the current bit error rate between the processors according to the state difference between the processors;

[0012] Determine a processor state adjustment plan for the device to be managed according to the bit error rate estimation results between the processors and the impact of the state difference on the bit error rate between the processors;

[0013] According to the processor state adjustment scheme, the state of each processor is adjusted accordingly.

[0014] Optionally, estimating the current bit error rates between the processors according to the state differences between the processors includes:

[0015] According to the relationship between the state difference and the bit error rate between processors, a bit error rate prediction model is constructed;

[0016] The state differences between the processors are input into the bit error rate prediction model to determine the current bit error rates between the processors based on the bit error rate prediction model.

[0017] Optionally, determining the processor state adjustment scheme of the device to be managed according to the bit error rate estimation result between the processors and the influence of the state difference on the bit error rate between the processors includes:

[0018] Locating a processor combination to be adjusted according to a bit error rate estimation result between the processors;

[0019] For each of the processor combinations, a processor state adjustment scheme for the processor combination is determined according to the impact of the state difference of the processor combination on the bit error rate between processors.

[0020] Optionally, determining a processor state adjustment scheme of the processor combination according to the influence of the state difference of the processor combination on the bit error rate between processors includes:

[0021] Determining the indicator to be adjusted of the processor combination according to the safety range of various difference indicators represented by the influence of the state difference of the processor combination on the bit error rate between processors;

[0022] A standard is formulated according to a preset processor state adjustment scheme, and a processor state adjustment scheme of the processor combination is determined according to the to-be-adjusted index of the processor combination.

[0023] Optionally, the current state information of the processor includes at least one of power consumption information, load mounting information and temperature of the processor.

[0024] Optionally, the state difference between the processors includes at least one of a power consumption difference, a load power consumption difference and a temperature difference.

[0025] A second aspect of the present application provides a processor management device, including:

[0026] An acquisition module is used to acquire the current status information of each processor in the device to be managed; wherein the current status information represents the working status and load mounting status of the processor itself;

[0027] A determination module, used for comparing the current status information of each of the processors to obtain the status difference between the processors;

[0028] The management module is used to adjust the status of each processor accordingly according to the influence of the status difference between each processor on the bit error rate between processors with the goal of reducing the status difference between each processor.

[0029] Optionally, the management module is specifically used to:

[0030] estimating the current bit error rate between the processors according to the state difference between the processors;

[0031] Determine a processor state adjustment plan for the device to be managed according to the bit error rate estimation results between the processors and the impact of the state difference on the bit error rate between the processors;

[0032] According to the processor state adjustment scheme, the state of each processor is adjusted accordingly.

[0033] Optionally, the management module is specifically used to:

[0034] According to the relationship between the state difference and the bit error rate between processors, a bit error rate prediction model is constructed;

[0035] The state differences between the processors are input into the bit error rate prediction model to determine the current bit error rates between the processors based on the bit error rate prediction model.

[0036] Optionally, the management module is specifically used to:

[0037] Locating a processor combination to be adjusted according to a bit error rate estimation result between the processors;

[0038] For each of the processor combinations, a processor state adjustment scheme for the processor combination is determined according to the impact of the state difference of the processor combination on the bit error rate between processors.

[0039] Optionally, the management module is specifically used to:

[0040] Determining the indicator to be adjusted of the processor combination according to the safety range of various difference indicators represented by the influence of the state difference of the processor combination on the bit error rate between processors;

[0041] A standard is formulated according to a preset processor state adjustment scheme, and a processor state adjustment scheme of the processor combination is determined according to the to-be-adjusted index of the processor combination.

[0042] Optionally, the current state information of the processor includes at least one of power consumption information, load mounting information and temperature of the processor.

[0043] Optionally, the state difference between the processors includes at least one of a power consumption difference, a load power consumption difference and a temperature difference.

[0044] A third aspect of the present application provides an electronic device, comprising: at least one processor and a memory;

[0045] The memory stores computer-executable instructions;

[0046] The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method described in the first aspect and various possible designs of the first aspect.

[0047] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method described in the first aspect and various possible designs of the first aspect are implemented.

[0048] The technical solution of this application has the following advantages:

[0049] The present application provides a processor management method, device, electronic device and storage medium, the method comprising: obtaining the current state information of each processor in the device to be managed; wherein the current state information represents the processor's own working state and load mounting situation; comparing the current state information of each processor to obtain the state difference between each processor; with the goal of reducing the state difference between each processor, according to the impact of the state difference between each processor on the bit error rate between processors, the state of each processor is adjusted accordingly. The processor management method provided by the above scheme adjusts the state of the processor with the goal of reducing the state difference between each processor, thereby fundamentally eliminating the factors that cause bit errors between processors, and can significantly reduce the bit error rate between processors in any application scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application, and a person skilled in the art can also obtain other drawings based on these drawings.

[0051] Figure 1 This is a schematic diagram of the structure of the processor management system based on the embodiment of the present application;

[0052] Figure 2 A flowchart of a processor management method provided in an embodiment of the present application;

[0053] Figure 3 A schematic diagram of the structure of an exemplary processor management system provided in an embodiment of the present application;

[0054] Figure 4 A schematic diagram of the structure of a processor management device provided in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0056] The above drawings have shown clear embodiments of the present application, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the following embodiments, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0059] With the rise of big data applications and the rapid growth of cloud computing, the demand for data center traffic processing capabilities will increase several times. However, the application of large-scale computing systems faces the problem of limited computer room space. High-density servers are server devices with optimized architectures launched for cloud computing, data centers, and Internet applications. They can integrate more processors and I / O expansion capabilities in a very small physical space. Such a design can greatly reduce customers' space costs and significantly improve computer performance. Servers with specifications such as 1U dual-channel and 2U 4-channel are developed with the goal of increasing computing power density in limited space. Here, multi-channel refers to multiple CPUs. There will be a large amount of data communication between CPUs. The most important stability indicator of multi-channel CPU products is the stability of the interconnection communication between CPUs. When the bit error rate of the interconnection channel between CPUs increases, it will cause stability problems for the entire machine. In serious cases, it will cause serious problems such as downtime, loss of connection from the CPU, and automatic restart.

[0060] In the prior art, the signal quality of the physical path between processors is usually increased to reduce the interference between communication signals, or the negotiation parameters of the high-speed interconnect path in the CPU are adjusted to the best. However, in high-density servers, even if the communication physical link between processors is adjusted to the best and the negotiation parameters are adjusted to the best, the bit error rate will still increase significantly in some application scenarios.

[0061] In response to the above problems, the processor management method, device, electronic device and storage medium provided in the embodiments of the present application obtain the current state information of each processor in the device to be managed; wherein the current state information represents the processor's own working state and load mounting status; compare the current state information of each processor to obtain the state difference between the processors; with the goal of reducing the state difference between the processors, according to the impact of the state difference between the processors on the bit error rate between the processors, the state of each processor is adjusted accordingly. The processor management method provided by the above scheme adjusts the state of the processor with the goal of reducing the state difference between the processors, fundamentally eliminating the factors that cause bit errors between processors, and can significantly reduce the bit error rate between processors in any application scenario.

[0062] The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0063] First, the structure of the processor management system on which this application is based is described:

[0064] The processor management method, device, electronic device and storage medium provided in the embodiments of the present application are applicable to multi-processor devices such as high-density servers. Figure 1As shown, it is a schematic diagram of the structure of the processor management system based on the embodiment of the present application, which mainly includes multiple processors, a data acquisition device and a processor management device for managing these processors. Specifically, the data acquisition device can be used to collect the current state information of each processor, and the collected information can be sent to the processor management device. After obtaining this information, the processor management device adjusts the state of each process for the purpose of reducing the bit error rate between processors.

[0065] The embodiment of the present application provides a processor management method for managing the status of multiple CPUs in the same device. The execution subject of the embodiment of the present application is an electronic device, such as a server, a desktop computer, a laptop computer, a tablet computer, and other electronic devices that can be used to include multiple CPUs.

[0066] like Figure 2 FIG. 1 is a flow chart of a processor management method provided in an embodiment of the present application, and the method includes:

[0067] Step 201: Acquire current status information of each processor in the device to be managed.

[0068] The current state information represents the working state and load status of the processor. In the embodiment of the present application, the processor may specifically refer to a central processing unit (CPU).

[0069] Specifically, the current status information of each processor may be collected based on components such as BIOS and BMC in the device.

[0070] Step 202, comparing the current status information of each processor to obtain the status difference between the processors.

[0071] The current status information of the processor includes at least one of power consumption information, load mounting information and temperature of the processor.

[0072] Accordingly, the state difference between the processors includes at least one of a power consumption difference, a load power consumption difference, and a temperature difference.

[0073] It should be noted that due to the different manufacturing processes of different processors, even if the load type, load model and mounting quantity represented by the load mounting information of two processors are the same, there will be certain differences in the power consumption generated when the two processors perform task processing.

[0074] Step 203 , with the goal of reducing the state differences between the processors, the state of each processor is adjusted accordingly according to the impact of the state differences between the processors on the bit error rate between the processors.

[0075] It should be noted that when the state differences between processors are large, the bit error rate between processors is high.

[0076] Specifically, since the state difference between processors may include differences in multiple state indicators, such indicators can be called difference indicators. Different difference indicators have different degrees of influence on the bit error rate between processors. Some difference indicators may not have a direct impact on the bit error rate between processors. Some state indicators may have a small degree of difference and may not have a direct impact on the bit error rate between processors. Therefore, the state adjustment plan for each processor can be determined based on the degree of influence of each difference indicator on the bit error rate between processors and the difference of each state indicator reflected by the current state difference between processors, and then the corresponding state adjustment can be performed to reduce the state difference between processors.

[0077] Based on the above embodiment, as an implementable manner, in one embodiment, according to the influence of the state difference between the processors on the bit error rate between the processors, the state of each processor is adjusted accordingly, including:

[0078] Step 2031, estimating the current bit error rate between the processors according to the state difference between the processors;

[0079] Step 2032, determining a processor state adjustment plan for the device to be managed according to the bit error rate estimation results between the processors and the impact of the state difference on the bit error rate between the processors;

[0080] Step 2033: According to the processor state adjustment plan, the state of each processor is adjusted accordingly.

[0081] Specifically, based on the bit error rate detection tool, the current bit error rate between the processors can be estimated according to the state difference between the processors. When the bit error rate prediction result between two processors exceeds a preset threshold, a processor state adjustment plan can be formulated for the two processors according to the impact of various difference indicators in the state difference between the two processors on the bit error rate between the processors, and then the processors can be adjusted accordingly.

[0082] Among them, since the state difference between processors is specifically the state difference between two processors, when a device is equipped with three or more processors, there may be no way to eliminate the impact of the state differences between all processors on the bit error rate between processors at one time. Therefore, after completing a round of processor status, you can return to the step of obtaining the current state information of each processor in the device to be managed to further adjust the state difference between processors until the impact of the state differences between all processors on the bit error rate between processors is completely eliminated, even if the state differences between processors are within a safe range.

[0083] Specifically, in one embodiment, in order to ensure the accuracy of the bit error rate prediction results, a bit error rate prediction model can be constructed according to the relationship between the state difference and the bit error rate between processors; the state difference between the processors is input into the bit error rate prediction model to determine the current bit error rate between the processors based on the bit error rate prediction model.

[0084] It should be noted that when the state differences between processors include three difference indicators: power consumption difference, load power consumption difference and temperature difference, during the equipment factory verification stage, a bit error rate detection tool can be used to detect the relationship between the power consumption difference, load power consumption difference, temperature difference and the bit error rate between processors, and then based on the relationship between the three currently determined difference indicators and the bit error rate between processors, a bit error rate estimation model is constructed, so that the bit error rate estimation model can determine the corresponding bit error rate between processors when the three difference indicators of power consumption difference, load power consumption difference and temperature difference between the two processors are determined.

[0085] Furthermore, in one embodiment, the processor combination to be adjusted can be located based on the bit error rate estimation results between the processors; for each processor combination, the processor state adjustment plan of the processor combination is determined based on the impact of the state difference of the processor combination on the bit error rate between the processors.

[0086] Each processor combination includes two processors.

[0087] Specifically, in one embodiment, the indicator to be adjusted of the processor combination can be determined based on the safety range of various difference indicators represented by the impact of the state difference of the processor combination on the bit error rate between processors; the processor state adjustment plan of the processor combination is determined according to the standard formulated according to the preset processor state adjustment plan based on the indicator to be adjusted of the processor combination.

[0088] Among them, the safety range of each difference indicator may include a maximum power consumption difference, a maximum load power consumption difference, and a maximum temperature difference.

[0089] Exemplarily, when the load power consumption difference of the processor group exceeds the maximum load power consumption difference, the load power consumption difference of the processor group is an indicator to be adjusted, and the processor state adjustment scheme of the processor combination may be to reduce the number of load mounts of the processor with higher load power consumption. In the case of load balancing of the processor group, if the power consumption difference of the processor group exceeds the maximum power consumption difference, the power consumption difference of the processor group is determined as an indicator to be adjusted, and the processor state adjustment scheme of the processor combination may be to migrate the task process of the processor with higher power consumption to another processor. In the case where the processor is a multi-core processor, due to the different task processing capabilities of different processing cores, the processor state adjustment scheme may be to migrate tasks between cores, which can also reduce the total power consumption of the processor. When the temperature difference of the processor group exceeds the maximum temperature difference, the processor state adjustment scheme of the processor combination may be to adjust the speed of the fan at the corresponding position of each processor to reduce the temperature difference of the processor group. Among them, when the load power consumption difference of the processor group exceeds the maximum load power consumption difference, corresponding alarm information may also be generated to remind relevant operators to make corresponding load adjustments to the processor.

[0090] For example, Figure 3 FIG. 1 is a schematic diagram of a structure of an exemplary processor management system provided in an embodiment of the present application. Figure 3 The load in can be devices such as GPU, network card and storage card, and there will be a large amount of data communication between CPUs through high-speed bus interconnection; BMC is a monitoring and management system for equipment, and the processor management method provided in the embodiment of the present application can be deployed in BMC, and the power consumption and temperature of the CPU can be obtained from the CPU through I2C or other buses; BIOS is a basic input and output management system, which can be connected to the CPU through the bus to obtain the load mounting information under the CPU and send this information to the BMC; BMC generates corresponding control instructions based on the information obtained (the current status information of CPU1 and CPU2) to adjust the status of CPU1 and CPU2 accordingly. Among them, the fan controller can adjust the speed of a single fan according to the temperature control instruction of the BMC to increase or decrease the air volume.

[0091] The processor management method provided in the embodiment of the present application obtains the current state information of each processor in the device to be managed; wherein the current state information represents the processor's own working state and load mounting situation; compares the current state information of each processor to obtain the state difference between each processor; with the goal of reducing the state difference between each processor, according to the influence of the state difference between each processor on the bit error rate between processors, the state of each processor is adjusted accordingly. The processor management method provided by the above scheme adjusts the state of the processor with the goal of reducing the state difference between each processor, fundamentally eliminates the factors that cause bit errors between processors, and can significantly reduce the bit error rate between processors in any application scenario, thereby ensuring the stability of multi-processor devices such as high-density servers. In addition, by constructing a bit error rate estimation model according to the relationship between the state difference and the bit error rate between processors, the accuracy of the bit error rate estimation results between processors is improved, laying a foundation for improving the reliability of processor management results.

[0092] An embodiment of the present application provides a processor management device, which is used to execute the processor management method provided in the above embodiment.

[0093] like Figure 4 , which is a schematic diagram of the structure of a processor management device provided in an embodiment of the present application. The processor management device 40 comprises: an acquisition module 401 , a determination module 402 and a management module 403 .

[0094] Among them, the acquisition module is used to obtain the current status information of each processor in the device to be managed; wherein the current status information represents the processor's own working status and load mounting status; the determination module is used to compare the current status information of each processor to obtain the status difference between the processors; the management module is used to reduce the status difference between the processors as the goal, and adjust the status of each processor accordingly according to the impact of the status difference between the processors on the bit error rate between the processors.

[0095] Specifically, in one embodiment, the management module is specifically used to:

[0096] According to the status differences between the processors, the current bit error rate between the processors is estimated;

[0097] Determine a processor status adjustment plan for the device to be managed based on the bit error rate estimation results between the processors and the impact of the status differences on the bit error rate between the processors;

[0098] According to the processor state adjustment plan, the state of each processor is adjusted accordingly.

[0099] Specifically, in one embodiment, the management module is specifically used to:

[0100] According to the relationship between the state difference and the bit error rate between processors, a bit error rate estimation model is constructed;

[0101] The state differences between the processors are input into a bit error rate prediction model to determine the current bit error rates between the processors based on the bit error rate prediction model.

[0102] Specifically, in one embodiment, the managed module is specifically used to:

[0103] Locate the processor combination to be adjusted based on the bit error rate estimation results between the processors;

[0104] For each processor combination, a processor state adjustment scheme of the processor combination is determined according to the influence of the state difference of the processor combination on the bit error rate between the processors.

[0105] Specifically, in one embodiment, the management module is specifically used to:

[0106] Determine the indicator to be adjusted of the processor combination according to the safety range of various difference indicators represented by the influence of the state difference of the processor combination on the bit error rate between the processors;

[0107] A standard is formulated according to a preset processor state adjustment scheme, and a processor state adjustment scheme of the processor combination is determined according to the to-be-adjusted index of the processor combination.

[0108] Specifically, in one embodiment, the current state information of the processor includes at least one of power consumption information, load mounting information, and temperature of the processor.

[0109] Specifically, in one embodiment, the state difference between the processors includes at least one of a power consumption difference, a load power consumption difference, and a temperature difference.

[0110] Regarding the processor management device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0111] The processor management device provided in the embodiment of the present application is used to execute the processor management method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0112] An embodiment of the present application provides an electronic device for executing the processor management method provided in the above embodiment.

[0113] like Figure 5 FIG. 5 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 50 includes: at least one processor 51 and a memory 52.

[0114] The memory stores computer-executable instructions; at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the processor management method provided in the above embodiment.

[0115] An electronic device provided in an embodiment of the present application is used to execute the processor management method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0116] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, a processor management method provided in any of the above embodiments is implemented.

[0117] The storage medium containing computer executable instructions in the embodiment of the present application can be used to store computer executable instructions of the processor management method provided in the aforementioned embodiment. Its implementation method and principle are the same and will not be repeated here.

[0118] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0121] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0122] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A processor management method, characterized in that: include: Obtaining current status information of each processor in the device to be managed; wherein the current status information represents the working status and load mounting status of the processor itself; Comparing the current status information of each of the processors to obtain the status difference between the processors; With the goal of reducing the state difference between the processors, the state of each processor is adjusted accordingly according to the influence of the state difference between the processors on the bit error rate between the processors; The step of adjusting the state of each processor accordingly according to the influence of the state difference between the processors on the bit error rate between the processors includes: estimating the current bit error rate between the processors according to the state difference between the processors; Determine a processor state adjustment plan for the device to be managed according to the bit error rate estimation results between the processors and the impact of the state difference on the bit error rate between the processors; According to the processor state adjustment scheme, the state of each processor is adjusted accordingly.

2. The method according to claim 1, characterized in that The estimating the current bit error rate between the processors according to the state difference between the processors includes: According to the relationship between the state difference and the bit error rate between processors, a bit error rate prediction model is constructed; The state differences between the processors are input into the bit error rate prediction model to determine the current bit error rates between the processors based on the bit error rate prediction model.

3. The method according to claim 1, characterized in that The step of determining a processor state adjustment scheme for the device to be managed according to the bit error rate estimation results between the processors and the influence of the state difference on the bit error rate between the processors includes: Locating a processor combination to be adjusted according to a bit error rate estimation result between the processors; For each of the processor combinations, a processor state adjustment scheme for the processor combination is determined according to the impact of the state difference of the processor combination on the bit error rate between processors.

4. The method according to claim 3, characterized in that The step of determining a processor state adjustment scheme for the processor combination according to the influence of the state difference of the processor combination on the bit error rate between processors includes: Determining the indicator to be adjusted of the processor combination according to the safety range of various difference indicators represented by the influence of the state difference of the processor combination on the bit error rate between processors; A processor state adjustment scheme is formulated according to a preset processor state adjustment scheme standard, and a processor state adjustment scheme for the processor combination is determined according to the to-be-adjusted index of the processor combination.

5. The method according to claim 1, characterized in that The current state information of the processor includes at least one of power consumption information, load mounting information and temperature of the processor.

6. The method according to claim 5, characterized in that The state difference between the processors includes at least one of a power consumption difference, a load power consumption difference and a temperature difference.

7. A processor management device, characterized in that: include: An acquisition module, used to acquire current status information of each processor in the device to be managed; wherein the current status information represents the working status and load mounting status of the processor itself; A determination module, used for comparing the current status information of each of the processors to obtain the status difference between the processors; A management module, configured to adjust the state of each processor accordingly according to the influence of the state difference between each processor on the bit error rate between processors with the goal of reducing the state difference between each processor; The management module is specifically used for: estimating the current bit error rate between the processors according to the state difference between the processors; Determine a processor state adjustment plan for the device to be managed according to the bit error rate estimation results between the processors and the impact of the state difference on the bit error rate between the processors; According to the processor state adjustment scheme, the state of each processor is adjusted accordingly.

8. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the method according to any one of claims 1 to 6 is implemented.

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