Peak power management in memory devices

Abstract

The present disclosure relates to peak power management in memory devices. Various applications may include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies the start of a cache operation performed on data, and a second flag from the data path identifies the end of the cache operation. A controller for peak power management may be implemented to control the power budget based on a use of current associated with the cache determined according to the first and second flags. In various embodiments, the controller is operable to feed a signal back to a memory controller external to the memory die to adjust the operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory devices and the operation of memory devices, and more particularly, to power budgeting of memory devices. Background Art

[0002] Memory devices are typically provided as internal circuits, semiconductor circuits, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint TM Memory, etc.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single-transistor, floating gate, or charge-trap memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named for the logical form in which the basic memory cell configuration of each is arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series in a source-to-drain manner between a source line and a data line.

[0004] In some NAND memory dies, peak power management (PPM) logic is implemented to control peak power consumption in the memory die. Existing PPM designs focus on memory array operations, such as erasing, programming the array, reading the array, or independent word line reads (iWLs). These designs do not consider the current in cache operations of the cache used in the data path to or from the memory array along with the memory array operations, such as reading data patterns from the cache and writing data patterns to the cache. In conventional practice, sufficient budget is reserved only for cache operations, which reduces the efficiency of NAND memory array operations. For example, in a universal flash storage (UFS) device implementation, 20% to 50% of the 800mA system budget may be allocated to NAND cache operations without considering the actual current usage of the cache operations. Summary of the Invention

[0005] In one aspect, the present disclosure relates to a memory device comprising: a memory die including: a memory array; a cache to store data in a data path leading to or originating from the memory array; and a controller including processing circuitry including one or more processors, the controller configured to perform operations including controlling a power budget for the cache and the memory array by using a first flag received from the data path to identify the start of a cache operation on the data and a second flag received from the data path to identify the end of the cache operation.

[0006] On the other hand, the present disclosure relates to a memory device comprising: an input node that receives a power supply voltage; and a plurality of memory dies coupled to the input node to form a peak power management group, wherein each memory die of the plurality of memory dies includes: a memory array; a cache for storing data in a data path leading to or starting from the memory array; a controller that includes a processing circuit system, the processing circuit system including one or more processors, the controller being configured to perform operations comprising: controlling a power budget for the cache and the memory array by using a first flag received from the data path that identifies the start of a cache operation performed on the data and a second flag received from the data path that identifies the end of the cache operation; and a connector that outputs data about the power budget to one or more other memory dies in the peak power management group.

[0007] In yet another aspect, the present disclosure relates to a method of controlling peak power management in a memory device, the method comprising: monitoring a data path leading to or starting from a memory array of a memory die, the data path including a cache for storing data; using a first flag received from the data path at a logic circuit system of the memory die to identify the start of a cache operation performed on the data; using a second flag received from the data path at the logic circuit system of the memory die to identify the end of the cache operation; and using the start and end of the cache operation in the logic circuit system of the memory die to control a power budget for the cache and the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings, which are not necessarily drawn to scale, generally illustrate various embodiments discussed in this document by way of example and not by way of limitation.

[0009] Figure 1 An example relationship of a memory device package to a system power management integrated circuit that provides a supply voltage to the memory device package via a system printed circuit board is shown in accordance with various embodiments.

[0010] Figure 2 An example memory die is shown coupled to a processing device via an interface in accordance with various embodiments.

[0011] Figure 3 is an example functional representation of peak power management for a current budget that considers the current budget of a cache associated with memory array operations along with the current budget of memory operations of a memory die in accordance with various embodiments.

[0012] Figure 4 An example use of a delay filter to maintain the current budget of a memory die is shown according to various embodiments.

[0013] Figure 5 An example memory die is shown coupled to a processing device via an interface and feedback connections in accordance with various embodiments.

[0014] Figures 6 to 8 Example feedback nodes for feeding back signals from a memory die to a processing device along a feedback connection are shown according to various embodiments.

[0015] Figure 9 is a block diagram illustrating an example memory controller external to a group of memory dies, wherein the memory controller is arranged to receive feedback signals from one or more of the memory dies, according to various embodiments.

[0016] Figures 10 to 13Example uses of an indicator signal or signals from a ready / busy pad of a memory die to stall output of data from a processor device's interface to the memory die are shown for cache current and memory array operation according to various embodiments.

[0017] Figure 14 is a flow chart of an example method of controlling peak power management in a memory device according to various embodiments.

[0018] Figure 15 A block diagram illustrating an embodiment of an example machine having one or more memory devices constructed with memory dies having logic management for peak power management in accordance with various embodiments. DETAILED DESCRIPTION

[0019] The following detailed description refers to the accompanying drawings that illustrate various embodiments that may be implemented. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be construed in a limiting sense.

[0020] Both NOR and NAND flash architecture semiconductor memory arrays of flash memory devices are accessed through a decoder that activates a specific memory cell by selecting the access line (WL) coupled to the gate of the specific memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on the data line, causing different currents to flow depending on the programmed state of the specific cell. In a NAND architecture semiconductor memory array, a relatively high bias voltage is applied to the drain-side select gate (SGD) line. The access line coupled to the gates of the unselected memory cells of each group is driven with a designated pass voltage (e.g., Vpass) to cause the unselected memory cells of each group to operate as pass transistors (e.g., pass current in a manner unconstrained by their stored data values). Current then flows in the line between the source line and the data line through each series-coupled group, constrained only by the selected memory cell of each group, thereby placing the current-encoded data value of the selected memory cell on the data line.

[0021] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), thereby representing one bit of data. Flash memory cells can also represent more than two programming states, allowing the manufacture of higher density memories without increasing the number of memory cells because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some instances, MLCs have been referred to as memory cells that can store two bits of data per cell (e.g., one of four programming states). MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programming states). Memory cells that can store two bits of data per cell (e.g., one of four programming states) may be referred to herein as dual-level cells (DLCs). Triple-level cells (TLCs) may refer to memory cells that can store three bits of data per cell (e.g., one of eight programming states). Quad-level cell (QLC) can store four bits of data per cell, and penta-level cell (PLC) can store five bits of data per cell.

[0022] In various embodiments, the PPM logic of a memory die, such as a NAND memory die, can be configured to consider and manage the current usage of cache operations as well as the current usage of memory operations. Considering the current usage of cache operations can provide enhanced operation of the memory die because the portion of cache operations that uses current along the data path is powered by the power supply voltage Vcc, which also supplies current to the memory array operations. The current budget associated with the common power supply that can be allocated for peak budgeting is shared by cache operations and memory array operations.

[0023] When data path speeds increase to 1200MT / s, 1600MT / s, or even higher, cache operations are non-negligible. For example, the write data cache current with four data channels (ICC4W) can be 92mA at 1600MT / s, while it can be 52mA at 800MT / s. The read data cache current with four data channels (ICC4R) can be 152mA at 1600MT / s, while it can be 82mA at 800MT / s. The clear trend is to increase the use of supply current (ICC) in cache operations. For example, for the above current values ​​for a UFS system with a peak power budget of 800mA in a mobile distribution with respect to the Vcc power rail of the UFS system, the ICC cache current is close to 20% of the peak power budget.

[0024] In conventional NAND designs, there is a trend to move the data path from the Vccq power supply to the Vcc power supply via power rail switches to address reliability issues and achieve fast transistor performance without expensive transistor improvements. Vcc is the power supply voltage for the core of the memory die, and Vccq is the power supply voltage for the inputs and outputs (I / O) of the memory die. This trend can also stress the Vcc power rail peak power budget, which can result in moving additional ICCQ4W and ICCQ4R into the ICC budget. For example, an ICCQ4W with four channels can rise to 164mA at 1600MT / s, while an ICCQ4R with four channels can rise to 360mA at 1600MT / s. Again, assuming an 800mA peak power budget for a UFS system, this indicates a trend where the additional cache current is approximately 45% of the UFS system peak power budget.

[0025] Conventional system designs reserve current for cache operations from the total peak power budget. For example, 100 mA might be reserved from the total budget for a four-channel device, with only 100 mA of the total budget allocated to the PPM manager in the NAND memory die. This approach still works for a four-channel memory running at 800 MT / s, because, for example, 100 mA is only 12.5% ​​of the 800 mA total budget, making PPM effective for a 700 mA budget running four to eight active memory dies. In another case, the total cache current might be 50% of the system peak power budget. However, if the cache current is 50% of the system peak power budget, PPM can be problematic. The period of cache current operation is short for most array operations, for example, on the order of 10 μs, but can be tens or hundreds of microseconds depending on the speed. If the system design reserves 50% of the cache current budget, it makes PPM ineffective, while the associated cache operation time is only about 10 μs. By preserving the cache current budget, PPM will waste a large amount of the budget due to the short cache operation time.

[0026] In various embodiments, a method for managing a power budget may include executing a program for managing cache operations in PPM logic of a memory die in conjunction with management operations of a memory array of the memory die. The program may include accounting for current in the data path used for write or read cache operations by the PPM logic to increase PPM efficiency in the memory die. In various embodiments, the PPM manager may be configured to monitor key circuit blocks or a command state machine to detect the start and end of cache write operations in the data path for writes. Additionally, the PPM manager may be configured to monitor key circuit blocks or a command state machine to detect the start and end of cache read operations for reads. Critical signals may be monitored, detected, or sent to the PPM manager of the memory die and used to participate in budget reservation and PPM policies for the memory die. For memory dies arranged together in a PPM group, the memory dies in the PPM group can effectively use the entire peak power budget.

[0027] Figure 1 An embodiment is shown of an example relationship of a memory device package 103 to a system power management integrated circuit (PMIC) 101, which provides Vcc to the memory device package 103 via a system printed circuit board (PCB) 102. The memory device package 103 includes memory dies 105-1, 105-2, 105-3, 105-4, 105-5, 105-6, 105-7, and 105-8 located on a substrate 104, which can serve as an internal PCB in the package. Although eight memory dies are shown, the memory device package can include more or fewer than eight memory dies. The memory dies 105-1, 105-2, 105-3, 105-4, 105-5, 105-6, 105-7, and 105-8 can be arranged in two layers or groups of memory dies. A first group may include memory dies 105-1, 105-2, 105-3, and 105-4 coupled to substrate 104 through wire bonds, such as wire bond 114-1, where substrate 104 provides electrical conductivity to system PCB 102. Wire bonds, such as wire bond 114-1, may provide a channel for operation of memory dies 105-1, 105-2, 105-3, and 105-4. A second group may include memory dies 105-5, 105-6, 105-7, and 105-8 coupled to substrate 104 through wire bonds, such as wire bond 114-2, where substrate 104 provides electrical conductivity to system PCB 102. Wire bonds, such as wire bond 114-2, may provide another channel for operation of memory dies 105-5, 105-6, 105-7, and 105-8. Figure 1In some examples, the memory device package of the memory die has two channels that can operate in parallel. In other examples, the stacked memory devices can be interconnected via through-substrate vias ("TSVs"), where selected dies in the stack are connected to operate as separate channels. In some such examples, the stacked die TSVs can connect to contacts on or within the substrate 104, or to a logic interface die (or assembly) between the substrate 104 and the stacked die.

[0028] Vcc is supplied to memory dies 105-1, 105-2, 105-3, 105-4, 105-5, 105-6, 105-7, and 105-8. Current for cache and memory operations performed on each of the memory dies 105-1, 105-2, 105-3, 105-4, 105-5, 105-6, 105-7, and 105-8 is provided by the Vcc external pads and Vcc wire bonds, which are resistive sources. Due to such resistance, a voltage drop may exist between cascades of memory dies, which may affect the current available for cache and memory array operations of memory dies at different cascade levels. Management of the current budget among the memory dies 105-1, 105-2, 105-3, 105-4, 105-5, 105-6, 105-7, and 105-8 may be handled by PPM logic management on each memory die to share the current budget among the memory dies.

[0029] Figure 2 An embodiment of an example memory die 205-1 is shown coupled to a processing device 210 via an interface 215. The memory die 205-1 is also coupled to another memory die 205-N. Although not shown, the memory die 205-1 may be coupled to other memory dies. These memory dies may be NAND memory dies, where the interface 215 is an Open NAND Flash Interface (ONFI). The memory die 205-1, the memory die 205-N, and the other memory dies coupled to the memory die 205-1 may be arranged in a memory device package, such as Figure 1 Memory device package 103. For ease of discussion of memory die 205-1, Figure 2 2. The memory device package is not shown in FIG. Processing device 210 may be external to the memory device package containing memory die 205-1. Processing device 210 may include processing circuitry having one or more processors, wherein processing device 210 is configured to perform operations to write to and read from memory die 205-1 and other memory dies associated with memory die 205-1. Processing device 210 may face a user device to interact with memory die 205-1 and other memory dies associated with memory die 205-1.

[0030] Memory die 205-1 may include, among other components, deserializer circuitry 206, page buffer 208, memory array 212, memory controller 230 associated with instructions 232, circuitry 233 coupling memory array 212 to memory controller 230, sense amplifier 209, serializer circuitry 207, timing logic 211, PPM logic management 220-1 with controller 222-1 and associated instructions 224-1. Circuitry 233 may be implemented using CMOS (complementary metal oxide semiconductor) circuitry or its equivalent. To facilitate discussion of the components and functionality used to control the current budget for cache operations and memory array operations of memory die 205-1, other components of memory die 205-1 are not shown. Components and functionality controlling the control budget may be implemented with PPM logic management 220-1.

[0031] In addition to controller 222-1 and instructions 224-1, PPM logic management 220-1 may also include logic circuits and registers. The logic circuits and registers may be used to receive signals from other components of memory die 205-1. Controller 222-1 may include processing circuitry, including one or more processors, and may be configured to perform peak power management operations for memory die 205-1 by executing instructions 224-1. Operations performed by PPM logic management 220-1 may include communicating current budgets with other PPM logic management components of other memory dies in a memory device package containing memory die 205-1. For example, memory die 205-N may include controller 222-N and instructions 224-N that may operate similarly to controller 222-1 and instructions 224-1 of memory die 205-1. Controller 222-1 may be a dedicated controller for PPM logic management 220-1. Alternatively, controller 222-1 may be a controller for memory die 205-1 that handles the operation of memory array 212 using instructions 224-1 dedicated to performing peak power management on memory die 205-1. PPM logic management 220-1 may be a dedicated state machine that handles all PPM related items.

[0032] For write operations to the memory array 212 of the memory die 205-1, data received as serial data from the interface 215 at the deserializer circuitry 206 is output as parallel data on a data path to the page buffer 208 for programming the memory array 212. Additional circuitry may be located along the data path from the deserializer circuitry 206 to the page buffer 208. Compared to the propagation speed within the memory die 205-1, the memory array 212 programming speed is relatively slow. In addition, if the memory array 212 is arranged as a memory array with MLC, programming the memory array 212 involves more operations. To address the complexity of programming data into the memory array 212, data is received and stored in the page buffer 208 while other data is loaded into the memory array 212. The page buffer 208 provides a cache to allow additional data to be loaded before the data is transferred for the next time the data is programmed into the memory array 212, thereby enhancing performance. Associated with the cache operation of page buffer 208 is current consumption using power supplied to memory die 205 - 1 using Vcc.

[0033] For read operations from memory array 212 of memory die 205-1, data is provided from memory array 212 to sense amplifier 209. When data is loaded from memory array 212, the data is stored in sense amplifier 209. Sense amplifier 209 provides a cache to allow data to be collected from memory die 205-1 before the data is transferred. The data loaded into sense amplifier 209 is sent to serializer circuitry 207, which can serialize the data for output to interface 215. Additional circuitry can be located along the data path from sense amplifier 209 to serializer circuitry 206. Associated with the caching operation of sense amplifier 209 is the current consumption of the power provided to memory die 205-1.

[0034] For write and read cache operations, a command state machine or circuitry along the data path between interface 215 and memory array 212 can provide signals to be monitored by PPM logic management 220-1. The use of signals regarding write and read cache operations within memory die 205-1 provides a mechanism for communicating information about current usage during write and read cache operations to PPM logic management 220-1. PPM logic management 220-1 can update parameters used by it based on current usage and update the status of cache operations and memory array operations. PPM logic management 220-1 can be implemented as predictive peak power manager (pPPM) logic management. Digital pPPM is a mechanism for tracking peak power consumption by the controller / firmware / logic and providing an emphasis on the efficiency of the controller / firmware / logic. The use of the pPPM feature can be implemented in a multi-die configuration, where various operations are run simultaneously on multiple dies. The pPPM manager can communicate within the memory die and suspend operations or reach a low peak power mode if the total peak power is greater than expected. The PPM logic management 220-1 can communicate with other memory dies, such as the memory die 205-N, to share information about the current budget for cache and memory array operations. Based on the updated current budget using the signal, the PPM logic management 220-1 can provide feedback to the memory controller 230 to control write and read operations within the memory array 212.

[0035] For write cache operations, for example, deserializer circuitry 206 can be used to identify the start of a write cache operation, and page buffer 208 can be used to identify the end of a write cache operation. Identification of a first specified event in the timing pattern input to deserializer circuitry 206 can be used to generate a signal along path 216 from deserializer circuitry 206 to PPM logic management 220-1. This signal provides a first flag received from the data path identifying the start of a write cache operation performed on the data of a write operation. Identification of a second specified event in the timing pattern input to page buffer 208 can be used to generate a signal along path 218 from page buffer 208 to PPM logic management 220-1. This signal provides a second flag received from the data path identifying the end of a write cache operation performed on the data of a write operation. Comparison circuitry can be used to identify the occurrence of the first and second specified events. By providing signals along path 221 to PPM logic management 220-1, timing logic 211 of memory die 205-1 can serve as a monitor for cache operations. Timing logic 211 can be used to identify the interface timing pattern for data input in write cache operations. Alternatively, command state machine 213 can be used as a monitor for cache operations by providing signals along path 223 to PPM logic management 220-1. Determining the start and stop of write operations is not limited by the use of deserializer circuitry 206 and page buffer 208. Other circuits in the data path from interface 215 to memory array 212 can be used to participate in PPM of memory die 205-1.

[0036] For read cache operations, for example, sense amplifier 209 can be used to identify the start of a read cache operation, and serializer circuitry 207 can be used to identify the end of a read cache operation. Identification of a first designated event in the timing pattern input to memory die 205-1 can be used to generate a signal along path 219 from sense amplifier 209 to PPM logic management 220-1. This signal provides a first flag received from the data path identifying the start of a read cache operation performed on the data of a read operation. Identification of a second designated event in the timing pattern input to memory die 205-1 can be used to generate a signal along path 217 from serializer circuitry 207 to PPM logic management 220-1. This signal provides a second flag received from the data path identifying the end of a read cache operation performed on the data of a read operation. Comparison circuitry can be used to identify the occurrence of the first and second designated events. By providing a signal along path 221 to PPM logic management 220-1, timing logic 211 of memory die 205-1 can serve as a monitor for cache operations. Timing logic 211 can be used to identify the interface timing mode for data output in read cache operations. Alternatively, command state machine 213 can be used as a monitor for cache operations by providing signals along path 223 to PPM logic management 220-1. Determining the start and stop of read operations is not limited by the use of sense amplifier 209 and serializer circuitry 207. Other circuits in the data path from memory array 212 to interface 215 can be used to participate in PPM of memory die 205-1.

[0037] PPM management logic 220-1 uses flags for write cache operations and read cache operations as a determination of the current being used during the corresponding cache operation. The amount of current used during the identified cache operation can be considered a fixed amount stored or hard-coded in PPM management logic 220-1. Alternatively, a lookup table accessed by PPM management logic 220-1 can be used, where the lookup table has current values ​​based on the programmed timing mode or speed of the data path for the corresponding write or read cache operation. When generating a flag for a cache operation, a value in the lookup table can be selected using a signal from timing logic 211.

[0038] In addition to receiving flags from the data path during cache operations associated with operating the memory array 212, the PPM management logic 220-1 also receives information about the memory array operation from the memory controller 230. Using the received flags and the information received from the memory controller 230, the PPM management logic 220-1 can monitor operations associated with the memory array 212 and the page buffer 208 during write operations, and monitor operations associated with the memory array 212 and the sense amplifier 209 during read operations, and calculate the total peak power used by the memory array and the corresponding cache. This total peak power can be calculated in terms of current. This can avoid activities associated with a separately reserved current budget for caching by external user devices to the memory device.

[0039] Cache operations and memory array operations can be performed simultaneously. Because memory die 205-1 has a constant Vcc provided during operation of memory die 205-1, peak current is a parameter to be managed according to a budget. During programming of memory array 212, pulses are used with periods of relatively high current and periods of relatively low current. Considering the total current of cache operations and memory array operations, PPM logic management 220-1 on memory die 205-1 can use high current peak times and low current peak times to stagger when allowing data to be moved within memory array 212. PPM logic management 220-1 communicates with memory controller 230 to control the staggering or pausing of data movement within memory array 212.

[0040] Memory controller 230 may include processing circuitry, including one or more processors, and may be configured to perform operations on memory array 212 by executing instructions 232. Memory controller 230, with instructions 232, may be configured as firmware for memory die 205-1 to control the functions of memory array 212. Memory controller 230 may be a dedicated programmable controller operating as firmware, or it may be a main memory controller for memory die 205-1, executing operations according to instructions 232. Firmware code in programmable memory controller 230 is used to implement array read and program operations, making requests to the PPM logic management state machine before entering "high current peak" operation. PPM logic management 220 confirms or places operations in a pending state based on the overall system current budget, which may include the current budgets of other memory dies arranged in a memory device package along with memory die 205-1. In other examples, at least some portions of the instructions executed by memory controller 230 may be stored in other memory structures and loaded, for example, into local memory of memory controller 230 for execution. The memory controller 230 waits until it receives a signal from the PPM logic management 220-1 to proceed before executing the code in the instruction 232, which causes an ICC spike in the memory array operation of the memory die 205-1.

[0041] Figure 3 1 is an embodiment of an example functional representation of a current budget for peak power management that considers the current budget of a cache associated with memory array operations along with the current budget of memory array operations of a memory die such as memory die 305-1. Memory die 305-1 may include PPM logic management 320-1 having a controller 322-1 and associated instructions 324-1. Memory die 305-1 may be associated with Figure 2 The memory die 205 - 1 has the same or similar structure. Figure 3 The operation of two caches is shown, where one cache is used for write operations and the other cache is used for read operations.

[0042] During a write operation, a timing signal is received from interface 315, wherein the timing signal includes a write preamble and a write postamble, wherein the data path is busy between the start of the write preamble and the end of the write postamble. This indicates a period of active write cache operation. The start of the write preamble can be used to provide a detection signal to send a write flag to identify the start of the write cache operation to set up monitoring of the cache operation. The end of the write postamble can be used to send a write flag to identify the end of the write cache operation to reset monitoring of the cache operation for the next write flag to set up monitoring of the cache operation.

[0043] During a read operation, a timing signal is sent to the interface 315, wherein the timing signal includes a read preamble and a read postamble, wherein the data path is busy between the start of the read preamble and the end of the read postamble. This indicates a period of active read cache operation. The start of the read preamble can be used to provide a detection signal to send a read flag to identify the start of the read cache operation to set up monitoring of the cache operation. The end of the read postamble can be used to send a read flag to identify the end of the read cache operation to reset monitoring of the cache operation for the next read flag to set up monitoring of the cache operation.

[0044] PPM logic management 320-1 may include a filter 325-1 for receiving a write flag for a set operation and a write flag for a reset operation, as these flags are generated by detecting appropriate signals on the data path for write operations. PPM logic management 320-1 may also include a filter 325-2 for receiving a read flag for a set operation and a read flag for a reset operation, as these flags are generated by detecting appropriate signals on the data path for read operations. Filters 325-1 and 325-2 may be implemented as a single filter with inputs from the data path for write operations and inputs from the data path for read operations. Filters 325-1 and 325-2 may use the received flags to avoid frequent cache operation power budget releases that could affect PPM budget allocation efficiency. Filters 325-1 and 325-2 may have timers 326-1 and 326-2, respectively, configured to release the previous cache operation budget only when the timer reaches its filter time, without a new cache operation occurring. As an example, the filter time may be, but is not limited to, approximately 10 μs.

[0045] In addition to receiving flags from the data path in connection with cache operations associated with operating the memory array of memory die 305-1, PPM logic management 320-1 also receives information regarding memory array operations from memory controller 330. Memory controller 330 may include processing circuitry, including one or more processors, and may be configured to perform operations on the memory array of memory die 305-1 by executing instructions 332. Memory controller 330, with instructions 332, may be configured as firmware for memory die 305-1 to control the functions of the memory array of memory die 305-1. Memory controller 330 may be a dedicated programmable controller to operate as firmware, or may be a primary memory controller for memory die 305-1 to perform operations according to instructions 332. Using the received flags and the information received from the memory controller 330, the PPM logic management 320-1 can monitor operations associated with the memory array and cache of the memory die 305-1 during write and read operations associated with the memory array and calculate the total peak power used by the memory array and the corresponding cache. This total peak power can be calculated in terms of current.

[0046] Memory die 305-1 can operate with several, N, other memory dies in a memory device package to share the total ICC budget provided to the memory die. These other memory dies, such as memory die 305-N, can be identical or similar in structure to memory die 305-1. Memory die 305-N can include a controller 322-N and associated instructions 324-N and can be operated to perform the same or similar functions on memory die 305-N as those performed by memory die 305-1. The memory dies sharing the total ICC budget form a PPM group. The PPM group operates with each of memory dies 305-1 ... 305-N coupled to a communication bus HC and an internal clock line ICLK in the memory device package. These memory dies can be NAND memory dies, with interface 315 being an interface constructed according to the ONFI specification.

[0047] Controllers 322-1...322-N of PPM logic management 320-1...320-N can execute instructions to respectively execute instructions 324-1...324-N to perform PPM operations, including features related to the total ICC budget of the PPM group. PPM features may include avoiding exceeding the total ICC budget in a multi-memory die configuration. Each memory die 305-j of memory dies 305-1...305-N can communicate to other memory dies within the same package via its PPM logic management 320-j coupled to the HC, the ICC value consumed within memory die 305-j, where 1≤j≤N. Multiple bits, such as, but not limited to, serial bits, can be used to represent the consumed ICC. For example, three serial bits can be used to represent the ICC. The number of bits can be more or less than three. Each of the memory dies 305 - 1 . . . 305 -N, via its respective PPM logic management, can store the ICC value transferred by another memory die to track the total ICC at the system level defined by the multiple memory dies.

[0048] Communication among the memory dies 305-1...305-N of a PPM group can utilize a round-robin token protocol. The use of ICLK during communication can be driven by one of the memory dies 305-1...305-N configured as a manager memory device. The ICLK can be driven by the manager memory die to synchronize all memory dies in the PPM group. Setting one of the memory dies 305-1...305-N as a manager memory device can be performed by a processing device external to the memory dies 305-1...305-N. Each of the memory dies 305-1...305-N has its own PPM logic management 320-1...320-N, which manages the ICC values ​​for all memory dies in the PPM group. In response to one of the memory dies 305-1...305-N determining that the available ICC budget is insufficient to execute cache or memory operations within the full peak ICC budget, the PPM logic management of that memory die can suspend the associated cache or memory operations. Alternatively, if a reduced ICC budget is available, then the PPM logic management of one memory die may allow for the performance of a reduced ICC phase.All memory dies 305-1...305-N may perform such ICC budget operations.

[0049] Figure 4 An embodiment showing an example use of a delay filter to maintain the current budget of a memory die is shown. Figure 3Filters 325-1 and 325-2 can be used to implement a delay filter. The delay filter can be used to avoid frequent release of the power budget for cache operations, which can affect the efficiency of PPM budget allocation. If the delay filter has a timer set to some value, such as, but not limited to, 10 μs, the previous cache operation budget can be controlled so that it is only released when the timer reaches the set time, and no new cache operation occurs. Segment 431, showing the timing pattern, is for an existing PPM budget allocated for cache operations. In segment 432, PPM logic manages the budget, which can be retained for the length of time set by its filter timer. Segment 433 shows cache operations being resumed based on their retained budget.

[0050] In data transfers, the transfer may pause and start multiple times, for example by the host stopping providing data to the memory die and then starting again. The filter can provide a clear time delay that acts as a mechanism to appear that data is still being transferred when it could actually be paused. The filter acts as a glitch filter that filters out glitches in the data transfer, eliminating pauses so that the current budget can be more smoothly controlled. Figure 4 The filter adds some clear time to the data from segment 431 to the data from segment 433. In segment 432, during the period t RHW and t CCS There is a pause or gap in the memory. Because the physical transmission stops during this time, it is necessary to preserve this budget, which can be achieved by the interference filter. Preserving this budget provides a mechanism that prevents other memory dies from using this budget.

[0051] To achieve better quality of service (QoS), read / write cache operations can be given the highest priority, including higher priority than NAND array operations. Because data cache read / write commands are based on nanoseconds, even if the operation takes 10 μs, QoS may not simply rely on traditional budget applications in microseconds. In various embodiments, the PPM logic management can internally reserve a specific budget for cache operations. For example, to have a one-channel ICC4R budget, which can be worst-case and greater than ICC4W, (360 mA + 82 mA) / 4 = 110.5 mA can be reserved for the next cache operation, allowing the NAND memory die to respond immediately to requests without exceeding the budget. Once a cache operation occurs and uses the reserved budget, the PPM logic management can continue to reserve one channel ICC4R for the next cache operation. The PPM logic management can maintain a one-channel cache operation budget for fast response. Based on the usage model of the memory system, this PPM internal budget reservation procedure can be tuned for fast response.

[0052] Additionally, if one channel's reserve budget is insufficient, cache busy time can be delayed to accommodate power budget. While cache busy time is typically short, such as 10 μs, timing signals can be delayed to align with the peak power budget until PPM power budget exists to allow cache operations to proceed. Control signals from the memory die's PPM logic can be used to pause sense amplifiers during read cache operations and page buffers during write cache operations based on the priority of operations required by the PPM logic. For example, if the system performance budget is impacted, delaying sensing or programming can have little or no benefit to cache timing. In some cases, delayed cache transfers can be performed to provide PPM budget to allow memory array operations to proceed.

[0053] In various embodiments, peak power management is provided to memory die cache operations across channels. Taking cache current operation into account can help improve PPM efficiency and ameliorate efficiency issues associated with increasing data path speeds and power rail switching. This approach can take into account future changes in memory die cache usage, such as NAND memory cache usage, where the characteristics of cache operations are moving toward large cache currents that can be 50% of the system ICC peak power budget with fast operation times, such as on the order of 10 μs, compared to memory array operations. An improved PPM design that manages memory die cache operations as well as memory array operations of a memory die can address the inefficiencies of conventional approaches associated with increased memory die cache frequencies and switching power rails from Vccq to Vcc data paths.

[0054] In various embodiments, PPM logic management can be structured to manage cache operations in memory dies and memory array operations of the memory dies, and can be structured to provide feedback to the system memory controller based on the PPM logic management of the current budget to slow down the operating frequency of the interface coupling the system memory controller to the memory dies. If the total peak power budget calculated by the PPM would exceed the system peak power budget, the operating frequency of the interface can be reduced to reduce the current operation of the cache of the memory die. The memory die can be a NAND memory die, wherein the interface is an interface constructed according to the ONFI specification. The memory dies in the PPM group can continue to cache at a low ONFI frequency during write operations to the cache of the NAND memory die. During write operations to the NAND cache, write cache slowdown is acceptable and does not adversely affect system performance.

[0055] The cache operation of a NAND memory die handles current almost linearly with respect to the ONFI data burst frequency. For interfaces operating according to the ONFI specification, the ONFI data burst frequency refers to the switching frequency of the data strobe (DQS) as a function of the clock. This frequency depends on the timing mode in which the system memory controller is operating. Methods for managing the current budget may include combining features with at least one frequency operating with respect to the interface frequency. First, as discussed above, NAND cache operations may be incorporated into a NAND PPM management scheme with memory array operations, allowing the memory array operations and cache operations to share the total peak power budget for more efficient system peak power control without significant performance penalties. A second feature may include hardware feedback to the system memory controller to automatically slow down or speed up the ONFI data burst frequency of the system memory controller. The feedback signal may be provided by using existing NAND memory die pads, such as ZQ pads, which provide for I / O impedance (Z) calibration. Feedback signals can be provided using the RB pads of the NAND memory die, which provide pins for ready / busy outputs that indicate the status of device operation. Feedback signals can be provided by creating new pads for the NAND memory die to feedback only high and low states. The feedback signal can be provided by an analog voltage based on the ONFI frequency suggested by the NANDPPM logic management. The system memory controller's internal ONFI frequency generator can be tuned using this hardware channel feedback.

[0056] Figure 5 An embodiment of an example memory die 505-1 is shown coupled to a processing device 510 via an interface 515 and a feedback connection 528. The memory die 505-1 may also be coupled to another memory die 505-N. Although not shown, the memory die 505-1 may be coupled to other memory dies. These memory dies may be NAND memory dies, where the interface 515 is an interface constructed according to the ONFI specification. The memory die 505-1, the memory die 505-N, and the other memory dies coupled to the memory die 505-1 may be arranged in a memory device package, such as Figure 1 Memory device package 103. For ease of discussion of memory die 505-1, Figure 5The memory device package is not shown in FIG. The processing device 510 may be external to the memory device package containing the memory die 505-1. The processing device 510 may include a processing circuit system having one or more processors, wherein the processing device 510 is configured to perform operations to write to and read from the memory die 505-1 and other memory dies associated with the memory die 505-1. The processing device 510 may face a user device to interact with the memory die 505-1 and other memory dies associated with the memory die 505-1. The processing device 510, the interface 515, and the memory dies 505-1...505-N may be implemented to include components and perform operations similar to Figure 2 The functions of the processing device 210, the interface 215 and the memory dies 205-1...205-N.

[0057] Memory die 505-1 may include, among other components, deserializer circuitry 506, page buffers 508, memory array 512, memory controller 530 associated with instructions 532, circuitry 533 coupling memory array 512 to memory controller 530, sense amplifiers 509, serializer circuitry 507, timing logic 511, and PPM logic management 520-1 with controller 522-1 and associated instructions 524-1. Memory die 505-1 may be coupled to processing device 510 via feedback connection 528 using feedback node 529. Circuitry 533 may be implemented by CMOS circuitry or its equivalent. To facilitate discussion of the components and functionality used to control the current budget for cache operations and memory array operations of memory die 505-1, other components of memory die 505-1 are not shown. Components and functionality controlling the control budget may be implemented with PPM logic management 520-1.

[0058] In addition to controller 522-1 and instructions 524-1, PPM logic management 520-1 may also include logic circuits and registers. The logic circuits and registers may be used to receive signals from other components of memory die 505-1. Controller 522-1 may include processing circuitry, including one or more processors, and may be configured to perform peak power management operations for memory die 505-1 by executing instructions 524-1. Operations performed by PPM logic management 520-1 may include communicating current budgets with other PPM logic management components of other memory dies in a memory device package containing memory die 505-1. For example, memory die 505-N may include controller 522-N and instructions 524-N that may operate similarly to controller 522-1 and instructions 524-1 of memory die 505-1. Controller 522-1 may be a dedicated controller for PPM logic management 520-1. Alternatively, controller 522-1 may be a controller for memory die 505-1 that handles the operation of memory array 512 using instructions 524-1 dedicated to performing peak power management on memory die 505-1. PPM logic management 520-1 may be a dedicated state machine that handles all PPM related items.

[0059] For write operations to memory array 512 of memory die 505-1, data received as serial data from interface 515 at deserializer circuitry 506 is output as parallel data on a data path to page buffer 508 for programming memory array 512. Additional circuitry may be located along the data path from deserializer circuitry 506 to page buffer 508. Memory array 512 programming speed is relatively slow compared to the propagation speed within memory die 505-1. Furthermore, in the case where, for example, the memory array 512 is arranged with MLCs, programming memory array 512 involves more operations. To address the complexity of programming data into memory array 512, data is received and stored in page buffer 508 while other data is loaded into memory array 512. Page buffer 508 provides a cache to allow additional data to be loaded before the data is transferred for the next time data is programmed into memory array 512, thereby enhancing performance. Associated with the cache operation of page buffer 508 is current consumption using power supplied to memory die 505 - 1 using Vcc.

[0060] For read operations from the memory array 512 of the memory die 505-1, data is provided from the memory array 512 to the sense amplifier 509. When data is loaded from the memory array 512, the data is stored in the sense amplifier 509. The sense amplifier 509 provides a cache to allow data to be collected from the memory die 505-1 before the data is transferred. The data loaded into the sense amplifier 509 is sent to the serializer circuitry 507, which can serialize the data for output to the interface 515. Additional circuitry can be located along the data path from the sense amplifier 509 to the serializer circuitry 506. Associated with the caching operation of the sense amplifier 509 is the current consumption of the power provided to the memory die 505-1.

[0061] For write and read cache operations, a command state machine or circuit along the data path between interface 515 and memory array 512 may provide signals to be monitored by PPM logic management 520-1. The use of signals regarding write and read cache operations in memory die 505-1 may provide a mechanism for communicating information about current usage in write and read cache operations to PPM logic management 520-1. PPM logic management 520-1 may update parameters used by it based on current usage and update the status of cache operations and memory array operations. PPM logic management 520-1 may communicate with other memory dies, such as memory die 505-N, to share information about the current budget for cache and memory array operations. Based on the use of signals to update the current budget, PPM logic management 520-1 may provide feedback to memory controller 530 to control write and read operations within memory array 512.

[0062] For write cache operations, for example, deserializer circuitry 506 can be used to identify the start of a write cache operation, and page buffer 508 can be used to identify the end of a write cache operation. Identification of a first specified event in the timing pattern input to deserializer circuitry 506 can be used to generate a signal along path 516 from deserializer circuitry 506 to PPM management logic 520-1. This signal provides a first flag received from the data path identifying the start of a write cache operation performed on the data of a write operation. Identification of a second specified event in the timing pattern input to page buffer 508 can be used to generate a signal along path 518 from page buffer 508 to PPM management logic 520-1. This signal provides a second flag received from the data path identifying the end of a write cache operation performed on the data of a write operation. Comparison circuitry can be used to identify the occurrence of the first and second specified events. By providing a signal along path 521 to PPM management logic 520-1, timing logic 511 of memory die 505-1 can serve as a monitor for cache operations. Timing logic 511 can be used to identify the interface timing mode for data input in write cache operations. Alternatively, command state machine 513 can be used as a monitor for cache operations by providing a signal along path 523 to PPM logic management 520-1. Determining the start and stop of write operations is not limited by the use of deserializer circuitry 506 and page buffer 508. Other circuits in the data path from interface 515 to memory array 512 can be used to provide signals as flags to participate in PPM of memory die 505-1.

[0063] For read cache operations, for example, sense amplifier 509 can be used to identify the start of a read cache operation, and serializer circuitry 507 can be used to identify the end of a read cache operation. Identification of a first designated event in the timing pattern input to memory die 505-1 can be used to generate a signal along path 519 from sense amplifier 509 to PPM logic management 520-1. This signal provides a first flag received from the data path identifying the start of a read cache operation performed on the data of a read operation. Identification of a second designated event in the timing pattern input to memory die 505-1 can be used to generate a signal along path 517 from serializer circuitry 507 to PPM logic management 520-1. This signal provides a second flag received from the data path identifying the end of a read cache operation performed on the data of a read operation. Comparison circuitry can be used to identify the occurrence of the first and second designated events. By providing a signal along path 521 to PPM logic management 520-1, timing logic 511 of memory die 505-1 can serve as a monitor for cache operations. Timing logic 511 can be used to identify the interface timing mode for data output in read cache operations. Alternatively, command state machine 513 can be used as a monitor for cache operations by providing a signal along path 523 to PPM logic management 520-1. Determining the start and stop of read operations is not limited to the use of sense amplifier 509 and serializer circuitry 507. Other circuits in the data path from memory array 512 to interface 515 can be used to provide signals as flags to participate in PPM of memory die 505-1.

[0064] The PPM management logic 520-1 uses flags for write cache operations and read cache operations as a determination of the current being used in the corresponding cache operation. The amount of current used during the identified cache operation can be considered a fixed amount stored or hard-coded in the PPM management logic 520-1. Alternatively, a lookup table accessed by the PPM management logic 520-1 can be used, where the lookup table has current values ​​based on the programmed timing mode or speed of the data path used for the corresponding write or read cache operation. When generating a flag for a cache operation, a value in the lookup table can be selected using a signal from the timing logic 511.

[0065] In addition to receiving flags from the data path during cache operations associated with operating the memory array 512, the PPM management logic 520-1 also receives information about the memory array operation from the memory controller 530. Using the received flags and the information received from the memory controller 530, the PPM management logic 520-1 can monitor operations associated with the memory array 512 and the page buffer 508 during write operations, and monitor operations associated with the memory array 512 and the sense amplifier 509 during read operations, and calculate the total peak power used by the memory array and the corresponding cache. This total peak power can be calculated in terms of current. This can avoid activities associated with a separately reserved current budget for caching by external user devices to the memory device.

[0066] Cache operations and memory array operations can be performed simultaneously. Since memory die 505-1 has a constant Vcc provided during operation of memory die 505-1, peak current is a parameter to be managed according to the current budget. During programming of memory array 512, pulses are used with periods of relatively high current and periods of relatively low current. Considering the total current of cache operations and memory array operations, PPM logic management 520-1 on memory die 505-1 can use high current peak times and low current peak times to stagger when allowing data to be moved into or out of memory array 512. PPM logic management 520-1 communicates with memory controller 530 to control the staggering or pausing of data movement in memory array 512.

[0067] Memory controller 530 may include processing circuitry, including one or more processors, and may be configured to perform operations on memory array 512 by executing instructions 532. Memory controller 530, with instructions 532, may be configured as firmware for memory die 505-1 to control the functions of memory array 512. Memory controller 530 may be a dedicated programmable controller operating as firmware, or it may be a main memory controller for memory die 505-1, performing operations according to instructions 532. Firmware code in programmable memory controller 530 is used to implement array read and program operations, making requests to the PPM logic management state machine before entering "high current peak" operation. PPM logic management 520 confirms the operation or may place it in a pending state based on the overall system current budget, which includes the current budgets of other memory dies arranged in the memory device package along with memory die 505-1. In other examples, at least some portions of the instructions executed by memory controller 530 may be stored in other memory structures and loaded, for example, into the local memory of memory controller 530 for execution. Memory controller 530 waits until it receives a signal to proceed from PPM logic management 520-1 before executing the code in instruction 532, which causes an ICC spike in the memory array operations of memory die 504-1.

[0068] PPM logic management 520-1 continuously monitors both memory array operations and cache operations to calculate the total peak power and communicates this information across all memory dies within the PPM group. PPM logic management 520-1 can communicate with the PPM logic management of other memory dies in the PPM group using one or more pads of memory die 505-1 to indicate when the available budget is insufficient to support full-speed cache operation. One or more pads can be pads for a memory die, such as a ZQ pad for a NAND memory die, which may have other functions. Alternatively, one or more pads can be dedicated pads for a memory die. Other memory dies in the PPM group of which memory die 505-1 is a component can be coupled together at corresponding pads on the memory die to indicate when the available budget is insufficient to support full-speed cache operation. If the available budget is insufficient to support full-speed cache operation, PPM logic management 520-1 can generate a switching signal or an analog signal as an indicator. This pad channel, shared between memory dies in the same PPM group, can be connected to a processing device 510, which is a system memory controller for the memory dies, via a feedback node (FN) 529 through a feedback connection 528. This pad channel can be shared as a reference, voltage-controlled oscillator (VCO) input, or other input to an interface frequency modulation circuit, such as the ONFI frequency modulation circuit. The processing device 510 can adjust and slow down the interface during data bursts based on this hardware feedback.

[0069] Figure 6 6. An embodiment of an example feedback node 629 is shown for feeding signals from the memory dies 605-1 and 605-N back to the processing device 610 along the feedback connection 628. The processing device 610 and the memory dies 605-1 and 605-N may be similar to Figure 5 The processing device 510 and memory dies 505-1 and 505-N are implemented. The processing device 610 can be implemented as a system memory controller for the memory die. The PPM logic management of the memory die 605-1 can, for example, use a pull-up resistor coupled between Vccq and the feedback connection 628 to switch the feedback signal. When the feedback circuit is in a digital state, for example Figure 6 In the event that _ is low active in _ and the PPM logic management determines that there is insufficient budget for one channel cache operation budget, the PPM logic management will pull down the feedback channel and the processing device 610 may operate at half speed or other predetermined low interface speed.

[0070] Figure 77. An embodiment of an example feedback node 729 is shown for feeding signals from the memory dies 705-1 and 705-N back to the processing device 710 along the feedback connection 728. The processing device 710 and the memory dies 705-1 and 705-N may be similar to Figure 5 The processing device 510 and memory dies 505-1 and 505-N are implemented as described above. The processing device 710 can be implemented as a system memory controller for the memory dies. The PPM logic management of the memory device 705-1 can, for example, use a pull-down resistor coupled between the feedback connection 628 and ground or a low reference voltage to switch the feedback signal. When the feedback circuit is in a digital state, for example Figure 7 In the event that IO_CONF_SOURCE_PPM is high active and the PPM logic management determines that there is insufficient budget for one channel cache operation budget, the PPM logic management will pull down the feedback channel and the processing device 710 may operate at half speed or other predetermined low interface speed.

[0071] Figure 8 805-1 and 805-N to the processing device 810. Figure 5 810 and memory dies 505-1 and 505-N. Processing device 810 may be implemented as a system memory controller for the memory dies. Feedback node 829 may include a resistor coupling feedback connection 828 to Vccq. The PPM logic management of memory die 805-1 may, for example, provide feedback as an analog voltage. Based on the voltage value, the feedback may be used to adjust the interface speed of processing device 810 directly within processing device 810 using VCO 836 and interface controller 835 of processing device 810. Memory die 805-1 and other memory dies in a common PPM group may have different pins 839 that are connected or disconnected to generate different analog voltages on feedback connection 828.

[0072] For example, about Figures 5 to 8The PPM logic management of the memory dies discussed may treat cache operations as the highest priority. If the PPM logic management determines that there is insufficient budget for the next cache operation, it begins to free up peak power budget internally by making internal adjustments, such as by adjusting the budget for memory array operations downward. Then, after a few microseconds, the memory die may suspend memory array operations or force a low-peak power mode of memory array operation to free up budget. The PPM logic management may switch or change the voltage at the hardware feedback pad to indicate that there is sufficient budget. The processing device, arranged as a system memory controller, may resume cache operations at full speed in the next data burst.

[0073] Figure 9 9 is a block diagram illustrating an embodiment of an example memory controller 910 external to a group of memory dies, wherein the memory controller 910 is arranged to receive feedback signals from one or more of the memory dies. The group of memory dies may include memory dies 905-1, 905-2, 905-3, and 905-4 in a memory device package. Although four memory dies are shown, a group of memory dies may be more or less than four. The memory dies may be NAND memory dies, wherein the interface 915 is an interface constructed according to the ONFI specification. The memory dies 905-1, 905-2, 905-3, and 905-4 may be arranged in a memory device package, for example Figure 1 Memory device package 103. For ease of discussion regarding feedback connection 928 to memory controller 910, Figure 9 The memory device package is not shown in FIG. Memory controller 910 may be external to the memory device package containing memory dies 905-1, 905-2, 905-3, and 905-4. Memory controller 910 may include processing circuitry having one or more processors, wherein memory controller 910 is configured to perform write and read operations on memory dies 905-1, 905-2, 905-3, and 905-4. Memory controller 910 may face a user device to interact with memory dies 905-1, 905-2, 905-3, and 905-4. Memory controller 910, interface 915, and memory dies 905-1, 905-2, 905-3, and 905-4 may be implemented to include components and perform operations similar to Figure 5 The functions of the processing device 510, the interface 515 and the memory dies 505-1...505-N, and the Figure 5 . . 505 -N.

[0074] The memory dies 905-1, 905-2, 905-3, and 905-4 can be configured into a PPM group that can share a total current budget, wherein each of the memory dies 905-1, 905-2, 905-3, and 905-4 has PPM logic management. The memory array of each memory die has peak operating times and off-peak operating times that use current, so that there are periods when one memory die operates and the other memory die is paused. The operation and interleaving of the memory arrays of different memory dies can be managed. In addition, the data paths in the memory dies can also be arranged or interleaved in this way. One memory die of the PPM group can be used to control the arrangement of the memory arrays of the memory dies 905-1, 905-2, 905-3, and 905-4. In Figure 9 In an example arrangement, memory die 905-1 is assigned as the manager die for memory dies 905-1, 905-2, 905-3, and 905-4. Memory dies 905-2, 905-3, and 905-4 are configured as follower memory dies. Memory controller 910 can assign memory die 905-1. Each of memory dies 905-1, 905-2, 905-3, and 905-4 can be configured with a means to operate as a manager memory die once selected as such. Each of memory dies 905-2, 905-3, and 905-4 effectively controls itself because the PPM logic management of each memory die can be programmed with a current budget that allows the amount of current to be budgeted simultaneously to the memory die at any one time. The PPM logic management of one memory die can be communicated to the PPM logic management of the other memory dies in the PPM group, so that each memory die has information about the activities of the other memory dies. Using this information, each memory die can perform its own budgeting and interleaving. The manager memory die 905-1 can control the initialization of communication between the memory die 905-1, 905-2, 905-3, and 905-4 to share the total current budget. Communication between the memory die 905-1, 905-2, 905-3, and 905-4 can communicate using a round-robin token protocol using the PPM ring bus 948. The ring bus 948 can include HC and ICLK lines that can be driven by the manager memory die 905-1.

[0075] Memory dies 905-1, 905-2, 905-3, and 905-4 of a memory device package may be coupled on a single channel, where the memory device package has multiple groups of memory dies coupled to different channels. If one memory die on each channel of a multi-channel memory device package simultaneously begins performing a read or write cache operation, the total current budget may be exceeded and the PPM budget may be full. Feedback connection 928 may be used to prevent system peak power from exceeding the total target budget. A signal on feedback connection 928 from one or more of memory dies 905-1, 905-2, 905-3, and 905-4 may be used to pause data operations on the channel from memory controller 910. The signal on feedback connection 928 is an indicator of peak power. Memory controller 910 may include instructions 937 that, upon receiving the indicator, cause interface controller 935 of memory controller 910 to pause I / O operations of interface 915. The pause may provide a delay to the memory die affected by the pause, which may adjust current usage to maintain the current budget of the memory die. An indicator from one or more memory dies 905-1, 905-2, 905-3, and 905-4 may be received as a pause request at an interface (IF) controller 935, which may provide appropriate notification to instructions 937. Alternatively, the pause request may be received from an input of the memory controller 910 at instructions 937. The indicator may be received using, for example, Figures 6 to 8 9. For example, Vccq may be coupled to the feedback connection 928 through impedance 929-1, and Vssq may be coupled to the feedback connection 928 through impedance 929-2.

[0076] For ease of presentation, Figure 9 While one channel is shown, the memory device package may include other groups of memory dies coupled to corresponding channels, each of which includes a feedback connection to the memory controller 910. The I / O path from the memory controller 910 can be paused by each channel by monitoring the corresponding peak power indicators from multiple groups of memory dies. Pausing can be performed in nanoseconds. The peak power indicator can be driven by only the manager memory die, which can wait for its token transition in a round-robin token protocol communication. Upon determining that the current budget exceeds a threshold portion of the total current budget, a fast response can be achieved by driving the indicator output by all memory dies.

[0077] Figures 10 to 13 An embodiment is shown of an example use of an indicator signal or signals from a ready / busy pad of a memory die for pausing the output of data from an interface of a processor device to a memory die for cache current and memory array operation. The indicator signal or signals from the ready / busy pad can be used, for example, with Figures 5 to 9 Associated PPM logical management driver.

[0078] Figure 10 An example of the use of an indicator signal for pausing a request to output data to a lower ICC4R is shown. For example, assume the PPM budget is equal to 800 mA, where ICC4R operation uses 0 mA, and the memory array uses 800 mA. A PPM datapath flag is received in the PPM logic management that indicates the start of a read cache operation, where there is a request for 150 mA for ICC4R and the memory array is operating at 800 mA, which exceeds the PPM budget of 800 mA. In response to the PPM logic management receiving the PPM datapath flag, the PPM logic management transmits an indicator signal to the memory controller that may be set low due to exceeding the ICC budget. After receiving the indicator signal, the interface controller of the interface from the memory controller to the memory device may suspend the read signal RE# when the indicator signal goes low to provide a pause to allow the current budget to be adjusted. When suspending providing current within the current budget, for example, 150 mA is allocated to budget ICC4R and the memory array has a budget of 600 mA, the indicator signal may be removed by raising the indicator signal high.

[0079] Figure 11 An example use of an indicator signal regarding a request to pause data output to a lower ICC4W is shown. For example, assume the PPM budget is equal to 800mA, where ICC4W operation uses 0mA and the memory array uses 800mA. A PPM datapath flag is received in the PPM logic management to indicate the start of a write cache operation, where there is a request for 200mA for ICC4W and the memory array is operating at 800mA, which exceeds the PPM budget of 800mA. In response to the PPM logic management receiving the PPM datapath flag, the PPM logic management transmits an indicator signal to the memory controller that may be set low due to exceeding the ICC budget. After receiving the indicator signal, an interface controller of an interface from the memory controller to the memory device may pause DQS when the indicator signal goes low to provide a pause to allow the current budget to be adjusted. When suspending providing current within the current budget, eg, 200 mA is allocated to budget ICC4W and the memory array has a budget of 600 mA, the indicator signal may be removed by raising the indicator signal high.

[0080] Figure 12An example use of an indicator signal regarding a request to pause data output to a lower ICC4R / W is shown. For example, imagine a PPM budget equal to 800mA, where ICC4R operation uses 150mA and the memory array uses 600mA, which is less than the PPM budget. Furthermore, imagine a situation where ICC4R goes to 0mA and the memory array uses 800mA, which is at the PPM budget limit. Information about the memory array current is provided by the controller of the memory die to the PPM logic management, which executes instructions, such as firmware, for reading and writing. With the combination of ICC4R and memory array current at the budget limit, the PPM logic management can transmit an indicator signal that can be set low to the memory controller. After receiving the indicator signal, the interface controller of the interface from the memory controller to the memory device can pause RE# when the indicator signal goes low to provide a pause before exceeding the ICC budget to allow the current budget to be adjusted. When the pause provides current below the current budget limit, for example 150mA is allocated to the budget ICC4R and the memory array has a budget of 600mA, the indicator signal can be removed by raising the indicator signal. There may be a threshold level within the budget at which the pause feature can be used to avoid exceeding the budget. Figure 12 The indicator signal may be used not only when cache current increases, but also when memory array current reaches or exceeds the current budget.

[0081] Figure 13 An example use of the RB signal to pause data output to a lower ICC4R is shown. After receiving the RB signal, the interface controller of the interface from the memory controller to the memory device can pause RE# when the RB signal goes low to provide a pause to allow the current budget to be adjusted. In this example, the RB signal goes high and low multiple times, which may be a result of the ICC4R budget having a duty cycle. Consider an 800mA system budget, where the memory array current budget is limited to 700mA, and the ICC4R budget is 100mA at a full duty cycle of 200mA. When the memory array current is at 700mA and the ICC4R budget is above 100mA during its cycle, the 800mA system budget will be exceeded. When the 700mA memory array ICC budget is used with the 100mA ICC4R budget at 50% duty cycle, the PPM logic management can cause the RB signal to go low. At the duty cycle, the RB signal pulses may indicate a need for power conservation.

[0082] Figure 14A flowchart of an embodiment of an example method 1400 for controlling peak power management in a memory die is provided. At 1410, a data path leading to or originating from a memory array of a memory die is monitored, wherein the data path includes a cache for storing data. At 1420, a first flag received from the data path at logic circuitry of the memory die is used to indicate the start of a cache operation performed on the data. The logic circuitry may be implemented by a controller having stored instructions. The controller may be implemented by processing circuitry including one or more processors. The logic circuitry may also include registers and logic circuits operable with the controller. The logic circuitry may be implemented as PPM logic management, which may include a controller having processing circuitry including one or more processors, wherein the controller is configured to perform operations for controlling peak power management in the memory die. At 1430, a second flag received from the data path at the logic circuitry of the memory die is used to indicate the end of the cache operation. At 1440, the start and end of cache operations are used in logic circuitry of the memory die to control a power budget for the cache and the memory array.

[0083] Variations of method 1400 or methods similar to method 1400 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the memory device in which such methods are implemented. Such methods may include: receiving a signal from sequential logic of a memory die at the logic circuitry of the memory die to monitor cache operations; and accessing information in a lookup table in the memory die, wherein the information includes a programmed timing pattern or operating speed of current for a data path. The signal and information from the sequential logic are used in the logic circuitry of the memory die to determine the current to be consumed during a write operation or a read operation associated with the cache operation.

[0084] Variations of method 1400 or methods similar to method 1400 may include calculating the total peak power used by the memory array and the cache in the logic circuitry of the memory die; and transferring the calculated total peak power to another memory die arranged in a peak power management group with the memory die. Controlling the power budget for the cache and the memory array may include using a filter to eliminate pauses in data transfer for the current budget of the cache and the memory array.

[0085] A variation of method 1400 or a method similar to method 1400 may include feeding back a signal via the interface to a memory controller coupled to the memory die to adjust the operating speed of the interface. The fed-back signal may be a switching signal or an analog signal generated by disconnecting or connecting different paths in the corresponding memory die.

[0086] In various embodiments, a memory device includes a memory die comprising a memory array, a cache, and a controller. The cache may be arranged to store data in a data path leading to or starting from the memory array. The controller may include a processing circuit system comprising one or more processors. The controller may be configured to perform operations, wherein the operations may include controlling the power budget for the cache and the memory array by using a first flag received from the data path to identify the start of a cache operation performed on the data and a second flag received from the data path to identify the end of the cache operation. The cache may be a page buffer of the memory die for write cache operations, wherein the first flag is a signal from the deserializer circuit system of the memory die and the second flag is a signal from the page buffer. The cache may be a sense amplifier of the memory die for read cache operations, wherein the first flag is a signal from the sense amplifier and the second flag is a signal from the serializer circuit system of the memory die. The controller may be arranged to operate together with multiple caches associated with the operation of the memory array. The controller may be arranged to operate with a first cache being a page buffer arranged to store data in a data path to a memory array, and wherein a second cache is a sense amplifier of a memory die to store data in a data path from the memory array. The controller may be configured to operate to monitor other components to control a power budget for such other components and the memory array, wherein these other components are used in the operation of the memory array.

[0087] Variations of such a memory device or similar memory devices may include several different embodiments that may be combined depending on the application of such a memory device and / or the architecture in which such a memory device is implemented. Such a memory device may include a controller coupled to the timing logic of the memory die to receive signals to monitor cache operations. The memory die may include a lookup table that is accessible to determine the current to be consumed during a write operation or a read operation associated with the cache operation using the signals from the timing logic.

[0088] A variation of such a memory device or a similar memory device may include a controller configured to perform operations associated with power budgeting for caches and memory arrays. Such operations may include determining the availability of power budget for a next cache operation and, in response to determining that the power budget is insufficient for the next cache operation, adjusting the operation of the memory array to free up an amount of the peak power budget for cache operations. A variation may include a controller that can be configured as a control manager for a group of managed memory dies, allowing selected dies of the group to operate during individual cache operations while allowing other dies of the group to suspend corresponding cache and memory array operations.

[0089] Operations performed by the controller may include monitoring the operation of the memory array and cache, and calculating the total peak power used by the memory array and cache. The controller may be operable to transmit the calculated total peak power of the memory device to controllers of other memory dies arranged with the memory device in a peak power management group. The controller may be operable to feed back a signal to a memory controller external to the memory die to adjust the operating speed of an interface from the memory controller to the memory die.

[0090] Variations of this or similar memory devices may include a controller having a filter to eliminate pauses in data transfers for the current budget of the cache and memory array, thereby controlling the current budget. The filter may include a timer to release the cache operation budget in response to the timer reaching the filter time if no new cache operation occurs.

[0091] In various embodiments, a memory device includes an input node for receiving a power supply voltage and a plurality of memory dies coupled to the input node, wherein the plurality of memory dies are arranged into a peak power management group. Each memory die of the plurality of memory dies may include a memory array, a cache, a logic circuit system, and a connector for outputting data. The cache may be a component of the memory die that stores data in a data path leading to or originating from the memory array. The controller includes a processing circuit system that includes one or more processors, wherein the controller is configured to perform an operation. The operation may include controlling a power budget for the cache and the memory array by using a first flag received from the data path to identify the start of a cache operation performed on the data and a second flag received from the data path to identify the end of the cache operation. The connector for outputting data may be arranged to output data about the power budget to one or more other memory dies in the peak power management group.

[0092] The cache may be a page buffer of a memory die for write cache operations, wherein the first flag is a signal from the deserializer circuitry of the memory die and the second flag is a signal from the page buffer. The cache may be a sense amplifier of a memory die for read cache operations, wherein the first flag is a signal from the sense amplifier and the second flag is a signal from the serializer circuitry of the memory die. The controller may be arranged to operate with multiple caches associated with the operation of the memory array. The controller may be arranged to operate with a first cache, wherein the first cache is a page buffer arranged to store data in a data path leading to the memory array, and wherein the second cache is a sense amplifier of a memory die for storing data in a data path starting from the memory array. The controller may be configured to operate to monitor other components to control the power budget for such other components and the memory array, wherein these other components are used in the operation of the memory array.

[0093] Variations of such a memory device or similar memory devices may include several different embodiments, which may be combined depending on the application of such a memory device and / or the architecture in which such a memory device is implemented. Such a memory device may include a controller for each memory die coupled to the timing logic of the memory die to receive signals to monitor cache operations. Each memory die of the plurality of memory die may include a lookup table that is accessible to determine the current to be consumed during a write operation or a read operation associated with the cache operation using signals from the timing logic of the corresponding memory die. For operation as part of a peak power management group, one of the memory dies may be configured as a manager for one or more other memory dies of the plurality of memory dies.

[0094] Variations of this type of memory device or similar memory devices may include a controller for each memory die operable to feed back a signal to a memory controller or interface controller of the plurality of memory dies to adjust the operating speed of the interfaces of the memory dies. The fed-back signal may be a switching signal or an analog signal generated by disconnecting or connecting different paths in the corresponding memory die.

[0095] Electronic devices such as mobile electronic devices (e.g., smart phones, tablet computers, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and networked electrical equipment or devices (e.g., Internet of Things (IoT) devices, etc.) have different storage needs depending on the type of electronic device, usage environment, performance expectations, etc.

[0096] An electronic device can be broken down into several major components: a processor (e.g., a central processing unit (CPU) or other host processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power double-data-rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, ROM, a solid-state drive (SSD), a multimedia controller (MMC), or other memory card structure or assembly). In some examples, the electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0097] Figure 15 A block diagram of an embodiment of an example machine 1500 having one or more memory devices configured with memory dies having PPM logic management is shown. The PPM logic management of each of the memory dies can be structured to manage cache operations in the memory die as well as memory array operations of the memory die, and can be structured to provide feedback to the system memory controller of the memory die to slow down the operating frequency of the interface coupling the system memory controller to the memory die based on the PPM logic management managing the current budget. As taught herein, the PPM logic management can be used for, but is not limited to, Figures 1 to 14 The associated example embodiments perform operations. Machine 1500, with one or more such memory devices, may operate as a standalone machine or may be connected, such as with a network, to other machines.

[0098] In a networked deployment, machine 1500 may operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In an example, machine 1500 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 1500 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an in-vehicle system, or any other machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by the machine. Furthermore, while a single machine is illustrated, the term "machine" should also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as in cloud computing, software as a service (SaaS), or other computer cluster configurations. Example machine 1500 may be arranged to operate with one or more memory devices containing memory dies managed by PPM logic, as taught herein.

[0099] As described herein, examples may include or be operable by logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., group) of circuits implemented in a tangible entity comprising hardware (e.g., simple circuits, gates, logic, etc.). The components of a circuit system can be flexible over time and as the underlying hardware changes. A circuit system includes components that, when in operation, can perform specific tasks individually or in combination. In an example, the hardware of a circuit system can be permanently designed to perform a specific operation (e.g., hard-wired). In an example, the hardware of a circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include computer-readable media that can be physically modified (e.g., magnetism of fixed centralized particles, electrically movable placement, etc.) to encode instructions for a specific operation. When the physical components are connected, the underlying electrical properties of the hardware component change, for example, from an insulator to a conductor, or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to generate, via variable connections, the circuit system components in the hardware to perform a portion of a specific task when in operation. Thus, when the device is in operation, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one component in more than one circuit system. For example, during operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and reused by a second circuit in the first circuit system at a different time, or reused by a third circuit in the second circuit system.

[0100] The machine (e.g., a computer system) 1500 may include a hardware processor 1550 (e.g., a CPU, a GPU, a hardware processor core, or any combination thereof), a main memory 1554, and a static memory 1556, some or all of which may communicate with each other via an interconnect (e.g., a bus) 1558. The machine 1500 may further include a display device 1560, an alphanumeric input device 1562 (e.g., a keyboard), and a user interface (UI) navigation device 1564 (e.g., a mouse). In an example, the display device 1560, the input device 1562, and the UI navigation device 1564 may be a touch screen display. The machine 1500 may also include a mass storage device (e.g., a drive unit) 1551, a signal generating device 1568 (e.g., a speaker), a network interface device 1553, and one or more sensors 1566, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1500 may include an output controller 1569, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0101] The machine 1500 may include a machine-readable medium 1552 having stored thereon one or more sets of data structures or instructions 1555 (e.g., software) that embody the machine 1500 or are utilized by the machine to perform any one or more of the techniques or functions for which the machine 1500 is designed. The instructions 1555 may also reside, completely or at least partially, within the main memory 1554, within the static memory 1556, or within the hardware processor 1550 during execution thereof by the machine 1500. In an example, one or any combination of the hardware processor 1550, the main memory 1554, the static memory 1556, or the mass storage device 1551 may constitute the machine-readable medium 1552.

[0102] Although machine-readable medium 1552 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 1555. The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by machine 1500 and causing machine 1500 to perform any one or more of the techniques for which machine 1500 is designed, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In an example, a centralized machine-readable medium includes a machine-readable medium having a plurality of particles having a constant (e.g., stationary) mass. Thus, the centralized machine-readable medium propagates signals non-transitorily. Specific examples of centralized machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., EPROM, EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and compact disc-ROM (CD-ROM) and digital versatile disc-read-only memory (DVD-ROM) disks.

[0103] Instructions 1555 (e.g., software, programs, operating system (OS), etc.) or other data stored on mass storage device 1551 can be accessed by main memory 1554 for use by processor 1550. Main memory 1554 (e.g., DRAM) is typically fast but volatile, and therefore a different type of memory than mass storage device 1551 (e.g., SSD), which is suitable for long-term storage, including when in a "disconnected" state. Instructions 1555 or data for use by a user or machine 1500 are typically loaded into main memory 1554 for use by processor 1550. When main memory 1554 is full, virtual space from mass storage device 1551 can be allocated to supplement main memory 1554; however, because mass storage device 1551 is typically slower than main memory 1554, with a read speed at least twice as fast as a write speed, the use of virtual memory can significantly reduce the user experience due to storage device latency (compared to main memory 1554, such as DRAM). Furthermore, the use of the mass storage device 1551 for virtual memory may significantly shorten the useful life of the mass storage device 1551 .

[0104] Compared to virtual memory, virtual memory compression (e.g. A kernel feature ("ZRAM") uses portions of memory as compressed block memory to avoid paging to mass storage 1551. Paging occurs in compressed blocks until it is necessary to write such data to mass storage 1551. Virtual memory compression increases the available size of main memory 1554 while reducing the wear and tear on mass storage 1551.

[0105] Storage devices optimized for mobile electronic devices or mobile storage have traditionally included MMC solid-state storage devices (e.g., micro Secure Digital (microSD) TM ) card, etc.). An MMC device includes several parallel interfaces (e.g., 8-bit parallel interfaces) with a host device and is typically a component that can be removed and separated from the host device. In contrast, an embedded multimedia controller (eMMC) TM ) devices are attached to a circuit board and treated as components of a host device, with read speeds comparable to Serial Advanced Technology Attachment (SATA)-based SSD devices. However, the demand for performance in mobile devices continues to increase, for example, to fully implement virtual or augmented reality devices, take advantage of increased network speeds, etc. In response to this demand, storage devices have transitioned from parallel to serial communication interfaces. UFS devices, which include a controller and firmware, communicate with host devices using a low-voltage differential signaling (LVDS) serial interface with dedicated read / write paths, further improving read / write speeds.

[0106] The instructions 1555 may further be transmitted or received over the communication network 1559 using a transmission medium via the network interface device 1553 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as IEEE 802.16 series of standards, known as ), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, and the like. In an example, the network interface device 1553 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 1559. In an example, the network interface device 1553 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" shall be deemed to include any tangible medium capable of carrying instructions to and for execution by the machine 1500, and including means for propagating digital or analog communication signals to facilitate communication of such instructions, which may be implemented by software.

[0107] The following are example embodiments of apparatus and methods according to the teachings herein.

[0108] An example memory device 1 may include a memory die comprising a memory array; a cache to store data in a data path leading to or originating from the memory array; and a controller comprising processing circuitry including one or more processors, the controller configured to perform operations comprising controlling a power budget for the cache and the memory array by using a first flag received from the data path to identify the start of a cache operation on the data and a second flag received from the data path to identify the end of the cache operation.

[0109] Example memory device 2 may include the features of example memory device 1 and may include a cache that is a page buffer of the memory die for write cache operations, wherein the first flag is a signal from the deserializer circuitry of the memory die and the second flag is a signal from the page buffer.

[0110] The example memory device 3 may include features of any of the aforementioned example memory devices and may include a cache that is a sense amplifier of the memory die for read cache operations, wherein the first flag is a signal from the sense amplifier and the second flag is a signal from the serializer circuitry of the memory die.

[0111] Example memory device 4 may include features of any of the aforementioned example memory devices and may include a controller coupled to the timing logic of the memory die to receive signals to monitor cache operations.

[0112] Example memory device 5 may include features of example memory device 4 and any of the aforementioned example memory devices and may include a memory die that includes a lookup table accessible to determine current to be consumed during a write operation or a read operation associated with a cache operation using signals from sequential logic.

[0113] Example memory device 6 may include features of any of the aforementioned example memory devices and may include operations comprising: determining the availability of a power budget for a next cache operation; and in response to determining that the power budget is insufficient for the next cache operation, adjusting operation of the memory array to free up an amount of the peak power budget for the cache operation.

[0114] The example memory device 7 may include features of any of the aforementioned example memory devices and may include a controller that can be configured as a control manager of controllers for a group of managed memory dies to allow selected dies of the group to operate during individual cache operations while allowing other dies of the group to suspend respective cache and memory array operations.

[0115] The example memory device 8 may include features of any of the aforementioned example memory devices and may include operations including: monitoring operation of the memory array and cache; and calculating the total peak power used by the memory array and cache.

[0116] Example memory device 9 may include features of example memory device 8 and any of the aforementioned example memory devices and may include a controller operable to communicate the calculated total peak power of the memory device to controllers of other memory dies arranged with the memory device into a peak power management group.

[0117] The example memory device 10 may include features of any of the aforementioned example memory devices and may include a controller that includes filters to eliminate pauses in data transfers for the current budget of the cache and memory array, thereby controlling the current budget.

[0118] Example memory device 11 may include features of example memory device 10 and any of the aforementioned example memory devices and may include a filter including a timer to release a cache operation budget in response to the timer reaching a filter time if no new cache operation occurs.

[0119] The example memory device 12 may include features of any of the aforementioned example memory devices and may include a controller operable to feed a signal back to the memory controller to adjust the operating speed of an interface from the memory controller to the memory die.

[0120] In example memory device 13, any of the memory devices in example memory devices 1-12 may comprise a memory device incorporated into an electronic memory apparatus further including a host processor and a communication bus extending between the host processor and the memory device.

[0121] In example memory device 14 , any one of the memory devices in example memory devices 1 - 13 may be modified to include any structure present in another one of example memory devices 1 - 13 .

[0122] In example memory device 15 , any apparatus associated with a memory device in example memory devices 1 - 14 may further include a machine-readable storage device configured to store instructions as a physical state, where the instructions may be used to perform one or more operations of the apparatus.

[0123] In example memory device 16 , any of the memory devices in example memory devices 1 - 15 may operate according to any of the following example methods 1 - 5 .

[0124] An example memory device 17 may include: an input node that receives a power supply voltage; and a plurality of memory dies coupled to the input node to form a peak power management group, wherein each memory die in the plurality of memory dies includes: a memory array; a cache to store data in a data path leading to or starting from the memory array; a controller that includes a processing circuit system, the processing circuit system including one or more processors, the controller being configured to perform operations comprising: controlling a power budget for the cache and the memory array by using a first flag received from the data path that identifies the start of a cache operation to be performed on the data and a second flag received from the data path that identifies the end of the cache operation; and a connector that outputs data regarding the power budget to one or more other memory dies in the peak power management group.

[0125] Example memory device 18 may include features of example memory device 17 and may include a controller operable to feed signals back to memory controllers or interface controllers of multiple memory dies to adjust the operating speed of the interfaces of the memory dies.

[0126] Example memory device 19 may include features of example memory device 18 and features of example memory device 17 and may include signals that are switching signals, or analog signals generated by opening or closing different paths in the memory die.

[0127] The example memory device 20 may include features of any of the aforementioned example memory devices 17 to 19 and may include a cache that is a page buffer of a memory die for write cache operations, wherein the first flag is a signal from the deserializer circuitry of the memory die and the second flag is a signal from the page buffer.

[0128] The example memory device 21 may include features of any of the aforementioned example memory devices 17-20 and may include a cache that is a sense amplifier of a memory die for read cache operations, wherein the first flag is a signal from the sense amplifier and the second flag is a signal from the serializer circuitry of the memory die.

[0129] The example memory device 22 may include features of any of the aforementioned example memory devices 17-21 and may include a controller coupled to the timing logic of the memory die to receive signals to monitor cache operations.

[0130] The example memory device 23 may include the features of any of the aforementioned example memory devices 17-22 and may include each memory die including a lookup table that is accessible to determine the current that will be consumed during a write operation or a read operation associated with a cache operation using signals from the timing logic of the memory die.

[0131] The example memory device 24 may include features of any of the aforementioned example memory devices 17-23 and may include one of the memory dies that is configured as a manager of one or more other memory dies of a plurality of memory dies for operation as part of a peak power management group.

[0132] In example memory device 25, any of the memory devices of example memory devices 17-24 may comprise a memory device incorporated into an electronic memory apparatus further including a host processor and a communication bus extending between the host processor and the memory device.

[0133] In example memory device 26 , any one of the memory devices of example memory devices 17 - 25 may be modified to include any structure present in another one of example memory devices 17 - 25 .

[0134] In example memory device 27 , any apparatus associated with a memory device in example memory devices 17 - 26 may further include a machine-readable storage device configured to store instructions as a physical state, where the instructions may be used to perform one or more operations of the apparatus.

[0135] In example memory device 28 , any of the memory devices in example memory devices 17 - 27 may operate according to any of the following example methods 1 - 5 .

[0136] Example memory device 29 may include features of any of the aforementioned example memory devices 1-28.

[0137] An example method 1 for controlling peak power management in a memory device may include: monitoring a data path leading to or originating from a memory array of a memory die, the data path including a cache for storing data; using a first flag received from the data path at a logic circuit system of the memory die to identify the start of a cache operation performed on the data; using a second flag received from the data path at the logic circuit system of the memory die to identify the end of the cache operation; and using the start and end of the cache operation in the logic circuit system of the memory die to control a power budget for the cache and the memory array.

[0138] Example method 2 of controlling peak power management in a memory device may include the features of example method 1 of controlling peak power management in a memory device, and may include: receiving a signal from timing logic of a memory die at a logic circuit system of the memory die to monitor cache operations; accessing information in a lookup table in the memory die, the information including programmed timing patterns or operating speeds of current for a data path; and determining, in the logic circuit system of the memory die, the current to be consumed during a write operation or a read operation associated with the cache operations using the signal and information from the timing logic.

[0139] Example method 3 of controlling peak power management in a memory device may include features of any of the aforementioned example methods of controlling peak power management in a memory device, and may include: calculating the total peak power used by the memory array and cache in a logic circuit system of a memory die; and transmitting the calculated total peak power to another memory die arranged into a peak power management group together with the memory die.

[0140] Example method 4 of controlling peak power management in a memory device may include features of any of the aforementioned example methods of controlling peak power management in a memory device, and may include: controlling a power budget for a cache and a memory array, including using a filter to eliminate pauses in data transfers for the current budget of the cache and memory.

[0141] Example method 5 for controlling peak power management in a memory device may include features of example method 4 for controlling peak power management in a memory device and features of any of the foregoing example methods for controlling peak power management in a memory device, and may include: feeding back a signal to a memory controller coupled to a memory die through an interface to adjust an operating speed of the interface.

[0142] In example method 6 of controlling peak power management in a memory device, any of example methods 1-5 of controlling peak power management in a memory device may be performed in an electronic memory apparatus further including a host processor and a communication bus extending between the host processor and the memory device.

[0143] In example method 7 of controlling peak power management in a memory device, any of example methods 1-6 of controlling peak power management in a memory device may be modified to include operations set forth in any other of method examples 1-6 of controlling peak power management in a memory device.

[0144] In example method 8 of controlling peak power management in a memory device, any of example methods 1-9 of controlling peak power management in a memory device may be implemented at least in part by using instructions stored as physical states in one or more machine-readable storage devices.

[0145] Example method 9 of controlling peak power management in a memory device may include features of any of the aforementioned example methods 1-10 of controlling peak power management in a memory device and may include performing functions associated with any features of example memory devices 1-29.

[0146] The example machine-readable storage device 1 storing instructions may include instructions to perform functions associated with any features of the example memory devices 1-16 and memory devices 17-29, or to perform methods associated with any features of the example methods 1-9, which instructions, when executed by one or more processors, cause the machine to perform operations.

[0147] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments utilize permutations and / or combinations of the embodiments described herein. The above description is intended to be illustrative, not restrictive, and the wording or terminology employed herein is for descriptive purposes. Furthermore, in the foregoing embodiments, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the present disclosure. Combinations of the above embodiments and other embodiments will be apparent to those skilled in the art upon studying the above description.

Claims

1. A memory device comprising: A memory die comprising: memory arrays; a cache memory for storing data in a data path leading to or from the memory array; as well as A controller comprising processing circuitry including one or more processors, the controller configured to perform operations comprising: A power budget for the cache and the memory array is controlled using a first flag received from a data path identifying the start of a cache operation performed on the data and a second flag received from the data path identifying the end of the cache operation.

2. The memory device of claim 1 , wherein the cache is a page buffer of the memory die used for write cache operations, wherein the first flag is a signal from a deserializer circuitry of the memory die and the second flag is a signal from the page buffer.

3. The memory device of claim 1 , wherein the cache is a sense amplifier of the memory die used for read cache operations, wherein the first flag is a signal from the sense amplifier and the second flag is a signal from serializer circuitry of the memory die.

4. The memory device of claim 1, wherein the controller is coupled to timing logic of the memory die to receive signals to monitor the cache operation.

5. The memory device of claim 4, wherein the memory die includes a lookup table accessible to determine, using the signal from the timing logic, a current to be consumed during a write operation or a read operation associated with the cache operation.

6. The memory device of claim 1 , wherein the operations comprise: determining availability of the power budget for a next cache operation; as well as In response to determining that the power budget is insufficient for the next cache operation, operation of the memory array is adjusted to free up an amount of the peak power budget for the cache operation.

7. The memory device of claim 1 , wherein the controller is capable of being configured as a control manager of controllers for a group of managed memory dies to allow selected dies of the group to operate during individual cache operations while allowing other dies of the group to suspend corresponding cache and memory array operations.

8. The memory device of claim 1 , wherein the operations comprise: monitoring operation of the memory array and the cache; as well as The total peak power used by the memory array and the cache is calculated.

9. The memory device of claim 8, wherein the controller is operable to communicate the calculated total peak power of the memory device to controllers of other memory dies arranged with the memory device in a peak power management group.

10. The memory device of claim 1, wherein the controller includes a filter to eliminate pauses in data transfer for a current budget of the cache and the memory array to control the current budget.

11. The memory device of claim 10, wherein the filter includes a timer to release a cache operation budget in response to the timer reaching a filter time without a new cache operation occurring.

12. The memory device of claim 1, wherein the controller is operable to feed a signal back to a memory controller to adjust an operating speed of an interface from the memory controller to the memory die.

13. A memory device comprising: an input node receiving a supply voltage; as well as a plurality of memory dies coupled to the input node forming a peak power management group, wherein each memory die of the plurality of memory dies comprises: memory arrays; a cache that stores data in a data path to or from the memory array; A controller comprising processing circuitry including one or more processors, the controller configured to perform operations comprising: controlling a power budget for the cache and the memory array by using a first flag received from a data path identifying the start of a cache operation performed on the data and a second flag received from the data path identifying the end of the cache operation; as well as A connection is provided to output data regarding the power budget to one or more other memory dies of the peak power management group.

14. The memory device of claim 13, wherein the controller is operable to feed back a signal to memory controllers or interface controllers of the plurality of memory dies to adjust an operating speed of an interface of the memory dies.

15. The memory device of claim 14, wherein the signal is a switching signal, or an analog signal generated by opening or closing different paths in the memory die.

16. The memory device of claim 13, wherein the cache is a page buffer of the memory die used for write cache operations, wherein the first flag is a signal from deserializer circuitry of the memory die and the second flag is a signal from the page buffer.

17. The memory device of claim 13, wherein the cache is a sense amplifier of the memory die used for read cache operations, wherein the first flag is a signal from the sense amplifier and the second flag is a signal from serializer circuitry of the memory die.

18. The memory device of claim 13, wherein the controller is coupled to timing logic of the memory die to receive signals to monitor the cache operation.

19. The memory device of claim 18, wherein each memory die includes a lookup table accessible to determine current to be consumed during a write operation or a read operation associated with the cache operation using the signal from the timing logic of the memory die.

20. The memory device of claim 13, wherein for operation as part of the peak power management group, one of the memory dies is provided as a manager for the one or more other memory dies of the plurality of memory dies.

21. A method of controlling peak power management in a memory device, the method comprising: monitoring a data path to or from a memory array of a memory die, the data path including a cache used to store data; identifying, at logic circuitry of the memory die, a start of a cache operation on the data using a first flag received from the data path; identifying, at the logic circuitry of the memory die, an end of the cache operation using a second flag received from the data path; as well as The start and end of the cache operation are used in the logic circuitry of the memory die to control a power budget for the cache and the memory array.

22. The method of claim 21, wherein the method comprises: receiving, at the logic circuitry of the memory die, a signal from sequential logic of the memory die to monitor the cache operation; accessing information from a lookup table in the memory die, the information including a programmed timing pattern or operating speed of current for the data path; as well as The signals from the sequential logic and the information are used in the logic circuitry of the memory die to determine a current to be consumed during a write operation or a read operation associated with the cache operation.

23. The method of claim 21, wherein the method comprises: calculating, in the logic circuitry of the memory die, a total peak power used by the memory array and the cache; and The calculated total peak power is transferred to another memory die that is arranged into a peak power management group with the memory die.

24. The method of claim 21, wherein controlling the power budget for the cache and the memory array comprises using filters to eliminate pauses in data transfers with respect to the current budgets of the cache and the memory array.

25. The method of claim 21, wherein the method includes feeding back a signal through an interface to a memory controller coupled to the memory die to adjust an operating speed of the interface.

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