Gate etching method, device preparation method, device, and equipment for GaN HEMT device

Abstract

The present invention provides a gate etching method for a GaN HEMT device, comprising: etching a P-type layer on a barrier layer; using the first patterned barrier layer as a mask, performing a first etching on the first P-type layer, and performing a first chemical treatment on the exposed side of the remaining first P-type layer; forming a second patterned barrier layer on the surface of the remaining P-type layer; using the second patterned barrier layer as a mask, performing a second etching on the second P-type layer to form a step structure; performing a second chemical treatment on the exposed side of the remaining second P-type layer and the exposed surface of the barrier layer; the method effectively suppresses charge movement from the barrier layer, eliminates sidewall defects of the P-type layer and surface defects of the barrier layer generated during the etching process, effectively reduces leakage and charge transfer to the gate, thereby improving the stability and reliability of the threshold voltage and solving a certain degree of drift phenomenon after long-term use.

Description

Technical Field

[0001] The present invention relates to the field of transistor devices, and in particular to a gate etching method, a device preparation method, a device, and equipment for a GaN HEMT device. Background Art

[0002] Gallium nitride on silicon high electron mobility transistors (GaN HEMTs) are widely used in power switching systems due to their high temperature resistance, high efficiency, high breakdown voltage, and low on-resistance. Devices with AlGaN / GaN epitaxial structures are normally-on devices, while traditional circuit topologies require devices to be normally off. Currently commercially available structures often utilize a p-GaN / AlGaN / GaN epitaxial structure to achieve normally-off devices.

[0003] However, existing p-GaN normally-off devices suffer from high gate leakage, low threshold voltage, and drift after long-term use. These problems are not conducive to the commercialization of p-GaN / AlGaN / GaN devices and require further improvement. Summary of the Invention

[0004] The present invention provides a gate etching method, a device preparation method, a device, and an apparatus for a GaN HEMT device, so as to solve the problems of large gate leakage, low threshold voltage, and drift after long-term use.

[0005] According to a first aspect of the present invention, a gate etching method for a GaN HEMT device is provided, comprising the following steps:

[0006] A nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-type layer are sequentially formed on the substrate in a direction away from the substrate; wherein,

[0007] The P-type layer includes a second P-type layer and a first P-type layer formed on the second P-type layer;

[0008] forming a first patterned barrier layer on the surface of the P-type layer;

[0009] Using the first patterned barrier layer as a mask, performing a first etching on the first P-type layer to remove the first P-type layer outside the area covered by the first patterned barrier layer, thereby exposing the second P-type layer;

[0010] performing a first chemical treatment on the exposed sidewalls of the remaining first P-type layer to eliminate sidewall defects;

[0011] removing the first patterned barrier layer; and forming a second patterned barrier layer on the surface of the remaining P-type layer;

[0012] Using the second patterned barrier layer as a mask, etching the second P-type layer for a second time to expose the barrier layer, so that the remaining second P-type layer and the remaining first P-type layer after the second etching form a step structure;

[0013] performing a second chemical treatment on the remaining exposed sidewalls of the second P-type layer and the exposed surface of the barrier layer;

[0014] removing the patterned second barrier layer;

[0015] forming a dielectric layer, wherein the dielectric layer covers the surface of the remaining P-type layer and the surface of the exposed barrier layer;

[0016] Wherein, the etching rate of the P-type layer by the second etching is lower than the etching rate of the P-type layer by the first etching.

[0017] Optionally, the material of the first patterned blocking layer and / or the second patterned blocking layer is any one of photoresist, SiNx, SiO2 or a combination thereof.

[0018] Optionally, the first etching uses a first etching gas.

[0019] Optionally, the first etching gas is ICP etching gas.

[0020] Optionally, the ICP etching gas is any one of Cl2, BCl, and N2.

[0021] Optionally, the second etching uses a second etching gas.

[0022] Optionally, the second etching gas is a combination of a Cl-based etching gas and an O-based etching gas.

[0023] Optionally, the material of the dielectric layer is any one of SiO2, SiNx, high-K dielectric materials, or a combination thereof.

[0024] Optionally, the nucleation layer is made of AlN, the buffer layer is made of GaN / AlGaN, the channel layer is made of GaN, the barrier layer is made of AlxGa1-xN; and the P-type layer is made of P-type GaN.

[0025] According to a second aspect of the present invention, a method for preparing a GaN HEMT device is provided, comprising: a gate etching method for a GaN HEMT device according to any one of the first aspect of the present invention.

[0026] According to a third aspect of the present invention, a GaN HEMT device is provided, which is manufactured using the manufacturing method provided by the second aspect of the present invention.

[0027] According to a fourth aspect of the present invention, an electronic device is provided, comprising the GaN HEMT device according to the third aspect of the present invention.

[0028] The present invention provides a gate etching method for a GaN HEMT device, wherein the P-type layer is etched twice, and during this process, a first chemical treatment is performed on the exposed side surface of the remaining first P-type layer, and a second chemical treatment is performed on the exposed sidewall of the remaining second P-type layer and the exposed surface of the barrier layer. This method not only effectively suppresses charge movement from the barrier layer by forming a stepped P-type layer through the two etching steps, but also eliminates sidewall defects of the P-type layer and surface defects of the barrier layer generated during the etching process, effectively reducing leakage and charge transfer to the gate, thereby improving the stability and reliability of the threshold voltage and resolving the problem of drift after a certain degree of long-term use. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 Schematic diagram of etching steps of a gate etching method for a GaN HEMT device according to the present invention;

[0031] Figure 2 Schematic diagram of the device structure at different stages of gate etching of a GaN HEMT device in one embodiment of the present invention Figure 1 ;

[0032] Figure 3 Schematic diagram of the device structure at different stages of gate etching of a GaN HEMT device in one embodiment of the present invention Figure 2 ;

[0033] Figure 4 Schematic diagram of the device structure at different stages of gate etching of a GaN HEMT device in one embodiment of the present invention Figure 3 ;

[0034] Description of reference numerals:

[0035] 101-substrate;

[0036] 102-nucleation layer;

[0037] 103- buffer layer;

[0038] 104-channel layer;

[0039] 105-barrier layer;

[0040] 106- second P-type layer;

[0041] 107-first P-type layer;

[0042] 108-first patterned barrier layer;

[0043] 109-second patterned barrier layer;

[0044] 201-gate;

[0045] 202-drain contact;

[0046] 203-source contact;

[0047] 204-Dielectric layer. DETAILED DESCRIPTION

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0049] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0050] Gallium nitride on silicon (GaN) high electron mobility transistors (HEMTs) are widely used in power switching systems. Currently commercially available structures often utilize a p-GaN / AlGaN / GaN epitaxial structure to achieve a normally-off device.

[0051] When a bias is applied between the source and drain contacts of a GaN HEMT device, current flows between the source and drain contacts, primarily through a two-dimensional region containing a two-dimensional electron gas (2DEG) and a thin barrier layer. During this process, the charge in the barrier layer is transferred to the gate due to the thinness of the barrier layer, causing current to leak into the gate, thereby forming an unwanted current from the source to the gate.

[0052] To address the aforementioned issues, a p-type layer is placed between the barrier layer and the gate in GaN HEMT devices to block charge movement from the barrier layer. For devices with an added p-type layer, the applicant has discovered through experiments and verification that if conventional etching techniques are used alone to prepare the p-type layer, the entire p-type layer should be etched in a single pass. However, due to the uneven etching depth achieved with conventional etching methods, over- and under-etching of the p-type layer can occur. Furthermore, after etching, a large number of dangling bonds remain on the sidewalls of the p-type layer and on the surface of the barrier layer, resulting in surface defects in the barrier layer and sidewall defects in the p-type layer.

[0053] Because GaN HEMT devices fabricated using traditional etching techniques have surface defects in the barrier layer and sidewall defects in the P-type layer, gate leakage occurs, affecting the stability and reliability of the threshold voltage. In addition, large gate leakage results in a low threshold voltage, which can drift after long-term use.

[0054] Therefore, the applicant discovered that the problem that needs to be solved in GaN HEMT devices is: how to eliminate the sidewall defects of the P-type layer and the surface defects of the barrier layer so that the P-type layer obtained by etching can effectively block the transfer of charge from the barrier layer to the gate, thereby improving the stability and reliability of the threshold voltage and solving the drift phenomenon that occurs after a certain degree of long-term use.

[0055] In view of this, the present invention creatively proposes a method for etching the P-type layer in batches, eliminating the sidewall defects of the P-type layer and the surface defects of the barrier layer through two chemical treatments, wherein the surface defects of the barrier layer are further reduced by reducing the rate of the second etching of the P-type layer.

[0056] The GaN HEMT device formed by the stepped P-type layer obtained by the technical solution proposed in the present invention not only effectively suppresses the charge movement from the barrier layer, but also eliminates the sidewall defects of the P-type layer and the surface defects of the barrier layer generated during the etching process, effectively reducing leakage and charge transfer to the gate, thereby improving the stability and reliability of the threshold voltage and solving the drift phenomenon that may occur after long-term use to a certain extent.

[0057] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0058] Please refer to Figures 1-4 According to an embodiment of the present invention, a gate etching method for a GaN HEMT device is provided, comprising the following steps:

[0059] S11 : forming a nucleation layer 102 , a buffer layer 103 , a channel layer 104 , a barrier layer 105 , and a P-type layer in sequence on a substrate 101 in a direction away from the substrate.

[0060] The channel layer 104 and the barrier layer 105 form a lateral heterojunction structure, and the lateral heterojunction structure is located on the buffer layer 103;

[0061] There is a two-dimensional electron gas 2DEG (not shown in the figure) at the interface of the lateral heterojunction structure, and the source contact 203 and the drain contact 202 are connected through the two-dimensional electron gas 2DEG;

[0062] The interface of the lateral heterojunction structure refers to the contact surface between the barrier layer 105 and the channel layer 104 .

[0063] In one embodiment, the nucleation layer 102, buffer layer 103, channel layer 104, barrier layer 105, and P-type layer in step S11 are all rectangular parallelepiped structures, and thus the ultimately formed cellular structure is also a rectangular parallelepiped structure. In other embodiments, the nucleation layer 102, buffer layer 103, channel layer 104, barrier layer 105, and P-type layer may be a cubic structure or other structures, as long as they are applicable to the cellular structure of the GaN HEMT device, they are all within the scope of protection of the present invention.

[0064] The P-type layer includes a second P-type layer 106 and a first P-type layer 107 formed on the second P-type layer 106;

[0065] The first P-type layer is the target of the first etching, and the second P-type layer is the target of the second etching;

[0066] The first P-type layer 107 and the second P-type layer 106 both belong to the P-type layer, and there is no interface between the first P-type layer 107 and the second P-type layer 106 . They are distinguished here only for the convenience of describing the step-by-step etching steps.

[0067] In one embodiment, the thickness of the first P-type layer 107 is greater than that of the second P-type layer 106; of course, the thickness of the first P-type layer 107 may also be equal to or less than that of the second P-type layer 106; when the thickness of the first P-type layer is greater than that of the second P-type layer, that is, when the thickness of the P-type layer etched away by the first etching is greater than the thickness of the P-type layer etched away by the second etching, since the etching rate of the first etching is greater than the etching rate of the second etching, the etching process time is saved.

[0068] S12: forming a first patterned barrier layer 108 on the surface of the P-type layer.

[0069] The sidewalls of the first P-type layer 107 and the second P-type layer 106 are shown in FIG. Figure 2-Figure 4 Indicated by the arrow pointing diagonally in the middle.

[0070] Specifically, the first patterned barrier layer 108 covers a portion of the first P-type layer 107 .

[0071] The step of forming the first patterned barrier layer 108 specifically includes:

[0072] Covering the surface of the first P-type layer 107 with a first barrier layer;

[0073] The first barrier layer is patterned to form a first patterned barrier layer.

[0074] The first barrier layer may be any one of photoresist, SiNx, and SiO2, or a combination thereof. Taking the photoresist as an example, patterning the first barrier layer specifically includes exposing and developing the photoresist to form a first patterned photoresist, wherein the first patterned photoresist matches the shape of the first P-type layer 107 to be formed by etching, i.e., the shape of the first P-type layer 107 remaining after forming the step structure as described later.

[0075] When the first barrier layer is made of other materials, the patterning generally includes first forming a patterned photoresist on the first barrier layer, and then etching the first barrier layer using the patterned photoresist as a mask to form a patterned first barrier layer.

[0076] S13: using the first patterned barrier layer 108 as a mask, performing a first etching on the first P-type layer 107 to remove the first P-type layer 107 outside the area covered by the first patterned barrier layer 108, thereby exposing the second P-type layer 106; Figure 2 As shown;

[0077] Using the first patterned barrier layer 108 as a mask, the first P-type layer 107 is subjected to a first etching. Since the shape of the first patterned barrier layer 108 matches the shape of the remaining first P-type layer 107 in the step structure to be formed later, under the protection of the first patterned barrier layer 108, after the first etching, the shape of the remaining first P-type layer 107 matches the shape of the first patterned photoresist. The portion of the first P-type layer 107 not covered by the first patterned barrier layer 108 is completely etched away, and the remaining first P-type layer 107 ultimately forms a first step layer. After step S13 is completed, the upper surface of the first step layer is covered with the first patterned barrier layer 108.

[0078] The first stepped structure refers to the first P-type layer 107 constituting the stepped structure.

[0079] S14: performing a first chemical treatment on the remaining exposed side surfaces of the first P-type layer 107 to eliminate sidewall defects.

[0080] After the first etching, the first step layer has sidewall defects due to the sidewalls formed by the first etching. Therefore, the sidewalls of the first step structure need to be chemically treated for the first time to eliminate the sidewall defects and reduce leakage.

[0081] During the first chemical treatment, due to the protection of the first patterned barrier layer 108, the surface of the first step layer will not be damaged by the first chemical treatment, thereby avoiding additional losses caused by the first chemical treatment and ensuring the performance of the device.

[0082] S15: removing the first patterned barrier layer 108; see Figure 3 , forming a second patterned barrier layer 109 on the surface of the remaining P-type layer;

[0083] The second barrier layer is formed on the surface and sidewalls of the first P-type layer 107 and completely surrounds the sidewalls and a portion of the surface of the second P-type layer 106, thereby protecting the surface and sidewalls of the first P-type layer 107 and a portion of the surface of the second P-type layer 106 from being damaged during the second etching, thereby ensuring the performance of the device.

[0084] In one embodiment, after the first patterned barrier layer 108 is removed, the surface of the first step layer and the second P-type layer 106 are covered with photoresist, and then the photolithography is patterned to form a second step layer. The shape of the second step layer is the shape of the remaining second P-type layer 106 obtained after the second etching in the steps described later.

[0085] In another embodiment, the step of removing the first patterned barrier layer 108 in step S15 may not be performed, and the first patterned barrier layer 108 and the portion newly formed on the second P-type layer 106 constitute the second patterned barrier layer 109 .

[0086] S16: Using the second patterned barrier layer 109 as a mask, perform a second etching on the second P-type layer 106 to expose the barrier layer 105 , so that the remaining second P-type layer 106 and the remaining first P-type layer 107 after the second etching form a step structure.

[0087] Under the protection of the second patterned barrier layer 109, the corresponding second step layer is etched to match the shape of the second patterned photoresist; the shapes of the second step layer, the first step layer, the first patterned barrier layer 108, and the second patterned barrier layer 109 are all the shapes of the top view of the corresponding structural layer.

[0088] The second P-type layer 106 not covered by the second patterned barrier layer 109 is etched away.

[0089] During the second etching, the second patterned barrier layer 109 not only protects the second P-type layer 106 to form the second stepped layer, but also protects the surface and sidewall of the first stepped layer from being damaged.

[0090] Wherein, the etching rate of the P-type layer by the second etching is lower than the etching rate of the P-type layer by the first etching.

[0091] During the second etching process, the portion of the second P-type layer 106 that is not protected by the second patterned barrier layer 109 will gradually be etched until the surface of the barrier layer 105 is exposed. Since the barrier layer 105 will gradually lose the protection of the second P-type layer, it is difficult to control the barrier layer 105 from being damaged or to reduce the loss while achieving complete etching of the second P-type layer 106 outside the second patterned barrier layer 109 in actual operation. Therefore, this solution reduces the etching rate of the second etching to reduce the surface loss of the barrier layer 105, thereby overcoming the operational difficulties.

[0092] S17: performing a second chemical treatment on the remaining exposed sidewalls of the second P-type layer 106 and the exposed surface of the barrier layer 105;

[0093] The second chemical treatment eliminates the surface defects of the sidewalls of the second P-type layer 106 and the surface defects of the barrier layer 105 , thereby further solving the above-mentioned problems in actual operation.

[0094] S18: removing the patterned second barrier layer.

[0095] In the GaN HEMT device obtained by etching the P-type layer using the present technical solution, the P-type layer can effectively block the charges from the barrier layer 105 .

[0096] S19: forming a dielectric layer, the dielectric layer covering the surface of the remaining P-type layer and the surface of the exposed barrier layer 105; the schematic diagram of the device structure after this step is completed is shown in FIG. Figure 4 .

[0097] Through the above steps of this embodiment, a cellular structure is finally formed. The surface of the finally formed cellular structure also includes a source contact 203 formed in the source region and a drain contact 202 in the drain region, and a gate formed on the P-type layer, wherein the drain contact 202, the source contact 203 and the gate are not covered with a dielectric layer.

[0098] In one embodiment, the first etching process uses a first etching gas. For example, the first etching gas may be an ICP etching gas. As a specific embodiment, the ICP etching gas is any one of Cl 2 , BCl 2 , and N 2 . Of course, it should be appreciated that other types of etching gases may also be used for the first etching process, and the present invention is not limited thereto.

[0099] In one embodiment, the second etching process uses a second etching gas. As a preferred embodiment, the second etching gas etches the second P-type layer 106 at a rate that is lower than the first etching gas etches the second P-type layer 106. Thus, the second etching gas is used as a means to reduce the second etching rate, thereby overcoming the aforementioned practical difficulties.

[0100] As an embodiment, the second etching gas is a combination of a Cl-based etching gas and an O-based etching gas. Of course, it should be appreciated that other types of etching gases may also be used for the second etching, and the present invention is not limited thereto.

[0101] In one embodiment, the material of the dielectric layer is any one of SiO2, SiNx, high-K dielectric materials, or a combination thereof.

[0102] In one embodiment, the nucleation layer 102 is made of AlN, the buffer layer 103 is made of GaN / AlGaN, the channel layer 104 is made of GaN, the barrier layer 105 is made of AlxGa1-xN; and the P-type layer is made of P-type GaN.

[0103] The present invention belongs to the field of gallium nitride power semiconductor devices. By performing two different etching processes on the gate p-GaN, steps are formed on both sides of the p-GaN, reducing defects on the p-GaN sidewalls and lowering the AlGaN surface defect density. The gate p-GaN refers to a p-type layer formed between the gate and the barrier layer, and the material of the p-type layer is GaN.

[0104] Furthermore, since the sidewall defects of the P-type layer and the surface defects of the barrier layer generated during the etching process are reduced, gate leakage is reduced and charge movement from the barrier layer is effectively suppressed, thereby improving the threshold voltage stability and reliability.

[0105] In addition, in other embodiments of the present invention, a method for preparing a GaN HEMT device is provided, comprising: a gate etching method for a GaN HEMT device provided in the aforementioned embodiment of the present invention.

[0106] Furthermore, in other embodiments of the present invention, a GaN HEMT device is provided. The device is specifically manufactured using the aforementioned method for manufacturing the GaN HEMT device.

[0107] In addition, in other embodiments of the present invention, an electronic device is provided, comprising the aforementioned GaN HEMT device.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate etching method for a GaN HEMT device, characterized in that: The following steps are involved: A nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-type layer are sequentially formed on the substrate in a direction away from the substrate; wherein, The P-type layer includes a second P-type layer and a first P-type layer formed on the second P-type layer, wherein the first P-type layer is thicker than the second P-type layer; forming a first patterned barrier layer on the surface of the P-type layer; Using the first patterned barrier layer as a mask, performing a first etching on the first P-type layer to remove the first P-type layer outside the area covered by the first patterned barrier layer, thereby exposing the second P-type layer; performing a first chemical treatment on the exposed sidewalls of the remaining first P-type layer to eliminate sidewall defects; removing the first patterned barrier layer; and forming a second patterned barrier layer on the surface of the remaining P-type layer; Using the second patterned barrier layer as a mask, etching the second P-type layer for a second time to expose the barrier layer, so that the remaining second P-type layer and the remaining first P-type layer after the second etching form a step structure; performing a second chemical treatment on the remaining exposed sidewalls of the second P-type layer and the exposed surface of the barrier layer; removing the patterned second barrier layer; forming a dielectric layer, wherein the dielectric layer covers the surface of the remaining P-type layer and the surface of the exposed barrier layer; Wherein, the etching rate of the P-type layer by the second etching is lower than the etching rate of the P-type layer by the first etching.

2. The gate etching method of a GaN HEMT device according to claim 1, characterized in that: The material of the first patterned blocking layer and / or the second patterned blocking layer is any one of photoresist, SiNx, SiO2 or a combination thereof.

3. The gate etching method of a GaN HEMT device according to claim 1, wherein: The first etching uses a first etching gas.

4. The gate etching method of a GaN HEMT device according to claim 3, characterized in that: The first etching gas is ICP etching gas.

5. The gate etching method of a GaN HEMT device according to claim 4, characterized in that: The ICP etching gas is any one of Cl2, BCl, and N2.

6. The gate etching method of a GaN HEMT device according to claim 1, wherein: The second etching uses a second etching gas.

7. The gate etching method of a GaN HEMT device according to claim 6, characterized in that: The second etching gas is a combination of a Cl-based etching gas and an O-based etching gas.

8. The gate etching method of a GaN HEMT device according to claim 1, wherein: The material of the dielectric layer is any one of SiO2, SiNx, high-K dielectric materials, or a combination thereof.

9. The gate etching method of a GaN HEMT device according to claim 1, wherein: The material of the nucleation layer is AlN, the material of the buffer layer is GaN / AlGaN, the material of the channel layer is GaN, and the material of the barrier layer is Al x Ga 1-x N; the material of the P-type layer is P-type GaN.

10. A method for preparing a HEMT device, characterized in that: include: The gate etching method for a GaN HEMT device according to any one of claims 1 to 9.

11. A GaN HEMT device, characterized in that: Prepared by the preparation method according to claim 10.

12. An electronic device comprising the GaN HEMT device according to claim 11.

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