A MOM capacitor

Abstract

Disclosed is a MOM capacitor, comprising: a substrate; a first conductive layer on the substrate, the first conductive layer being a conductive plate; a second conductive layer on the first conductive layer, the second conductive layer comprising a plurality of first electrode strips and a plurality of second electrode strips spaced apart from each other; a third conductive layer on the second conductive layer, the third conductive layer being a conductive plate; and a plurality of through holes for electrically connecting the first electrode strips to the first conductive layer and the third conductive layer to form a first electrode, and electrically connecting the plurality of second electrode strips to form a second electrode, the second electrode being opposite in polarity to the first electrode; wherein the first electrode strips and the second electrode strips are alternately arranged in a surrounding manner in a plane in which the second conductive layer is located; one of the plurality of second electrode strips is located at the center of the plane in which the second conductive layer is located, and one of the plurality of first electrode strips is located at the edge of the plane in which the second conductive layer is located.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOM capacitor. Background Art

[0002] In the field of capacitor array structures, capacitors are very important basic components. Metal-Oxide-Metal (MOM) capacitors and Metal-Insulator-Metal (MIM) capacitors are two common capacitor structures. MIM capacitors use metal patterns located on the same layer or on different layers to form the same electrode, and their capacitance value is mainly composed of the capacitance formed by different conductor layers. MOM capacitors use metal patterns on the same layer to simultaneously form two electrodes with opposite polarities, so their capacitance value can include the capacitance formed by the same conductor layer.

[0003] refer to Figure 1 As shown, MOM capacitor 100 includes substrate 101 and conductor layer M1, conductor layer M1 includes a first electrode 102 and a second electrode 103 of two comb-shaped structures, the first electrode and the second electrode having opposite polarities, and the electrode strips respectively included in the two comb-shaped structures are staggered so as to form a capacitor between the electrode strips of different electrodes, and the capacitance value of capacitor 100 is equal to the sum of the capacitances formed by these electrode strips. This design mode of MOM capacitor helps to improve the capacitance per unit area, thereby helping to reduce the area occupied by MOM capacitors, and then helps to improve the integration of semiconductor circuits. In order to increase the capacitance value, Figure 1 The MOM capacitor shown can also adopt a stacked design so that the total capacitance is mainly equal to the sum of the capacitance in the same layer, the capacitance between different layers, and the capacitance between each electrode strip and the through hole.

[0004] However, for a capacitor array with a large number of capacitors, the size of the capacitor array is huge. Figure 1 The MOM capacitor shown needs further improvement to further reduce the size of the capacitor. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a MOM capacitor to improve the utilization rate of capacitance area.

[0006] The present invention provides a MOM capacitor, comprising:

[0007] substrate;

[0008] a first conductive layer located on the substrate, wherein the first conductive layer is a conductive plate;

[0009] a second conductive layer located on the first conductive layer, the second conductive layer comprising a plurality of first electrode strips and second electrode strips separated from each other;

[0010] a third conductive layer located on the second conductive layer, wherein the third conductive layer is a conductive plate; and

[0011] a plurality of through holes for electrically connecting the first electrode strips to the first conductive layer and the third conductive layer to form a first electrode, and a plurality of the second electrode strips are electrically connected to each other to form a second electrode, wherein the second electrode has an opposite polarity to the first electrode; and

[0012] Among them, the first electrode strips and the second electrode strips are alternately arranged in an encircling shape on the plane where the second conductive layer is located; the one located at the center of the plane where the second conductive layer is located is one of the multiple second electrode strips, and the one located at the edge of the plane where the second conductive layer is located is one of the multiple first electrode strips.

[0013] Preferably, the first electrode strips and the second electrode strips are in the shape of one or more of rectangles, circles, polygons or irregular shapes, so as to form first electrode strips and second electrode strips that are surrounded and alternately distributed on the plane where the second conductive layer is located.

[0014] Preferably, the second conductive layer further comprises a third electrode strip for connecting the second electrode strips separated from each other;

[0015] The third electrode strip is isolated from the first electrode strip;

[0016] The second electrode strips and the third electrode strips connected to the second electrode strips form a second electrode.

[0017] Preferably, the third electrode strip is a straight line, one end of which is connected to the innermost second electrode strip; the other end passes through the opening of the first electrode strip and extends to the outermost second electrode strip.

[0018] Preferably, the first conductive layer, the second conductive layer and the third conductive layer are made of metal.

[0019] Preferably, the MOM capacitor includes a plurality of stacked second conductive layers, and the plurality of through holes are further used to electrically connect the first electrode strips of the second conductive layers of adjacent layers together, and to electrically connect the second electrode strips of the second conductive layers of adjacent layers together.

[0020] Preferably, the first conductive layer and the third conductive layer at least shield the second electrode strips.

[0021] Preferably, a virtual layer is further included between the substrate and the first conductive layer, and the virtual layer includes a well layer, an active layer, a virtual active layer and a virtual gate layer from bottom to top, wherein the well layer and the active layer are connected through contact holes.

[0022] Preferably, projections of the first conductive layer and the second conductive layer on the substrate fall into the region where the well layer is located.

[0023] In the MOM capacitor provided by the present invention, the electrode strips serving as the first electrode and the electrode strips serving as the second electrode in the second conductive layer are spaced and alternately arranged in an encircling manner, with the innermost layer being the second electrode and the outermost layer being the first electrode. The electrode strips serving as the first electrode and the electrode strips serving as the second electrode in the second conductive layer are radiated outward from the center of the layer in a circle-enclosing manner, such that the arrangement of the electrode strips is compact. Compared with the electrode distribution in the prior art, the embodiment of the present invention achieves the same capacitance value, requires a smaller line width and spacing between the first electrode and the second electrode, and further requires a smaller area. That is, within the same area, the density of the embodiment is higher, the utilization rate is higher, and the cost is lower.

[0024] Furthermore, since each second electrode strip is surrounded by a first electrode strip and the second electrode strip does not face the power ground, the size of the MOM capacitor can be flexibly adjusted (for example, the middle circle of second electrode strips can be directly deleted) while the area and capacitance to ground remain unchanged, and layout work is convenient.

[0025] Furthermore, since each second electrode strip is surrounded by a first electrode strip and the second electrode strip does not face the power ground, the area and capacitance to ground can be kept unchanged. The capacitance value can be easily adjusted by adjusting the line width of the first electrode and the spacing between the first electrode and the second electrode, making the layout design work easier.

[0026] Furthermore, the MOM capacitor provided by the embodiment of the present invention uses the electrode strips of the first electrode to protect the electrode strips of the second electrode, thereby introducing parasitic capacitance only between the power ground and the first electrode, and the parasitic capacitance between the second electrode and the power ground can be basically ignored.

[0027] In a preferred embodiment, the overall capacitance value of the MOM capacitor is increased by the fourth conductive layer and the second conductive layer of the stacked design.

[0028] In a preferred embodiment, a well layer, an active layer, a virtual active layer and a virtual gate layer are provided in the semiconductor substrate to block noise from the semiconductor substrate, thereby preventing noise from entering the MOM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0030] Figure 1 Shown is a structural diagram of a MOM capacitor in the prior art;

[0031] Figure 2 A schematic diagram of the three-dimensional structure of a MOM capacitor according to a first embodiment of the present invention is shown;

[0032] Figure 3 shows a schematic top view of the structure of the second conductive layer according to the first embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the three-dimensional structure of a MOM capacitor according to a second embodiment of the present invention is shown;

[0034] Figure 5 shows a top view of a conductor layer according to a second embodiment of the present invention;

[0035] Figure 6 A schematic diagram showing a projection of a second through hole between a conductor layer and a first conductive layer on the first conductive layer according to a second embodiment of the present invention is shown;

[0036] Figure 7 A schematic diagram of a projection of a first through hole between the second conductive layer and the third conductive layer on the third conductive layer according to the second embodiment of the present invention is shown;

[0037] Figure 8 A schematic diagram of the projection structure of the third through hole and the fourth through hole on the conductor layer according to the second embodiment of the present invention is shown;

[0038] Figure 9 A cross-sectional view of a MOM capacitor according to a third embodiment of the present invention is shown. DETAILED DESCRIPTION

[0039] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0040] The present invention may be embodied in various forms, some examples of which are described below.

[0041] Figure 2 FIG. 4 shows a schematic diagram of the three-dimensional structure of a MOM capacitor 200 according to a first embodiment of the present invention; FIG. Figure 2As shown, the MOM capacitor 200 includes a substrate 201, a plurality of conductive layers 202 located on the substrate 201, and an insulating layer (not shown) filled between each conductive layer 202 and between electrode strips of the same conductive layer 202. The conductive layer 202 includes a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23.

[0042] Each of the first to third conductive layers 21, 23 can be made of various metals. The first conductive layer 21 is located above the substrate 201. The first and third conductive layers 21, 23 form a metal plate without any openings or hollows. A second conductive layer 22 is formed above the first conductive layer 21. A third conductive layer 23 is formed above the second conductive layer 22. The second conductive layer 22 includes a plurality of electrode strips. A portion of the electrode strips in the second conductive layer 22 are electrically connected to the first and third conductive layers 21, 23 via the through-holes 203 to form first electrodes. The remaining portion of the electrode strips in the second conductive layer 22 form second electrodes. The first and second electrodes have opposite polarities.

[0043] Figure 3 FIG. 4 shows a schematic top view of the second conductive layer according to the first embodiment of the present invention. Figure 3 As shown, the second conductive layer 22 includes a plurality of first electrode strips 221 and second electrode strips 222 separated from each other. The plurality of first electrode strips 221 and second electrode strips 222 separated from each other are arranged alternately and spaced in a surrounding manner on the plane where the second conductive layer 22 is located. The plurality of second electrode strips 222 are located at the center of the plane where the second conductive layer 22 is located, and the plurality of first electrode strips 221 are located at the edge of the plane where the second conductive layer 22 is located, so as to ensure that each second electrode strip 222 is surrounded by a first electrode strip 221. The plurality of second electrode strips 222 are electrically connected to each other via third electrode strips 223.

[0044] In this embodiment, the first electrode strips 221 and the second electrode strips 222 are spaced apart and alternately arranged in a "U" shape on the plane where the second conductive layer 22 is located. Specifically, the second conductive layer 22 includes two first electrode strips 221 and two second electrode strips 222, namely the first electrode strip 2211, the first electrode strip 2212, the second electrode strip 2221, and the second electrode strip 2222. Among them, on the plane where the entire second conductive layer 22 is located, the second electrode strips 2221, the first electrode strips 2211, the second electrode strips 2222, and the first electrode strips 2212 are arranged in a "U" shape from the inside to the outside.

[0045] Specifically, the second electrode strip 2221 is rectangular and located at the center of the plane of the entire second conductive layer 22. The first electrode strip 2211 is a rectangular frame surrounding the second electrode strip 2221 and is isolated from the second electrode strip 2221. The first electrode strip 2211 has an opening for the third electrode strip 223 to pass through. The second electrode strip 2222 is a rectangular frame surrounding the first electrode strip 2211 and is isolated from the first electrode strip 2211. The first electrode strip 2212 is a rectangular frame surrounding the second electrode strip 2222 and is isolated from the second electrode strip 2222. The first electrode strip 2212 has an opening for the third electrode strip 223 to pass through. The third electrode strip 223 is a straight line, one end of which is connected to the second electrode strip 2221 and the other end extends outward through the openings of the first electrode strip 2211 and the first electrode strip 2212 to achieve connection between the second electrode strip 2221 and the second electrode strip 2222 and electrical connection between adjacent MOM capacitors.

[0046] In the MOM capacitor 200, the first conductive layer 21, the third conductive layer 23, and the second conductive layer 22. A portion of the electrode strips (first electrode strips) electrically connected to the first conductive layer 21 and the third electrode layer 23 serve as first electrodes, and the remaining portion of the electrode strips (second electrode strips and third electrode strips) of the second conductive layer 22 serve as second electrodes. The first electrode and the second electrode have opposite polarities, thereby forming a capacitor between the first electrode and the second electrode.

[0047] In this embodiment, the electrode strips serving as the first electrodes and the electrode strips serving as the second electrodes in the second conductive layer are spaced and alternately arranged in a "U" shape, with the innermost layer being the second electrodes and the outermost layer being the first electrodes; the electrode strips serving as the first electrodes and the electrode strips serving as the second electrodes in the second conductive layer are radiated outward from the center of the layer in a circle-enclosing manner, so that the arrangement of the electrode strips is compact, which is different from the prior art (such as Figure 1 Compared with the distribution between the electrodes in the embodiment shown in FIG, the total spacing between the first electrode and the second electrode is larger within the same area, so that the capacitance between the first electrode and the second electrode is larger, and a larger capacitance value can be obtained for the same area. In other words, the present embodiment obtains a larger capacitance than the prior art (such as FIG). Figure 1 As shown in the figure, for the same capacitance value, the required line width and spacing of the first electrode and the second electrode are smaller, and the required area is further smaller, that is, within the same area, the density of this embodiment is higher, the utilization rate is higher, and the cost is lower.

[0048] Furthermore, in this embodiment, since the first and third conductive layers are planar and serve as first electrodes, only the first electrode faces the power ground, and thus parasitic capacitance is introduced only between the power ground and the first electrode opposite the power ground. The electrode strips serving as the second electrodes are surrounded by the electrode strips serving as the first electrodes, so the parasitic capacitance between the second electrode and the power ground is essentially negligible. Therefore, in this embodiment, the parasitic capacitance between the second electrode and the power ground can be significantly reduced. Furthermore, by increasing the surface area of ​​the first conductive layer, although the parasitic capacitance between the first electrode and the power ground also increases, the parasitic capacitance between the second electrode and the power ground can be further reduced.

[0049] Certainly, the surface area of ​​the first conductive layer also can suitably reduce to further reduce cost.For example, the surface area of ​​the first conductive layer can be reduced to each end of the electrode strip used as the second electrode in the second conductive layer just enough to block, although the parasitic capacitance between the second electrode and the power supply ground may increase like this, the amplitude of increase is within the tolerable range.Generally speaking, parasitic capacitance should be less than 5% of the capacitance value between the first electrode and the second electrode.In summary, although there is the parasitic capacitance between the first electrode and the power supply ground in the MOM capacitor that the present embodiment provides, because the second electrode is almost fully protected by the first electrode, the parasitic capacitance between the second electrode and the power supply ground is very little, even close to 0.

[0050] For the sake of convenience, Figure 3 A specific layout design is shown, but the implementation of the present invention is not limited to this layout design. Figure 3 The illustrated layout design is intended to illustrate the core concept that "the electrode strips serving as the first electrodes and the electrode strips serving as the second electrodes in the second conductive layer are spaced and alternately arranged in a "U" shape, with the innermost layer being the second electrode and the outermost layer being the first electrode." In other layout designs, any number of first and second electrode strips can be provided. In other layout designs, the shapes of the plurality of spaced-apart first and second electrode strips 221, 222 can also be circular, polygonal, or irregular, and the circular, polygonal, or irregular first and second electrode strips 221, 222 are spaced and alternately arranged on the plane of the second conductive layer 22. As long as the above core concept is met, the same or similar effects can be produced.

[0051] In the embodiment of the present invention, since each second electrode strip is surrounded by the first electrode strip and the second electrode strip does not face the power ground, it is possible to flexibly adjust the size of the MOM capacitor value while maintaining the area and capacitance to ground. In particular, when the layout work of the capacitor array has been completed, the middle circle of the second electrode strip can be directly deleted to adjust the size of the MOM capacitor value, which facilitates the layout work.

[0052] Furthermore, since each second electrode strip is surrounded by a first electrode strip and the second electrode strip does not face the power ground, the area and capacitance to ground can be kept unchanged. The capacitance value can be easily adjusted by adjusting the line width of the first electrode and the spacing between the first electrode and the second electrode, making the layout design work easier.

[0053] Figure 4 1 shows a schematic diagram of the three-dimensional structure of a MOM capacitor according to a second embodiment of the present invention; Figure 4 As shown, compared with the first embodiment, the MOM capacitor of this embodiment has a fourth conductive layer 301 added.

[0054] Figure 5 FIG. 3 shows a top view of the fourth conductive layer 301 according to the second embodiment of the present invention. Figure 5 As shown, the layout design of the fourth conductive layer 301 is substantially the same as the layout design of the second conductive layer 22 .

[0055] Specifically, the fourth conductive layer 301 includes a plurality of separated fourth electrode strips 321 and fifth electrode strips 322. The plurality of separated fourth electrode strips 321 and fifth electrode strips 322 are spaced and alternately arranged in a U-shaped pattern on the plane where the fourth conductive layer 301 is located. One of the plurality of fifth electrode strips 322 is located at the center of the plane where the fourth conductive layer 301 is located, and one of the plurality of fourth electrode strips 321 is located at the edge of the plane where the fourth conductive layer 301 is located, ensuring that each of the fifth electrode strips 322 is surrounded by a fourth electrode strip 321. The plurality of fifth electrode strips 322 are electrically connected to each other via a sixth electrode strip 623.

[0056] The number of fourth electrode strips 321 on the fourth conductive layer 301 is the same as the number of first electrode strips 221 on the second conductive layer 22, and the projection of the fourth electrode strips 321 on the second conductive layer 22 substantially overlaps with the projection of the first electrode strips 221 on the second conductive layer 22 on the second conductive layer 22. The number of fifth electrode strips 322 on the third conductive layer 23 is the same as the number of second electrode strips 222 on the second conductive layer 22, and the projection of the fifth electrode strips 322 on the second conductive layer 22 substantially overlaps with the projection of the second electrode strips 222 on the second conductive layer 22 on the second conductive layer 22.

[0057] The fourth conductive layer 301 includes a fourth electrode strip 3211, a fourth electrode strip 3212, a fifth electrode strip 3221, and a fifth electrode strip 3222. The fifth electrode strip 3221, the fourth electrode strip 3211, the fifth electrode strip 3222, and the fourth electrode strip 3212 form a "U" shape, arranged from the inside out, on the plane of the entire fourth conductive layer 301. The plurality of fifth electrode strips 322 are connected by sixth electrode strips 323, which are isolated from the fourth electrode strips 321.

[0058] The fifth electrode strip 3221 is located at the center of the plane of the entire fourth conductive layer 301, the fourth electrode strip 3211 is arranged around the fifth electrode strip 3221 and isolated from the fifth electrode strip 3221; the fifth electrode strip 3222 is arranged around the fourth electrode strip 3211 and isolated from the fourth electrode strip 3211; the fourth electrode strip 3212 is arranged around the fifth electrode strip 3222 and isolated from the fifth electrode strip 3222.

[0059] Different from the second conductive layer 22 , only the fourth electrode strips 3212 have openings, while the outermost fourth electrode strips 3212 have no openings. The sixth electrode strips 323 only pass through the inner fourth electrode strips 3212 and stop at the fifth electrode layer 3222 .

[0060] In this embodiment, the first electrode strip 221 of the second conductive layer 22 is electrically connected to the third conductive layer 23 via the first through hole 331; the fourth electrode strip 321 of the fourth conductive layer 301 is connected to the first conductive layer 21 via the second through hole 332; Figure 6 Schematic diagram of a projection of a second through hole 332 between the fourth conductive layer 301 and the first conductive layer 21 on the first conductive layer 21 according to the second embodiment of the present invention is shown; Figure 7 FIG. 3 is a schematic projection diagram of a first through hole 331 between the second conductive layer 22 and the third conductive layer 23 on the third conductive layer 23 according to the second embodiment of the present invention.

[0061] The first electrode strip 221 in the second conductive layer 22 and the corresponding fourth electrode strip 321 in the fourth conductive layer 301 , as well as the second electrode strip 222 in the second conductive layer 22 and the corresponding fifth electrode strip 322 in the fourth conductive layer 301 are connected via the third through hole 333 and the fourth through hole 334 , respectively. Figure 8 A schematic diagram of the projection structure of the third through hole and the fourth through hole on the fourth conductive layer 301 according to the second embodiment of the present invention is shown.

[0062] In this embodiment, the overall capacitance of the MOM capacitor is increased by the stacked fourth conductive layer 301 and the second conductive layer 22.

[0063] In other embodiments, a three-layer or higher stacked structure may be used to increase the overall capacitance of the capacitor, for example, by increasing the number of conductor layers. However, the core concept of such a layout design is essentially the same as the aforementioned layout design.

[0064] Figure 9 FIG. 4 shows a cross-sectional view of a MOM capacitor according to a third embodiment of the present invention. Figure 9 As shown, compared with the second embodiment, the MOM capacitor shown in this embodiment further includes a virtual layer located between the substrate 201 and the first conductive layer 21, and the virtual layer includes, from bottom to top, a well layer 401, an active layer 402, a virtual active layer 403 and a virtual gate layer 404, wherein the well layer 401 and the active layer 402 are connected via a contact hole 405.

[0065] For the semiconductor device according to the embodiment of the present invention, the well layer 401 and the active layer 402 can block the noise from the semiconductor substrate 201, thereby preventing the noise from entering the MOM capacitor.

[0066] Wherein, the projection of the MOM capacitor on the upper surface of the semiconductor substrate 201 can be made to fall completely into the region where the well layer 401 is located by adjusting the design scheme. This design can better prevent the noise from the semiconductor substrate 201 from entering the MOM capacitor.

[0067] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A MOM capacitor, characterized in that: include: substrate; a first conductive layer located on the substrate, wherein the first conductive layer is a conductive plate; a second conductive layer located on the first conductive layer, the second conductive layer comprising a plurality of first electrode strips and second electrode strips separated from each other; a third conductive layer located on the second conductive layer, wherein the third conductive layer is a conductive plate; as well as a plurality of through holes, used to electrically connect the first electrode strips to the first conductive layer and the third conductive layer to form a first electrode, and a plurality of the second electrode strips are electrically connected to each other to form a second electrode, wherein the second electrode has an opposite polarity to the first electrode; The first electrode strips and the second electrode strips are alternately arranged in a surrounding shape on the plane where the second conductive layer is located; the first electrode strip located at the center of the plane where the second conductive layer is located is one of the plurality of second electrode strips, and the second electrode strip located at the edge of the plane where the second conductive layer is located is one of the plurality of first electrode strips; It also includes a virtual layer located between the substrate and the first conductive layer, and the virtual layer includes a well layer, an active layer, a virtual active layer and a virtual gate layer from bottom to top, wherein the well layer and the active layer are connected through a contact hole.

2. MOM capacitor according to claim 1, characterized in that, The first electrode strips and the second electrode strips are in the shape of one or more of a circle, a polygon or an irregular shape, so as to form the first electrode strips and the second electrode strips which are surrounded and alternately distributed on the plane where the second conductive layer is located.

3. MOM capacitor according to claim 1, characterized in that, The second conductive layer further includes a third electrode strip for connecting the second electrode strips separated from each other; The third electrode strip is isolated from the first electrode strip; The second electrode strips and the third electrode strips connected to the second electrode strips form a second electrode.

4. MOM capacitor according to claim 3, characterized in that, The third electrode strip is a straight line, one end of which is connected to the innermost second electrode strip; the other end passes through the opening of the first electrode strip and extends to the outermost second electrode strip.

5. MOM capacitor according to claim 1, characterized in that, The first conductive layer, the second conductive layer and the third conductive layer are made of metal.

6. MOM capacitor according to claim 1, characterized in that, The MOM capacitor includes a plurality of stacked second conductive layers, and the plurality of through holes are further used to electrically connect the first electrode strips of the second conductive layers of adjacent layers together, and to electrically connect the second electrode strips of the second conductive layers of adjacent layers together.

7. The MOM capacitor according to claim 1, wherein The first conductive layer and the third conductive layer at least shield the second electrode strips.

8. The MOM capacitor according to claim 1, wherein Projections of the first conductive layer and the second conductive layer on the substrate fall into the region where the well layer is located.

Images