An active drive circuit and a parallel SiC MOSFET power module

Abstract

The active driving circuit disclosed by the present invention is disposed between the main SiC MOSFET and the slave SiC MOSFETs connected in parallel, and includes one main SiC MOSFET and at least one slave SiC MOSFET. The active driving circuit includes: a di / dt detection circuit I, a di / dt detection circuit II, a voltage-controlled current sinking source circuit, and a voltage-controlled current sourcing source circuit. Among them, the di / dt detection circuit I detects the voltage V sl across the source stray inductance L of the main SiC MOSFET sl ; the di / dt detection circuit II detects the voltage V sn across the source stray inductance L of the slave SiC MOSFET sn ; when the voltage V sl is greater than the voltage V sn , the voltage-controlled current sinking source circuit injects current from the gate of the slave SiC MOSFET to make the drain current of the slave SiC MOSFET approach the drain current of the main SiC MOSFET; when the voltage V sl is less than the voltage V sn , the voltage-controlled current sourcing source circuit extracts current from the gate of the slave SiC MOSFET to make the drain current of the slave SiC MOSFET approach the drain current of the main SiC MOSFET. The active driving circuit proposed by the present invention is simple, has a fast dynamic response, and has a good effect on solving the problem of dynamic current sharing imbalance of multiple parallel SiC MOSFETs.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit control. More specifically, the present invention relates to an active drive circuit and a parallel SiC MOSFET power module. Background Art

[0002] SiC MOSFETs are suitable for high-power and high-frequency application fields. The current-carrying capacity of a single discrete SiC MOSFET device is limited. To improve the current-carrying capacity, multiple discrete SiC MOSFET devices are usually used in parallel. Uneven dynamic current between parallel devices will cause uneven thermal distribution, and in extreme cases, overcurrent SiC MOSFETs will overheat and fail. Therefore, improving the dynamic current sharing of parallel SiC MOSFETs has practical significance.

[0003] The dynamic current sharing problem of SiC MOSFETs is closely related to the discreteness of the dynamic parameters of the devices themselves and the asymmetry of the stray parameters of the circuit. Measures to solve the uneven current sharing problem of SiC MOSFETs include:

[0004] (1) Classify devices according to the relevant parameter range of SiC MOSFETs for parallel use;

[0005] (2) Improve the symmetry of the printed circuit wiring of the drive and power circuits of parallel SiC MOSFETs. (1) and (2) propose current sharing methods that are effective under certain specific influencing factors, but the applicability is insufficient;

[0006] (3) Connecting a coupling inductor in series at the drain of each parallel SiC MOSFET is a solution with relatively good effects, but this method is not suitable for more than two SiC MOSFET devices in parallel, and the volume increases relatively large;

[0007] (4) Implementing current sharing drive based on a digital chip CPLD or FPGA, its disadvantages are slow dynamic response, unsatisfactory current sharing effect during high-frequency operation, and complex control circuits. Summary of the Invention

[0008] The present invention provides an active drive circuit to improve the above problems.

[0009] The present invention is implemented as follows. An active drive circuit is provided between a main SiC MOSFET and a slave SiC MOSFET connected in parallel, including a main SiC MOSFET and at least one slave SiC MOSFET. The main drive circuit includes:

[0010] di / dt detection circuit I, di / dt detection circuit II, voltage-controlled current sinking source circuit, and voltage-controlled current sourcing source circuit, where;

[0011] The di / dt detection circuit I detects the source stray inductance L of the main SiC MOSFET sl of the voltage V across both ends sl ;

[0012] The di / dt detection circuit II detects the source stray inductance L of the slave SiC MOSFET sn of the voltage V across both ends sn ;

[0013] When the voltage V sl is greater than the voltage V sn , the voltage-controlled sinking current source circuit injects current from the gate of the slave SiC MOSFET to make the drain current of the slave SiC MOSFET approach the drain current of the main SiC MOSFET;

[0014] When the voltage V sl is less than the voltage V sn , the voltage-controlled sourcing current source circuit extracts current from the gate of the slave SiC MOSFET to make the drain current of the slave SiC MOSFET approach the drain current of the main SiC MOSFET.

[0015] Further, the voltage-controlled sourcing current source circuit consists of a voltage feedback circuit I and a current mirror circuit I. The voltages V sl and V sn are input to the voltage feedback circuit I. Based on the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET, the voltage V sn is compensated. The compensated voltage is V' sn . The differential voltage (V' sn - V sl ) is proportionally amplified to obtain the output V am1 of the feedback circuit I. Based on the output V am1 of the voltage feedback circuit I, the current mirror circuit I outputs the corresponding sourcing current I sink .

[0016] Further, the voltage feedback circuit I includes: an operational amplifier U1. The voltages V sn and V s1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier U1 through a resistor R1 and a resistor R3. The non-inverting input terminal is connected to the signal ground terminal through a resistor R2, and the inverting input terminal is connected to the output terminal through a resistor R4;

[0017] The current mirror circuit I includes: a transistor Q1 and a transistor Q2 whose bases are connected to the output terminal of the operational amplifier U1. The emitters of the transistor Q1 and the transistor Q2 are connected to the collector of the transistor Q3 and the base of the transistor Q4 through a resistor R5. The collector of the transistor Q1 is connected to the power supply terminal Vcc. The base of the transistor Q3 is connected to the base of the transistor Q4. The collector of the transistor Q4 is connected to the gate of the SiC MOSFET through a diode D1. The collector of the transistor Q2, the emitters of the transistor Q3 and the transistor Q4 are connected to the signal ground terminal;

[0018] Adjust the resistors R1 and R2 for the voltage V sn for compensation, and the compensated voltage is V' sn = k3V sn The compensation coefficient k3 is the ratio of the source stray inductance L sl to the source stray inductance L sn , that is

[0019] Further, the voltage-controlled sink current source circuit is composed of a voltage feedback circuit II and a current mirror circuit II. Input the voltage V sn and the voltage V sl into the voltage feedback circuit II. Based on the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET, compensate the voltage V sl , and the compensated voltage is V' sl . Amplify the differential voltage (V' sl -V sn ) proportionally to form the output V am2 of the voltage feedback circuit II. Based on the output V am2 of the voltage feedback circuit II, the current mirror circuit II outputs the corresponding sink current I source .

[0020] Further, the voltage feedback circuit II includes:

[0021] An operational amplifier U2. The voltage V sn , the voltage V s1 are respectively connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier U2 through a resistor R8 and a resistor R9. The non-inverting input terminal is connected to the signal ground terminal through a resistor R10. The inverting input terminal is connected to the output terminal through a resistor R7;

[0022] The current mirror circuit II includes: a transistor Q9 and a transistor Q10 whose bases are connected to the output terminal of the operational amplifier U2. The collector of the transistor Q9 is connected to the power supply terminal Vcc. The emitters of the transistor Q9 and the transistor Q10 are connected to the bases of the transistor Q7 and the transistor Q8 through a resistor R6. The emitters of the transistor Q7 and the transistor Q8 are connected to the signal ground terminal. The base of the transistor Q7 is connected to the base of the transistor Q8. The collector of the transistor Q7 is connected to the bases of the transistor Q6 and the transistor Q5 through a diode D2. The emitters of the transistor Q6 and the transistor Q5 are grounded. The base of the transistor Q6 is connected to the base of the transistor Q5. The collector of the transistor Q5 is connected to the gate of the SiC MOSFET through a diode D3;

[0023] Adjust the resistances of the resistor R9 and the resistor R10 for the voltage V sl for compensation, and the compensated voltage is V' sl = m3V sl , and the compensation coefficient m3 is the ratio of the source stray inductance L sn to the source stray inductance L sl , that is

[0024] The present invention is implemented as follows. A parallel-connected SiC MOSFET power module, the parallel-connected SiC MOSFET power module includes:

[0025] n ((n >= 2)) parallel-connected SiC MOSFETs, including 1 main SiC MOSFET and (n - 1) slave SiC MOSFETs; the main SiC MOSFET is connected to each slave SiC MOSFET through the above-mentioned main drive circuit.

[0026] The proposed active drive scheme for parallel-connected SiC MOSFETs in the present invention is based on an analog circuit, with simple design and fast dynamic response; moreover, it is effective for the uneven current sharing problems caused by the discreteness of device dynamic parameters and the asymmetry of circuit stray parameters; in addition, there is no limit to the number of parallel-connected devices. All in all, the proposed active drive circuit in the present invention is simple and has a good effect on solving the dynamic uneven current sharing problem of parallel-connected SiC MOSFETs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of the main drive circuit for driving a parallel-connected SiC MOSFET power module provided by an embodiment of the present invention;

[0028] Figure 2 is a circuit diagram of the parallel-connected SiC MOSFET power module provided by an embodiment of the present invention;

[0029] Figure 3The circuit diagram of the voltage-controlled pull current source provided by the embodiment of the present invention;

[0030] Figure 4 The circuit diagram of the voltage-controlled sink current source provided by the embodiment of the present invention;

[0031] Figure 5 The waveform diagram of the turn-on transient process of two parallel SiC MOSFETs provided by the embodiment of the present invention. Detailed implementation manners

[0032] The following further describes in detail the specific implementation manners of the present invention by describing the embodiments with reference to the accompanying drawings, so as to help those skilled in the art have a more complete, accurate and in-depth understanding of the inventive concept and technical solutions of the present invention.

[0033] The source stray inductance includes the circuit wiring stray inductance and the device itself stray inductance. In most cases, the circuit wiring stray inductance is the main one; the voltage across the source stray inductance L S is:

[0034]

[0035] It can be seen from formula (1) that by detecting the voltage V S across the source stray inductance L S the change rate di d / dt of the drain current of the SiC MOSFET can be detected;

[0036]

[0037] g m represents the transconductance of the SiC MOSFET, I g represents the gate current of the SiC MOSFET, and C iss represents the input capacitance of the SiC MOSFET; it can be seen from formula (2) that the rise speed of the drain current of the SiC MOSFET is controlled by the gate current I g Therefore, the present invention takes the change rate of the drain current of the main device as a reference, and adjusts the change rate of its drain current by extracting or injecting the gate current of the slave device, so that the drain current of the slave device approaches the drain current of the main device to achieve current sharing. The devices in the present invention are SiC MOSFET, Si MOSFET or IGBT. The present invention takes SiC MOSFET as an example for related description.

[0038] Figure 1 The structural schematic diagram of the main drive circuit for driving the parallel SiC MOSFET power module provided by the embodiment of the present invention. For the sake of convenience of description, only the parts related to the embodiment of the present invention are shown.

[0039] The main drive circuit is arranged between the main SiC MOSFET and the slave SiC MOSFET connected in parallel, and includes one main SiC MOSFET and at least one slave SiC MOSFET, and it includes:

[0040] A di / dt detection circuit I, a di / dt detection circuit II, a voltage-controlled current sinking source circuit, and a voltage-controlled current sourcing source circuit. Among them, the di / dt detection circuit I detects the voltage V across the source stray inductance L of the main SiC MOSFET sl ; The di / dt detection circuit II detects the voltage V across the source stray inductance L of the slave SiC MOSFET sl ; sn ; sn

[0041] When the voltage V sl is greater than the voltage V sn , the voltage-controlled current sinking source circuit injects current from the gate of the slave SiC MOSFET. The gate-injected current can accelerate the rising speed of the drain current, so that the drain current of the slave SiC MOSFET approaches the drain current of the main SiC MOSFET, and then the current sharing effect is achieved;

[0042] When the voltage V sl is less than the voltage V sn , the voltage-controlled current sourcing source circuit extracts current from the gate of the slave SiC MOSFET. The gate-extracted current can reduce the rising speed of the drain current, so that the drain current of the slave SiC MOSFET approaches the drain current of the main SiC MOSFET, and then the current sharing effect is achieved.

[0043] Taking the voltage V sl of the SiC MOSFET as the voltage reference, the voltage difference (V sn -V sl ) of the main and slave parallel SiC MOSFETs reflects the current sharing state in the turn-on transient process of the main SiC MOSFET and the slave SiC MOSFET, and the following is a detailed analysis.

[0044] When V sn -V sl >0, there are two possible situations for the current sharing of the parallel SiC MOSFET devices:

[0045] (1) The drain current of the slave SiC MOSFET starts to rise, but the drain current of the main SiC MOSFET has not started to rise yet. At this time, V sn >0 and V sl =0.

[0046] (2) When both the slave SiC MOSFET and the main SiC MOSFET are in the transient process of rising drain current, only the drain current of the slave SiC MOSFET rises faster than that of the main SiC MOSFET during the turn-on process. At this time, V sn > V sl > 0.

[0047] For the above two cases, the voltage-controlled current sinking source starts. Therefore, the gate charging current of the slave SiC MOSFET weakens, and the rising rate of the drain current of the slave SiC MOSFET slows down, which is beneficial to reducing the drain current deviation between the slave SiC MOSFET and the main SiC MOSFET.

[0048] Similarly, when V sn - V sl < 0, there are also two possible cases:

[0049] (1) The drain current of the slave SiC MOSFET has not risen yet, but the main SiC MOSFET is already in the process of rising drain current. At this time, V sn = 0 while V sl > 0.

[0050] (2) When both the slave SiC MOSFET and the main SiC MOSFET are in the transient process of rising drain current, only the drain current of the slave SiC MOSFET rises slower than that of the main SiC MOSFET. At this time, 0 < V sn < V sl .

[0051] For the above two cases, the voltage-controlled current sourcing source starts at this time. The gate charging current of the slave SiC MOSFET is strengthened, so the drain current of the slave SiC MOSFET rises faster, which is beneficial to reducing the drain current deviation between the slave SiC MOSFET and the main SiC MOSFET.

[0052] In the embodiment of the present invention, the voltage-controlled current sinking source circuit is composed of a voltage feedback circuit I and a current mirror circuit I. The voltages V sl and V sn are input to the voltage feedback circuit I. Based on the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET, the voltage V sn is compensated. The compensated voltage is V' sn . The differential voltage (V' sn - V sl ) is proportionally amplified to obtain the output V am1 of the feedback circuit I. Based on the output V am1 of the voltage feedback circuit I, the current mirror circuit I outputs the corresponding sinking current I sink .

[0053] In the embodiment of the present invention, in combination with Figure 3 the voltage feedback circuit I and the current mirror circuit I are described. Among them, the voltage feedback circuit I includes: an operational amplifier U1, a voltage V sn and a voltage V s1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier U1 through a resistor R1 and a resistor R3. The non-inverting input terminal is connected to the signal ground terminal through a resistor R2, and the inverting input terminal is connected to the output terminal through a resistor R4; the current mirror circuit I includes: a transistor Q1 and a transistor Q2 whose bases are connected to the output terminal of the operational amplifier U1. The emitters of the transistor Q1 and the transistor Q2 are connected to the collector of the transistor Q3 and the base of the transistor Q4 through a resistor R5. The collector of the transistor Q1 is connected to the power supply terminal Vcc. The base of the transistor Q3 is connected to the base of the transistor Q4. The collector of the transistor Q4 is connected to the gate of the SiC MOSFET through a diode D1. The collectors of the transistor Q2, the transistor Q3 and the emitter of the transistor Q4 are connected to the signal ground terminal.

[0054] All the resistance values of the resistors R3, R4 and R5 in the SiC MOSFET remain unchanged. By adjusting the resistor R1 and the resistance value R2, the voltage V sn is compensated. The compensated voltage is V' sn = k3V sn , and the compensation coefficient k3 is the ratio of the source stray inductance L sl to the source stray inductance L sn , that is Furthermore, the current unevenness caused by the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET is reduced. Then, the operational amplifier U1 proportionally amplifies the differential voltage (k3V sn -V sl ). The feedback circuit I outputs V am1 , V am1 = k2(k3V sn -V sl ), and the current mirror circuit I inputs the pull current I am1 corresponding to V sink .

[0055] In the embodiment of the present invention, the voltage-controlled pull current I sink is calculated as follows:

[0056]

[0057] Among them, k1 is the sampling coefficient of the signal at the positive input terminal of the operational amplifier U1, k2 is the amplification factor of the differential signal input to the operational amplifier U1, k3 is the compensation coefficient of the signal at the positive input terminal of the operational amplifier U1. V BE,Q1 is the bias voltage between the base and emitter of the transistor Q1, and V BE,Q3 is the bias voltage between the base and emitter of the transistor Q3.

[0058] In the embodiment of the present invention, the voltage-controlled sink current source circuit is composed of the voltage feedback circuit II and the current mirror circuit II. The voltages V sn and V sl are input to the voltage feedback circuit II. Based on the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET, the voltage V sl is compensated. The compensated voltage is V′ sl . The differential voltage (V′ sl - V sn ) is proportionally amplified to form the output V am2 of the voltage feedback circuit II. Based on the output V am2 of the voltage feedback circuit II, the current mirror circuit II outputs the corresponding sink current I source .

[0059] In the embodiment of the present invention, the voltage feedback circuit II and the current mirror circuit II are described in combination with Figure 4 . Among them, the voltage feedback circuit II includes:

[0060] The operational amplifier U2. The voltages V sn and V s1 are respectively connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier U2 through the resistor R8 and the resistor R9. The non-inverting input terminal is connected to the signal ground terminal through the resistor R10, and the inverting input terminal is connected to the output terminal through the resistor R7.

[0061] The current mirror circuit II includes: the transistors Q9 and Q10 whose bases are connected to the output terminal of the operational amplifier U2. The collector of the transistor Q9 is connected to the power supply terminal Vcc. The emitters of the transistors Q9 and Q10 are connected to the bases of the transistors Q7 and Q8 through the resistor R6. The emitters of the transistors Q7 and Q8 are connected to the signal ground terminal. The base of the transistor Q7 is connected to the base of the transistor Q8. The collector of the transistor Q7 is connected to the bases of the transistors Q6 and Q5 through the diode D2. The emitters of the transistors Q6 and Q5 are grounded. The base of the transistor Q6 is connected to the base of the transistor Q5. The collector of the transistor Q5 is connected to the gate of the SiC MOSFET through the diode D3.

[0062] The resistance values of the resistors R7, R8, and R6 in all the slave SiC MOSFETs remain unchanged. The resistors R9 and the resistance value R10 are adjusted for the voltage V slCompensation is performed, and the voltage after compensation is V'. sl = m3V sl , where the compensation coefficient m3 is the ratio of the source stray inductance L sn to the source stray inductance L sl , that is Furthermore, the current imbalance caused by the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET is reduced. Then, the differential voltage (m3V sl - V sn ) is proportionally amplified by the operational amplifier U2 to form the output V am2 of the voltage feedback circuit II. V am2 = m2(m3V sl - V sn ). Based on the output V am2 of the voltage feedback circuit II, the current mirror circuit II outputs the corresponding sink current I source .

[0063] In the embodiment of the present invention, the formula for the voltage-controlled sink current is as follows:

[0064]

[0065] Among them, m1 is the sampling coefficient of the signal at the positive input terminal of the operational amplifier U2, m2 is the amplification factor of the input differential signal of the operational amplifier U2, m3 is the compensation coefficient of the signal at the positive input terminal of the operational amplifier U2, V BE,Q9 is the bias voltage between the base and emitter of the transistor Q9, and V BE,Q7 is the bias voltage between the base and emitter of the transistor Q7.

[0066] In the embodiment of the present invention, the source stray inductance L sl and the source stray inductance L sn can be estimated by engineering according to the actual circuit board wiring or extracted by relevant simulation software. It is also possible not to obtain the source stray inductance L sl and the source stray inductance L sn . During the actual circuit debugging, directly adjust m3 or k3 around 1 up and down so that the dynamic drain current of the slave SiC MOSFET optimally tracks the dynamic drain current of the slave SiC MOSFET.

[0067] Figure 5 Taking the turn-on transient process of two parallel SiC MOSFETs as an example, the current sharing control process between the main SiC MOSFET (denoted as T1) and the slave SiC MOSFET (denoted as Tn) is analyzed in detail, where V PWMIndicates the SiC MOSFET PWM drive signal, and the analysis is as follows:

[0068] (t0 - t1) stage: At time t0, the traditional drive circuit starts to charge the gate-source capacitors C of T1 and Tn. By time t1, the gate-source capacitor C of Tn is charged to the turn-on threshold voltage V gs . gsn TH,n .

[0069] (t1 - t2) stage: At time t1, the gate-source voltage of Tn reaches the turn-on threshold voltage V TH,n , the drain current I dn of Tn starts to rise, and the voltage V of the source stray inductance L sn starts to build up. V sn > 0. In this stage, the gate-source voltage of T1 has not reached the turn-on threshold V sn , so V TH,l remains 0. When V sl - V sn > 0V, the voltage-controlled current-sinking source current starts, and extra current is drawn from the gate of Tn. As a result, the charging speed of the gate-source capacitor of Tn decreases, and the rising rate of the drain current I sl of Tn slows down. dn

[0070] (t2 - t3) stage: At time t2, the gate-source capacitor voltage of T1 rises to the turn-on threshold V TH,l , the drain current I d1 of T1 starts to rise, and the voltage V of the source stray inductance L sl starts to build up. At this time, the rising slopes di sl / dt of the drain currents of the master and slave switching transistors together determine whether the voltage-controlled current-sinking source circuit or the voltage-controlled current-sourcing source circuit starts. Specifically, if the current change rate of the drain of Tn is greater than the current change rate of the drain of T1, that is, di d / dt > di n / dt, then the voltage-controlled current-sinking source circuit continues to work; if the current change rate of the drain of Tn is less than the current change rate of the drain of T1, that is, di l / dt < di n / dt, then the voltage-controlled current-sinking source circuit stops, and the voltage-controlled current-sourcing source circuit starts to work, injecting extra current into the gate of Tn, and the charging speed of the gate of Tn increases. l

[0071] (t3 - t4) stage: At time t3, the rising transient process of the drain currents of T1 and Tn ends, and the current enters the steady state. The difference between the current change rates di n / dt and di l / dt is relatively small, and the voltage-controlled current-source current stops working.​​​

[0072] (t4 - t5) stage: The gate - source voltage V of T1 gl and the gate - source voltage V of Tn gn continuously rises to the driving voltage. After time t5, the entire turn - on transient process ends.

[0073] Figure 2 FIG. is a schematic structural diagram of the parallel - connected SiC MOSFET power module provided by an embodiment of the present invention. For the sake of convenience of description, only the part related to the embodiment of the present invention is shown. The parallel - connected SiC MOSFET power module includes:

[0074] n ((n >= 2)) parallel - connected SiC MOSFETs, including 1 main SiC MOSFET and (n - 1) slave SiC MOSFETs; the main SiC MOSFET is connected to each slave SiC MOSFET through the above - mentioned main drive circuit;

[0075] The SiC MOSFET power module is composed of multiple discrete SiC MOSFET devices T1, T2, T3... Tn connected in parallel. Any one of them is defined as the main SiC MOSFET, and the rest are slave SiC MOSFETs. Taking the drain current of the main SiC MOSFET as a reference, the drain currents of all slave SiC MOSFETs are adjusted to approach the drain current of the main SiC MOSFET, so as to achieve current sharing of the parallel - connected SiC MOSFET power module.

[0076] L sn (n = 1, 2, 3...) represents the source stray inductance of the SiC MOSFET device Tn, R g1 , R g2 , R g3 …R gn are gate drive resistors, R s1 , R s2 , R s3 …R sn are resistors connected between the source of the parallel - connected devices and the ground of the traditional drive circuit. The same traditional drive circuit drives all the parallel - connected SiC MOSFETs.

[0077] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited by the above - mentioned manner. As long as various non - substantial improvements are made by adopting the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. An active drive circuit is provided between a main SiC MOSFET and a slave SiC MOSFET connected in parallel, including one main SiC MOSFET and at least one slave SiC MOSFET, characterized in that, The active drive circuit includes: a di / dt detection circuit I, a di / dt detection circuit II, a voltage-controlled pull current source circuit, and a voltage-controlled sink current source circuit, where; The di / dt detection circuit Ⅰ detects the source stray inductance L of the main SiC MOSFET sl at both ends of the voltage V sl ; di / dt detection circuit II, which detects the voltage V across the source stray inductance L of the SiC MOSFET sn sn ;​ At voltage V sl Greater than voltage V sn When, the voltage-controlled sink current source circuit injects current from the gate of the SiC MOSFET, so that the drain current of the slave SiC MOSFET approaches the drain current of the main SiC MOSFET; At voltage V sl Less than voltage V sn When, the voltage-controlled current-sinking source circuit draws current from the gate of the SiC MOSFET to make the drain current of the slave SiC MOSFET approach the drain current of the main SiC MOSFET; The voltage-controlled pull current source circuit consists of a voltage feedback circuit I and a current mirror circuit I, and inputs voltage V sl and voltage V sn to the voltage feedback circuit I. Based on the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET, voltage V sn is compensated, and the compensated voltage is V s ′ n . The differential voltage (V′ sn -V sl ) is proportionally amplified to obtain the output V am1 of the feedback circuit I. Based on the output V am1 of the voltage feedback circuit I, the current mirror circuit I outputs the corresponding pull current I sink ; The voltage feedback circuit I includes: an operational amplifier U1, voltage V sn and voltage V s1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier U1 through a resistor R1 and a resistor R3. The non-inverting input terminal is connected to the signal ground terminal through a resistor R2, and the inverting input terminal is connected to the output terminal through a resistor R4; The current mirror circuit I includes: a transistor Q1 and a transistor Q2 whose bases are connected to the output terminal of the operational amplifier U1. The emitters of the transistor Q1 and the transistor Q2 are connected to the collector of the transistor Q3 and the base of the transistor Q4 through a resistor R5. The collector of the transistor Q1 is connected to the power supply terminal Vcc. The base of the transistor Q3 is connected to the base of the transistor Q4. The collector of the transistor Q4 is connected to the gate of the SiC MOSFET through a diode D1. The collectors of the transistor Q2, the transistor Q3, and the emitter of the transistor Q4 are connected to the signal ground terminal; Adjust the resistances R1 and R2 to compensate for the voltage V sn The compensated voltage is V′ sn = k3V sn where the compensation factor k3 is the ratio of the source stray inductance L sl to the source stray inductance L sn , that is 2. The active drive circuit according to claim 1, characterized in that, The voltage-controlled sink current source circuit consists of a voltage feedback circuit II and a current mirror circuit II. The voltages V sn and V sl are input to the voltage feedback circuit II. Based on the difference in the source stray inductance values of the main SiC MOSFET and the slave SiC MOSFET, the voltage V sl is compensated. The compensated voltage is V' sl . The differential voltage (V' sl -V sn ) is amplified proportionally to form the output V am2 of the voltage feedback circuit II. Based on the output V am2 of the voltage feedback circuit II, the current mirror circuit II outputs the corresponding sink current I source .

3. The active drive circuit according to claim 2, characterized in that, The voltage feedback circuit II includes: Operational amplifier U2, voltage V sn and voltage V s1 are respectively connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier U2 through resistor R8 and resistor R9. The non-inverting input terminal is connected to the signal ground terminal through resistor R10, and the inverting input terminal is connected to the output terminal through resistor R7; The current mirror circuit II includes: a transistor Q9 and a transistor Q10 whose bases are connected to the output terminal of the operational amplifier U2. The collector of the transistor Q9 is connected to the power supply terminal Vcc. The emitters of the transistor Q9 and the transistor Q10 are connected to the base of the transistor Q7 and the base of the transistor Q8 through a resistor R6. The emitters of the transistor Q7 and the transistor Q8 are connected to the signal ground terminal. The base of the transistor Q7 is connected to the base of the transistor Q8. The collector of the transistor Q7 is connected to the bases of the transistor Q6 and the transistor Q5 through a diode D2. The emitters of the transistor Q6 and the transistor Q5 are grounded. The base of the transistor Q6 is connected to the base of the transistor Q5. The collector of the transistor Q5 is connected to the gate of the SiC MOSFET through a diode D3; Adjust the resistances R9 and R10 for the voltage V sl for compensation. The compensated voltage is V′ sl = m3V sl , where the compensation factor m3 is the ratio of the source stray inductance L sn to the source stray inductance L sl , that is 4. A parallel SiC MOSFET power module, characterized in that, The parallel SiC MOSFET power module includes: n SiC MOSFETs connected in parallel, where n >= 2; One of them is the main SiC MOSFET and (n - 1) are slave SiC MOSFETs. The main SiC MOSFET and each slave SiC MOSFET are connected through the active drive circuit described in any one of claims 1 to 3.

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