Circuit and method for constant pressure slew rate in high voltage charge pump

Abstract

This disclosure relates to circuits and methods for a constant slew rate in a high-voltage charge pump. For example, an integrated circuit includes: a non-volatile memory; a charge pump that generates a high voltage for programming operations on a non-volatile memory array; and a charge pump regulator that controls the slew rate of the charge pump. The charge pump regulator generates a sense current indicating the slew rate and adjusts the frequency of a clock signal supplied to the charge pump based on the sense current.

Description

TECHNICAL FIELD

[0001] The present invention relates to non-volatile memory, and more specifically, to the generation of program and erase voltages for non-volatile memory. BACKGROUND

[0002] Many non-volatile memories include floating gate transistors that serve as data storage elements for non-volatile memory cells. Data is written to or erased from a memory cell by adding or removing electrons from the floating gate of the floating gate transistor through a process known as Fowler-Nordheim tunneling. Fowler-Nordheim tunneling is accomplished in part by applying a high voltage between the control gate of the floating gate transistor and the source terminal of the floating gate transistor.

[0003] If a high voltage is applied for too long of a time during a program or erase cycle, the endurance of the non-volatile memory cell can be adversely affected. If a high voltage is applied for too short of a time, the efficiency and data retention characteristics of the memory cell can also be adversely affected. To obtain good program and erase efficiency, the amplitude and duration of the applied voltage are carefully selected.

[0004] However, other factors related to the application of program and erase functions can also adversely affect the memory cell. For example, a charge pump is typically used to generate the high voltage for program and erase operations. The slew rate of the output voltage of the charge pump can affect the program and erase cycle.

[0005] All of the subject matter discussed in the Background section is not necessarily prior art, and should not be assumed to be prior art merely because it is discussed in the Background section. In light of this, any recognition of the presence of a problem with, or related to, the prior art discussed in the Background section should not be inferred as an admission that the prior art is prior art. Rather, discussion of any subject matter in the Background section should be viewed as a method of describing the inventive process of the inventor(s), which can also themselves be inventive. SUMMARY

[0006] Embodiments of the present disclosure provide a charge pump regulator that controls a charge pump during program and erase operations of a non-volatile memory. The charge pump regulator ensures that the output of the charge pump has characteristics that will result in efficient and effective program and erase operations. Specifically, the charge pump regulator monitors the change in the output voltage of the charge pump and uses feedback principles to ensure that the rate of change of the output voltage (slew rate) is within a desired range. BRIEF DESCRIPTION OF DRAWINGS

[0007] Reference will now be made to the drawings solely for the purpose of illustrating example embodiments. In the drawings, like reference numerals designate like elements or acts. However, different reference numerals can be used to designate the same or similar elements or acts in some of the drawings. The size and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements can be exaggerated or altered for the purpose of illustrating the example embodiments.

[0008] Figure 1 is a block diagram of an integrated circuit including a charge pump regulator according to one embodiment.

[0009] Figure 2 is a block diagram of an integrated circuit including a charge pump regulator according to one embodiment.

[0010] Figure 3 is a schematic diagram of an integrated circuit including a charge pump regulator according to one embodiment.

[0011] Figure 4 is a schematic diagram of an integrated circuit including a charge pump regulator according to one embodiment.

[0012] Figure 5 is a schematic diagram of an integrated circuit including a charge pump regulator according to one embodiment.

[0013] Figure 6 is a schematic diagram of an integrated circuit including a charge pump regulator according to one embodiment.

[0014] Figure 7 is a block diagram of an integrated circuit according to one embodiment.

[0015] Figure 8 is a flowchart of a method 800 for operating an integrated circuit according to one embodiment. DETAILED DESCRIPTION

[0016] In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant arts will recognize that embodiments can be practiced without one or more of the specific details, or with other methods, components, materials, etc.

[0017] Unless the context clearly requires otherwise, throughout the present specification and claims, the word “comprise,” and variations thereof (such as “comprises” and “comprising”), will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers. In addition, the terms “first,” “second,” and similar

[0018] Reference in the specification to “one embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearance of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. In addition, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0019] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its broadest sense, that is, the inclusive sense unless the content clearly dictates otherwise.

[0020] Figure 1 is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes a memory array 102, a charge pump 104, and a charge pump regulator 106. The charge pump 104 of the charge pump regulator 106 cooperate to ensure efficient and effective memory programming and erase operations of the memory array 102.

[0021] The memory array 102 is a non-volatile memory array that includes a plurality of memory cells. In one example, the memory cells include floating gate transistors. The floating gate transistors have a floating gate. Data is stored in or erased from the floating gate by applying a high voltage between a control gate of the floating gate transistor and a source terminal of the floating gate transistor. Electrons tunnel through the channel of the floating gate transistor to the floating gate or from the floating gate to the channel, as appropriate, to program data or erase data from the floating gate. The tunneling process is known as Fowler-Nordheim tunneling. While the present disclosure primarily describes embodiments in which the memory array 102 is a non-volatile memory array and the memory cells include floating gate transistors as the memory devices, other types of memory arrays and memory cells can be used without departing from the scope of the present disclosure. Moreover, the principles of the present disclosure are extendable to memory arrays other than non-volatile memory arrays.

[0022] The charge pump 104 generates high voltages for programming and erase operations of the memory cells of the memory array 102. Generally, the charge pump 104 receives a clock signal having a VDD amplitude and a selected frequency, and generates high voltages for the programming and erase operations. In one embodiment, the charge pump 104 includes a plurality of charge pump stages. Each charge pump stage adds VDD to the output of the previous charge pump stage. If the first charge pump stage receives VDD as an input, the first charge pump stage outputs 2*VDD as an output. The second charge pump stage receives 2*VDD from the first charge pump stage, and outputs 3*VDD. This continues until the last charge pump stage outputs an output voltage Vout of the charge pump 104. In one example, Vout is between 15V and 20V.

[0023] When a program or erase operation is to be performed, the charge pump 104 initially has an output voltage of 0V or the supply voltage VDD. The output voltage then rises to the output voltage for the program or erase operation. The initial rise time of the output of the charge pump 104 is factored into the total time for the program or erase operation. Thus, if the rise time is very slow, the program and erase operations are correspondingly slower. However, if the rise time is too fast, this can cause other problems in the program or erase operation, such as over-programming or over-erasing of the memory cells. The change in the output voltage over time is known as the slew rate of the charge pump 104. A high slew rate corresponds to a fast change in the output voltage. A low slew rate corresponds to a slow change in the output voltage.

[0024] One of the conditions that affects the slew rate is the load of the charge pump. The load corresponds to the amount of current used in the program or erase operation. In addition to the current load, there is also a capacitive load that is charged by the charge pump. If the program or erase operation is to be performed for only a single row of memory cells, the load current and load capacitance are relatively small. If the program or erase operation is to be performed for multiple rows of memory cells, the load current and load capacitance are relatively large. As will be explained in more detail below, the total load can be modeled as a load capacitor and a load current source. Generally, a higher load results in a lower slew rate or requires more resources to provide a higher slew rate. Generally, a smaller load results in a higher slew rate or requires fewer resources to provide a higher slew rate.

[0025] Another condition that affects the slew rate is the frequency of the clock signal provided to the charge pump 104. As explained above, the charge pump 104 receives a clock signal having a VDD amplitude and a selected frequency and generates a high output voltage. Generating a high output voltage from an input amplitude of VDD is done in part based on the clock signal switching between high and low values. The faster the switching, or in other words, the higher the frequency of the clock signal, the higher the slew rate of the charge pump 104. The lower the frequency of the clock signal, the lower the slew rate of the charge pump 104.

[0026] The charge pump regulator 106 regulates the slew rate of the charge pump 104. The charge pump regulator 106 is coupled to the output of the charge pump 104. The charge pump regulator 106 detects the slew rate of the charge pump 104 and adjusts the function of the charge pump 104 to achieve a desired slew rate.

[0027] The charge pump regulator 106 includes a sense current generator 108. The sense current generator 108 is coupled to the output of the charge pump 104. The sense current generator 108 generates a sense current based on the slew rate of the output voltage of the charge pump 104.

[0028] The charge pump regulator includes a reference current generator 110. The reference current generator 110 generates a reference current. As will be described in greater detail below, the reference current has a value selected for comparison with the sense current.

[0029] The charge pump regulator includes a current differentiator 112. The current differentiator 112 receives the sense current from the sense current generator 108 and the reference current from the reference current generator 110. The current differentiator 112 generates a differential current corresponding to the difference between the sense current and the reference current. Thus, the differential current can provide an indication of adjustments made to the slew rate of the charge pump 104.

[0030] The charge pump regulator 106 includes a clock generator 113. The clock generator 113 generates a clock signal provided to the charge pump 104. The clock signal has an amplitude of VDD and a selected frequency. As described above, the frequency of the clock signal partially controls the slew rate of the charge pump 104.

[0031] The charge pump regulator 106 receives the differential current from the current differentiator 112. The charge pump generator adjusts the clock signal provided to the charge pump 104 in response to the differential current received from the current differentiator 112. The adjustment to the clock signal results in an adjustment to the slew rate of the output voltage of the charge pump 104.

[0032] In one example, the sense current generator 108 generates a sense current that is greater than the reference current generated by the reference current generator 110. This can indicate that the slew rate of the charge pump 104 is too high. The current differentiator 112 generates a differential current indicating that the sense current is greater than the reference current. The clock generator 113 receives the differential current and decreases the frequency of the clock signal provided to the charge pump 104. The decrease in the clock signal frequency results in a decrease in the slew rate of the charge pump 104.

[0033] In another example, the sense current generator 108 generates a sense current that is lower than the reference current generated by the reference current generator 110. The current differentiator 112 generates a differential current indicating that the sense current is lower than the reference current. The clock generator 113 receives the differential current and increases the frequency of the clock signal provided to the charge pump 104. The increase in the clock signal frequency results in an increase in the slew rate of the charge pump 104.

[0034] The slew rate of the charge pump 104 is continuously sensed and adjusted during operation of the charge pump 104. If the slew rate falls below a desired value or outside a desired range, the charge pump regulator 108 increases the frequency of the clock signal. If the slew rate increases above a desired value or outside a desired range, the charge pump regulator 108 decreases the frequency of the clock signal. This feedback mechanism keeps the output of the charge pump 104 within a desired value or range.

[0035] The clock generator 113 can adjust the output of the charge pump 104 in ways other than simply reducing the frequency of the clock signal. For example, the clock generator 113 can periodically interrupt the clock signal to reduce the slew rate or to reduce the total output voltage. Thus, the clock generator 113 can adjust the slew rate and the amplitude of the output voltage of the charge pump 104.

[0036] The charge pump regulator 106 includes a sense current generator 108, a reference current generator 110, a current differentiator 112, and a clock generator 113. The sense current generator 108 generates a sense current indicative of the slew rate of the charge pump 104. The sense current generator 108 provides the sense current to the current differentiator 112. The reference current generator 110 generates a reference current. The reference current generator 110 provides the reference current to the current differentiator 112. The current differentiator 112 compares the sense current to the reference current.

[0037] Figure 2 is a block diagram of an integrated circuit 100 according to one embodiment. Figure 2 The integrated circuit 100 of Figure 1 is similar to the integrated circuit 100 of The integrated circuit 100 includes a memory array 102, a charge pump 104, and a charge pump regulator 106.

[0038] The charge pump regulator 106 includes a sense current generator 108, a reference current generator 110, and a current differentiator 112. The sense current generator 108 is coupled to the output of the charge pump 104. The sense current generator 108 generates a sense current Is based on an indication of the slew rate of the output voltage Vout of the charge pump 104. The reference current generator 110 generates a reference current IR. The current differentiator receives the sense current Is and the reference current IR and generates a differential current ID indicative of the difference between the sense current Is and the reference current IR.

[0039] The integrated circuit 100 includes a clock generator 113. The clock generator 113 generates a clock signal CLK and a complementary clock signal CLKN. The clock signal CLK and the complementary clock signal CLKN have the same frequency. The complementary clock signal CLKN is the logical complement of the clock signal CLK. When CLK is high, CLKN is low. When CLK is low, CLKN is high.

[0040] The clock generator 113 includes a current-controlled oscillator 114. The current-controlled oscillator 114 is coupled to the current differentiator 112. The current-controlled oscillator 114 receives the differential current ID from the current differentiator 112. The current-controlled oscillator 114 generates an oscillation signal having a frequency based on the differential current ID. The amplitude of the differential current ID controls the frequency of the oscillation signal output by the current-controlled oscillator. The shape of the oscillation signal generated by the current-controlled oscillator 114 can be a square wave.

[0041] The oscillation signal output by the current-controlled oscillator can have an amplitude that is lower than VDD. This is because the current-controlled oscillator is powered in part by the differential current ID. The input voltage to the current-controlled oscillator 114 can be based on the voltage drop caused by the differential current ID. Thus, the amplitude of the oscillation signal generated by the current-controlled oscillator 114 can be lower than VDD.

[0042] The clock generator 113 includes a level shifter 116 coupled to the current-controlled oscillator 114. The level shifter 116 receives the oscillation signal from the current-controlled oscillator 114. The level shifter 116 shifts the amplitude of the oscillation signal received from the current-controlled oscillator 114 to VDD. Thus, if the oscillation signal generated by the current-controlled oscillator 114 is less than VDD, the level shifter 116 increases the amplitude of the oscillation signal to VDD. The level shifter 116 does not adjust the frequency of the oscillation signal. The level shifter 116 outputs the level-shifted oscillation signal. The level-shifted oscillation signal corresponds to the oscillation signal of the current-controlled oscillator 114 being level-shifted to have an amplitude of VDD.

[0043] The clock generator 113 includes a phase generator 118 coupled to the level shifter 116 and the charge pump 104. The phase generator 118 receives the level-shifted oscillation signal from the level shifter 116. The phase generator 118 generates the clock signal CLK from the level-shifted oscillation signal provided by the level shifter 116.

[0044] The charge pump regulator 106 includes a control circuit 120. The control circuit 120 can provide control signals to one or both of the sense current generator 108 and the reference current generator 110. In some cases, it can be desirable to increase the sensitivity of the sense current generator. In these cases, the control circuit 120 can provide control signals that will cause the sense current generator 108 to generate a greater sense current IS for a given slew rate of the output voltage Vout. In some cases, it can be advantageous to provide a greater reference current IR from the reference current generator 110. In these cases, the control circuit 120 can provide control signals to the reference current generator to select or adjust the amplitude of the reference current.

[0045] The control circuit 120 can also be coupled to the phase generator 118. The control circuit 120 can measure the output voltage Vout and can control the phase generator 118 to adjust the clock signals CLK and CLKN to decrease or increase Vout. Thus, the control circuit 120 can also include a voltage regulator.

[0046] Figure 3is a schematic diagram of an integrated circuit 100 including a charge pump 104 and a charge pump regulator 106. The charge pump regulator 106 can include a sense current generator 108, a reference current generator 110, a current differencer 112, and a clock generator 113. The charge pump regulator controls the charge pump 104.

[0047] In Figure 3 the sense current generator 108 includes a sense capacitor Cs and a current mirror 121. When the output voltage Vout of the charge pump 104 changes, the voltage across the sense capacitor Cs also changes. When the voltage on the sense capacitor changes, a corresponding sense current Is flows into or out of the sense capacitor according to the following equation:

[0048] dV / dt = Is / C,

[0049] where dV / dt is the change in voltage across the plates of the capacitor with time, Is is the current flowing into or out of the capacitor, and C is the capacitance of the capacitor. dV / dt is also the slew rate of the output voltage Vout of the charge pump 104. Rearranging the equation, the sense current Is is given by the following relationship:

[0050] Is = C * dV / dt.

[0051] Accordingly, the slew rate of the charge pump 104 forces the sense current Is to flow into or out of the sense capacitor Cs. The current mirror 121 includes NMOS transistors Nl and N2 coupled together in a current mirror configuration. The gate terminals of transistors Nl and N2 are coupled together. The source terminals of transistors Nl and N2 are coupled to ground. The drain terminal of transistor Nl is coupled to the gate terminals of transistors Nl and N2. As a result of this configuration, the voltage at the gate terminals of Nl and N2 will be forced to the value that provides the gate-source voltage VGS such that the drain current reaches the value of Is. Because the gate terminals of transistors Nl and N2 are coupled together and the source terminals of transistors Nl and N2 are coupled together, the gate-source voltage VGS in transistor N2 is equal to the gate-source voltage in transistor Nl. Accordingly, the current Is will also flow through transistor N2.

[0052] The drain terminal of transistor N2 is coupled to the reference current generator 110. The reference current generator is configured as a current source that outputs a reference current IR. The current differencer 112 corresponds to the branch circuit annotated between the drain of transistor N2 and the reference current generator 110. Because Is will flow through transistor N2, if IR is greater than Is, a differential current ID equal to the difference between IR and Is will flow out of node 112 and into the current-controlled oscillator 114. If IR is less than Is, the direction of ID will reverse and the differential current will flow out of the current-controlled oscillator 114 and into the current differencer node 112 and into transistor N2 as part of the sense current Is.

[0053] As described above, the value of the current ID controls the frequency of the oscillating signal output from the current-controlled oscillator 114. Depending on whether IS is greater than or less than IR, the differential current ID can flow in either direction. In this way, the sense current and the reference current IR control the frequency of the current-controlled oscillator 114.

[0054] In Figure 3 , the integrated circuit 100 further includes a voltage detector 122, a comparator 124, and an AND gate 126. The voltage detector 122 detects the output voltage Vout of the charge pump 104. The voltage detector 122 includes a voltage divider that provides a divided voltage by dividing Vout. The voltage detector 122 can include a resistive voltage divider or a capacitive voltage divider. The divided voltage is provided to the comparator 124. The comparator 124 also receives a reference voltage Vref. The comparator 124 compares Vref to the divided voltage. In this way, the comparator 124 effectively compares Vout and Vref. The comparator 124 outputs a comparison signal to the AND gate 126. If the divided voltage is greater than Vref, the output of the comparator 124 is low. If the divided voltage is less than Vref, the output of the comparator is high. Thus, the comparator output is a signal that indicates whether Vout is above or below a desired value. The AND gate 126 also receives the level-shifted oscillating signal from the level shifter 116.

[0055] The AND gate 126 outputs a high voltage when both inputs are high. The AND gate 126 outputs a low voltage when either input is low. If the output of the comparator is high, the output of the AND gate 126 will mirror the level-shifted oscillating signal. The output of the AND gate 126 is high whenever the level-shifted oscillating signal is high. The output of the AND gate 126 is low whenever the level-shifted oscillating signal is low. However, if the output of the comparator 124 is low, the output of the AND gate will be low.

[0056] One effect of the configuration of the voltage detector 122, the comparator 124, and the AND gate 126 is that any time when Vout is higher than the desired voltage (i.e., any time when the divided voltage is higher than Vref), the phase generator 118 will not output the clock signals CLK and CLKN, because the level-shifted oscillation voltage is not passed from the AND gate 126 to the phase generator 118 due to the output of the comparator 124 being low. This will cause the output voltage Vout of the charge pump 104 to gradually decrease, because the charge pump 104 is unable to generate a high voltage without the clock signals CLK and CLKN. In this way, the voltage detector 122 and the comparator 124 act as a voltage regulator that regulates the output voltage Vout of the charge pump 104. As long as Vout is less than a selected value determined by the relationship between the divided voltage and Vref, the output of the comparator 124 will be high, and the AND gate 126 will pass the level-shifted oscillation signal from the level shifter 116 to the phase generator 118. This, in turn, will cause the phase generator 118 to output the clock signals CLK and CLKN to the charge pump 104.

[0057] In Figure 3 , the load of the charge pump 104 is modeled as a load capacitance CL and a load current IL. In practice, the load current of the charge pump 104 can correspond to Figure 1 and Figure 2 the memory array 102 shown in FIG. 1. Alternatively, the charge pump 104 can output a high voltage Vout to a load other than a memory array without departing from the scope of the present disclosure.

[0058] Figure 4 is a schematic diagram of an integrated circuit 100 including a charge pump 104 and a charge pump regulator 106 according to one embodiment. Figure 4 The integrated circuit 100 of Figure 3 is substantially similar to the integrated circuit 100 of Figure 2 except for the reference current generator 112. The reference current generator 112 includes a current source 128. The current source 128 generates a reference seed current. The reference current generator 112 generates a reference current IR based on the reference seed current and a control signal provided by the control circuit 120 shown in FIG. 1.

[0059] The reference current generator 112 includes PMOS transistors P1 and P2. The source terminal of the transistor P1 is coupled to a supply voltage VDD. The gate terminal of the transistor P1 is coupled to the drain terminal of the transistor P1 and the source terminal of the transistor P2. The gate terminal of the transistor P2 receives an enable signal EN that enables the reference current generator 112. The drain terminal of the transistor P2 is coupled to the current source 128.

[0060] When the enable signal EN is low, the reference seed current IRS flows through transistors P1 and P2. Because the drain terminal of transistor P1 is coupled to the gate terminal of transistor P1, the gate voltage of transistor P1 will be at a voltage such that the gate-source voltage has a value that drives the reference seed current IRS through transistor P1.

[0061] The reference current generator 112 includes N current mirror paths, each coupled to transistor P1 in a current mirror configuration. The first current mirror path includes transistors P3 and P4. Transistor P3 is coupled to transistor P1 in a current mirror configuration. Transistor P4 is coupled between transistor P3 and the current differencer node 112. The gate terminal of transistor P4 receives a control signal CI that selectively enables or disables transistor P4, thereby selectively enabling or disabling the first current mirror path of the reference current generator 110. The second current mirror path includes transistors P5 and P6. Transistor P5 is coupled to transistor P1 in a current mirror configuration. The gate terminal of transistor P6 receives a control signal C2 that selectively enables or disables transistor P6. Transistor P6 is coupled between transistor P5 and the current differencer node 112. The Nth current mirror path includes transistors P7 and P8. Transistor P7 is coupled to transistor P1 and the current mirror configuration. Transistor P8 receives a control signal CN that selectively enables or disables the Nth current mirror path.

[0062] Because of the current mirror configuration, each enabled current mirror path passes a current equal to the reference seed current IRS. The reference current IR is equal to the reference seed current IRS multiplied by the number of enabled current mirror paths. Thus, if all N current mirror paths are enabled, IR will be equal to N*IRS. If only one current mirror path is enabled, IR will be equal to IRS. The sense current IS can be generated substantially as described above with respect to Figure 3

[0063] Figure 5 is a schematic diagram of an integrated circuit 100 including a charge pump 104 and a charge pump regulator 106 according to one embodiment. Figure 5 The integrated circuit 100 is substantially similar to the integrated circuit 100 of Figure 3 except for the sense current generator 108. As described above with respect to Figure 3 the sense current generator 108 generates the sense current IS based on the sense capacitor CS and the current mirror transistor Nl. However, the sense current generator 108 also includes N current mirror paths, each of which can be selectively enabled to pass the sense current IS. The current mirror paths can be selectively enabled by control signals provided by a control circuit 120 as shown. Figure 2

[0064] ​​The first current mirror path includes transistors N2 and N3. Transistor N2 is coupled to transistor Nl in a current mirror configuration. Transistor N3 is coupled between transistor N2 and current differencer node 112. The gate terminal of transistor N3 receives a control signal Cl that selectively enables or disables transistor N3, thereby selectively enabling or disabling the first current mirror path of sense current generator 108. The second current mirror path includes transistors N4 and N5. Transistor N4 is coupled to transistor Nl in a current mirror configuration. The gate terminal of transistor N5 receives a control signal C2 that selectively enables or disables transistor N5. Transistor N5 is coupled between transistor N4 and current differencer node 112. The Nth current mirror path includes transistors N6 and N7. Transistor N6 is coupled to transistor Nl in a current mirror configuration. Transistor N7 receives a control signal CN that selectively enables or disables the Nth current mirror path.

[0065] Due to the current mirror configuration, each enabled current mirror path passes a current equal to the sense current IS. The total sense current m*IS flows out of current differencer node 112, where m is the number of enabled current mirror paths. Control circuit 120 can enable additional current mirror paths in sense current generator 108 in order to increase the sensitivity of the sense current generator. The greater the number of enabled current mirror paths, the greater the total sense current generated for a given slew rate of output voltage Vout. The fewer the number of enabled current mirror paths, the lower the total sense current generated for a given slew rate of output voltage Vout. The reference current IR and the differential current ID can be generated substantially as described in U.S. Patent No. 6,670,996, which is incorporated herein by reference. Figure 3

[0066] Figure 6 is a schematic diagram of an integrated circuit 100 including charge pump 104 and charge pump regulator 106, according to one embodiment. Figure 6 Integrated circuit 100 is substantially similar to integrated circuit 100 of Figure 3 , except for sense current generator 108. Sense current generator 108 includes N sense capacitors CS-CSN and a corresponding number of current paths upstream of current mirror transistor Nl.

[0067] The first selectively enabled current path includes sense capacitor CS2 and switch SI. The Nth selectively enabled current path includes sense capacitor CSN. Figure 2 ​The illustrated control circuit 120 can selectively open and close switches S1-SN to selectively enable current paths associated with each sense capacitor CS1-CSN. The control circuit 120 can selectively enable the switches S1-SN to increase or decrease the sensitivity of the sense current generator 108. The sense current IS corresponds to the sum of the currents flowing through each enabled current path. The reference current IR and the differential current ID can be generated substantially as illustrated and described Figure 2

[0068] Figure 7 is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes a memory array 102. The memory array 102 is a non-volatile memory that includes a plurality of memory cells 138 arranged in rows and columns. Each memory cell 138 includes a floating gate transistor NFG and a select transistor NS. The control gate of the floating gate transistor NFG is coupled to a word line corresponding to a row of memory cells 138. The select transistor receives a select signal SEL that selects the memory cell for a read, erase, or program operation.

[0069] The select transistor NS and the floating gate transistor NFG of a memory cell 138 are coupled between two bit lines BL. The bit lines BL can alternatively operate as source lines. Various configurations of word lines, bit lines, source lines, and select lines can be used for the non-volatile memory array 102 without departing from the scope of the present disclosure.

[0070] The integrated circuit 100 includes a row decoder 130. The row decoder 130 receives a high voltage Vout from the charge pump 104 for a program or erase operation. The row decoder 130 then provides the high voltage Vout to a word line WL associated with a row on which a program or erase operation is to be performed.

[0071] The integrated circuit 100 also includes a column decoder 132 for selecting a bit line associated with a memory cell 138 on which a read, erase, or program operation is to be performed. A sense amplifier 134 senses the value of data stored in a memory cell during a read operation. A program circuitry 136 is coupled to the bit line BL and can provide voltages for performing a read, erase, or program operation.

[0072] Although not shown in Figure 7 , additional voltage step-down circuitry can be provided to reduce the magnitude of the output voltage provided from the charge pump 104 to the column decoder 132 and the program circuitry 136. For example, if the output voltage of the charge pump 104 is between 15V and 20V, the step-down circuitry can provide a voltage between 5V and 10V to the column decoder 132 and the program circuitry 136. The charge pump regulator 106 operates substantially as previously described with respect to Figures 1-6 ​​

[0073] Figure 8 is a flowchart of a method 800 for operating an integrated circuit according to one embodiment. The method 800 can utilize any of the circuits, components, and processes described in Figures 1-7

[0074] In one embodiment, an integrated circuit includes a charge pump configured to receive a supply voltage and provide an output voltage higher than the supply voltage. The integrated circuit includes a charge pump regulator coupled to the charge pump. The charge pump regulator includes a sense current generator coupled to the charge pump and configured to generate a sense current indicative of a slew rate of the output voltage, a reference current generator configured to generate a reference current, and a current differencer configured to receive the sense current and the reference current and generate a difference current indicative of a difference between the sense current and the reference current. The charge pump regulator also includes a clock generator configured to generate a clock signal having a frequency based on the difference current and provide the clock signal to the charge pump.

[0075] In one embodiment, an integrated circuit includes a memory array including a plurality of memory cells, a charge pump having an output coupled to the memory array, a sense current generator coupled to the output of the charge pump, a reference current generator, and a current differencer. The current differencer includes a first input coupled to the sense current generator, a second input coupled to the reference current generator, and an output. The charge pump regulator includes a clock generator having a current-controlled oscillator coupled to the charge pump and having the output of the current differencer coupled to the current-controlled oscillator.

[0076] In one embodiment, a method includes generating an output voltage using a charge pump, generating a sense current indicative of a slew rate of the output voltage using a slew rate generator, and generating a reference current using a reference current generator. The method includes generating a difference current indicative of a difference between the reference current and the sense current, generating a clock signal having a frequency based on the difference current using a clock generator, and providing the clock signal to the charge pump.

[0077] ​The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the detailed description. In general, the selected terms employed in the following claims are to be interpreted as including all embodiments which fall within the scope of the terminology employed, according to the doctrine of equivalents. Accordingly, the claims are not to be limited by the disclosure.

Claims

1. An integrated circuit comprising: a charge pump configured to receive a supply voltage and provide an output voltage higher than the supply voltage; and a charge pump regulator coupled to the charge pump and comprising: a sense current generator coupled to the charge pump and configured to generate a sense current indicative of a slew rate of the output voltage, wherein the sense current generator comprises: a first transistor having a source terminal coupled to ground, a gate terminal, and a drain terminal coupled to the gate terminal; a plurality of sense capacitors each having a first terminal coupled to an output terminal of the charge pump, and a second terminal; and a plurality of switches each coupled between the second terminal of a respective sense capacitor and the drain terminal of the first transistor and configured to engage the corresponding sense capacitor in generating the sense current; a second transistor having a source terminal coupled to ground, a drain terminal, and a gate terminal coupled to the gate terminal of the first transistor; a reference current generator coupled between a high supply voltage and the drain terminal of the second transistor and configured to generate a reference current; a clock generator configured to generate a clock signal having a frequency based on a differential current corresponding to a difference between the reference current and the sense current, and provide the clock signal to the charge pump, the clock generator comprising: a current-controlled oscillator having an input directly coupled to the drain terminal of the second transistor and receiving the differential current from the drain terminal of the second transistor, wherein the current-controlled oscillator generates an oscillation signal having a frequency based on the differential current; and a level shifter configured to shift a level of the oscillation signal.

2. The integrated circuit of claim 1, wherein the sense current corresponds to a charging current of the capacitor.

3. The integrated circuit of claim 2, wherein the charging current corresponds to the slew rate of the output voltage.

4. The integrated circuit of claim 1, wherein the sense current generator comprises a plurality of parallel sense current paths coupled together in a current mirror configuration, the plurality of parallel sense current paths being selectively enabled to adjust a sensitivity of the sense current generator.

5. The integrated circuit of claim 4, further comprising a control circuit that selectively enables the plurality of parallel sense current paths based on a load of the charge pump.

6. The integrated circuit of claim 1, wherein the reference current generator comprises a plurality of parallel reference current paths coupled together in a current mirror configuration, the plurality of parallel reference current paths being selectively enabled to adjust the reference current.

7. An integrated circuit comprising: a memory array comprising a plurality of memory cells; a charge pump having an output coupled to the memory array; a sense current generator coupled to the output of the charge pump, wherein the sense current generator comprises: a first transistor having a source terminal coupled to ground, a gate terminal, and a drain terminal coupled to the gate terminal; a plurality of sense capacitors each having a first terminal coupled to an output terminal of the charge pump, and a second terminal; and a plurality of switches each coupled between the second terminal of a respective sense capacitor and the drain terminal of the first transistor and configured to engage the corresponding sense capacitor in generating the sense current; a second transistor having a source terminal coupled to ground, a drain terminal, and a gate terminal coupled to the gate terminal of the first transistor; a reference current generator coupled between a high supply voltage and the drain terminal of the second transistor and configured to generate a reference current; a clock generator configured to generate a clock signal having a frequency based on a differential current corresponding to a difference between the reference current and the sense current, and provide the clock signal to the charge pump, the clock generator comprising: a current-controlled oscillator having an input directly coupled to the drain terminal of the second transistor and receiving the differential current from the drain terminal of the second transistor, wherein the current-controlled oscillator generates an oscillation signal having a frequency based on the differential current; and a level shifter configured to shift a level of the oscillation signal. a plurality of sense capacitors, each sense capacitor having a first terminal coupled to an output terminal of the charge pump, and a second terminal; and a plurality of switches, each switch coupled between the second terminal of a respective sense capacitor and the drain terminal of the first transistor, and configured to engage the corresponding sense capacitor in generating the sense current; a second transistor having a source terminal coupled to ground, a drain terminal, and a gate terminal coupled to the gate terminal of the first transistor; a reference current generator coupled between a high supply voltage and the drain terminal of the second transistor and configured to generate a reference current; a clock generator coupled to the charge pump and having: a current-controlled oscillator having an input directly coupled to the drain terminal of the second transistor and receiving a differential current from the drain terminal of the second transistor, the differential current corresponding to a difference between the reference current and the sense current, wherein the current-controlled oscillator generates an oscillation signal having a frequency based on the differential current; and a level shifter configured to shift a level of the oscillation signal.

8. The integrated circuit of claim 7, wherein the clock generator comprises a phase generator that receives an oscillation signal from the current-controlled oscillator, generates a clock signal from the oscillation signal, and provides the clock signal to the charge pump.

9. The integrated circuit of claim 8, further comprising: a voltage divider having: an input coupled to an output of the charge pump and configured to receive an output voltage of the charge pump; and an output configured to provide a divided voltage from the output voltage; a comparator having: a first input coupled to the output of the voltage divider and configured to receive the divided voltage; a second input configured to receive a reference voltage; and an output configured to output a comparison signal; and a logic gate having: a first input configured to receive the oscillation signal; a second input configured to receive the output of the comparator; and an output configured to provide or not provide the oscillation signal to the phase generator based on a value of the comparison signal.

10. A method for operating an integrated circuit, comprising: generating an output voltage using a charge pump; generating a sense current indicative of a slew rate of the output voltage using a sense current generator, wherein the sense current generator comprises: a first transistor having a source terminal coupled to ground, a gate terminal, and a drain terminal coupled to the gate terminal; a plurality of sense capacitors, each sense capacitor having a first terminal coupled to an output terminal of the charge pump, and a second terminal; and a plurality of switches, each switch coupled between the second terminal of a respective sense capacitor and the drain terminal of the first transistor, and configured to engage the corresponding sense capacitor in generating the sense current; a second transistor having a source terminal coupled to ground, a drain terminal, and a gate terminal coupled to the gate terminal of the first transistor; generating a reference current using a reference current generator coupled between a high supply voltage and the drain terminal of the second transistor; and generating a clock signal from the reference current using a clock generator coupled to the charge pump. ​ ​ generating a clock signal having a frequency based on a differential current using a clock generator, wherein generating the clock signal comprises: receiving a differential current using an input of a current-controlled oscillator directly coupled to a drain terminal of the second transistor, the differential current corresponding to a difference between the reference current and the sense current; generating an oscillation signal having a frequency based on the differential current using the current-controlled oscillator; and shifting a level of the oscillation signal using a level shifter; and providing the clock signal to the charge pump.

11. The method of claim 10, further comprising: adjusting the slew rate of the output voltage by adjusting a frequency of the clock signal based on the sense current.

12. The method of claim 10, wherein adjusting the frequency of the clock signal comprises: adjusting a frequency of the oscillation signal based on the differential current.

13. The method of claim 10, further comprising: adjusting a proportion of the sense current relative to the slew rate by selectively enabling parallel current paths of the sense current generator.

14. The method of claim 10, further comprising: adjusting a proportion of the sense current relative to the slew rate by selectively enabling parallel current paths of the reference current generator.

15. The method of claim 10, further comprising: providing the output voltage to a non-volatile memory array.

16. The method of claim 15, further comprising: programming a non-volatile memory cell of the memory array by applying the output voltage to a control gate of a floating gate transistor of the memory cell.

17. The method of claim 10, wherein the clock generator comprises a phase generator coupled to an output of the level shifter and configured to provide the clock signal and a complementary clock signal.

18. The method of claim 10, comprising generating a complementary clock signal using the clock generator.

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