Methods for forming microelectronic devices with self-aligned interconnects and related devices and systems

Abstract

This application relates to methods and related devices and systems for forming microelectronic devices with self-aligned interconnects. A method for forming a microelectronic device includes forming an interconnect self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of the interconnect is defined when subtractively patterning the lower conductive structure and a first sacrificial material. At least another lateral dimension of the interconnect is defined by patterning a second sacrificial material, or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material and the second sacrificial material exposed within the opening through the dielectric material is removed and replaced with a conductive material to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between a vertically overlapping area of the lower conductive structure and the upper conductive structure, where such overlapping area coincides with the opening through the dielectric material.

Description

[0001] Priority Claim

[0002] This application is the national phase application of International Patent Application PCT / US2020 / 051445, filed on September 18, 2020, designating the People's Republic of China and published in English on April 22, 2021 as International Patent Publication WO 2021 / 076269 A1. This application claims the benefit of U.S. Patent Application Serial No. 16 / 653,442, filed on October 15, 2019, pursuant to Article 8 of the Patent Cooperation Treaty. Technical Field

[0003] Embodiments of this disclosure relate to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods for forming a microelectronic device (e.g., a memory device) having self-aligned interconnects between a lower conductive structure and an upper conductive structure. This disclosure also relates to and includes apparatuses and systems for such self-aligned interconnects. Background Technology

[0004] Integrated circuits (ICs) (critical components in thousands of electronic systems) generally comprise an interconnect network of electrical components (e.g., semiconductor devices) fabricated on a common substrate or base. Semiconductor devices may include capacitors, resistors, transistors, diodes, or other devices, which may be arranged in different layers supported by a substrate. Interconnect structures (referred to herein as “interconnects”) are a means of electrically connecting different layers of semiconductor devices. Interconnects generally comprise regions of conductive material formed between electrically connected semiconductor devices or other portions of semiconductor devices. Interconnects provide conduits for carrying current between electrically connected devices or regions. Certain types of interconnects include vias, plugs, filled trenches, local interconnects, and buried contacts.

[0005] Sufficient electrical connectivity through interconnects largely depends on adequate physical contact between interconnects and the structures or regions that provide electrical communication between them. Ensuring adequate physical contact can be challenging when forming interconnects between lower and upper levels of an IC. Fabricating a multi-level structure is generally simplest if each level of material is formed sequentially from bottom to top. Thus, a first conductive structure can be formed at a lower level, an interconnect can be formed at an intermediate level on the first conductive structure and in contact with it, and then a second conductive structure can be formed at an upper level on the interconnect and in contact with it. However, this fabrication method can present challenges in ensuring that the interconnects adequately physically contact the first and second conductive structures.

[0006] Interconnect fabrication challenges are also influenced by the conductive material of the interconnect and the interconnect itself. After all, interconnects not only require sufficient physical contact with the electrically interconnected lower and upper conductive structures, but the material of the interconnect must also typically meet sufficient performance characteristics, such as low resistivity. Previously, aluminum (Al) was an advantageous conductive material for interconnects fabricated using conventional processes. That is, aluminum is generally suitable for fabrication processes in which material layers can be patterned into the desired interconnect structure. However, as ICs have scaled down to increasingly smaller sizes, the lower resistivity of copper (Cu) has made it a more popular interconnect choice than aluminum (Al). However, copper (Cu) is generally difficult to pattern, so the same formation followed by etching methods used for interconnects made of Al are generally disadvantageous for interconnects made of Cu. A so-called "dotting" process has been developed, in which the conductive material of the interconnect (e.g., Cu) is formed on the first conductive structure by substantially depositing the conductive material of the interconnect into a "mold" (e.g., a negative space defined by another material formed on the first conductive structure). Therefore, before forming the conductive material in the negative space, another material is formed on the lower layer including the first conductive structure, and then the other material is patterned by subtractive etching to define the negative space. Subsequently, an upper layer including the second conductive structure is formed on the interconnect.

[0007] A "dual damascene" fabrication process has been developed for forming interconnects from difficult-to-etch materials (e.g., Cu), offering enhanced reliability by creating interconnects with sufficient physical contact between a lower conductive structure and an upper conductive structure. The dual damascene process combines (e.g., deposition) the conductive material of the interconnect with the conductive material forming (e.g., deposition) the second conductive structure that provides electrical communication with it. Specifically, a double layer of another material is formed above a lower layer including a first conductive structure; this double layer is etched in one or more stages to define a negative space defining the structure for both the interconnect and the second conductive structure; and then the negative space is filled with conductive material for both the interconnect and the second conductive structure. Through this dual damascene fabrication, the second conductive structure and the interconnect are "self-aligned," for example, formed to ensure physical contact between the two structures. However, the dual damascene process generally does not guarantee sufficient alignment (e.g., physical and electrical contact) between the interconnect and the first conductive structure. Therefore, fabricating interconnects with reliable physical contact between the interconnect and the associated lower and upper conductive structures remains a challenge. Summary of the Invention

[0008] A method for forming a microelectronic device is disclosed. The method includes patterning a first conductive material and a first sacrificial material to form at least one first feature including a first conductive structure. A dielectric material is formed adjacent to the at least one first feature. Another dielectric material is formed on the first sacrificial material and the dielectric material. At least one opening is formed through the other dielectric material to expose at least one portion of the first sacrificial material. A second sacrificial material is formed on the other dielectric material and the at least one portion of the first sacrificial material exposed by the at least one opening. The second sacrificial material is patterned to form at least one second feature. Additional dielectric material is formed adjacent to the at least one second feature. The second sacrificial material and the at least one portion of the first sacrificial material are removed to form an extended opening therein exposing at least one portion of the first conductive material. The extended opening is filled with a second conductive material to form at least one interconnect in each of the extended openings.

[0009] A microelectronic device is also disclosed. The microelectronic device includes an interconnect between a lower conductive structure and an upper conductive structure. The interconnect occupies only the volume between the lower and upper conductive structures, which are vertically overlapping. The microelectronic device also includes a dielectric material through which the interconnect extends.

[0010] Furthermore, a method for forming a microelectronic device is disclosed. The method includes subtractively forming an elongated feature including a first sacrificial material on a first conductive structure. Forming a dielectric material on the first sacrificial material. Forming at least one opening through the dielectric material to expose a portion of the first sacrificial material. Forming a second sacrificial material on the portion of the first sacrificial material in the first opening. Patterning the second sacrificial material to form another elongated feature. Forming another dielectric material adjacent to the other elongated feature. Removing the second sacrificial material and the portion of the first sacrificial material to form a second opening exposing a portion of the first conductive structure. Additively forming at least one second conductive material on the portion of the first conductive structure in the second opening to form a second conductive structure integrally formed with an interconnect physically in contact with the first conductive structure.

[0011] A microelectronic device is also disclosed. The microelectronic device includes a first conductive structure vertically overlapping a second conductive structure. An interconnect is integral with the second conductive structure and directly disposed between the first and second conductive structures. The interconnect includes at least one vertical sidewall coplanar with at least one vertical sidewall of the first conductive structure. The interconnect also includes at least another vertical sidewall coplanar with at least one vertical sidewall of the second conductive structure. A dielectric material is disposed between the first and second conductive structures. The dielectric material defines at least one opening through which the interconnect extends.

[0012] Furthermore, a system is disclosed, comprising at least one microelectronic device, at least one processor, and at least one peripheral device. The at least one microelectronic device includes at least one interconnect between a lower conductive structure and an upper conductive structure. The at least one interconnect extends through discrete openings in a dielectric material. The horizontal cross-sectional region of the interconnect is the region where the upper conductive structure and the lower conductive structure vertically overlap. The at least one processor is operatively in communication with the at least one microelectronic device. The at least one peripheral device is operatively in communication with the at least one processor. Attached Figure Description

[0013] Figures 1 to 14 This is an isometric illustration of a cross-section during various processing stages used to fabricate a microelectronic device structure, which includes interconnects that are self-aligned with conductive structures pointing in intersecting directions.

[0014] Figure 14 This is a cross-sectional isometric illustration of a microelectronic device structure containing self-aligned interconnects between conductive structures pointing in intersecting directions.

[0015] Figures 15 to 21 It is in combination Figures 1 to 14 The diagram illustrates the stages described herein and the various processing stages for fabricating a microelectronic device structure that follow these stages, with the microelectronic device structure comprising multiple layers of interconnects self-aligned with conductive structures pointing in intersecting directions.

[0016] Figure 21 This is a cross-sectional isometric illustration of a multi-level microelectronic device structure containing interconnects with self-aligned conductive structures pointing in intersecting directions.

[0017] Figures 22 to 25 This is a cross-sectional isometric illustration during various processing stages of fabricating a microelectronic device structure, which includes interconnects that are self-aligned with conductive structures pointing in a collinear direction.

[0018] Figure 25This is a cross-sectional isometric illustration of a microelectronic device structure containing interconnects with conductive structures that are self-aligned and collinear with each other.

[0019] Figure 26 A block diagram illustrating an electronic system including microelectronic devices according to embodiments of the present disclosure. Detailed Implementation

[0020] The method for forming a structure (e.g., a microelectronic device structure) with interconnects according to embodiments of the present disclosure ensures self-alignment between the interconnects and both the lower and upper conductive structures. At least a portion of a first lateral dimension (e.g., width) and height of the interconnects is defined when the lower conductive structure and a first sacrificial material are patterned. A barrier material is formed on the first sacrificial material, and an opening is formed in the barrier material to expose the first sacrificial material where the interconnects are to be formed. A second sacrificial material is formed on the barrier material and in the opening. The second sacrificial material is patterned to define the upper conductive structure. The second sacrificial material and portions of the first sacrificial material exposed in the opening are removed and replaced with conductive material to form the interconnects and the upper conductive structure. Thus, the second lateral dimension (e.g., length) of the interconnects is defined by the width of the upper conductive structure (e.g., in embodiments where the lower and upper conductive structures are formed in intersecting directions) or by the length of the opening in the barrier material (e.g., in embodiments where the lower and upper conductive structures are formed in collinear directions). The barrier material may also define the remainder of the height of the interconnects. The resulting interconnect is self-aligned with both the upper and lower conductive structures, thereby achieving reliable physical contact and electrical connection through the interconnect.

[0021] As used herein, the term "intersecting direction" when referring to the orientation of structures means and includes that each structure defines a length (e.g., the longest horizontal length) along that direction, such that if such directions are drawn in the same plane, the orientation of at least one of the structures will intersect (e.g., not perfectly parallel) the orientation of at least another of the structures. For example, "intersecting direction" includes, but is not limited to, a vertical direction, wherein at least one structure points along the x-axis and at least another structure points along the y-axis, but the structures may be in different levels of the device structure.

[0022] As used herein, the term "collinear direction" when referring to the orientation of structures means and includes that each structure defines a length (e.g., the longest horizontal scale) along a direction such that, when such a direction is drawn in the same plane, the orientations of each of the structures will completely overlap (e.g., not deviating from each other, not intersecting each other, and not perfectly parallel to each other). For example, "collinear direction" includes, but is not limited to, one structure in one level of the device structure pointing along the x-axis, and at least one other structure in at least another level of the device structure also pointing along the x-axis.

[0023] As used herein, the term "opening" means a volume extending through at least one structure or at least one material, leaving a gap within said at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between said structures or materials. Unless otherwise described, an "opening" does not necessarily contain no material. That is, an "opening" is not necessarily a void space. An "opening" formed in or between a structure or material may include structures or materials other than those in which or between which the opening is formed. Moreover, the structure or material "exposed" within an opening is not necessarily in contact with an atmosphere or non-solid environment. The structure or material "exposed" within an opening may be adjacent to or in contact with other structures or other materials disposed within the opening.

[0024] As used herein, the term "sacrificial material" means and includes material that is formed and / or adopted during the manufacturing process but is subsequently removed wholly or partially before the completion of the manufacturing process. "Partially sacrificed" material means and includes sacrificial material from which only one or more portions are removed before the completion of the manufacturing process. "Completely sacrificed" material means and includes sacrificial material that is substantially completely removed before the completion of the manufacturing process.

[0025] As used herein, the term "substrate" means and includes the base material or other construction on which components (e.g., components within a microelectronic device) are formed. A substrate can be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. A substrate can be a conventional silicon substrate or other bulk substrate containing a semiconducting material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates (e.g., silicon-on-sapphire ("SOS") or silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a base semiconductor basis), or other semiconductor or optoelectronic materials (e.g., silicon-germanium (Si...). 1-x Ge x (where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when referred to as "substrate" in the following description, previous process stages may have been used to form the material, structure, or junction in the substrate semiconductor structure or base.

[0026] As used herein, the terms “horizontal” or “lateral” mean and include a direction parallel to the main surface of the substrate on which the mentioned material or structure is positioned. The width and length of the corresponding material or structure can be defined as dimensions in the horizontal plane.

[0027] As used herein, the terms “vertical” or “longitudinal” mean and include a direction perpendicular to the main surface of the substrate on which the mentioned material or structure is positioned. The height of the corresponding material or structure can be defined as its dimension in a vertical plane.

[0028] As used herein, the terms “thickness,” “thinness,” or “height” mean and include a dimension in a straight line direction normal to the nearest surface of a material or structure that has a different composition or may otherwise distinguish it from a structure or material whose thickness, thinness, or height is discussed.

[0029] As used herein, the term "between" is a spatial relative term used to describe the relative placement of a material, structure, or substructure with respect to at least two other materials, structures, or substructures. The term "between" can encompass placements where a material, structure, or substructure is directly adjacent to other materials, structures, or substructures, and placements where a material, structure, or substructure is indirectly adjacent to other materials, structures, or substructures.

[0030] As used herein, the term "proximity" is a spatial relative term used to describe the placement of one material, structure, or substructure in proximity to another material, structure, or substructure. The term "proximity" includes placement that is indirectly adjacent to, directly adjacent to, and internal to another.

[0031] As used herein, the term "adjacent" when referring to a material or structure means and refers to the next closest material or structure having an identified composition or property. A material or structure having a composition or property other than the identified composition or property may be positioned between a material or structure and its "adjacent" material or structure having the identified composition or property. For example, a structure of material X "adjacent" to a structure of material Y is, for example, the first material X structure that is the next closest specific structure of material Y among a plurality of material X structures. "Adjacent" materials or structures may be directly or indirectly adjacent to a structure or material having an identified composition or property.

[0032] As used herein, either the terms “about” or “approximately” include, when used with respect to a numerical value of a particular parameter, the degree of difference from the numerical value that a person skilled in the art would understand to be within acceptable tolerances for the particular parameter. For example, with respect to a numerical value, “about” or “approximately” may include additional values ​​in the range of 90.0% to 110.0% of the numerical value (e.g., in the range of 95.0% to 105.0%, in the range of 97.5% to 102.5%, in the range of 99.0% to 101.0%, in the range of 99.5% to 100.5%, in the range of 99.9% to 100.1%).

[0033] As used herein, the term "substantially" when referring to a parameter, property, or condition means and includes that the parameter, property, or condition is equal to or within the degree of difference from a given value such that a person skilled in the art would understand that the given value is acceptablely satisfied, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be "substantially" the value when it is satisfied by at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0034] As used herein, referring to an element as “on” or “above” another element means and includes that the element is directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) the other element, below the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) the other element, below the other element, or near the other element, wherein other elements are present therein. In contrast, when an element is referred to as “directly on” or “directly adjacent to” another element, there is no intervening element.

[0035] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “bottom,” “above,” “upper,” “top,” and the like may be used to describe the relationship of one element or feature to another(s) illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover not only the orientation depicted in the figures but also different orientations of the material. For example, if the material in the figures were inverted, then an element described as “below,” “under,” or “bottom” of other elements or features would be oriented “above” or “top” of said other elements or features. Thus, the term “below” may cover both above and below orientations, depending on the context in which the term is used, as will be understood by one of ordinary skill in the art. Material may be oriented in other ways (rotated 90 degrees, inverted, etc.) and the spatial relative descriptors used herein shall be interpreted accordingly.

[0036] As used herein, the terms “level” and “height” are spatially relative terms used to describe the relationship between one element or feature as illustrated in the figures and another element or feature(s), using the main surface of the substrate on which the reference material or substrate is positioned as a reference point. As used herein, “level” and “height” are each defined by a horizontal plane parallel to the main surface. “Lower level” and “lower height” are closer to the main surface of the substrate, while “higher level” and “higher height” are further away from the main surface. Unless otherwise specified, these spatially relative terms are intended to cover different orientations of the material in addition to those depicted in the figures. For example, the material in the figures may be inverted, rotated, etc., while the spatially relative “height” descriptor remains constant because the reference main surface will also be reoriented, respectively.

[0037] As used herein, the terms “comprises / comprising” and / or “includes / including” specify the presence of the stated features, structures, stages, operations, elements, materials, components and / or groups, but do not exclude the presence or addition of one or more other features, structures, stages, operations, elements, materials, components and / or groups thereof.

[0038] As used in this document, “and / or” includes any and all combinations of one or more of the items listed in the associated list.

[0039] As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to also include the plural forms.

[0040] As used herein, the terms “configured” and “configured” mean and refer to the size, shape, material composition, orientation, and arrangement of the mentioned material, structure, assembly, or device in a predetermined manner to facilitate the mentioned operation or properties of the mentioned material, structure, assembly, or device.

[0041] The descriptions presented herein are not intended to be actual views of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but are merely idealized representations for describing embodiments of this disclosure.

[0042] The embodiments described herein are illustrated with reference to cross-sectional views, which are schematic illustrations. Therefore, variations in shape from the illustrations are expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as being limited to a specific shape or structure as illustrated, but may include shape deviations caused by factors such as manufacturing techniques. For example, a structure illustrated or described as box-shaped may have rough and / or non-linear characteristics. Furthermore, the acute angles illustrated may be rounded. Therefore, the materials, features, and structures illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the materials, features, or structures and do not limit the scope of the claims.

[0043] The following description provides a thorough description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods, offering specific details such as material types and processing conditions. However, those skilled in the art will understand that embodiments of the apparatus and methods can be practiced without these specific details. In fact, embodiments of the apparatus and methods can be practiced in conjunction with conventional semiconductor fabrication techniques used in the industry.

[0044] The manufacturing processes described herein do not form a complete process flow for processing equipment (e.g., apparatus, system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, only the methods and structures necessary for understanding embodiments of the equipment (e.g., apparatus, system) and methods of this disclosure are described herein.

[0045] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, a person skilled in the art may choose the technique for depositing or growing the material.

[0046] Unless the context otherwise indicates, the removal of the material described herein can be accomplished by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization, chemical mechanical polishing (“CMP”) or other known methods.

[0047] The diagram will now be referenced, where the same element symbol refers to the same component in various places. The diagram is not necessarily drawn to scale.

[0048] Figures 1 to 14The description outlines various stages of a method for forming a microelectronic device structure comprising interconnects self-aligned with conductive structures pointing in intersecting directions. Material stacking may be achieved by forming a substrate 102, on which a first conductive material 104, a first sacrificial material 106, and a hard mask 108 may be sequentially formed (e.g., deposited).

[0049] The first conductive material 104 may be a patterned subtractively conductive material (e.g., initially formed as a monolithic structure before the removal of selected portions of the material). The first conductive material 104 may comprise or be composed of tungsten (W), aluminum (Al), or other patterned subtractively conductive materials. In some embodiments, the first conductive material 104 may not contain copper (Cu). In other embodiments, the first conductive material 104 may comprise or be composed of copper.

[0050] In some embodiments, the first sacrificial material 106 may comprise one or more of the following: a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride), another silicon material (e.g., polysilicon / polycrystalline silicon, amorphous silicon), carbon, and / or metal nitrides, or a combination thereof. The first sacrificial material 106 may be a portion of the sacrificial material.

[0051] In some embodiments, the first sacrificial material 106 may be formed to a thickness (e.g., height) approximately equal to the desired height of the interconnect to be formed. The height can be tailored to design parasitic requirements, such as being large enough to allow sufficient space between the first and second conductive structures to avoid capacitance issues, but short enough to achieve low resistance in the interconnect. For example, the height of the first sacrificial material 106 may range from about 250 angstroms (about 25 nm) to about 1000 angstroms (about 100 nm), but shorter or taller heights are also considered.

[0052] The hard mask 108 may comprise a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride), a metal, a metal oxide (e.g., aluminum oxide, titanium oxide), a metal nitride, or a combination thereof, or may be composed of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride), a metal, a metal oxide (e.g., aluminum oxide, titanium oxide), a metal nitride, or a combination thereof. The hard mask 108 may be selectively configured to have a composition different from that of the first sacrificial material 106. That is, the composition of the first sacrificial material 106 and the hard mask 108 may be selected such that the hard mask 108 can be selectively removed subsequently without substantially removing the first sacrificial material 106.

[0053] refer to Figure 2 Next, the first conductive material 104, the first sacrificial material 106, and the hard mask 108 can be subtractively patterned. Subtractive patterning can employ at least one material removal process, which may include photolithographic patterning and etching operations. In some such embodiments, subtractive patterning achieves pitch multiplication (e.g., single pitch multiplication, double pitch multiplication, or greater than two pitch multiplications). In other embodiments, the materials can be patterned by ion milling or (e.g., if the first conductive material 104 comprises or is composed of copper (Cu)) high-temperature subtractive etching.

[0054] Patterning can form elongated features 202 including first conductive structures 204, each of the first conductive structures 204 defining a width W1. A first sacrificial material 106 of each of the elongated features 202 also has a width W1.

[0055] The number, relative arrangement, and spacing of the elongated features 202 can be customized according to design requirements. In some embodiments, discrete features may be formed instead of elongated features.

[0056] Next, as Figure 3 As described above, electrically insulating filler material 302 can be used to fill the mixture made of... Figure 2Patterned openings (e.g., trenches) are formed. The filler material 302 may include, or be composed of, materials selected from dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride) and polymeric materials (e.g., hydrocarbon materials, silicon-carbon-oxygen-hydrogen-containing materials, hydrogen methyl materials, hydrogen silsesquioxane, methylsilsesquioxane). The filler material 302 may be selected to have a chemical composition different from that of the first sacrificial material 106, such that the first sacrificial material 106 can be selectively removed subsequently without substantially removing the filler material 302.

[0057] The filler material 302 can be formed, for example, by deposition (e.g., ALD; CVD, such as plasma-enhanced chemical vapor deposition (PE-CVD); combinations thereof). In some embodiments, the filler material 302 is formed using a single (e.g., only one) deposition of the material. In other embodiments, the filler material 302 is formed using multiple (e.g., more than one) depositions of the material or multiple depositions of different materials.

[0058] The filler material 302 may be planarized (e.g., by CMP) to provide an upper surface of the filler material 302 that is coplanar with the upper surface of the hard mask 108, such as... Figure 3 As explained in the text. Therefore, filler material 302 can be formed to initially overfill. Figure 2 The openings (e.g., grooves) between the elongated features 202. In embodiments where a material is used in a single (e.g., only once) deposition to form the filler material 302, a single (e.g., only one) planarization action may also be used to planarize the filler material 302. In embodiments where a material is used in multiple (e.g., more than once) depositions or multiple depositions of different materials to form the filler material 302, one or more planarization actions may be used to planarize the filler material 302 to provide Figure 3 The structure.

[0059] Next, as Figure 4As described, the hard mask 108 can be removed to expose the first sacrificial material 106. The hard mask 108 can be removed (e.g., by planarization, such as CMP). Some of the first sacrificial material 106 may be removed together with the hard mask 108. However, whether the first sacrificial material 106 is removed without being removed with the hard mask 108 or some of the first sacrificial material 106 is removed with the hard mask 108, a sufficient amount of first sacrificial material remains to define a first height portion H1(I) of the interconnect. In some embodiments, the first height portion H1(I) may be a majority of the final height of the interconnect. The remaining first sacrificial material 106 may have an upper surface coplanar with the upper surface of the remaining fill material 302.

[0060] refer to Figure 5 Next, a barrier material 502 is formed (e.g., deposited) on the first sacrificial material 106 and the filler material 302 (e.g., directly). The barrier material 502 comprises or is composed of a dielectric material having a composition tailored to allow subsequent removal of the barrier material 502 without substantially removing either the first sacrificial material 106 or the filler material 302. For example, the barrier material 502 may comprise or be composed of carbides (e.g., silicon carbide) and / or amorphous carbon.

[0061] The barrier material 502 can be formed to completely cover Figure 4 The upper surface of the structure. Next, as... Figure 6 As illustrated, one or more openings 602 are formed through the barrier material 502 to expose a portion of the first sacrificial material 106 where the interconnect is to be formed. The openings 602 can be formed by forming a mask 604 on the barrier material 502 and selectively removing portions of the barrier material 502 in the region where the interconnect is to be formed using photolithography. The mask 604 may comprise only a photoresist material. In other embodiments, the mask 604 may be a multilayer hard mask comprising, for example, a carbide material, a dielectric antireflective coating (DARC) material, and a photoresist material.

[0062] Opening 602 may be a discrete opening. As used herein, the term "discrete opening" means and includes an opening whose horizontal perimeter is completely defined by another material (e.g., another material). Opening 602 may be a discrete opening whose horizontal perimeter is completely defined by barrier material 502. It should be understood that when opening 602 is depicted in the figures as not having a completely enclosing perimeter defined by barrier material 502, these drawings are sectional views in which portions of the structure including opening 602 are not shown for the sake of visibility of materials and structures that would not otherwise be easily seen in the drawings.

[0063] The thickness H2(I) of the barrier material 502, together with the height H1(I) of the first sacrificial material 106, defines the total height H(I) of the interconnect to be formed. In some embodiments, the thickness H2(I) of the barrier material 502 may be minimal, such that the height H1(I) of the first sacrificial material 106 substantially defines the height of the interconnect to be formed. In some embodiments, the barrier material 502 may be formed to a substantial height, such that the thickness H2(I) becomes a substantial part of the total height H(I) of the interconnect. Therefore, the thickness of the first sacrificial material 106 (e.g., height H1(I)) and the thickness of the barrier material 502 (e.g., thickness H2(I)) can be customized to achieve the desired height of the interconnect.

[0064] The opening 602 may be formed having one or more lateral dimensions (e.g., width W(B) and length L(B)) that are larger than one or more corresponding lateral dimensions of the interconnect to be formed. For example, the opening 602 may be formed having a width W(B) that is larger than the width W1 (the width of both the first conductive structure 204 and at least the lower portion of the interconnect to be formed). In some embodiments, the opening 602 may expose some filler material 302 next to the exposed portion of the first sacrificial material 106. Therefore, the opening 602 does not need to be formed with strict precision, but the resulting interconnect can be precisely aligned with the corresponding first conductive structure 204.

[0065] Although Figure 6 Only two openings 602 are described, but only one of the openings 602 may be formed (e.g., if only one interconnect is to be formed), or more than two openings 602 may be formed, wherein the number of openings 602 is equal to the number of interconnects to be formed. In some embodiments, one or more of the openings 602 may overlap with one or more first conductive structures 204, such that the interconnect will be formed to be electrically connected to one or more first conductive structures 204. Therefore, the size and placement of the openings 602 can be customized according to the desired electrical connection to be provided by the interconnects to be fabricated.

[0066] Mask 604 can be completely removed (e.g., peeled off) leaving behind... Figure 7 The structure described herein has an opening 602 through the selected area of ​​the blocking material 502, through which the selected portion of the first sacrificial material 106 is exposed. Therefore, as discussed above, mask 604 ( Figure 6 The composition can be selectively or otherwise customized to allow for selective removal of the mask 604 relative to the first sacrificial material 106 and the filler material 302.

[0067] refer to Figure 8Next, a second sacrificial material 802 and another hard mask 804 are formed (e.g., continuously deposited) over the barrier material 502, thereby filling and covering the opening 602. The second sacrificial material 802 may be in direct physical contact with portions of the first sacrificial material 106 exposed by the opening 602. The upper surface of the second sacrificial material 802 may be planarized before the formation of the other hard mask 804.

[0068] The second sacrificial material 802 may be selected from the same material as the first sacrificial material 106; however, the second sacrificial material 802 may be selected from the materials that are different from the material selected for the first sacrificial material 106, wherein the selection is made so that the second sacrificial material 802 can be removed without removing the first sacrificial material 106. For example, if the first sacrificial material 106 is formed of polycrystalline silicon, then the second sacrificial material 802 may be formed of silicon oxide.

[0069] Although the first sacrificial material 106 may be a partial sacrificial material such that a portion of the first sacrificial material 106 can be retained in the final structure, the second sacrificial material 802 may be a complete sacrificial material such that no part of it remains in the final structure (or substantially no part of it remains).

[0070] Another hard mask 804 can be selected from the above for hard mask 108 ( Figure 1 The same material discussed.

[0071] Next, as Figure 9 As illustrated, (e.g., by anisotropic etching using another hard mask 804) the second sacrificial material 802 and the other hard mask 804 are patterned to define elongated structures 902, wherein at least one of the elongated structures 902 corresponds to each of the openings 602 and has a width W2, which will define and thus resemble the width of the upper second conductive structure to be formed. The lateral dimension (e.g., width) of the second sacrificial material 802, which is in physical contact with the first sacrificial material 106 exposed within the opening 602, will define and thus resemble the length L(I) of the interconnect to be formed. Therefore, if the elongated structure 902 is formed such that the entire width W2 of the second sacrificial material 802 is within the lateral width of the corresponding one in the opening 602, then the length L(I) of the interconnect to be formed will be equal to the width W2 of the second sacrificial material 802 after patterning. However, even if the pattern of the elongated structure 902 is not ideally aligned to some extent, the width of the opening 602 will still provide a processing margin for achieving sufficient physical contact between the second sacrificial material 802 and the first sacrificial material 106 (and therefore sufficient physical contact between the subsequent upper conductive structure and the interconnect to be formed), which is greater than the length L(I) of the interconnect to be formed.

[0072] The actual length and width of the slender structure 902 can be customized to meet design requirements. Therefore, although Figure 9 The elongated structure 902 is described as terminating along line Y-Y in the longitudinal direction, but in other embodiments, the length of the elongated structure 902 may continue until its termination and be coplanar with the filler material 302, the barrier material 502, or other underlying materials.

[0073] To facilitate the explanation of the subsequent processing stages of the embodiments of this disclosure, along with... Figure 9 The following explains the subsequent processing stages for segment line (X-X) and Y-Y segmentation. Therefore, Figure 10 The explanation is along Figure 9 The segment lines X—X and Y—Y cut Figure 9 A cross-sectional view. Segment lines X—X and Y—Y pass along the sidewall or end of the second sacrificial material 802 of the elongated structure 902 through the corresponding one in the opening 602. Therefore, Figure 10 Explanation relative to Figure 9 This is another cross-sectional view, but it is not indicated that it comes from... Figure 9 Additional production processing as described in the document. Subsequent... Figures 11 to 21 The same X-X and Y-Y sectional views are maintained, but additional fabrication processes are explained below.

[0074] With a second sacrificial material 802 patterned into the elongated structure 902 and another hard mask 804, the space between the elongated structures 902 can then be filled with a filler material 1102, such as Figure 11 As described above, the filler material 1102 may include any of the filler materials described above with respect to the filler material 302 adjacent to the first conductive structure 204, or may be composed of any of the filler materials described above, and the filler material 1102 may be formed as described above with respect to the filler material 302 adjacent to the first conductive structure 204 (e.g., by deposition and planarization). Therefore, the upper surface of the filler material 1102 is coplanar with the upper surface of the other hard mask 804. In some embodiments, the filler material 1102 may be selected to have a chemical composition different from that of the filler material 302 adjacent to the first conductive structure 204. In other embodiments, the filler material 1102 and the filler material 302 may have the same chemical composition.

[0075] The space between the elongated structures 902 may be filled by depositing a filling material 1102 in one or more material deposition processes.

[0076] Next, as Figure 12 As described, another hard mask 804 is removed (e.g., by planarization, such as CMP or dry etching) to expose the second sacrificial material 802 and the filler material 1102.

[0077] Next, the second sacrificial material 802 (which, as discussed above, may be a complete sacrificial material) may be completely removed (e.g., eroded) along with the portion of the first sacrificial material 106 exposed by the opening 602, forming an extended opening 1302, as... Figure 13 As described in the text. The extended opening 1302 exposes the upper surface of the first conductive material 104 of the first conductive structure 204 between the elongated filling structures 1304 of the filling material 1102. The extended opening 1302 and the exposed portion of the first conductive material 104 encompass the entire width W1 of the first conductive structure 204 because the first sacrificial material 106 and the first conductive structure 204 are patterned together. Adjacent to the opening of the extended opening 1302, the extended opening 1302 has a width W(B) equal to that of the opening 602. Figure 6 The width of the opening 1302. However, the opening of the extended opening 1302 does not share the length L(B) of the opening 602. Figure 6 This is because the length L(I) of the extended opening 1302 is formed by the elongated structure 902 of the second sacrificial material 802. Figure 9 The width W2 defined by the given information is defined and equal to the width W2. Finally, the extended opening 1302 has a depth H, which is equal to the height of the interconnect to be formed plus the height of the upper conductive structure to be formed.

[0078] Extended opening 1302 effectively defines the negative space mold, such as Figure 14 As described, one or more other conductive materials 1402 are formed (e.g., deposited) in the negative space mold to fabricate the second conductive structure 1404 and the interconnect 1406. Therefore, the other conductive materials 1402 can be formed via a dual damascene process, but the other conductive materials 1402 extend into a lower material level patterned together with the first conductive material 104 of the first conductive structure 204. The interconnect 1406 has a height H1(I) equal to or substantially equal to the height H1(I) of the first sacrificial material 106. Figure 6 The thickness H2(I) of the added barrier material 502 Figure 6 The total height H(I).

[0079] In some embodiments, the other conductive material 1402 may be formed by a deposition of one or more conductive materials, which may be the same as or different from the conductive material of the first conductive material 104 of the first conductive structure 204. However, since the other conductive material 1402 is formed by a dual damascene process, even difficult-to-pattern conductive materials (e.g., copper (Cu)) may be included in the other conductive material 1402.

[0080] Other conductive material 1402 may be formed to overfill the extended opening 1302 and then subjected to planarization (e.g., CMP) to planarize the upper surface of the microelectronic device structure 1400, such that the upper surface of the other conductive material 1402 is coplanar with the upper surface of the filling material 1102, and a second conductive structure 1404 is formed through the elongated filling structure 1304 with the filling materials 1102 spaced apart from each other.

[0081] In some embodiments, before forming the main conductive material of the other conductive material 1402, the extension opening 1302 ( Figure 13 A barrier, seed crystal, and / or nucleating material are formed conformally within the structure. Therefore, other conductive material 1402 may comprise barrier material and / or seed crystal material. For example, in some embodiments, other conductive material 1402 includes copper (Cu) as the primary (e.g., majority) conductive material, which may be formed along the defining extension opening 1302 before the copper (Cu) is formed to fill the remainder of the extension opening 1302. Figure 13 A barrier material (e.g., nitride, such as tantalum nitride, titanium nitride, and / or tungsten nitride; silicon-containing barrier materials; or combinations of such barrier materials, such as a bilayer of different barrier materials) may be conformally formed (e.g., deposited) on the surface of the silicon-containing barrier material. This barrier material may also be used as a seed material to facilitate the conformal growth of copper (Cu) on the seed material to fill the extended opening 1302. As another example, in some embodiments, other conductive material 1402 may include tungsten as the primary conductive material, having a nucleation layer formed first to facilitate tungsten adhesion.

[0082] Other conductive material 1402 is formed to fill the extended opening 1302. Figure 13 The second conductive structure 1404 and the interconnect 1406 are integrally formed; therefore, the interconnect 1406 is self-aligned with the second conductive structure 1404. The second conductive structure 1404 is also self-aligned with the first conductive structure 204 because at least one lateral dimension of the interconnect 1406 (e.g., width W(I)) is defined by a subtractive patterning of the first conductive structure 204 with a width W1 (which is greater than W(I)). That is, the interconnect 1406 is formed only within the volume between the overlapping regions of the first conductive structure 204 and the second conductive structure 1404. Therefore, the horizontal cross-sectional region of each of the interconnects 1406 is the same as the region in which the first conductive structure 204 and the second conductive structure 1404 overlap each other (e.g., vertically overlap). Therefore, as Figure 14 As can be seen, each pair of vertical sidewalls of the interconnect 1406 can be aligned with (e.g., coplanar with) a corresponding pair of vertical sidewalls of the first conductive structure 204 and the second conductive structure 1404. For example, with the x-axis (in Figure 14The vertical sidewalls of the interconnect 1406 (indicated by arrow X) intersecting with the first conductive structure 204 (which intersects the x-axis) are coplanar with the vertical sidewalls of the first conductive structure 204 (which intersects the x-axis); and, with the y-axis (indicated by arrow X), the vertical sidewalls of the interconnect 1406 are coplanar with the vertical sidewalls of the first conductive structure 204 (which intersect Figure 14 The vertical sidewalls of the interconnect 1406 (indicated by arrow Y) intersecting with the first conductive structure 204 and the second conductive structure 1404 are coplanar with the vertical sidewalls of the second conductive structure 1404, which intersects with the y-axis. This is because the interconnect 1406 can be characterized to be "perfectly aligned" with both the first and second conductive structures 204, since the interconnect 1406 can extend beyond the sidewalls of both the first and second conductive structures 204 without overhanging or laterally extending beyond their respective sidewalls.

[0083] Therefore, this disclosure discloses a method for forming a microelectronic device structure. The method includes patterning a first conductive material and a first sacrificial material to form at least one first feature including a first conductive structure. A dielectric material is formed adjacent to the at least one first feature. Another dielectric material is formed on the first sacrificial material and the dielectric material. At least one opening is formed through the other dielectric material to expose at least one portion of the first sacrificial material. A second sacrificial material is formed on the other dielectric material and the at least one portion of the first sacrificial material exposed by the at least one opening. The second sacrificial material is patterned to form at least one second feature. Additional dielectric material is formed adjacent to the at least one second feature. The second sacrificial material and the at least one portion of the first sacrificial material are removed to form an extended opening therein exposing at least one portion of the first conductive material. The extended opening is then filled with a second conductive material to form at least one interconnect in each of the extended openings.

[0084] Figure 14 The description also describes a microelectronic device structure 1400 comprising interconnects 1406 that are self-aligned with both a lower conductive structure (e.g., a first conductive structure 204) and an upper conductive structure (e.g., a second conductive structure 1404), wherein the interconnected conductive structures point in intersecting directions. For example, the first conductive structure 204 is described as pointing along the y-axis (indicated by arrow Y), while the second conductive structure 1404 is described as pointing along the x-axis (indicated by arrow X). In other words, the directions of the elongated lengths of the corresponding conductive structures are non-collinear. By forming the microelectronic device structure 1400 using the method described above, the interconnects 1406 can be formed only where the first conductive structure 204 and the second conductive structure 1404 vertically overlap each other, if this overlapping area coincides with the opening 602 in the barrier material 502 ( Figure 6One of them overlaps. No interconnect is formed where the barrier material 502 is inserted between the overlapping areas of the first conductive structure 204 and the second conductive structure 1404. Therefore, the patterning of the barrier material 502 enables the selection of the position of the interconnect 1406, and the aforementioned manufacturing method achieves self-alignment between the interconnect 1406 and both the first conductive structure 204 and the second conductive structure 1404.

[0085] In the microelectronic device structure 1400, the lower portion of each of the interconnects 1406 is disposed between segments of the remaining portion of the first sacrificial material 106, the segments defining the same width W1 as the first conductive structure 204.

[0086] In some embodiments, the microelectronic device structure 1400 includes a barrier material 502 and at least a portion of the first sacrificial material 106 between the overlapping portions of the first conductive material 104 and other conductive materials 1402 (e.g., between them in the vertical direction), at least where one of the interconnects 1406 is not present. Where the first sacrificial material 106 overlaps with the first conductive material 104, the materials may have coplanar vertical sidewalls.

[0087] Therefore, this disclosure discloses a microelectronic device including an interconnect between a lower conductive structure and an upper conductive structure. The interconnect occupies only the volume between the lower and upper conductive structures, which are vertically overlapping. The interconnect extends through a dielectric material.

[0088] Although Figure 14 The microelectronic device structure 1400 only illustrates two levels of interconnected conductive structures (e.g., the lower conductive structure of the first conductive structure 204 and the upper conductive structure of the second conductive structure 1404), but the method of this disclosure can also be adapted to form a microelectronic device structure having two or more levels of interconnected conductive structures, including a plurality of interconnects self-aligned with a pair of corresponding second conductive structures above and below. This method can be achieved by removing (e.g., by etching) a portion of other conductive material 1402 to make the other conductive material 1402 recessed relative to the filler material 1102 (e.g., ...). Figure 15 (as explained in the text) and from Figure 14 The manufacturing process continues as described in the diagram. The remaining conductive material 1402 is structured in the recessed elongated feature 1502 to form a recess 1504 between the other conductive material 1402 and the sidewalls of the filling material 1102.

[0089] Next, the recess 1504 can be filled by forming (e.g., depositing) an additional amount of the first sacrificial material 106 (or another portion of the material discussed above regarding the first sacrificial material 106 on the first conductive material 104, provided that the selected sacrificial material is formulated to be selectively removable relative to the filler material 1102). In some embodiments, the additional amount of the first sacrificial material 106 may be formed to initially overfill the recess 1504 and then planarized (e.g., by CMP) to expose the filler material 1102 through the first sacrificial material 106. Figure 16 The structure described herein essentially provides the same as Figure 3 The processing stage is similar to the previous processing stage, wherein an additional amount of first sacrificial material 106 defines a pattern of other conductive material 1402 that matches the pattern of the second conductive structure 1602 on which the first sacrificial material 106 is formed. However, while the first sacrificial material 106 on the first conductive structure 204 is subtractively patterned together with the first conductive material 104, the first sacrificial material 106 on the second conductive structure 1062 is additively formed (e.g., by a dual damascene process) within the negative space defined by the recess 1504.

[0090] refer to Figure 17 And similar to Figures 5 to 7 In the next processing stage, another structure of the barrier material 502 can be formed. Figure 16 The structure covers the first sacrificial material 106 on the second conductive structure 1602 and the fill material 1102 between the second conductive structures 1602. Then, one or more additional openings 602 may be formed (e.g., etched) through the barrier material 502 where additional interconnects are to be formed. One or more additional openings 602 expose at least a portion of the first sacrificial material 106 and, where appropriate, a portion of the fill material 1102. As formed in the first conductive structure 204 ( Figure 7 In some embodiments, the opening 602 formed above the first conductive structure 204 can be sized and positioned to form an interconnect for connection to one or more second conductive structures 1602 if an electrical connection via an interconnect is desired. Therefore, the size and positioning of the opening 602 (whether above the first conductive structure 204 or above the second conductive structure 1602, etc.) can be customized to provide electrical connections as needed between a pair of conductive structures, one above and one below; between a lower conductive structure and multiple upper conductive structures; between multiple lower conductive structures and one upper conductive structure; or between multiple lower conductive structures and multiple upper conductive structures.

[0091] refer to Figure 18 And similar to Figures 8 to 10In the next processing stage, an additional amount of the second sacrificial material 802 (or another fully sacrificial material of the material discussed above regarding the second sacrificial material 802, which is later replaced by another conductive material 1402 of the second conductive structure 1602) and another portion of the other hard mask 804 may be formed (e.g., deposited) and patterned to define a width W3, which defines and is therefore similar to the width W(I2) of the additional interconnect to be formed. The second sacrificial material 802 may be in direct physical contact with the first sacrificial material 106 in one or more openings 602.

[0092] refer to Figure 19 And similar to Figure 11 and Figure 12 During the processing stage, an additional amount of filler material 302 (or another filler material discussed above with respect to filler material 302 adjacent to the first conductive structure 204) may be formed (e.g., deposited and planarized) to fill the space adjacent to the patterned second sacrificial material 802.

[0093] refer to Figure 20 And similar to Figure 13 During the processing stage, the second sacrificial material 802 may be removed (e.g., etched) to leave an extended opening 1302 that exposes a portion of the upper surface of the other conductive material 1402, a portion of the opening 602, and a portion of the blocking material 502.

[0094] refer to Figure 21 And similar to Figure 14 In the next processing stage, the extended opening 1302 can be filled with another conductive material 1402 (which may have a material composition substantially the same as or different from that of the other conductive material 1402 of the second conductive structure 1602). Figure 20 ), to form a third conductive structure 2102 integrally formed with the additional interconnect 2104, the additional interconnect 2104 and the... Figure 20 The extended opening 1302 exposes the second conductive structure 1602 in partial physical contact with other conductive material 1402.

[0095] The additional interconnect 2104 is self-aligned with both the second conductive structure 1602 and the third conductive structure 2102. The additional interconnect 2104 has: a width W (I2), defined by and equal to the width W3 of the additional interconnect 2104; a length L (I), defined by and equal to the width W2 of the second conductive structure 1602; and a height H (I2), formed from the... Figure 15 The thickness of the first sacrificial material 106 in the recess 1504 plus the thickness of the blocking material 502 formed on (e.g., above) the second conductive structure 1602 is defined and equal to the thickness of the material formed on (e.g., above) the second conductive structure 1602. Figure 15The thickness of the first sacrificial material 106 in the recess 1504 is added to the thickness of the blocking material 502 formed on (e.g., above) the second conductive structure 1602. The additional interconnect 2104 has a pair of vertical sidewalls coplanar with the corresponding vertical sidewall pairs of the second conductive structure 1602 and the third conductive structure 2102, but does not have an overhang.

[0096] Therefore, this disclosure discloses a method for forming a microelectronic device structure. The method involves: forming an elongated feature portion, the elongated feature portion including a first sacrificial material on a first conductive structure; forming a dielectric material on the first sacrificial material; forming an opening through the dielectric material to expose a portion of the first sacrificial material; forming a second sacrificial material on the portion of the first sacrificial material in the opening; patterning the second sacrificial material to form another elongated feature portion; forming another dielectric material adjacent to the other elongated feature portion; removing the second sacrificial material and the portion of the first sacrificial material to form another opening exposing a portion of the first conductive structure; and adding at least one second conductive material on the portion of the first conductive structure in the other opening to form a second conductive structure integrally formed with an interconnect that is physically in contact with the first conductive structure.

[0097] Figure 21 The text also describes a microelectronic device structure 2100 comprising multiple interconnects self-aligned with multiple layers of a conductive structure, wherein each layer is arranged in a direction intersecting the direction of the conductive structure of at least another layer. For example, as... Figure 21 As described, the first conductive structure 204 and the third conductive structure 2102 point along the y-axis (indicated by arrow Y), while the second conductive structure 1602 points along the x-axis (indicated by arrow X). Although Figure 21 The intersecting directions are described as generally perpendicular, but in other embodiments, if defined on the xy plane, the intersecting directions may be acute or obtuse. However, interconnect 1406 and additional interconnect 2104 are formed in an embodiment of this disclosure in a manner that is self-aligned with the conductive structures above and below, and are formed only where the conductive structures vertically overlap, provided that the blocking material 502 is not involved (e.g., due to the selectively formed opening 602).

[0098] Embodiments of this disclosure can also be used to form microelectronic devices having interconnects with self-aligned conductive structures pointing in a collinear direction. For example, see reference... Figure 22The first conductive material 104 and the first sacrificial material 106 may be formed and subtractively patterned to form at least one conductive structure 2202, a filling material 302 formed in the space between adjacent features of the first conductive material 104, and a barrier material 502 formed and selectively etched to form an opening 602 at the desired interconnect location (similar to) Figures 1 to 7 (The production stage).

[0099] refer to Figure 23 A second sacrificial material 802 can be formed above the blocking material 502 and in the opening 602, and then the second sacrificial material 802 can be patterned (similar to) before the empty space is filled with the filling material 1102. Figures 8 to 12 (The manufacturing stage). However, in this embodiment, the second sacrificial material 802 is patterned to define a length that is collinear with the length of the first sacrificial material 106 and the first conductive material 104. For example, the first conductive material 104, the first sacrificial material 106, and the second sacrificial material 802 may all be patterned to form an elongated structure pointing along the y-axis.

[0100] As described in the embodiments above, the thickness of the first sacrificial material 106 and the thickness H2(I) of the blocking material 502 define the height H(I) of the interconnect to be formed.

[0101] Similar to Figure 13 The production stage, such as Figure 24 As explained, the second sacrificial material 802 can then be completely removed (e.g., eroded) along with portions of the first sacrificial material 106 exposed by one or more openings 602, leaving an extended opening 2402 exposing a portion of the first conductive material 104. The extended opening 2402 has a width W1 defined by and equal to the width of the first conductive material 104 (and the first sacrificial material 106), which also defines the width W(I) of the interconnect to be formed. The extended opening 2402 has a depth H(I) defined by and equal to the height of the interconnect to be formed.

[0102] Next, as Figure 25 The description in the document (and similar to) Figure 14 During the manufacturing stage, the extended opening 2402 can be filled with other conductive materials 1402 to integrally form the second conductive structure 2502 and the interconnect 2504.

[0103] like Figure 25As described herein, the microelectronic device structure 2500 includes interconnects 2504 between collinearly oriented conductive structures. The width W(I) of the interconnect 2504 is defined by the width of a second sacrificial material 802 that vertically overlaps with a first sacrificial material 106 within each of one or more openings 602. The second sacrificial material 802 is patterned to perfectly align with the patterns of the first sacrificial material 106 (and the first conductive material 104) within the corresponding openings 602 (e.g., ...). Figure 23 In the embodiment described herein, the width W(I) of the interconnect 2504 is equal to the width W1 of both the first conductive material 104 and the second conductive structure 2502. However, if the pattern of the second sacrificial material 802 has slightly shifted from the pattern of the first sacrificial material 106 (and the first conductive material 104), then the width W(I) of the interconnect 2504 will be narrower, but it will still be self-aligned with the first conductive material 104 and the second conductive structure 2502.

[0104] Because the first conductive material 104 and the second conductive structure 2502 are collinearly aligned, in this embodiment, the length L(I) of the interconnect 2504 is defined not only by the length or width of either the first conductive material 104 or the second conductive structure 2502, but also by the length of the corresponding part of the opening 602. Therefore, the longer the opening 602 is formed, the wider the first conductive structure 2202 will be. Thus, the length of the opening 602 can be customized according to the design requirements of the length L(I) of the interconnect 2504.

[0105] Therefore, this disclosure also discloses a microelectronic device structure. The microelectronic device structure includes a first conductive structure vertically overlapping a second conductive structure. An interconnect is integral with the second conductive structure and directly disposed between the first and second conductive structures. The interconnect includes at least one vertical sidewall coplanar with at least one vertical sidewall of the first conductive structure. At least another vertical sidewall of the interconnect is coplanar with at least one vertical sidewall of the second conductive structure. A dielectric material is disposed between the first and second conductive structures. The dielectric material defines at least one opening through which the interconnect extends.

[0106] Figure 26 A block diagram of a system 2600 according to an embodiment of the present disclosure is shown. System 2600 includes a memory 2602, which includes multiple layers of electrically interconnected conductive structures. The architecture and structure of memory 2602 may include those of embodiments according to the present disclosure. Figure 14 Microelectronic device structure 1400, Figure 21 Microelectronic device structure 2100 and / or Figure 25 The microelectronic device structure is 2500, and can be referenced above. Figures 1 to 25 One or more of the methods described are used to make it.

[0107] System 2600 may include a controller 2604 operatively coupled to memory 2602. System 2600 may also include another electronic device 2606 and one or more peripheral devices 2608. In some embodiments, the other electronic device 2606 may include components according to embodiments of this disclosure. Figure 14 Microelectronic device structure 1400, Figure 21 Microelectronic device structure 2100 and / or Figure 25 One or more of the microelectronic device structures 2500, and can be manufactured according to one or more of the methods described above. One or more of the controller 2604, memory 2602, another electronic device 2606 and peripheral device 2608 may be in the form of one or more integrated circuits (ICs).

[0108] Bus 2610 provides conductivity and operable communication between and / or among the various components of system 2600. Bus 2610 may include address buses, data buses, and control buses, each with its own independent configuration. Alternatively, bus 2610 may use conductive lines to provide one or more of the address, data, or control functions that can be adjusted by controller 2604. Controller 2604 may be in the form of one or more processors.

[0109] Another electronic device 2606 may include additional memory (e.g., having an embodiment according to this disclosure). Figure 14 Microelectronic device structure 1400, Figure 21 Microelectronic device structure 2100 and / or Figure 25 (One or more of the microelectronic device structures 2500, and which can be fabricated according to one or more of the methods described above) Other memory structures of memory 2602 and / or another electronic device 2606 may be configured as, for example, 3D NAND, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic RAM (DDR), double data rate SDRAM and / or magnetic-based memory (e.g., spin-transfer torque magnetic RAM (STT-MRAM)).

[0110] Peripheral device 2608 may include a display, imaging device, printing device, wireless device, additional storage memory and / or control device that can operate in conjunction with controller 2604.

[0111] System 2600 may include, for example, fiber optic systems or devices, electro-optic systems or devices, optical systems or devices, imaging systems or devices, and information processing systems or devices (e.g., wireless systems or devices, telecommunications systems or devices, and computers).

[0112] Therefore, a system is disclosed comprising at least one microelectronic device structure, at least one processor, and at least one peripheral device. The at least one microelectronic device structure includes at least one interconnect between a lower conductive structure and an upper conductive structure. The at least one interconnect extends through discrete openings in a dielectric material. The horizontal cross-sectional region of the interconnect is the region where the upper conductive structure and the lower conductive structure vertically overlap. The at least one processor is operatively in communication with the at least one microelectronic device structure. The at least one peripheral device is operatively in communication with the at least one processor.

[0113] Non-limiting examples may include the following examples, alone or in combination:

[0114] Example 1: A method of forming a microelectronic device, the method comprising: patterning a first conductive material and a first sacrificial material to form at least one first feature including a first conductive structure; forming a dielectric material adjacent to the at least one first feature; forming another dielectric material on the first sacrificial material and the dielectric material; forming at least one opening through the other dielectric material to expose at least one portion of the first sacrificial material; forming a second sacrificial material on the other dielectric material and the at least one portion of the first sacrificial material exposed by the at least one opening; patterning the second sacrificial material to form at least one second feature; forming additional dielectric material adjacent to the at least one second feature; removing the second sacrificial material and the at least one portion of the first sacrificial material to form an extended opening therein exposing at least one portion of the first conductive material; and filling the extended opening with a second conductive material to form at least one interconnect in each of the extended openings.

[0115] Example 2: According to the method of Example 1, removing the second sacrificial material and at least one portion of the first sacrificial material includes: completely removing the second sacrificial material; and removing at least one portion of the first sacrificial material while leaving at least another portion of the first sacrificial material adjacent to the other dielectric material.

[0116] Example 3: The method according to any one of Examples 1 and 2, wherein patterning the first conductive material and the first sacrificial material includes: forming an elongated feature portion pointing along a first axis.

[0117] Example 4: According to the method of Example 3, patterning the second sacrificial material includes forming another elongated feature along a second axis that is not collinear with the first axis.

[0118] Example 5: According to the method of Example 3, patterning the second sacrificial material includes forming another elongated feature along a second axis collinear with the first axis.

[0119] Example 6: The method according to any one of Examples 1 to 5 further includes forming the at least one interconnect to a height equal to the height of the first sacrificial material plus the thickness of the other dielectric material.

[0120] Example 7: The method according to any one of Examples 1 to 6, wherein forming at least one opening through the other dielectric material comprises: forming at least one discrete opening through the other dielectric material.

[0121] Example 8: The method according to any one of Examples 1 to 7, wherein filling the extended opening with the second conductive material comprises: forming the second conductive material to include one or more of a barrier material, a seed material, and a nucleating material; and at least one other conductive material on one or more of the barrier material, the seed material, and the nucleating material.

[0122] Example 9: The method according to Example 1 to 8 further includes forming a region of the first conductive material to cover the substrate before patterning the first conductive material and the first sacrificial material, wherein the first conductive material does not contain copper.

[0123] Example 10: According to the method of Example 9, wherein forming the second conductive material to fill the extended opening includes: forming copper within the extended opening.

[0124] Example 11: A microelectronic device comprising: an interconnect between a lower conductive structure and an upper conductive structure, the interconnect occupying only the volume in which the lower conductive structure and the upper conductive structure vertically overlap each other; and a dielectric material through which the interconnect extends.

[0125] Example 12: The microelectronic device according to Example 11, wherein the interconnect is integrally formed with the upper conductive structure.

[0126] Example 13: A microelectronic device according to any one of Examples 11 and 12, wherein the lower portion of the interconnect is disposed between segments of a portion of sacrificial material having a width equal to the width of the lower conductive structure.

[0127] Example 14: A microelectronic device according to any one of Examples 11 to 13, wherein the interconnects extend through discrete openings formed in the dielectric material.

[0128] Example 15: The microelectronic device according to Example 14, wherein the width of the discrete opening is greater than the width of the interconnect.

[0129] Example 16: A microelectronic device according to any one of Examples 14 and 15, wherein the length of the discrete opening is greater than the length of the interconnect.

[0130] Example 17: A microelectronic device according to any one of Examples 14 and 15, wherein the length of the discrete opening is equal to the length of the interconnect.

[0131] Example 18: A method of forming a microelectronic device, the method comprising: subtracting an elongated feature including a first sacrificial material on a first conductive structure; forming a dielectric material on the first sacrificial material; forming a first opening through the dielectric material to expose a portion of the first sacrificial material; forming a second sacrificial material on the portion of the first sacrificial material in the first opening; patterning the second sacrificial material to form another elongated feature; forming another dielectric material adjacent to the other elongated feature; removing the second sacrificial material and the portion of the first sacrificial material to form a second opening exposing a portion of the first conductive structure; and adding at least one second conductive material on the portion of the first conductive structure in the second opening to form a second conductive structure integrally formed with an interconnect physically in contact with the first conductive structure.

[0132] Example 19: The method according to Example 18 further includes: recessing the second conductive material relative to the other dielectric material to form a recess; and forming a third sacrificial material in the recess.

[0133] Example 20: The method according to Example 19 further includes: forming the dielectric material on the third sacrificial material; forming a third opening through the dielectric material to expose a portion of the third sacrificial material; forming a fourth sacrificial material on the portion of the third sacrificial material in the third opening; patterning the fourth sacrificial material to form an additional elongated feature; forming another dielectric material adjacent to the additional elongated feature; removing the fourth sacrificial material and the portion of the third sacrificial material to form a fourth opening exposing a portion of the second conductive structure; and adding at least one third conductive material on the portion of the second conductive structure in the fourth opening to form a third conductive structure integrally formed with another interconnect in physical contact with the second conductive structure.

[0134] Example 21: A microelectronic device comprising: a first conductive structure vertically overlapping a second conductive structure; an interconnect integrally formed with the second conductive structure and directly disposed between the first conductive structure and the second conductive structure, the interconnect comprising: at least one vertical sidewall coplanar with at least one vertical sidewall of the first conductive structure; and at least another vertical sidewall coplanar with at least one vertical sidewall of the second conductive structure; and a dielectric material between the first conductive structure and the second conductive structure, the dielectric material defining at least one opening, the interconnect extending through the at least one opening.

[0135] Example 22: The microelectronic device according to Example 21 further includes: a third conductive structure that vertically overlaps with the second conductive structure; another interconnect that is integral with the third conductive structure and directly disposed between the second conductive structure and the third conductive structure, the other interconnect being disposed only in the region where the third conductive structure overlaps with the second conductive structure; and another dielectric material between the second conductive structure and the third conductive structure, the other dielectric material defining at least one other opening, the other interconnect extending through the at least one other opening.

[0136] Example 23: The microelectronic device according to Example 22, wherein the third conductive structure is collinearly pointed with the first conductive structure, but not collinearly pointed with the second conductive structure.

[0137] Example 24: A system comprising: at least one microelectronic device including at least one interconnect between a lower conductive structure and an upper conductive structure and extending through a discrete opening in a dielectric material, the horizontal cross-sectional region of the interconnect being a region where the upper conductive structure and the lower conductive structure vertically overlap; at least one processor operatively communicating with the at least one microelectronic device; and at least one peripheral device operatively communicating with the at least one processor.

[0138] Example 25: The system according to Example 24, wherein: the upper conductive structure and the lower conductive structure completely overlap, the interconnect has a width equal to the width of the upper conductive structure and the width of the lower conductive structure, and the horizontal cross-sectional region of the interconnect has the length of the discrete opening, and the interconnect has a length equal to the length of the discrete opening.

[0139] Example 26: The system according to Example 24, wherein the upper conductive structure partially overlaps with the lower conductive structure, and the discrete opening has a region larger than the horizontal cross-sectional region of the interconnect.

[0140] While the disclosed structures, apparatuses, systems, and methods are susceptible to various modifications and alternatives in their implementation, specific embodiments have been illustrated by way of example in the drawings and described in detail herein. However, this disclosure is not intended to limit it to the specific forms disclosed. Rather, this disclosure covers all modifications, combinations, equivalents, variations, and alternatives that fall within the scope of this disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A method for forming a microelectronic device, the method comprising: Patterning a first conductive material and a first sacrificial material to form at least one first feature including a first conductive structure; A dielectric material is formed adjacent to the at least one first feature portion; Another dielectric material is formed on the first sacrificial material and the dielectric material; Form at least one opening through the other dielectric material to expose at least a portion of the first sacrificial material; A second sacrificial material is formed on the other dielectric material and on at least a portion of the first sacrificial material exposed by the at least one opening; The second sacrificial material is patterned to form at least one second feature; Forming additional dielectric material adjacent to the at least one second feature portion; Remove at least one portion of the second sacrificial material and the first sacrificial material to form an extended opening in which at least one portion of the first conductive material is exposed; and The extended openings are filled with a second conductive material to form at least one interconnect in each of the extended openings.

2. The method of claim 1, wherein removing the second sacrificial material and at least one portion of the first sacrificial material comprises: Completely remove the second sacrificial material; and Remove at least one portion of the first sacrificial material while leaving at least another portion of the first sacrificial material adjacent to the other dielectric material.

3. The method according to any one of claims 1 and 2, wherein patterning the first conductive material and the first sacrificial material comprises: A slender feature portion is formed along the first axis.

4. The method of claim 3, wherein patterning the second sacrificial material comprises: Another elongated feature is formed along a second axis that is not collinear with the first axis.

5. The method according to claim 3, wherein The patterned second sacrificial material includes: Another elongated feature is formed along a second axis that is collinear with the first axis.

6. The method according to any one of claims 1 and 2, further comprising forming the at least one interconnect to a height equal to the height of the first sacrificial material plus the thickness of the other dielectric material.

7. The method according to any one of claims 1 and 2, wherein forming at least one opening through the other dielectric material comprises forming at least one discrete opening through the other dielectric material.

8. The method according to any one of claims 1 and 2, wherein filling the extended opening with the second conductive material comprises: The second conductive material is formed to include: One or more of the following: barrier materials, seed materials, and nucleating materials; and At least one other conductive material on one or more of the barrier material, the seed material, and the nucleating material.

9. The method according to any one of claims 1 and 2, further comprising forming a region of the first conductive material to cover the substrate before patterning the first conductive material and the first sacrificial material, wherein the first conductive material is copper-free.

10. The method of claim 9, wherein forming the second conductive material to fill the extended opening comprises: Copper is formed within the extended opening.

11. A method of forming a microelectronic device, the method comprising: An elongated feature portion comprising a first sacrificial material is formed on the first conductive structure; A dielectric material is formed on the first sacrificial material; An opening is formed through the dielectric material to expose a portion of the first sacrificial material; A second sacrificial material is formed on the portion of the first sacrificial material in the opening; The second sacrificial material is patterned to form another elongated feature; Another dielectric material is formed adjacent to the other elongated feature; Remove the portion of the second sacrificial material and the first sacrificial material to form another opening that exposes a portion of the first conductive structure; and At least one second conductive material is added to the portion of the first conductive structure in the other opening to form a second conductive structure integrally formed with an interconnect that is in physical contact with the first conductive structure.

12. The method of claim 11, further comprising: The second conductive material is recessed relative to the other dielectric material to form a recess; and A third sacrificial material is formed in the recess.

13. The method of claim 12, further comprising: The dielectric material is formed on the third sacrificial material; A third opening is formed through the dielectric material to expose a portion of the third sacrificial material; A fourth sacrificial material is formed on the portion of the third sacrificial material in the third opening; Pattern the fourth sacrificial material to form additional elongated features; Another dielectric material is formed adjacent to the additional elongated feature portion; Remove the portion of the fourth sacrificial material and the third sacrificial material to form a fourth opening that exposes a portion of the second conductive structure; and At least one third conductive material is added to the portion of the second conductive structure in the fourth opening to form a third conductive structure integrally formed with another interconnect that is in physical contact with the second conductive structure.

14. A microelectronic device comprising: An interconnection element located between a lower conductive structure and an upper conductive structure, the interconnection element occupying only the volume between the lower conductive structure and the upper conductive structure, wherein the lower conductive structure and the upper conductive structure are vertically overlapping each other and the lower conductive structure is in the intersecting direction relative to the upper conductive structure; and Dielectric material, the interconnects extending through the dielectric material, The lower portion of the interconnect is disposed between segments of partially sacrificial material, the segments of which are located below the dielectric material and have a width equal to the width of the lower conductive structure.

15. The microelectronic device of claim 14, wherein the interconnect is integrally formed with the upper conductive structure.

16. The microelectronic device according to any one of claims 14 and 15, wherein the interconnects extend through discrete openings formed in the dielectric material.

17. The microelectronic device of claim 16, wherein the width of the discrete opening is greater than the width of the interconnect.

18. The microelectronic device of claim 16, wherein the length of the discrete opening is greater than the length of the interconnect.

19. The microelectronic device of claim 17, wherein the length of the discrete opening is equal to the length of the interconnect.

20. A microelectronic device comprising: A first conductive structure is vertically overlapped with a second conductive structure, wherein the elongated length of the first conductive structure is not collinear with the elongated length of the second conductive structure; An interconnecting element, integral with the second conductive structure and directly disposed between the first conductive structure and the second conductive structure, the interconnecting element comprising: At least one vertical sidewall that is coplanar with at least one vertical sidewall of the first conductive structure; and At least one other vertical sidewall coplanar with at least one vertical sidewall of the second conductive structure; and A dielectric material is disposed between the first conductive structure and the second conductive structure, the dielectric material defining at least one opening, and the interconnect extending through the at least one opening. The lower portion of the interconnect is disposed between segments of partially sacrificial material, the segments of which are located below the dielectric material and have a width equal to that of the first conductive structure.

21. The microelectronic device of claim 20, further comprising: The third conductive structure is vertically overlapped with the second conductive structure; Another interconnecting element is integral with the third conductive structure and is directly disposed between the second conductive structure and the third conductive structure, wherein the other interconnecting element is disposed only in the region where the third conductive structure and the second conductive structure overlap; and Another dielectric material is disposed between the second conductive structure and the third conductive structure, the other dielectric material defining at least another opening, and the other interconnect extending through the at least another opening.

22. The microelectronic device of claim 21, wherein the third conductive structure is collinearly pointed with the first conductive structure but not collinearly pointed with the second conductive structure.

23. An electronic system comprising: At least one microelectronic device includes at least one interconnect between a lower conductive structure and an upper conductive structure and extending through discrete openings in a dielectric material, wherein a horizontal cross-sectional region of the interconnect is a region in which the upper conductive structure and the lower conductive structure vertically overlap, and a lower portion of the at least one interconnect is disposed between segments of partially sacrificial material located below the dielectric material and having a width equal to the width of the lower conductive structure. At least one processor that is operatively in communication with the at least one microelectronic device; and At least one peripheral device that is operable and communicative with the at least one processor.

24. The electronic system according to claim 23, wherein: The upper conductive structure completely overlaps with the lower conductive structure, and the at least one interconnect has a width equal to the width of both the upper and lower conductive structures. The horizontal cross-sectional region of the at least one interconnect has the length of the discrete opening, and the at least one interconnect has a length equal to the length of the discrete opening.

25. The electronic system of claim 23, wherein the upper conductive structure partially overlaps with the lower conductive structure, and the discrete opening has a region larger than the horizontal cross-sectional region of the at least one interconnect.

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