Storage device, control method of storage device, and storage medium

Abstract

A storage device, a control method of the storage device, and a storage medium, which can be used in a device having a memory. The storage device controller provides a super-block valid page count table for a plurality of super-blocks and a plurality of internal block valid page count tables for the plurality of super-blocks, and provides a plurality of virtual block mapping tables for the plurality of memory chips to map a first super-block among the plurality of super-blocks associated with a physical block address to a second super-block among the plurality of super-blocks. Accordingly, when the storage device needs to perform garbage collection, the effective number of pages of the super-block can be reduced by updating and mapping the internal blocks of the selected super-block to be garbage collected, so as to improve the efficiency of garbage collection.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to a storage device, a control method of the storage device and a storage medium. Background Art

[0002] Since the data stored in non-volatile storage devices will not disappear after power failure, and they are power-saving and small in size, non-volatile storage devices such as flash memory-based storage devices are widely used in electronic devices. In addition, non-volatile storage devices such as solid-state storage devices (SSDs) have gradually become storage devices equipped in computer systems such as desktop computers, notebook computers, and servers.

[0003] When an electronic device executes an application to store text, data, photos, play audio or video and other data, it often needs to make a large amount of data write action request to the storage device in a short period of time. The controller of the storage device can generate a write command under the write request of the electronic device (i.e., the host) and execute the generated write command. The controller of the storage device can use a command queue to store the host write command. The host write commands stored in the command queue can be output sequentially to the memory of the storage device to perform data write actions. On the other hand, the storage device also has the need for internal data movement. If the storage device processes internal data movement, it may affect the efficiency of the execution of the write command from the electronic device, resulting in a decrease and fluctuation in the write performance of the electronic device. In this way, the decrease and fluctuation of the write performance is reflected in the fluctuating and unstable situation of the fluency reflected by the application or the efficiency of the service provided by the application.

[0004] For storage devices such as flash memory or solid-state drives, write amplification (WA) is an undesirable phenomenon, that is, the actual amount of physical data written is multiple times the amount of data written. In flash memory and solid-state drives, data is written to the flash memory in pages consisting of multiple storage units (cells). However, it can only be erased in larger units, such as blocks consisting of multiple pages. If some pages in a block have data that is no longer needed, these pages are called invalid pages, and the pages in the block that have the required data are called valid pages. In order to make the block available for rewriting data, the storage device will perform a process called garbage collection (GC), which reads only the valid pages in the block and rewrites them to another previously erased empty block, and then erases the aforementioned block to make it a new empty block. All SSDs contain garbage collection mechanisms to varying degrees, but they vary in the frequency and speed of execution. Garbage collection accounts for a large part of the write amplification of the above storage devices.

[0005] Therefore, among the many internal data movement requirements of storage devices, garbage collection plays an important role, and the performance of garbage collection will affect the overall write performance of electronic devices. Summary of the invention

[0006] An embodiment provides a storage device, a control method for a storage device, and a storage medium, which can be used in a device having a memory and can be used to improve the efficiency of garbage collection by processing a super block selected for garbage collection to reduce the number of valid pages of the super block when the storage device needs to perform garbage collection regarding internal data movement.

[0007] An embodiment provides a control method for a storage device, the storage device comprising a storage device controller and a memory comprising a plurality of memory chips, the control method comprising the following steps. (a) The storage device controller provides a plurality of superblock valid page count tables of superblocks and a plurality of internal block valid page count tables of the plurality of superblocks, wherein each superblock corresponds to a set of different, non-overlapping multiple physical blocks belonging to the plurality of memory chips, each physical block corresponds to a portion of multiple pages of a corresponding memory chip in the plurality of memory chips, and the superblock valid page count table includes the total valid page count of multiple physical blocks corresponding to each of the plurality of superblocks, and each internal block valid page count table corresponds to a superblock in the plurality of superblocks and includes multiple valid page counts corresponding to multiple physical blocks of the superblock. (b) The storage device controller provides a plurality of virtual block mapping tables of the plurality of memory chips to map a first superblock in the plurality of superblocks associated with a physical block address to a second superblock in the plurality of superblocks. (c) Based on the super block valid page count table, the storage device controller determines at least one selected super block from the plurality of super blocks to be processed for garbage collection. (d) The storage device controller reduces the total number of valid pages of the at least one selected super block by re-mapping the at least one selected super block based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables. (e) Performing a garbage collection step on the re-mapped at least one selected super block.

[0008] In one embodiment, the step (d) includes: (d1) determining, based on the multiple internal block valid page count tables, whether the memory chip to which the first physical block among the multiple physical blocks of the at least one selected super block belongs has a second physical block, the number of valid pages of the second physical block being less than the number of valid pages of the first physical block; and (d2) if it is determined that the memory chip to which the first physical block among the multiple physical blocks of the at least one selected super block belongs has a second physical block whose number of valid pages is less than the number of valid pages of the first physical block, re-mapping the first physical block and the second physical block by updating at least one of the multiple virtual block mapping tables.

[0009] In one embodiment, when the number of valid pages of the first physical block is greater than or equal to a valid page number threshold, the step (d1) is executed.

[0010] In one embodiment, in the step (d2), the first physical block and the second physical block are remapped by updating the virtual block mapping table of the memory chip to which the first physical block of the at least one selected super block and the second physical block of another super block belong.

[0011] In one embodiment, the virtual block mapping table of the memory chip is updated to include data indicating that the first physical block of the at least one selected super block is mapped to a second physical block of another super block.

[0012] The embodiment further provides a storage medium which records a program code for causing a storage device to execute a storage device control method as described in any one of the above-mentioned embodiments.

[0013] The embodiment further provides a storage device, comprising a memory and a storage device controller. The memory comprises a plurality of memory chips. The storage device controller is electrically connected to the memory and is used to control the memory to access data to the memory, wherein the storage device controller is configured to perform a plurality of steps. The plurality of steps include the following. (a) The storage device controller provides a plurality of superblock valid page count tables of superblocks and a plurality of internal block valid page count tables of the plurality of superblocks, wherein each superblock corresponds to a set of different, non-overlapping multiple physical blocks belonging to the plurality of memory chips, each physical block corresponds to a portion of a plurality of pages of a corresponding memory chip in the plurality of memory chips, and the superblock valid page count table includes a total valid page count of a plurality of physical blocks corresponding to each of the plurality of superblocks in the plurality of superblocks, and each internal block valid page count table corresponds to a superblock in the plurality of superblocks and includes a plurality of valid page counts corresponding to the plurality of physical blocks of the superblock. (b) The storage device controller provides a plurality of virtual block mapping tables of the plurality of memory chips to map a first super block of the plurality of super blocks associated with the physical block address to a second super block of the plurality of super blocks. (c) Based on the super block valid page count table, the storage device controller determines at least one selected super block of the plurality of super blocks to be processed for a garbage collection step. (d) The storage device controller reduces the total number of valid pages of the selected super block by re-mapping the at least one selected super block based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables. (e) Performing a garbage collection step on the re-mapped at least one selected super block.

[0014] In one embodiment, the step (d) includes: (d1) determining, based on the multiple internal block valid page count tables, whether the memory chip to which the first physical block among the multiple physical blocks of the at least one selected super block belongs has a second physical block, the number of valid pages of the second physical block being less than the number of valid pages of the first physical block; and (d2) if it is determined that the memory chip to which the first physical block among the multiple physical blocks of the at least one selected super block belongs has a second physical block whose number of valid pages is less than the number of valid pages of the first physical block, re-mapping the first physical block and the second physical block by updating at least one of the multiple virtual block mapping tables.

[0015] In one embodiment, when the number of valid pages of the first physical block is greater than or equal to a valid page number threshold, the storage device controller executes the step (d1).

[0016] In one embodiment, in the step (d2), the storage device controller remaps the first physical block and the second physical block by updating the virtual block mapping table of the memory chip to which the first physical block of the at least one selected super block and the second physical block of another super block belong.

[0017] In one embodiment, the storage device controller updates the virtual block mapping table of the memory chip to include data indicating that the first physical block of the at least one selected super block is mapped to a second physical block of another super block.

[0018] Thus, the above embodiments provide a storage device, a control method for a storage device, and a storage medium, which can be used in a device having a memory, and can be used to improve the performance of garbage collection by updating the super block selected for garbage collection and mapping the internal block to reduce the number of valid pages of the super block when the storage device needs to perform garbage collection on internal data movement. In this way, the overall write performance of the electronic device using the storage device can be improved.

[0019] In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and are not intended to limit the scope of rights of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 is a schematic block diagram of an embodiment of a storage device;

[0022] Figure 2 is a schematic block diagram of an embodiment of a storage device controller;

[0023] Figure 3 A schematic flow chart of an embodiment of a method for controlling a storage device;

[0024] Figure 4 is a schematic diagram of an embodiment of a superblock;

[0025] Figure 5 A schematic diagram of an embodiment of a valid page count table for multiple internal blocks of multiple memory chips;

[0026] Figure 6 A schematic diagram of an embodiment of a plurality of virtual block mapping tables of a plurality of memory chips;

[0027] Figure 7 for Figure 3 A schematic flow chart of an embodiment of step S40;

[0028] Fig. 8A A schematic diagram of an embodiment of remapping internal blocks for a selected super block;

[0029] Figure 8B A schematic diagram of an embodiment of remapping internal blocks for a selected super block;

[0030] Fig. 9A A schematic diagram of an embodiment of a mapping relationship between internal blocks of a super block;

[0031] Fig. 9B A schematic diagram of an embodiment of a mapping relationship of internal blocks of a super block after re-mapping of internal blocks of a selected super block; and

[0032] Fig.10 for Figure 3 A schematic flowchart of another embodiment of step S40 in FIG.

[0033] Reference numerals

[0034] 10 Host

[0035] 100, 300 storage device controller

[0036] 110 Processing Units

[0037] 120 Buffer Unit

[0038] 130_1~130_N storage channels

[0039] 140 Memory channel control unit

[0040] 150 Host Interface Unit

[0041] 160 Bus

[0042] 200 Memory

[0043] D1_1~D1_M、DN_1~DN_M memory chips

[0044] 310 Host Interface Layer

[0045] 320 Flash Memory Translation Layer

[0046] 330 Flash Memory Interface Layer

[0047] CH0, CH1, CH2, CH3 storage channels

[0048] D0, D1~D31 memory chips

[0049] B_D0, B_D1~B_D31 solid blocks

[0050] CE0, CE1~CE7 enable signals

[0051] SB, SB0, SBX, SBY, SBZ super blocks

[0052] SB_VT superblock valid page count table

[0053] SB0_IT, SB1_IT~SBP_IT internal block valid page count table

[0054] L2PMT Logical to Physical Mapping Table

[0055] LBA Logical Block Address

[0056] D0_VMT, D1_VMT~DQ-1_VMT virtual block mapping table

[0057] Steps S10 to S50

[0058] Steps S41 and S45

[0059] Steps S110 to S170 DETAILED DESCRIPTION

[0060] In order to facilitate understanding of the purpose, features and effects of the present invention, embodiments for describing the present invention in detail and the accompanying drawings are provided.

[0061] Please refer to Figure 1 , which illustrates an embodiment of the storage device of the present invention, Figure 1 Storage devices can be used to implement Figure 3 , 5 The control method of 10 or 11 (which will be described in detail later and is temporarily omitted here) can be used to realize that when the storage device needs to perform garbage collection on internal data movement, the efficiency of garbage collection can be improved by updating the internal blocks of the super blocks selected for garbage collection to reduce the number of valid pages of the super blocks. Figure 1 As shown, the storage device includes a storage device controller 100 and a memory 200. The storage device controller 100 includes a processing unit 110, a buffer unit 120, a plurality of storage channels 130_1 to 130_N (where N is an integer greater than 1) and a corresponding storage channel control unit 140. The buffer unit 120 can be implemented using a volatile memory or a non-volatile memory. The memory 200 includes a plurality of memory chips D1_1 to D1_M to DN_1 to DN_M (where N and M are integers greater than 1). For example, the memory chip is a flash memory, such as a NOR memory or a NAND memory, but the implementation of the present invention is not limited to this example.

[0062] The storage device controller 100 can communicate with the host 10 through the host interface unit 150 to receive a read request or a write request from the host 10. The storage device controller 100 generates a corresponding read command or a write command for the host read request or the host write request, and transmits the generated corresponding command to the storage channel control unit 140 of the corresponding storage channel (such as 130_1 to 130_N). The storage channel control unit 140 is used to control at least one memory chip. For example, the storage channel control unit 140 transmits a data read command to a certain memory chip and transmits the data read thereby to the storage device controller 100, such as the buffer unit 120. The storage device controller 100 transmits the data requested by the host 10 to the host 10. For another example, the storage channel control unit 140 writes the data to be written into the memory chip according to the data write command. When the storage device controller 100 controls the operation of the memory 200, the buffer unit 120 can store data used by the storage device controller 100 and the memory 200 for various operations such as read operations, write operations, programming operations, and erase operations. exist Figure 1In the embodiment, the plurality of storage channel control units 140 perform read or write operations in a parallel processing manner. In addition, the processing unit 110 can be electrically coupled to the storage channels (such as 130_1 to 130_N) through the bus 160. However, the implementation of the present invention is not limited to the above examples. For example, each of the aforementioned storage channel control units can be implemented using a logic circuit or a programmable circuit, or implemented in a software manner and executed by the processing unit 110.

[0063] The host interface unit 150 can process commands and data provided from the host 10, and can communicate with the host 10 through at least one of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-E), serial attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).

[0064] Please also refer to Figure 1 and Figure 2 ,in Figure 2 A schematic block diagram of an embodiment of a storage device controller is shown. Figure 2 The present invention shows the architecture of the storage device controller 300 when it is implemented in firmware or software. For example, the storage device controller 300 includes a host interface layer 310, a flash memory translation layer 320, and a flash memory interface layer 330. The host interface layer 310 is used to communicate with the host 10 and serves as an interface between the host 10 and the storage device controller 300. The flash memory translation layer 320 is used to manage read, write, and erase operations. The flash memory translation layer 320 is further used to convert a logical address (such as a logical block address or a logical page address) into a physical address (such as a physical block address or a physical page address) corresponding to a memory chip (such as D1_1~D1_M to DN_1~DN_M) of the memory 200. The flash memory interface layer 330 is used to process the communication between the flash memory translation layer 320 and the memory 200, such as transmitting a command from the flash memory translation layer 320 to the memory 200.

[0065] Figure 2 The storage device controller 300 shown may utilize Figure 1The hardware architecture is implemented. The flash memory conversion layer 320 needs to refer to and maintain the address mapping table when converting the logical address to the physical address. Due to the large amount of data in the address mapping table, the flash memory conversion layer 320 stores part of the segment of the address mapping table in the cache. When there is no correspondence between the logical address and the physical address required for the conversion in the cache, the flash memory conversion layer 320 needs to update the segment content of the address mapping table in the cache and generate a mapping table read command. In addition, in some application scenarios of memory products, such as embedded multimedia cards (eMMC) or other memory products, the address mapping table is stored in the memory of the memory product, and the present invention is not limited to this example.

[0066] The storage device controller 300 controls various operations for the memory 200, such as write operations, read operations, programming operations, and erase operations. For example, the storage device controller may generate a write command under a write request from the host 10 and execute the generated write command. The storage device controller may use a command queue to store the host write command. The storage device controller may sequentially process the host write commands stored in the command queue to perform data write operations.

[0067] In particular, the storage device controller 300 controls the firmware algorithms for the flash memory translation layer 320. For example, the storage device controller 300 may implement algorithms including garbage collection (GC), wear-leveling (WL), block reclaim (BC), and runtime bad block (RBB). Therefore, when executing any of the algorithms, such as garbage collection, wear-leveling, block reclaim, and runtime bad block, the storage device also has internal data movement requirements.

[0068] As the storage device performs internal data movement and host data writing, the write performance may decrease or fluctuate. If the storage device controller needs to process a large amount of internal data movement, it may affect the efficiency of executing write commands from the host, resulting in a decrease in write performance for the electronic device. Conversely, if the storage device controller has less or no internal data movement requirements, the write performance increases. In order to promote the stability or performance improvement of the host data writing efficiency, an embodiment of the control method of the storage device is proposed below.

[0069] Please refer to Figure 3 , which is a schematic flow chart of an embodiment of a method for controlling a storage device. Figure 3The embodiment shown can be used in a device having a memory, and can be used to improve the performance of garbage collection by processing a super block selected for garbage collection to reduce the number of valid pages of the super block when the storage device needs to perform garbage collection on internal data movement. Figure 1 and 3 , Figure 3 An embodiment of a method for controlling a storage device includes the following steps S10 to S50. Figure 1 The components in the example are used as examples to assist in explanation, but the implementation of the control method is not limited to the examples.

[0070] As shown in step S10, the storage device controller 100 provides a plurality of superblock valid page count tables of superblocks and a plurality of internal block valid page count tables of the plurality of superblocks, wherein each superblock corresponds to a group of different, non-overlapping multiple physical blocks belonging to a plurality of memory chips (such as D1_1~D1_M to DN_1~DN_M) of the storage device, each physical block corresponds to a portion of multiple pages of a corresponding memory chip (such as one of D1_1~D1_M to DN_1~DN_M) among the plurality of memory chips, and the superblock valid page count table includes a total valid page count of multiple physical blocks corresponding to each of the plurality of superblocks, and each internal block valid page count table corresponds to a superblock among the plurality of superblocks and includes multiple valid page counts corresponding to the multiple physical blocks of the superblock.

[0071] As shown in step S20, the storage device controller 100 provides a plurality of virtual block mapping tables of the plurality of memory chips to map a first super block in the plurality of super blocks associated with a physical block address to a second super block in the plurality of super blocks.

[0072] As shown in step S30, based on the super-block valid page count table, the storage device controller 100 determines at least one selected super-block from the plurality of super-blocks to be processed for the garbage collection step. For example, based on the total number of valid pages of each super-block from the plurality of super-blocks, a super-block with the least or fewer total valid pages is determined as the at least one selected super-block.

[0073] As shown in step S40, the storage device controller 100 reduces the total number of valid pages of the selected super block by re-mapping the at least one selected super block based on the multiple internal block valid page count tables and the multiple virtual block mapping tables.

[0074] As shown in step S50, a garbage collection step is performed on the at least one selected super block of the re-mapped pair.

[0075] Thus, the above embodiments provide a storage device control method and storage medium, which can be used in a device with a memory, and can be used in a device with a memory, and can be used to realize that when the storage device needs to perform garbage collection on internal data movement, the number of valid pages of the super block is reduced by updating the internal block selected for garbage collection, so as to improve the performance of garbage collection. In this way, the overall write performance of the electronic device using the storage device can be improved.

[0076] The following Figure 3 Steps S10 to S50 in the embodiment are respectively described as follows with examples.

[0077] For the superblock in step S10, please refer to Figure 4 , which is a schematic diagram of an embodiment of a super block. Figure 4 As shown, a super block SB corresponds to a group of different, non-overlapping physical blocks (such as B_D0, B_D1~B_D31) belonging to multiple memory chips (such as D0, D1~D31). Each physical block (such as B_D0, B_D1 or B_D31) corresponds to a portion of multiple pages of a corresponding memory chip (such as D0, D1 or D31) among the multiple memory chips. In other words, the super block SB is a collection of a physical block (such as B_D0, B_D1~B_D31) in each memory chip (such as D0, D1~D31). Then, another physical block that does not overlap with the physical block (such as B_D0, B_D1~B_D31) of the super block SB can be further selected from each memory chip (such as D0, D1~D31) to form another super block. In this way, multiple super blocks are established, each super block corresponding to a group of different, non-overlapping physical blocks belonging to the multiple memory chips (such as D0, D1-D31).

[0078] In addition, in some embodiments, for Figure 2 For the storage device controller 300 implemented by the flash memory translation layer 320, the flash memory translation layer 320 can use the super block SB as the block allocation unit. Figure 1 , 2In the example of implementing a storage device using , 4, memory chips D0, D4-D28 may correspond to storage channel CH0 in the storage device, memory chips D1, D5-D29 may correspond to storage channel CH1 in the storage device, memory chips D2, D6-D30 may correspond to storage channel CH2 in the storage device, and memory chips D3, D7-D31 may correspond to storage channel CH3 in the storage device. Furthermore, in the above example, the storage device may implement multiple chip enable (CE) signals to control the corresponding memory chips, so that multiple storage channels may be used to read or write multiple memory chips to increase the read and write performance, for example Figure 4 8 enable signals represented by CE0, CE1-CE7 are shown to illustrate the corresponding relationship. For example, the enable signal CE0 can be applied to D0-D3, and the others can be applied in the same way. However, the implementation of the present invention is not limited to this example.

[0079] In such Figure 3 In the control method shown, processing is performed on a super block, so in steps S10 and S20, look-up tables associated with multiple super blocks are proposed to facilitate the implementation of the control method. The multiple look-up tables include: super block valid page count tables of multiple super blocks, multiple internal block valid page count tables, and multiple virtual block mapping tables of the multiple memory chips.

[0080] In step S10, the super block valid page count table includes the total valid page count of multiple physical blocks corresponding to each of the multiple super blocks. For example, if there are 20 super blocks, the super block valid page count table can be configured to have 20 corresponding columns to record the total valid page count of the corresponding super blocks. Figure 1 or Figure 2 The storage device controller can establish the super-block valid page count table, set its initial value, and record, count or update the total number of valid pages of each super-block during the operation of the storage device controller. These implementation methods can be implemented using the flash memory conversion layer 320.

[0081] In such Figure 3 In the control method shown, the storage device controller (or flash memory translation layer) further provides multiple internal block valid page count tables. Figure 4 The physical blocks (such as B_D0, B_D1-B_D31) formed in the SB can be called internal blocks, so for the super blocks (such as Figure 4 SB), the storage device controller (or flash memory translation layer) provides a corresponding to the super block (such as Figure 4For example, Figure 4 Taking the example of the super block SB, the internal block valid page count table includes the same number (such as 32) of corresponding columns for multiple physical blocks (such as B_D0, B_D1~B_D31) of the super block SB, that is, each column records the number of valid pages of the corresponding physical area.

[0082] Please refer to Figure 5 , which is a schematic diagram of an embodiment of a valid page count table of multiple internal blocks of multiple memory chips. Figure 1 , Figure 2 In an example of a storage device, the storage device controller of the storage device may be configured to provide P+1 super blocks (e.g., P is an integer greater than or equal to 1, wherein the plurality of super blocks may be represented by symbols SB0, SB1~SBP, respectively), and the super block valid page count table SB_VT of the P+1 super blocks has P+1 fields, each field recording the total number of valid pages of all physical blocks of the corresponding super block, such as Figure 5 In addition, Figure 5 As shown, corresponding to P+1 super blocks, there are P+1 internal block valid page count tables SB0_IT, SB1_IT~SBP_IT, and each internal block valid page count table records the valid page number of each physical block of the corresponding super block (such as SB0, SB1~SBP). For example, the storage device has Q (such as 16=4x 4) memory chips (such as Q=N x M, N, M are integers greater than 1), then each super block has Q physical blocks, so the internal block valid page count table corresponding to each super block also has Q fields, and the Q fields respectively record the individual valid page numbers of all internal blocks of the super block (such as SB0, SB1 or SBP). For example, based on Figure 1 or Figure 2 The storage device controller can establish an internal block valid page count table corresponding to each super block, set its initial value, and record, count or update the individual valid page counts of the internal blocks of each super block during the operation of the storage device controller. These implementations can be implemented using the flash memory translation layer 320. However, the implementation of the present invention is not limited to the above examples.

[0083] For step S20, please refer to Figure 6 , which is a schematic diagram of an embodiment of a plurality of virtual block mapping tables of a plurality of memory chips. Figure 1 , Figure 2In an example of a storage device, the memory of the storage device includes Q memory chips (represented by symbols D0, D1 to DQ-1, respectively). The storage device controller may be configured to provide Q virtual block mapping tables D0_VMT, D1_VMT to DQ-1_VMT corresponding to the Q memory chips, respectively. Figure 6 As shown. For example, the multiple virtual block mapping tables are used to map the first super block of the multiple super blocks associated with a physical block address obtained from the logical to physical mapping table L2PMT to the second super block of the multiple super blocks, wherein the physical block address corresponds to a logical block address (LBA), and the physical block address can represent a memory chip corresponding to a physical block and a page in the memory chip (such as represented by a number), or represent a storage channel corresponding to a physical block, a memory chip of the storage channel and a page in the memory chip (such as represented by a number), or any other suitable method. For example, initially, the storage device controller can be configured to record multiple pages of the memory chip D0 in the virtual block mapping table D0_VMT according to the value of the super block to which each page is allocated, and set them to correspond to the same super block; similar processing can be performed initially for other virtual block mapping tables. Thereby, when the above Figure 3 When step S40 of the control method is executed, the plurality of initialized virtual block mapping tables can facilitate re-mapping of the at least one selected super block to reduce the total number of valid pages of the selected super block. However, the implementation of the present invention is not limited to the above example.

[0084] Regarding step S30, in one embodiment, the storage device controller determines the super block with the least total valid page number as at least one selected super block based on the change of the total valid page number of each super block. In another embodiment, the storage device controller determines at least one selected super block based on whether the total valid page number of each super block meets a judgment criterion. For example, the judgment criterion is a total valid page number threshold value, if the storage device controller determines that the super block with a total valid page number less than or equal to the total valid page number threshold value is at least one selected super block.

[0085] For step S40, please refer to Figure 7 , which is Figure 3 FIG. 4 is a schematic flow chart of an embodiment of step S40 in FIG. 4. In the embodiment, step S40 includes steps S41 and S45.

[0086] As shown in step S41, based on the multiple internal block valid page count tables, it is determined whether the memory chip to which the first physical block among the multiple physical blocks of the at least one selected super block belongs has a second physical block, and the number of valid pages of the second physical block is less than the number of valid pages of the first physical block.

[0087] As shown in step S45, if it is determined that the memory chip to which the first physical block among the multiple physical blocks of the at least one selected super block belongs has a second physical block whose valid page number is less than the valid page number of the first physical block, the first physical block and the second physical block are remapped by updating at least one of the multiple virtual block mapping tables.

[0088] In some embodiments, if there are two or more selected super blocks, steps S41 and S45 can be used to perform a re-mapping operation on each selected super block respectively, wherein if a corresponding second physical block is not found for a selected super block when executing step S41, step S41 can be further executed on the remaining selected super blocks.

[0089] For step S41, please refer to Fig. 8A , which is a schematic diagram of an embodiment of remapping internal blocks for a selected super block. Fig. 8A As shown, the selected super block (such as represented by SBX) is represented by a square matrix, and each grid in the square matrix represents an internal block of the selected super block, and a number is displayed in the grid to indicate the number of valid pages of the internal block. However, please note that Fig. 8A Or other diagrams are only for the convenience of explanation, so the implementation of the present invention is not limited to the examples or schematic diagrams in this article. When implementing, it can be implemented in various suitable software (such as data structure or database), hardware or firmware.

[0090] For example, based on the multiple internal block valid page count tables, the number of valid pages of the internal blocks of the selected super block SBX (such as represented by VPC) is 39. In order to reduce the number of valid pages of the internal blocks of the selected super block SBX, the storage device controller can be configured to select an appropriate number of physical blocks from the multiple physical blocks (i.e., internal blocks) of the selected super block SBX to perform steps S41 and S45, so as to effectively reduce the number of valid pages of the internal blocks of the selected super block SBX. For example, in one embodiment, the storage device controller can be configured to perform step S41 when it finds that the number of valid pages in the internal blocks of the selected super block SBX is greater than or equal to the valid page number threshold value (e.g., 10). For example, for Fig. 8AFor example, there are at least two internal blocks that meet the threshold of the number of valid pages. Figure 4 In the block naming method, the two internal blocks B_D3 and B_D10 correspond to valid page numbers 15 and 12 respectively, and the two internal blocks B_D3 and B_D10 correspond to memory chips D3 and D10 respectively. Thus, the valid page number threshold value can avoid finding an inappropriate number of internal blocks when implementing step S41, which can improve the execution efficiency of steps S41 and S45; on the other hand, if step S41 is performed for an internal block with a valid page number of 1, 2 or 3, it is likely to cause a waste of time and computing resources.

[0091] In addition, step S41 is to find out whether there is an internal block with a smaller number of valid pages in other super blocks, so as to remap with the aforementioned internal blocks B_D3 and B_D10 in step S45, that is, to exchange the internal blocks, so that the remapped and selected super block SBX has a smaller total number of valid pages. For an internal block such as B_D3 (or the first physical block) of the selected super block SBX to be remapped, it is necessary to find out whether there is an internal block with a smaller number of valid pages (or the second physical block) in the same memory chip D3 to which the internal block B_D3 belongs, so as to maintain better performance.

[0092] exist Fig. 8A In the example, the internal block B_D3 of another super block SBZ and the internal block B_D3 of the selected super block SBX belong to the same memory chip D3, and the valid page number of the internal block B_D3 of the block SBY (such as 3) is less than the valid page number of the internal block B_D3 of the selected super block SBX (such as 15). In addition, similarly, the internal block B_D10 of another super block SBY and the internal block B_D10 of the selected super block SBX belong to the same memory chip D10, and the valid page number of the internal block B_D10 of the block SBY (such as 0) is less than the valid page number of the internal block B_D10 of the selected super block SBX (such as 12). Therefore, the internal block B_D3 of the super block SBZ and the internal block B_D10 of the super block SBY can be taken as the second physical block described in step S41, so as to further execute step S45.

[0093] Please refer to Figure 8BWhen executing step S45, the first physical block (such as the internal block B_D3 or B_D10 of the super block SBX) and the second physical block (such as the internal block B_D3 of the super block SBZ or the internal block B_D10 of the super block SBY) are remapped by updating at least one of the plurality of virtual block mapping tables. In other words, the internal block B_D3 of the super block SBX is exchanged with the internal block B_D3 of the super block SBZ, and the internal block B_D10 of the super block SBX is exchanged with the internal block B_D10 of the super block SBY.

[0094] In one embodiment, in the step S45, the first physical block and the second physical block are remapped by updating the virtual block mapping table of the memory chip to which the first physical block of the at least one selected super block (such as the internal block B_D3 or B_D10 of the super block SBX) and the second physical block of another super block (such as the internal block B_D3 of the super block SBZ or the internal block B_D10 of the super block SBY) belong. Please refer to Fig. 9A , 9B , Fig. 9A is a schematic diagram of an embodiment of the mapping relationship between internal blocks of a super block, Fig. 9B FIG. 1 is a schematic diagram of an embodiment of a mapping relationship of internal blocks of a super block after re-mapping of internal blocks of a selected super block. Fig. 9A , 9B In the figure, each long bar corresponds to a certain memory chip (such as D0 to D16); the grid of each long bar indicates the number of the super block to which the block consisting of at least one page in the corresponding memory chip belongs. For example, the value in the first grid of the long bar corresponding to the memory chip D0 is 0, indicating that the corresponding block belongs to the super block SB0, and the same applies to other blocks. In order to facilitate understanding, the symbol of the super block corresponding to the grid at the beginning is displayed on the left side of the long bar, such as SB0, SBX, SBY, SBZ, etc. Assume that the mapping relationship between the internal blocks of the initial super blocks SBX, SBY, and SBZ is as follows: Fig. 9A As shown in FIG. 1 , three horizontal straight lines crossing the plurality of long strips are used to illustrate the blocks (or internal blocks of each super block) respectively included in the super blocks SBX, SBY, and SBZ. After the re-mapping in step S45, the mapping relationship of the internal blocks of the re-mapped super blocks SBX, SBY, and SBZ is as follows: Fig. 9B As shown, the aforementioned three lines have been directly changed into three cross-sectional lines spanning the plurality of long strips to illustrate the blocks (or internal blocks of each super block) respectively included in the super blocks SBX, SBY, and SBZ. Please note that Fig. 9A , 9B The above examples are only for illustration purposes, and the implementation of the present invention is not limited to the above examples.

[0095] In one embodiment, the virtual block mapping table of the memory chip is updated to include data indicating that the first physical block of the at least one selected super block is mapped to a second physical block of another super block. Figure 6 and Fig. 9A , 9B ,like Fig. 9B The updated mapping relationship can be achieved by using Figure 6 For example, in the virtual block mapping table D3_VMT corresponding to the memory chip D3, it can be recorded that the page corresponding to the physical address of the internal block B_D3 of the original super block SBX of the memory chip D3 is mapped to SBZ, and it can be recorded that the page corresponding to the physical address of the internal block B_D3 of the original super block SBZ is mapped to SBX; in addition, in the virtual block mapping table D10_VMT corresponding to the memory chip D10, it can be recorded that the page corresponding to the physical address of the internal block B_D10 of the original super block SBX of the memory chip D10 is mapped to the super block SBY, and it can be recorded that the page corresponding to the physical address of the internal block B_D10 of the original super block SBY is mapped to the super block SBX. For example, Figure 6 The virtual block mapping table of each memory chip shown can be configured to record the number of the memory chip, the number of the storage channel, and the number of the super block corresponding to each physical page in the memory chip at the beginning and the number of the super block corresponding to the re-mapping, so as to facilitate the implementation of the above re-mapping. However, the implementation of the virtual block mapping table can be simplified or configured in other ways under appropriate circumstances, so the implementation of the present invention is not limited to the above examples.

[0096] Please refer to Fig.10 , which is Figure 3 As shown in step S110, a block (such as represented by block_x) for a memory chip (such as assuming parameter DN=0, representing starting from memory chip D0) in the selected super block is determined; for example, from the virtual block mapping table (such as Figure 6As shown in step S120, determine whether the number of valid pages of the block block_x is greater than a threshold value (for example, the threshold value is 5, 10 or other); if the number of valid pages of the block (such as block_x) is greater than the threshold value, execute step S130. As shown in step S130, find a block with a smaller number of valid pages in the same memory chip (such as represented by block_y). As shown in step S140, determine whether the block to be found in step S130 can be found; if so, execute step S150; if not, execute step S160. As shown in step S150, remap blocks block_x and block_y; Figure 8B , 9B As shown in step S160, set the next memory chip (e.g., set the parameter DN to increase by one, such as DN++ in virtual program code). As shown in step S170, determine whether all memory chips have been processed, for example, determine whether the parameter DN is greater than the maximum number of memory chips (e.g., Q=16 or 32, etc.); if so, execute step S110; if not, stop the process, or execute other steps. In this way, using Fig.10 The embodiment can implement based on the selected super block Figure 4 If there are two or more super blocks selected, the super blocks can be reused. Fig.10 The embodiment performs step S40.

[0097] In addition, in some embodiments, a non-transitory storage medium is provided, which records the data for allowing a computing device (such as the aforementioned Figure 1 or the storage device shown in 2), a program code of a storage device control method is executed by a storage device controller in the storage device, wherein the method includes a method according to Figure 3 For example, the program code is one or more programs or program modules, such as for implementing the method according to Figure 3 Steps S10 to S50, Figure 7 Steps S41 and S45 or Fig.10 In steps S110 to S170, the program codes of these modules operate in coordination and can be executed in any suitable order or in parallel. When the computing device executes this program code, it can cause the computing device to execute based on Figure 3 The above-mentioned readable storage medium is, for example, firmware, ROM, RAM, memory card, optical information storage medium, magnetic information storage medium or any other type of storage medium or memory, and the implementation of the present invention is not limited to this example.

[0098] In addition, in the above-mentioned embodiments of the storage device (such as Figure 1 , Figure 2 ), at least one of the processing unit 110, the storage channel control unit 140, and the host interface unit 150, or a combination thereof, can be implemented using one or more circuits, such as a processor, a digital signal processor, or a programmable integrated circuit such as a microcontroller, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or the like, or can be implemented using a dedicated circuit or module. Furthermore, the storage channel control unit can also be implemented using software methods such as a process, an execution thread, a program module or other software methods. However, the implementation of the present invention is not limited to these examples. In addition, the aforementioned Figure 7 Steps S41, 45 or Fig.10 Steps S130 and S140 in the above process may also be implemented by hardware circuits, such as logic circuits or other suitable digital circuits, so as to improve the performance of searching for other physical blocks with smaller valid page numbers.

[0099] Thus, the above-mentioned embodiments provide a storage device, a control method of the storage device, and a storage medium, which can be used in a device having a memory. The storage device controller provides a plurality of super-block valid page count tables of super-blocks and a plurality of internal block valid page count tables of the plurality of super-blocks, and provides a plurality of virtual block mapping tables of the plurality of memory chips to map a first super-block of the plurality of super-blocks associated with a physical block address to a second super-block of the plurality of super-blocks. And when the storage device needs to perform garbage collection, it can be realized that by updating the mapping of the internal blocks of the selected super-block to be garbage collected, the number of valid pages of the super-block is reduced to improve the efficiency of garbage collection.

[0100] Although the present invention has been described through specific embodiments, one skilled in the art may make various modifications, combinations and variations thereto without departing from the scope and spirit of the invention as set forth in the claims.

[0101] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention.

Claims

1. A control method for a storage device, the storage device including a storage device controller and a memory including a plurality of memory chips, characterized in that, the control method includes the following steps: (a) providing, by the storage device controller, a super-block valid page count table for a plurality of super-blocks and a plurality of internal block valid page count tables for the plurality of super-blocks, where each super-block corresponds to a different, non-overlapping group of a plurality of physical blocks belonging to the plurality of memory chips, each physical block corresponding to a part of a plurality of pages of a corresponding memory chip among the plurality of memory chips, and the super-block valid page count table includes the total number of valid pages of the plurality of physical blocks corresponding to each super-block among the plurality of super-blocks, each internal block valid page count table corresponding to one of the plurality of super-blocks and including a plurality of valid page numbers corresponding to the plurality of physical blocks of the super-block; (b) providing, by the storage device controller, a plurality of virtual block mapping tables for the plurality of memory chips to map a first super-block among the plurality of super-blocks associated with a physical block address to a second super-block among the plurality of super-blocks, where each of the virtual block mapping tables records the number of the memory chip, the number of the storage channel, and the number of the super-block corresponding to each physical page in the memory chip initially and the number of the super-block corresponding after re-mapping; (c) determining, by the storage device controller based on the super-block valid page count table, at least one selected super-block among the plurality of super-blocks to be processed for a garbage collection step; (d) reducing, by the storage device controller, the total number of valid pages of the at least one selected super-block by re-mapping the at least one selected super-block based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables; and (e) performing a garbage collection step on the at least one selected super-block after re-mapping.

2. The control method for a storage device according to claim 1, characterized in that, the step (d) includes: (d1) determining, based on the plurality of internal block valid page count tables, whether a memory chip to which a first physical block among the plurality of physical blocks of the at least one selected super-block belongs has a second physical block, the number of valid pages of the second physical block being less than the number of valid pages of the first physical block; and (d2) if it is determined that the memory chip to which the first physical block among the plurality of physical blocks of the at least one selected super-block belongs has a second physical block with the number of valid pages less than the number of valid pages of the first physical block, then re-mapping the first physical block and the second physical block by updating at least one of the plurality of virtual block mapping tables.

3. The control method for a storage device according to claim 2, characterized in that, when the number of valid pages of the first physical block is greater than or equal to a valid page number threshold value, the step (d1) is performed.

4. The control method for a storage device according to claim 2, characterized in that, in the step (d2), Remap the first physical block and the second physical block by updating the virtual block mapping table of the memory chip to which the first physical block of the at least one selected superblock and the second physical block of another superblock belong.

5. The control method of a storage device according to claim 4, wherein, the virtual block mapping table of the memory chip is updated to include data for indicating mapping the first physical block of the at least one selected superblock to the second physical block of another superblock.

6. A storage medium, wherein, the storage medium records program code for enabling a storage device to execute the control method of the storage device according to any one of claims 1 to 5.

7. A storage device, wherein, comprising: a memory including a plurality of memory chips; and a storage device controller electrically connected to the memory and configured to control the memory to perform data access on the memory, wherein the storage device controller is configured to execute a plurality of steps, and the plurality of steps include: (a) The storage device controller provides a superblock valid page count table of a plurality of superblocks and a plurality of internal block valid page count tables of the plurality of superblocks, wherein each superblock corresponds to a different, non-overlapping set of a plurality of physical blocks belonging to the plurality of memory chips, each physical block corresponds to a part of a plurality of pages of a corresponding memory chip in the plurality of memory chips, and the superblock valid page count table includes the total number of valid pages of the plurality of physical blocks corresponding to each superblock in the plurality of superblocks, and each internal block valid page count table corresponds to one superblock in the plurality of superblocks and includes a plurality of valid page numbers corresponding to the plurality of physical blocks of the superblock; (b) The storage device controller provides a plurality of virtual block mapping tables of the plurality of memory chips to map a first superblock among the plurality of superblocks associated with a physical block address to a second superblock among the plurality of superblocks, wherein each virtual block mapping table records the number of the memory chip, the number of the storage channel, and the number of the superblock corresponding to each physical page in the memory chip initially and the number of the superblock corresponding after remapping; (c) Based on the superblock valid page count table, the storage device controller determines at least one selected superblock among the plurality of superblocks to be processed for garbage collection steps; (d) The storage device controller reduces the total number of valid pages of the at least one selected superblock by remapping the at least one selected superblock based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables; and (e) Perform a garbage collection step on the at least one selected superblock after remapping.

8. The storage device according to claim 7, wherein, the step (d) includes: (d1) Determine, based on the plurality of internal block valid page count tables, whether a memory chip to which a first physical block among the plurality of physical blocks of the at least one selected superblock belongs has a second physical block, where the number of valid pages of the second physical block is less than the number of valid pages of the first physical block; and (d2) If it is determined that the memory chip to which the first physical block among the plurality of physical blocks of the at least one selected superblock belongs has a second physical block with a number of valid pages less than the number of valid pages of the first physical block, re-map the first physical block and the second physical block by updating at least one of the plurality of virtual block mapping tables.

9. The storage device according to claim 8, wherein, when the number of valid pages of the first physical block is greater than or equal to a valid page threshold value, the storage device controller executes the step (d1).

10. The storage device according to claim 8, wherein, in the step (d2), the storage device controller re-maps the first physical block and the second physical block by updating the virtual block mapping table of the memory chip to which the first physical block of the at least one selected superblock and the second physical block of another superblock belong.

11. The storage device according to claim 10, wherein, the storage device controller updates the virtual block mapping table of the memory chip to include data indicating that the first physical block of the at least one selected superblock is mapped to the second physical block of another superblock.

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