An Embedded Data Memory Based on FPGA and Solid State Drive

Abstract

The present invention discloses an embedded data memory based on FPGA and solid-state drive, including a memory. A solid-state drive socket is provided on the memory, and a solid-state drive is plugged into the upper end of the solid-state drive socket. The memory includes an FPGA, an SPI Flash, and a solid-state drive. The FPGA is integrated with a file data read / write module and a data-to-be-stored read / write module. The SPI Flash is electrically connected to the FPGA. The sending end of the file data read / write module is electrically connected to the SPI Flash, and the sending and receiving end of the data-to-be-stored read / write module is electrically connected to the solid-state drive. This FPGA and solid-state drive-based design uses the SPI Flash as a file data buffer, temporarily stores the file data in the SPI Flash, and then reads and transfers it to the solid-state drive by the FPGA after the amount of file data reaches a certain quantity, thereby reducing the data update frequency in the file area of the solid-state drive, achieving consistent read / write times in each area, and thus greatly reducing the file time cost and achieving wear leveling.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and particularly to an embedded data memory based on FPGA and solid-state drive. Background Art

[0002] Solid-state drives use NAND Flash as the storage medium, and have the advantages of fast storage speed, anti-vibration, high storage density, large capacity, stable performance, and wide application range. They are widely used in embedded data storage of aviation, aerospace, and mobile sensors.

[0003] Most embedded solid-state data storage adopts the method of using a processor to control the storage medium. Common controllers include FPGA, DSP, and single-chip microcomputer. DSP works serially, controlling the storage medium to work, but cannot perform other tasks simultaneously; the processor main frequency of the single-chip microcomputer is generally low, and it is only suitable for medium- and low-speed data storage. FPGA has a parallel working mechanism and can perform multiple processes simultaneously. Therefore, it is a commonly used controller in high-speed and highly reliable embedded storage.

[0004] In data storage, there are two types of data storage, namely the real data to be stored and the file data that manages the storage location and index. During the embedded storage process, the file data has a high update frequency and a large time cost, which cannot be ignored compared to the real data storage time, and will cause inconsistent read and write frequencies of the storage medium, resulting in uneven wear and affecting the service life of the storage medium. When a computer uses a solid-state drive for read and write operations, due to rich cache and computing resources, and less restrictions in terms of volume, weight, and power consumption, the above problems are relatively easy to solve.

[0005] When the existing data storage device is in use, in embedded storage, the computing cache resources are relatively scarce and are easily restricted by the micro-miniature size of the device. The large file time cost and uneven wear will seriously reduce the data storage rate and affect the service life of the data storage device. This patent proposes an embedded data memory based on FPGA and solid-state drive, so that the read and write times of each area are consistent, thereby achieving the purpose of greatly reducing the file time cost and realizing wear leveling. Summary of the Invention

[0006] The purpose of the present invention is to provide an embedded data memory based on FPGA and solid-state drive, so as to solve the problems mentioned in the above background art that when the data memory is in use, in embedded storage, the computing cache resources are relatively scarce and are easily restricted by the micro-miniature size of the device, and the large file time cost and uneven wear will seriously reduce the data storage rate and affect the service life of the data storage device.

[0007] To achieve the above object, the present invention provides the following technical solution: An embedded data memory based on FPGA and solid-state drive, including a memory, on which a solid-state drive socket is provided, and a solid-state drive is plugged into the upper end of the solid-state drive socket. The memory includes an FPGA, an SPI Flash, and a solid-state drive. The FPGA is integrated with a file data read / write module and a data-to-be-stored read / write module. The SPI Flash is electrically connected to the FPGA. The sending end of the file data read / write module is electrically connected to the SPI Flash. The sending and receiving ends of the data-to-be-stored read / write module are electrically connected to the solid-state drive. The solid-state drive is integrated with pins AGND, TXDP, TXDN, RXDP, and RXDN. The SPI Flash is integrated with pins CS#, MOSI, MISO, and SCLK.

[0008] Preferably, an electrical plug block is provided at the lower end of the solid-state drive, and the solid-state drive is wrapped and inserted into the solid-state drive socket through the electrical plug block.

[0009] Preferably, welding blocks are provided on both sides of the solid-state drive, and the welding blocks are distributed in an L-shaped parallel position. The solid-state drive is fixedly welded to the memory through the welding blocks.

[0010] Preferably, CS# is a chip select signal, MOSI is a data line, SCLK is a communication clock, and the receiving ends of CS#, MOSI, and SCLK are all electrically connected to the FPGA.

[0011] Preferably, MISO is a data line, and the sending end of MISO is electrically connected to the FPGA.

[0012] Preferably, AGND is a digital ground, and the sending and receiving ends of AGND are all electrically connected to the FPGA.

[0013] Preferably, TXDP is a data transmission positive signal interface, TXDN is a data transmission negative signal interface, and the sending ends of TXDP and TXDN are electrically connected to the FPGA.

[0014] Preferably, RXDP is a data reception positive signal interface, RXDN is a data reception negative signal interface, and the receiving ends of RXDP and RXDN are all electrically connected to the FPGA.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: The embedded data storage device based on FPGA and solid-state drive uses SPI Flash as a file data buffer, temporarily stores the file data in SPI Flash, and then reads and transfers the file data to the solid-state drive by FPGA after the amount of file data reaches a certain quantity, thereby reducing the data update frequency in the file area of the solid-state drive, making the read and write times of each area consistent, and thus greatly reducing the file time cost and achieving wear leveling. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. is a schematic connection diagram of a solid-state drive and a solid-state drive socket of an embedded data storage device based on FPGA and solid-state drive according to the present invention;

[0017] Figure 2 FIG. is a system diagram of an embedded data storage device based on FPGA and solid-state drive according to the present invention;

[0018] Figure 3 FIG. is a hardware signal connection diagram between FPGA and solid-state drive of an embedded data storage device based on FPGA and solid-state drive according to the present invention.

[0019] In the figure: 1, solid-state drive; 2, welding block; 3, solid-state drive socket; 4, electrical plug; 5, SPI Flash; 6, CS#; 7, MOSI; 8, MISO; 9, SCLK; 10, file data read / write module; 11, FPGA; 12, data to be stored read / write module; 13, AGND; 14, TXDP; 15, TXDN; 16, RXDP; 17, RXDN; 18, memory. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] Please refer to Figures 1 - 3, the present invention provides a technical solution: an embedded data memory based on FPGA and solid-state drive, including a solid-state drive 1, a welding block 2, a solid-state drive socket 3, an electrical plug block 4, an SPI Flash 5, a CS# 6, a MOSI 7, a MISO 8, an SCLK 9, a file data read / write module 10, an FPGA 11, a data to be stored read / write module 12, an AGND 13, a TXDP 14, a TXDN 15, an RXDP 16, an RXDN 17, and a memory 18. A solid-state drive socket 3 is provided on the memory 18, and a solid-state drive 1 is plugged into the upper end of the solid-state drive socket 3. An electrical plug block 4 is provided at the lower end of the solid-state drive 1, and the solid-state drive 1 is wrapped and inserted with the solid-state drive socket 3 through the electrical plug block 4. Pins AGND 13, TXDP 14, TXDN 15, RXDP 16, and RXDN 17 are integrated on the solid-state drive 1, which makes it convenient for the solid-state drive 1 to be wrapped and inserted. Welding blocks 2 are provided on both sides of the solid-state drive 1, and the welding blocks 2 are distributed in an L-shaped parallel position. The solid-state drive 1 is fixedly welded to the memory 18 through the welding blocks 2, which makes the installation of the solid-state drive 1 more stable and safer to use. The memory 18 includes an FPGA 11, an SPI Flash 5, and a solid-state drive 1. A file data read / write module 10 and a data to be stored read / write module 12 are integrated on the FPGA 11. Pins CS# 6, MOSI 7, MISO 8, and SCLK 9 are integrated on the SPI Flash 5, which makes the SPI Flash 5 have a higher integration level. The SPI Flash 5 is electrically connected to the FPGA 11. The sending end of the file data read / write module 10 is electrically connected to the SPI Flash 5. The sending and receiving ends of the data to be stored read / write module 12 are electrically connected to the solid-state drive 1. CS# 6 is the chip select signal of the FPGA 11 for the SPI Flash 5, and the receiving end of CS# 6 is electrically connected to the FPGA 11, which makes it output from the FPGA 11 to the SPI Flash 5. MOSI 7 is the data line output from the FPGA 11 to the SPI Flash 5, and the receiving end of MOSI 7 is electrically connected to the FPGA 11, which makes it convenient for data transmission. MISO 8 is the data line output from the SPI Flash 5 to the FPGA 11. The sending end of MISO 8 is electrically connected to the FPGA 11. SCLK 9 is the communication clock output from the FPGA 5 to the SPI Flash 11, and the receiving end of SCLK 9 is electrically connected to the FPGA 11. AGND 13 is the digital ground, and the sending and receiving ends of AGND 13 are electrically connected to the FPGA 11. TXDP 14 is the data sending positive signal interface, and the sending end of TXDP 14 is electrically connected to the FPGA 11, which is convenient for data sending. TXDN 15 is the data sending negative signal interface, and the sending end of TXDN 15 is electrically connected to the FPGA 11. RXDP 16 is the data receiving positive signal interface,Moreover, the receiving ends of RXDP16 are all electrically connected to FPGA11 for convenient data reception. RXDN17 is the negative data reception signal interface, and the receiving ends of RXDN17 are all electrically connected to FPGA11.

[0022] Working principle: When using the embedded data memory based on FPGA and solid-state drive, first take out the solid-state drive 1, then electrically insert it into the solid-state drive socket 3 through the electrical insertion block 4 for electrical insertion and installation, so that the solid-state drive 1 is connected to the SPI Flash 5 and FPGA11, and the solid-state drive 1 is wrapped. Then, the solid-state drive 1 is welded and fixed to the memory 18 through the welding blocks 2 distributed on both sides. Next, during storage, according to the characteristics of small file data volume and frequent updates integrated in the FPGA11 file data reading and writing module 10, instead of directly storing to the solid-state drive which will cause frequent discontinuous address jumps on the hard disk during data writing, the file data is first controlled to be saved to the SPI Flash 5, and then after the file data volume reaches a certain amount, it is read out by the to-be-stored data reading and writing module 12 of the FPGA11 and transferred and stored in the solid-state drive 1. This is the usage process of the embedded data memory based on FPGA and solid-state drive.

[0023] Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An embedded data memory based on FPGA and solid-state drive, comprising a memory (18), on which a solid-state drive socket (3) is provided, and a solid-state drive (1) is plugged into the upper end of the solid-state drive socket (3). Characterized in that: The memory (18) includes an FPGA (11), an SPI Flash (5) and a solid-state drive (1), and a file data read / write module (10) and a data-to-be-stored read / write module (12) are integrated on the FPGA (11). The SPI Flash (5) is electrically connected to the FPGA (11). The sending end of the file data read / write module (10) is electrically connected to the SPI Flash (5). The sending and receiving end of the data-to-be-stored read / write module (12) is electrically connected to the solid-state drive (1). The solid-state drive (1) is integrated with pins AGND (13), TXDP (14), TXDN (15), RXDP (16) and RXDN (17). The SPI Flash (5) is integrated with pins CS# (6), MOSI (7), MISO (8) and SCLK (9). Control the file data to be first saved to the SPI Flash (5), and then read by the data-to-be-stored read / write module (12) of the FPGA (11) and transferred and stored in the solid-state drive (1) after the amount of file data reaches a certain quantity.

2. An embedded data memory based on FPGA and solid-state drive according to claim 1, Characterized in that: An electrical plug block (4) is provided at the lower end of the solid-state drive (1), and the solid-state drive (1) is wrapped and inserted with the solid-state drive socket (3) through the electrical plug block (4).

3. An embedded data memory based on FPGA and solid-state drive according to claim 2, Characterized in that: Welding blocks (2) are provided on both sides of the solid-state drive (1), and the welding blocks (2) are distributed in an L-shaped parallel position. The solid-state drive (1) is fixedly welded to the memory (18) through the welding blocks (2).

4. An embedded data memory based on FPGA and solid-state drive according to claim 3, Characterized in that: The CS# (6) is a chip select signal, the MOSI (7) is a data line, the SCLK (9) is a communication clock, and the receiving ends of the CS# (6), MOSI (7) and SCLK (9) are all electrically connected to the FPGA (11).

5. An embedded data memory based on FPGA and solid-state drive according to claim 4, Characterized in that: The MISO (8) is a data line, and the sending end of the MISO (8) is electrically connected to the FPGA (11).

6. An embedded data memory based on FPGA and solid-state drive according to claim 5, Characterized in that: The AGND (13) is a digital ground, and the sending and receiving ends of the AGND (13) are all electrically connected to the FPGA (11).

7. An embedded data memory based on FPGA and solid-state drive according to claim 6, Characterized in that: The TXDP (14) is a positive data transmission signal interface, the TXDN (15) is a negative data transmission signal interface, and the transmitting ends of the TXDP (14) and the TXDN (15) are electrically connected to the FPGA (11).

8. An embedded data memory based on an FPGA and a solid-state drive according to claim 7, wherein: The RXDP (16) is a positive data reception signal interface, the RXDN (17) is a negative data reception signal interface, and the receiving ends of the RXDP (16) and the RXDN (17) are both electrically connected to the FPGA (11).

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