Three-dimensional integrated chip and testing method and power-on method thereof

Abstract

The application provides a three-dimensional integrated chip, a testing method and a power-on method of the three-dimensional integrated chip. The three-dimensional integrated chip comprises a logic unit, at least one storage unit, and a storage array and a functional circuit of the storage array. The at least one storage unit is arranged in a stacked bonding mode with the logic unit. The storage array is arranged in the storage unit, and the functional circuit is arranged in the logic unit. Specifically, the functional circuit originally arranged in the storage unit is arranged in the logic unit, so that the functional circuit in the logic unit is shared by the plurality of storage units. On the one hand, the storage area of the storage unit is expanded, and on the other hand, the consistency between the plurality of storage units when working independently is ensured, and the reliability of the working is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a three-dimensional integrated chip and a test method and a power-on method of the three-dimensional integrated chip. BACKGROUND

[0002] The traditional dynamic memory (DRAM) internally contains interface modules, protocol analysis modules, data paths, test modules, internal voltage and current control modules, array repair modules, storage arrays and control logic modules, etc. In some systems that require large-capacity cache, there are usually many DRAMs, and 3DIC technology can stack package multiple DRAMs and logic chips. When a logic chip and multiple DRAMs are stacked and packaged, from the perspective of the logic chip, these stacked DRAMs can be regarded as a storage whole, but the same functional modules are provided on each DRAM, which will cause waste of chip area. In addition, since each DRAM works independently, it is difficult to achieve consistency between them, which will cause poor work reliability. SUMMARY

[0003] The present application provides a three-dimensional integrated chip and a test method and a power-on method of the three-dimensional integrated chip, which can expand the storage area of the storage unit and ensure the consistency between multiple storage units when working independently, thereby improving the work reliability.

[0004] To solve the above technical problems, the first technical solution provided by the present application is to provide a three-dimensional integrated chip, comprising: a logic unit; at least one storage unit, the at least one storage unit is stacked and bonded with the logic unit; the three-dimensional integrated chip is configured with a storage array and a functional circuit of the storage array, the storage array is arranged in the storage unit, and the functional circuit is arranged in the logic unit.

[0005] Among them, the area of the storage unit is equal to the area of the storage array.

[0006] Among them, each storage unit includes a first bonding port, the logic unit includes a second bonding port, the first bonding port of each storage unit is bonded and connected with the second bonding port to form a three-dimensional heterogeneous bonding structure, and the at least one storage unit is stacked and bonded with the logic unit.

[0007] The logic unit further comprises a function pin connected to the function circuit, the function pin receives an external function signal, and the external function signal is transmitted to the function circuit, so that the function circuit generates a control signal based on the external function signal, and the control signal is transmitted to the storage unit through the three-dimensional heterojunction bonding structure to perform predetermined processing on the storage unit.

[0008] The signal transmission line parameters between each storage unit and the function circuit are the same, so that the control signal is transmitted to each storage unit at the same time, thereby simultaneously performing predetermined processing on each storage unit.

[0009] The function circuit comprises at least one of a test circuit, a repair circuit, a voltage control circuit, a current control circuit, a protocol analysis circuit, an interface circuit, and a logic control circuit, or any combination thereof.

[0010] The number of function circuits is N, and the storage units are divided into N groups; each group of storage units shares one function circuit.

[0011] To solve the above technical problems, the second technical solution provided by the present application is to provide a test method of a three-dimensional integrated chip, the three-dimensional integrated chip comprising: a logic unit and at least one storage unit, the at least one storage unit and the logic unit are laminated and bonded; a storage array and a function circuit of the storage array are configured in the three-dimensional integrated chip, the storage array is arranged in the storage unit, and the function circuit is arranged in the logic unit, wherein the function circuit comprises a test circuit, and the test method comprises: at least one storage unit receives a test control signal from the test circuit, the test control signal is generated by the test circuit based on an external test signal; and the corresponding storage unit is tested based on the test control signal.

[0012] The at least one storage unit simultaneously receives the test control signal from the test circuit.

[0013] The step of receiving the test control signal from the test circuit by the at least one storage unit comprises: the test circuit analyzes the external test signal, and performs key matching based on the analysis result; in response to the matching being passed, the at least one storage unit receives the test control signal from the test circuit.

[0014] To solve the above technical problems, the third technical solution provided by the present application is to provide a power-on method of a three-dimensional integrated chip, the three-dimensional integrated chip comprising: a logic unit and at least one storage unit, the at least one storage unit being arranged in a stacked bonding manner with the logic unit; a storage array and a functional circuit of the storage array being configured in the three-dimensional integrated chip, the storage array being arranged in the storage unit, and the functional circuit being arranged in the logic unit, wherein the functional circuit comprises a power supply circuit, and the power-on method comprises: the at least one storage unit receiving a power-on control signal from the power supply circuit, the power-on control signal being generated by the power supply circuit based on an external power-on signal; and powering on the corresponding storage unit based on the power-on control signal.

[0015] The at least one storage unit simultaneously receives the power-on control signal from the power supply circuit.

[0016] The three-dimensional integrated chip of the present application comprises: a logic unit; at least one storage unit arranged in a stacked bonding manner with the logic unit; a storage array and a functional circuit of the storage array being configured in the three-dimensional integrated chip, the storage array being arranged in the storage unit, and the functional circuit being arranged in the logic unit. Specifically, the functional circuit originally arranged in the storage unit is arranged in the logic unit, so that the multiple storage units share the functional circuit in the logic unit, which on the one hand expands the storage area of the storage unit, and on the other hand ensures the consistency between the multiple storage units when they work independently, thereby improving the reliability of work. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 The structural schematic diagram of an embodiment of the three-dimensional integrated chip of the present application;

[0019] Figure 2 The structural schematic diagram of an embodiment of the three-dimensional integrated chip of the present application; Figure 1 The structural schematic diagram of an embodiment of the three-dimensional integrated chip of the present application;

[0020] Figure 3 The flowchart of an embodiment of the test method of the three-dimensional integrated chip;

[0021] Figure 4 The flowchart of an embodiment of the power-on method of the three-dimensional integrated chip. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0023] Please refer to Figure 1 , Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of a three-dimensional integrated chip of the present application, which specifically comprises a logic unit 11 and at least one memory unit 12. The at least one memory unit 12 is stacked and bonded with the logic unit 11. In a specific embodiment, each memory unit 12 comprises a first bonding port, and the logic unit 11 comprises a second bonding port. The first bonding port of each memory unit is bonded with the second bonding port, forming a three-dimensional heterogeneous bonding structure 13, and thereby the at least one memory unit 12 is stacked and bonded with the logic unit 11.

[0024] The three-dimensional integrated chip is configured with a memory array and a functional circuit of the memory array. The memory array is arranged in the memory unit 12, and the functional circuit is arranged in the logic unit 11.

[0025] In the prior art, each storage unit 12 is provided with a corresponding functional circuit, and the functions of the functional circuits are the same. In actual application, the functional pins of the logic unit 11 output functional signals to the functional circuits of each storage unit 12, and then the functional circuits of each storage unit 12 respond to the functional signals to perform corresponding operations. On the one hand, since the signal transmission lines of each storage unit 12 and the functional pins are different, the functional signals transmitted to each storage unit 12 will be different in time, thereby causing clock difference. On the other hand, since the response rates of the functional circuits of each storage unit 12 to the functional signals are different, the time for performing corresponding operations will be different, thereby exacerbating the generation of clock difference. In addition, the same functional circuits are provided on each storage unit 12, which will cause waste of the storage unit 12. In the present application, the functional circuit for controlling the storage array that is common to each storage unit 12 is arranged in the logic unit 11, and the storage unit 12 only arranges the storage array. That is, the area of the storage unit 12 is equal to the area of the storage array. The storage unit 12 is at least one of a dynamic random access memory (DRAM) and a static random access memory (SRAM). The "unit" can be represented as "wafer", "die", "chip", and the "chip" is obtained by packaging the "die".

[0026] For details, please refer to Figure 2 In the present embodiment, the logic unit 11 includes a functional pin 21, the functional pin 21 is connected to the functional circuit 22, the functional pin 21 receives an external functional signal, transmits the external functional signal to the functional circuit 22, so that the functional circuit 22 generates a control signal based on the external functional signal, and transmits the control signal to the storage unit 12 through the three-dimensional heterojunction bonding structure 13, to perform a predetermined processing on the storage unit 12.

[0027] In a specific embodiment, the functional circuit includes at least one of a test circuit, a repair circuit, a voltage control circuit, a current control circuit, a protocol analysis circuit, an interface circuit, and a logic control circuit, or any combination thereof.

[0028] In an embodiment, the signal transmission line parameters between each storage unit 12 and the functional circuit 22 are the same, so that the control signal is transmitted to each storage unit 12 at the same time, thereby performing a predetermined processing on each storage unit 12 at the same time.

[0029] For details, please refer to Figure 2In this circuit, the signal transmission lines between the 6×6 storage cells 12 and the functional circuit 22 have the same parameters, including the length and impedance of the signal transmission lines. This allows control signals to be transmitted simultaneously from the functional circuit 22 to the storage cells 12. This ensures consistency among the multiple storage cells 12 when they operate independently, improving operational reliability.

[0030] like Figure 2 As shown, the functional circuit 22 on the storage cell 12 is moved to the logic cell 11 for implementation. For a case where 36 storage cells 12 and logic cells 11 are stacked, only one functional circuit 22 needs to be designed on the logic cell 11. By having all 36 storage cells 12 share the functional circuit 22, the intended function is achieved while saving the area of ​​36 functional circuits 22. In some cases, for ease of wiring, more than one functional circuit 22 may be designed on the logic cell 11. For example, 6 storage cells 12 per row may share the functional circuit 22 on one logic cell 11, saving the area of ​​30 functional circuits 22. Specifically, the number of functional circuits 22 is N, and the storage cells are divided into N groups; each group of storage cells shares one functional circuit. Figure 2 As shown, assuming there are 6 functional circuits 22 and the 36 storage units 12 are divided into 6 groups, with each row forming one group, then the first row of storage units 12 shares one functional circuit 22, the second row of storage units 12 shares one functional circuit 22, and so on. In another embodiment, each column of storage units 12 can share one functional circuit 22. It is understood that to ensure operational consistency, the arrival time of the functional signal output from each functional circuit 22 at each storage unit 12 should be the same. Of course, to meet certain special requirements, the arrival time of the functional signal output from each functional circuit 22 at each storage unit 12 can also be set to meet predetermined conditions, without specific limitations.

[0031] Furthermore, these functional circuits 22, which were originally located in the storage cell 12, are now located in the logic cell 11, freeing up more storage space for the storage cell 12 and increasing its storage area. In one embodiment, if the process conditions are met, all the functional circuits 22 on the storage cell 12 are located in the logic cell 11, so that only the storage array is located in the storage cell 12, that is, the area of ​​the storage cell 12 is equal to the area of ​​the storage array.

[0032] In one feasible embodiment, process requirements can be considered, and functional circuits that match the process of logic unit 11 can be set in logic unit 11, thereby improving product yield and increasing the storage area of ​​storage unit 12 to some extent.

[0033] Please refer to Figure 3 The application also provides a test method of a three-dimensional integrated chip. The three-dimensional integrated chip comprises a logic unit and at least one memory unit, and the at least one memory unit is arranged in a flip-chip manner with the logic unit. The three-dimensional integrated chip is configured with a memory array and a functional circuit of the memory array. The memory array is arranged in the memory unit, and the functional circuit is arranged in the logic unit. Please refer to Figure 1 and Figure 2 for details. The functional circuit comprises a test circuit. Specifically, the test method comprises the following steps.

[0034] Step S31: The at least one memory unit receives a test control signal from the test circuit. The test control signal is generated by the test circuit based on an external test signal.

[0035] Specifically, the test circuit on the logic unit receives an external test signal. The external test signal is generated by an external device, which can be a chip testing machine. The test circuit generates a test control signal based on the external test signal.

[0036] Step S32: The corresponding memory unit is tested based on the test control signal.

[0037] The test control signal is transmitted to the memory unit, and the corresponding memory unit is tested based on the test control signal. In a specific embodiment, the parameters of the signal transmission lines from each memory unit to the test circuit are the same, so that the at least one memory unit simultaneously receives the test control signal from the test circuit.

[0038] In a specific embodiment, after receiving the external test signal, the test circuit further analyzes the external test signal and performs key matching based on the analysis result. If the matching is passed, the at least one memory unit receives the test control signal from the test circuit. In this way, the access privacy of the memory unit can be ensured. Specifically, the test circuit stores pre-set verification data. After analyzing the external test signal, the analysis result is matched with the verification data. If they are consistent, the verification is passed. If the verification is passed, the test control signal controls the memory unit to enter a test mode, which includes a parallel read-write self-comparison test mode.

[0039] The test method of the application can simultaneously test all memory units, so that the multiple memory units can be consistent with each other when working independently, thereby improving the reliability of the work.

[0040] In another embodiment, the internal operating voltage of the memory cell (for example, the WL control voltage is usually about 2.9V) and the interface voltage (usually about 1.2V) are different, which requires an internal voltage module to convert the external voltage to the internal voltage required by the memory cell. Each memory cell internal voltage control and generation module occupies a lot of area, and these voltage modules play the same role in each memory cell, so they can be moved to the logic chip to generate, thereby saving area. For details, see Figure 4 A power-on method of a three-dimensional integrated chip is provided. The three-dimensional integrated chip includes a logic unit and at least one memory unit, and the at least one memory unit is stacked and bonded with the logic unit. A storage array and a functional circuit of the storage array are configured in the three-dimensional integrated chip. The storage array is arranged in the memory unit, and the functional circuit is arranged in the logic unit. For details, see Figure 1 And Figure 2 The functional circuit includes a power supply circuit, and the power-on method includes:

[0041] Step S41: The at least one memory unit receives a power-on control signal from the power supply circuit, and the power-on control signal is generated by the power supply circuit based on an external power-on signal.

[0042] Specifically, the power supply circuit on the logic unit receives an external power-on signal, and the external power-on signal is generated by an external device, which can be a chip power-on machine. The power supply circuit generates a power-on control signal based on the external power-on signal.

[0043] Step S42: Power on the corresponding memory unit based on the power-on control signal.

[0044] The power-on control signal is transmitted to the memory unit, and the corresponding memory unit is powered on based on the power-on control signal. In a specific embodiment, the parameters of the signal transmission line from each memory unit to the power supply circuit are the same, so that the at least one memory unit simultaneously receives the power-on control signal from the power supply circuit. This can ensure that the memory units are powered on at the same time, so that multiple memory units can work independently and consistently with each other, improving the reliability of the work.

[0045] Specifically, the power supply circuit converts the voltage of the external power-on signal to obtain a power-on control signal matching the voltage of the memory unit, and uses the power-on control signal to control the power-on of the memory unit.

[0046] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A three-dimensional integrated chip, characterized by, Comprise: A logic unit; At least one storage unit, which is stacked and bonded with the logic unit; The three-dimensional integrated chip is configured with a storage array and a functional circuit of the storage array, the storage array is arranged in the storage unit, and the functional circuit is arranged in the logic unit; wherein, the storage unit is only provided with the storage array; The area of the storage unit is equal to the area of the storage array; The signal transmission line parameters between each storage unit and the functional circuit are the same, so that the control signal is transmitted to each storage unit at the same time, thereby simultaneously performing predetermined processing on each storage unit; wherein, the control signal is generated by the functional circuit based on an external function signal.

2. The three-dimensional integrated chip of claim 1, wherein, Each of the storage units includes a first bonding port, The logic unit includes a second bonding port, the first bonding port of each storage unit is bonded and connected with the second bonding port to form a three-dimensional heterogeneous bonding structure, and the at least one storage unit is stacked and bonded with the logic unit.

3. The three-dimensional integrated chip of claim 2, wherein, The logic unit further comprises: A function pin connected to the functional circuit, which receives an external function signal and transmits the external function signal to the functional circuit, so that the functional circuit generates a control signal based on the external function signal and transmits the control signal to the storage unit through the three-dimensional heterogeneous bonding structure to perform predetermined processing on the storage unit.

4. The three-dimensional integrated chip of claim 1, wherein, The functional circuit includes at least one of a test circuit, a repair circuit, a voltage control circuit, a current control circuit, a protocol analysis circuit, an interface circuit, and a logic control circuit, or any combination thereof.

5. The three-dimensional integrated chip of claim 1, wherein, The number of functional circuits is N, and the storage units are divided into N groups; each group of storage units shares one functional circuit.

6. A method of testing a three-dimensional integrated chip, characterized by, The three-dimensional integrated chip comprises a logic unit and at least one storage unit, which is stacked and bonded with the logic unit; the three-dimensional integrated chip is configured with a storage array and a functional circuit of the storage array, the storage array is arranged in the storage unit, and the functional circuit is arranged in the logic unit, wherein, the functional circuit includes a test circuit, and the storage unit is only provided with the storage array; the area of the storage unit is equal to the area of the storage array, the signal transmission line parameters between each storage unit and the functional circuit are the same, so that the control signal is transmitted to each storage unit at the same time, thereby simultaneously performing predetermined processing on each storage unit; wherein, the control signal is generated by the functional circuit based on an external function signal, and the test method comprises: The at least one storage unit receives a test control signal from the test circuit, which is generated by the test circuit based on an external test signal; Test the corresponding storage unit based on the test control signal; Wherein, the at least one storage unit simultaneously receives the test control signal from the test circuit.

7. The test method of claim 6, wherein, The step of receiving a test control signal from the test circuit by the at least one storage unit comprises: The test circuit parses the external test signal, and performs key matching based on the parsed result; In response to a match pass, the at least one memory unit receives a test control signal from the test circuit.

8. A power-up method of a three-dimensional integrated chip, characterized by, The three-dimensional integrated chip comprises: a logic unit and at least one memory unit, the at least one memory unit is stacked and bonded with the logic unit; a storage array and a functional circuit of the storage array are configured in the three-dimensional integrated chip, the storage array is arranged in the memory unit, and the functional circuit is arranged in the logic unit, wherein the functional circuit comprises a power supply circuit, and the memory unit is only provided with the storage array; the area of the memory unit is equal to the area of the storage array, the signal transmission line parameters between each memory unit and the functional circuit are the same, so that a control signal is transmitted to each memory unit at the same time, thereby predetermined processing is performed on each memory unit at the same time; wherein the control signal is generated by the functional circuit based on an external function signal, and the power-on method comprises: The at least one memory unit receives a power-on control signal from the power supply circuit, and the power-on control signal is generated by the power supply circuit based on an external power-on signal; Power on the corresponding memory unit based on the power-on control signal; Wherein, the at least one memory unit simultaneously receives the power-on control signal from the power supply circuit.

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