Method for improving IGBT trench size accuracy

Abstract

The application provides a method for improving IGBT trench size precision, comprising the following steps: S1, P+ push well, and growing a thick oxide layer; S2, photoetching a trench pattern; S3, performing trench oxide layer etching, and removing surface photoresist after etching; S4, photoetching a BUSBAR pattern, photoetching a BUSBAR oxide layer, and protecting the BUSBAR oxide layer; S5, using the oxide layer as a hard mask, and performing trench silicon etching; S6, removing the surface excess oxide layer, and removing the surface photoresist; S7, growing a thin oxide layer; S8, filling the trench with photoresist; S9, removing part of the surface photoresist, and reserving the photoresist in the trench; S10, PWELL injection, and forming a PWELL layer; S11, removing the photoresist in the trench; and S12, removing the thin oxide layer. The method for improving IGBT trench size precision provided by the application eliminates the influence of the BUSBAR step on the trench size by adjusting process steps, using a hard mask, and using photoresist to fill deep holes, so that the trench size has good uniformity.

Description

Technical Field

[0001] This invention belongs to the field of IGBT manufacturing technology, specifically relating to a method for improving the dimensional accuracy of IGBT trenches. Background Technology

[0002] In the IGBT process, P+ implantation is first performed on the BUSBAR and termination regions, followed by P+ push-in and impurity activation. During this process, a 1-2 μm thick oxide layer is grown simultaneously. Then, photolithography and etching are performed on the BUSBAR, retaining the oxide layer above the BUSBAR and termination regions while removing oxide layers elsewhere. A thin oxide layer is then grown as a PWELL implantation buffer layer before PWELL implantation. Due to the limitations of PWELL implantation, trench photolithography and etching can only be performed after PWELL implantation. Figure 1 As shown, due to the small size of the trench, the photoresist thickness at this location decreases due to the influence of the BUSBAR oxide layer steps. This difference in film thickness leads to significant fluctuations in the trench size near the steps. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method for improving the dimensional accuracy of IGBT grooves by eliminating the influence of BUSBAR steps on groove dimensions and achieving good uniformity of groove dimensions.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows: a method for improving the dimensional accuracy of IGBT trenches, comprising the following steps:

[0005] S1, P+ pusher trap, growth of thick oxide layer;

[0006] S2, photolithographic groove pattern;

[0007] S3, perform trench oxide layer etching, and remove surface photoresist after etching;

[0008] S4, BUSBAR patterning photolithography, BUSBAR oxide layer photolithography, protection of BUSBAR oxide layer;

[0009] S5, using an oxide layer as a hard mask, performs trench silicon etching;

[0010] S6, Remove excess oxide layer from the surface and remove surface photoresist;

[0011] S7, thin oxide layer growth;

[0012] S8, the trench is filled with photoresist;

[0013] S9, partial removal of photoresist on the surface, leaving photoresist in the trench;

[0014] S10, PWELL injection, forming a PWELL layer;

[0015] S11, Photoresist removal in the trench;

[0016] S12, thin oxide layer removal, continue with subsequent processes.

[0017] Preferably, in step S1, the thickness of the grown oxide layer is 0.5-2 μm.

[0018] Preferably, in step S2, the trench width is 0.13 μm to 1.5 μm.

[0019] Preferably, in step S5, the trench etching depth is 3µm to 7µm.

[0020] Preferably, in step S7, the thickness of the thin oxide layer is 0.02 μm to 0.15 μm.

[0021] Preferably, in step S8, the groove holes are filled with photoresist by uniformly applying the photoresist to the entire surface.

[0022] Preferably, in step S9, exposure or etching is used to remove part of the photoresist on the surface.

[0023] Preferably, in steps S6 and S12, wet etching is used to remove the oxide layer.

[0024] Preferably, in step S8, an anti-reflective coating or spin-coated glass is used as the trench filling material.

[0025] Optionally, step S7 can be removed, and step S6 can be moved after step S9.

[0026] The beneficial effects of this invention are as follows: After forming a thick oxide layer in the P+ layer push-well, trench photolithography is performed first, followed by trench oxide layer etching. This eliminates the thickness difference of photoresist near the step caused by oxide layer steps, improving the uniformity of trench size. Then, photoresist is used to fill the inside of the trench, serving as a barrier layer to protect the bottom of the trench during PWELL implantation. By adjusting the order of BUSBAR oxide layer etching and trench etching, the oxide layer on the trench is etched first, followed by trench silicon etching. This allows the thick oxide layer generated by the P+ push-well to be used as a hard mask during trench etching, eliminating the influence of BUSBAR oxide layer steps on trench size and improving trench size uniformity. The use of photoresist to fill the inside of the trench protects the bottom of the trench from the influence of PWELL implantation, allowing PWELL implantation to be performed after trench etching, ensuring the feasibility of using the thick oxide layer generated by the P+ push-well as a hard mask. Attached Figure Description

[0027] Figure 1A schematic diagram showing the decreasing trend of photoresist thickness due to the BUSBAR oxide layer steps;

[0028] Figure 2 This is a flowchart illustrating one embodiment of the present invention;

[0029] Figure 3 Here is a schematic diagram of the structure of S1;

[0030] Figure 4 This is a schematic diagram of the structure of S2;

[0031] Figure 5 Here is a schematic diagram of the structure of S3;

[0032] Figure 6 This is a schematic diagram of the structure of S4;

[0033] Figure 7 Here is a schematic diagram of the structure of S5;

[0034] Figure 8 This is a schematic diagram of the structure of S6;

[0035] Figure 9 This is a schematic diagram of the structure of S7;

[0036] Figure 10 This is a schematic diagram of the structure of S8;

[0037] Figure 11 This is a schematic diagram of the S9 structure;

[0038] Figure 12 This is a schematic diagram of the structure of S10;

[0039] Figure 13 This is a schematic diagram of the structure of S11;

[0040] Figure 14 This is a schematic diagram of the structure of S12;

[0041] Figure 15 This is a flowchart illustrating another embodiment of the present invention. Detailed Implementation

[0042] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0043] Please refer to the following: Figure 1-14 The method for improving the dimensional accuracy of IGBT trenches provided in this embodiment includes the following steps:

[0044] S1, P+ pusher trap, growth of thick oxide layer;

[0045] S2, photolithographic groove pattern;

[0046] S3, perform trench oxide layer etching, and remove surface photoresist after etching;

[0047] S4, BUSBAR patterning photolithography, BUSBAR oxide layer photolithography, protection of BUSBAR oxide layer;

[0048] S5, using an oxide layer as a hard mask, performs trench silicon etching;

[0049] S6, Remove excess oxide layer from the surface and remove surface photoresist;

[0050] S7, thin oxide layer growth;

[0051] S8, the trench is filled with photoresist;

[0052] S9, partial removal of photoresist on the surface, leaving photoresist in the trench;

[0053] S10, PWELL injection, forming a PWELL layer;

[0054] S11, Photoresist removal in the trench;

[0055] S12, thin oxide layer removal, continue with subsequent processes.

[0056] In this embodiment, after forming a thick oxide layer in the P+ layer push-well, trench photolithography is performed first, followed by trench oxide layer etching to eliminate the photoresist thickness difference near the step caused by the oxide layer step, thereby improving the uniformity of the trench size. Then, photoresist is used to fill the inside of the trench as a barrier layer to protect the bottom of the trench from PWELL implantation. By adjusting the order of BUSBAR oxide layer etching and trench etching, the oxide layer on the trench is etched first, followed by trench silicon etching, so that the thick oxide layer generated by the P+ push-well can be used as a hard mask for trench etching. Photoresist is used to fill the inside of the trench to protect the inside of the trench from the influence of PWELL implantation.

[0057] More specifically, in step S1, the thickness of the grown oxide layer is 0.5-2 μm.

[0058] More specifically, in step S2, the trench width is 0.13 μm to 1.5 μm.

[0059] More specifically, in step S5, the trench etching depth is 3µm to 7µm.

[0060] More specifically, in step S7, the thickness of the thin oxide layer is 0.02 μm to 0.15 μm.

[0061] More specifically, in step S8, the trench holes are filled with photoresist by uniformly applying the photoresist to the entire surface.

[0062] More specifically, in step S9, exposure or etching is used to remove part of the photoresist on the surface.

[0063] More specifically, in steps S6 and S12, wet etching is used to remove the oxide layer. Wet etching is a process in which a patterned photoresist is used as a mask, and the wafer is immersed in acid or sprayed with acid to etch away the material in the areas not covered by the photoresist.

[0064] More specifically, in step S8, an anti-reflective coating or spin-coated glass is used as the trench filling material.

[0065] Example 2

[0066] Please see Figure 15 This embodiment is basically the same as the technical solution provided in Embodiment 1, except that step S7 in Embodiment 1 is removed and step S6 is moved to after step S9. This embodiment can save the cost of one oxide layer removal and one oxide layer growth, shorten the wafer fabrication cycle, and improve production efficiency.

[0067] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving the dimensional accuracy of IGBT trenches, characterized in that, Includes the following steps: S1, P+ push-well is performed on the silicon substrate to grow a thick oxide layer; S2, Photolithographically pattern trenches on a thick oxide layer; S3, perform trench oxide etching on the thick oxide layer, and remove the surface photoresist after etching; S4. On the formed trench oxide layer structure, a BUSBAR photomask is used for spin coating, exposure and development to form a BUSBAR photomask pattern and protect the BUSBAR oxide layer. S5, using BUSBAR oxide layer as hard mask, performs trench silicon etching; S6, perform wet etching on the oxide layer to remove the oxide layer other than the BUSBAR pattern completed in step S4; after the oxide layer etching is completed, perform a photoresist stripping process to remove the photoresist on the oxide layer surface. S7, thin oxide layer is grown on the unetched surface and trench surface of the silicon substrate; S8, the trench is filled with photoresist; S9, the photoresist on the unetched surface of the silicon substrate is removed, while the photoresist in the trench is retained; S10, PWELL implantation is performed on the unetched surface of the silicon substrate to form a PWELL layer; S11, Photoresist removal in the trench; S12, thin oxide layer removal, continue with subsequent processes; The thickness of the thick oxide layer is 0.5 μm to 2 μm, and the thickness of the thin oxide layer is 0.02 μm to 0.15 μm.

2. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: In step S2, the trench width is 0.13μm~1.5μm.

3. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: In step S5, the trench etching depth is 3μm~7μm.

4. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: In step S8, the trench holes are filled with photoresist by uniformly applying the photoresist to the entire surface.

5. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: In step S9, exposure or etching is used to remove part of the photoresist on the surface.

6. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: In both steps S6 and 12, wet etching is used to remove the oxide layer.

7. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: In step S8, an anti-reflective coating or spin-coated glass is used as the trench filling material.

8. The method for improving the dimensional accuracy of IGBT trenches as described in claim 1, characterized in that: Remove step S7 and move step S6 after step S9.

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