A Low Output Voltage Ripple Control Method and Device for a Dual-Output LLC Resonant Converter

Abstract

The present invention belongs to the technical field of resonant switching converters, and particularly relates to a low output voltage ripple control method and device for a dual-output LLC resonant converter, which are used to solve the problems of low-frequency oscillation and increased output ripple existing in traditional LLC resonant converters. The present invention includes a power supply, a power supply circuit TD, a feedback circuit, an output load R1, and an output load R2. In the present invention, the power supply circuit TD is the main circuit, and the feedback circuit collects current and voltage. Through logical selection by a logical selection circuit, a pulse generation circuit generates three pulse signals with different frequencies, and the output of the power supply circuit TD is adjusted by the pulse signals with different frequencies, so as to achieve a fast load transient response speed, a small output voltage ripple, and a wide load stability range.

Description

Technical Field

[0001] The present invention relates to the technical field of resonant switch converters, and particularly to a low output voltage ripple control method and device for a dual-output LLC resonant converter. Background Art

[0002] A switch mode power supply (SMPS), also known as a switched-mode power supply or a switch converter, is a high-frequency power conversion device and a type of power supply. Its function is to convert a voltage level into the voltage or current required by the user through different forms of architectures. The input of a switch power supply is mostly an AC power supply (such as mains power) or a DC power supply, and the output is mostly devices that require a DC power supply, such as a personal computer, and the switch power supply performs the conversion of voltage and current between the two.

[0003] Different from a linear power supply, a switch power supply uses switching transistors that mostly switch between the fully-on mode (saturation region) and the fully-off mode (cut-off region). Both of these modes have the characteristic of low dissipation. Although there is relatively high dissipation during the switching transition, the time is very short, so it is more energy-saving and generates less waste heat. Ideally, a switch power supply itself does not consume electrical energy. Voltage regulation is achieved by adjusting the on and off times of the transistor. In contrast, during the process of generating the output voltage, a linear power supply has the transistor operating in the amplification region and consuming electrical energy itself. The high conversion efficiency of a switch power supply is one of its major advantages, and because the switch power supply operates at a high frequency, a small-sized and lightweight transformer can be used. Therefore, the switch power supply is also smaller in size and lighter in weight than a linear power supply.

[0004] When the high efficiency, volume, and weight of the power supply are the key considerations, a switch power supply is better than a linear power supply. However, a switch power supply is more complex, and the internal transistors switch frequently. If the switching current is not processed, it may generate noise and electromagnetic interference that affect other devices. Moreover, if the switch power supply is not specially designed, its power factor may not be high.

[0005] With the development of power electronics technology, modern switching power supplies are evolving towards high frequency, digitalization, and integration. The LLC resonant converter is widely used in a series of fields that require power conversion, such as communication power supplies, server power supplies, data center power supplies, charging piles, and aviation power supplies, due to its simple topology, high-frequency soft switching, and high efficiency. In addition, portable products require an increasing number of voltage levels. Among them, liquid crystal displays usually require two or more levels of supply voltage, and the number of special voltage levels required for various devices and functions in smart phones has exceeded 20. Research shows that the dual-output LLC resonant converter can provide two independent power supplies for products such as server power supplies, liquid crystal displays, smart phones, and tablet computers, reducing the power supply volume, lowering the loss of the switching power supply, and improving the conversion efficiency of the converter, thus attracting extensive attention at home and abroad.

[0006] For the traditional dual-frequency control LLC resonant converter, its control idea is as follows: The control circuit consists of a sampling circuit, a logic control circuit, a comparator, and a pulse selection circuit. After each cycle ends, the sampling circuit samples the output voltage. The logic control circuit inputs high-frequency pulse P H and low-frequency pulse P L The pulse frequencies are used to compare the sampled output voltage with the reference voltage. The comparison result is used to control the pulse selection circuit to output a high-frequency pulse or a low-frequency pulse, and the pulse signal controls the on or off of the switching tube. When this method is used in a dual-output LLC resonant converter, there is always a low-frequency oscillation phenomenon in the output, resulting in an increase in output ripple and affecting the stable characteristics of the output. Summary of the Invention

[0007] The purpose of the present invention is to provide a method and device for controlling low output voltage ripple of a dual-output LLC resonant converter to solve the problems proposed in the above background technology. The purpose is to provide a method to achieve a fast load transient response speed, small output voltage ripple, and a wide load stable range. The present invention is applicable to various topological structures of LLC resonant converters.

[0008] The present invention provides the following technical solutions to solve the above technical problems:

[0009] A device for controlling low output voltage ripple of a dual-output LLC resonant converter includes a power supply, a power supply circuit TD, a feedback circuit, an output load R1, and an output load R2. The power supply circuit TD includes a full-bridge conversion circuit coupled to the power supply with a drive circuit, a resonant network coupled to the full-bridge conversion circuit, an isolation transformer coupled to the resonant network, a first rectifier filter circuit and a second rectifier circuit coupled to the isolation transformer, a load output R1 coupled to the first rectifier filter circuit, and a load output R2 coupled to the second rectifier filter circuit;

[0010] The drive circuit of the full-bridge conversion circuit includes drive circuit DR1 and drive circuit DR2; the full-bridge conversion circuit includes switch tubes Q1, Q2, Q3, and Q4 connected in a bridge; the drive circuit DR1 is connected to the gates of switch tubes Q1 and Q4, and the drive circuit DR2 is connected to the gates of switch tubes Q2 and Q3;

[0011] A current acquisition point is provided on either side of the capacitance of the resonant cavity in the resonant network; a voltage acquisition point is provided on either side of the load output R1 of the first rectification and filtering circuit;

[0012] The feedback circuit includes an output voltage acquisition circuit, a capacitance current acquisition circuit, a logic selection circuit, a pulse generation circuit, and a dead-time generation circuit;

[0013] The input end of the capacitance current acquisition circuit is connected to the current acquisition point; the input end of the output voltage acquisition circuit is connected to the voltage acquisition point; the first input end of the logic selection circuit is connected to the first output end of the capacitance current acquisition circuit, and the second input end of the logic selection circuit is connected to the output end of the output voltage acquisition circuit;

[0014] The first input end of the pulse generation circuit is connected to the second output end of the capacitance current acquisition circuit, the second input end of the pulse generation circuit is connected to the first output end of the logic selection circuit, and the third input end of the pulse generation circuit is connected to the second output end of the logic selection circuit;

[0015] The input end of the dead-time generation circuit is connected to the first output end of the pulse generation circuit; the drive circuit DR1 is connected to the first output end of the pulse generation circuit, and the drive circuit DR2 is connected to the output end of the dead-time generation circuit;

[0016] The logic selection circuit includes a NOT gate NOT1 connected to the first output end of the capacitance current acquisition circuit, a D flip-flop connected to the output end of the output voltage acquisition circuit, an AND gate AND1, and an AND gate AND2; the input end of the AND gate AND1 is connected to the output end of the NOT gate NOT1 and the first output end of the D flip-flop, and the input end of the AND gate AND2 is connected to the output end of the NOT gate NOT1 and the second output end of the D flip-flop; the output end of the AND gate AND1 forms the first output end of the logic selection circuit; the output end of the AND gate AND2 forms the second output end of the logic selection circuit.

[0017] After adopting this technical solution, the feedback circuit collects current and voltage, selects through a logic selection circuit, enables the pulse generation circuit to generate three pulse signals with different frequencies, and adjusts the output of the power supply circuit TD through the duty cycle of the pulse signal, achieving a fast load transient response speed, a small output voltage ripple, and a wide load stable range.

[0018] Preferably, the output voltage acquisition circuit includes an output voltage detection circuit VS1 and a comparator CMP1. The output voltage detection circuit VS1 is connected to the voltage acquisition point. The negative input terminal of the comparator CMP1 is connected to the output terminal of the output voltage detection circuit VS1. The output terminal of the comparator CMP1 forms the output terminal of the output voltage acquisition circuit.

[0019] The capacitor current acquisition circuit includes a capacitor current detection circuit IS1 and a comparator CMP2. The capacitor current detection circuit IS1 is connected to the current acquisition point. The positive input terminal of the comparator CMP2 is connected to the output terminal of the capacitor current detection circuit IS1. The first output terminal and the second output terminal of the comparator CMP2 respectively form the first output terminal and the second output terminal of the capacitor current acquisition circuit.

[0020] After adopting this preferred technical solution, when the load and input voltage of the dual-output LLC resonant converter change, compared with the output current acquisition circuit, the capacitor current acquisition circuit of the present invention can quickly respond to the change of capacitor current, can quickly adjust the control pulse of the switching MOS transistor, shorten the adjustment time of the output voltage, and has a very fast load transient response speed.

[0021] Preferably, the pulse generation circuit includes a DC voltage source V connected in sequence DC1 , a selection circuit, a current-controlled current source ICCCS1, a switching transistor MOS1, a charge and discharge capacitor C OSC , and a comparator CMP4. The current-controlled current source ICCCS1 is connected to the source electrode of the switching transistor MOS1. The charge and discharge capacitor C OSC is connected to the drain electrode of the switching transistor MOS1.

[0022] The charge and discharge capacitor C OSC is connected to a voltage detection circuit V sen . The voltage detection circuit V sen is connected to a comparator CMP3. The comparator CMP3 is connected to a time delay device TD1. The time delay device TD1 is connected to the gate electrode of the switching transistor MOS1. The first output terminal and the second output terminal of the comparator CMP4 form the first output terminal and the second output terminal of the pulse generation circuit.

[0023] Preferably, the selection circuit is composed of a first selection circuit, a second selection circuit, and a third selection circuit connected in parallel; the first selection circuit, the second selection circuit, and the third selection circuit are each composed of a simple switch and a resistor; the resistances of the resistor in the first selection circuit, the resistor in the second selection circuit, and the resistor in the third selection circuit are different;

[0024] The simple switch SS1 of the first selection circuit is connected to the second output terminal of the capacitor current acquisition circuit; the simple switch SS2 of the second selection circuit is connected to the first output terminal of the logic selection circuit; the simple switch SS3 of the third selection circuit is connected to the second output terminal of the logic selection circuit.

[0025] After adopting the above preferred technical solution, by controlling the opening and closing of the simple switch to conduct the selection circuit with different resistors, pulse signals with different frequencies are generated; the principle is that: the frequency of the pulse signal generated by the pulse generation circuit is related to the resistor, capacitor C osc and the charging voltage across the capacitor. The greater the charging current of capacitor C osc , the shorter the time to reach the voltage across the capacitor, and the shorter the time, the greater the pulse frequency; the resistor is one of R1, R2, or R3, the resistance value of resistor R1 is less than the resistance value of resistor R2, and the resistance value of resistor R2 is less than the resistance value of resistor R3.

[0026] Preferably, the dead zone generation circuit includes a logic NOT gate NOT2 and a time delay device TD2. The logic NOT gate NOT2 is connected to the first output terminal of the pulse generation circuit, and the time delay device TD2 is connected to the drive circuit DR2; the output terminal of the logic NOT gate NOT2 forms the output terminal of the pulse generation circuit.

[0027] After adopting this preferred technical solution, within the time from when the control signal flips to when the feedback signal stabilizes at one end, the operation circuit of the feedback signal is shielded by the time delay device TD2, avoiding the influence of spike noise.

[0028] Preferably, the resonant network is one of an LLC resonant network, an LCC resonant network, or a CLLC resonant network.

[0029] After adopting this preferred technical solution, the present invention is applicable to multiple topological structures of the resonant network at the same time.

[0030] A method for controlling low output voltage ripple of a dual-output LLC resonant converter includes the following steps:

[0031] Step 1: The output voltage detection circuit detects the main output voltage V of the dual-output LLC resonant converter 01 , and sends it to the negative input terminal of the comparator CMP1, and sets the preset voltage reference value V refis fed into the positive input terminal of comparator CMP1, V 01 and V ref The comparison result is fed into the D terminal of the D flip-flop;

[0032] Step 2: Detect the resonant capacitor current I Cr through the capacitor current detection circuit, and the detected resonant capacitor current I Cr is fed into the positive input terminal of comparator CMP2, and the preset current reference value I ref is fed into the negative input terminal of comparator CMP2;

[0033] Step 3: When the resonant capacitor current I Cr rises to the reference current I ref , the output result of comparator CMP2 in the capacitor current acquisition circuit is 1. At this time, the logic selection circuit turns on the simple switch SS1 to connect the resistor R1 to the circuit, and the pulse generation circuit generates the highest frequency pulse P Hmax ;

[0034] Step 4: When the resonant capacitor current I Cr is less than the reference current I ref , the output result of comparator CMP2 in the capacitor current acquisition circuit is 0. After receiving the output result of comparator CMP2, the NOT gate NOT1 of the logic selection circuit outputs 1;

[0035] When the resonant capacitor current I Cr is less than the reference current I ref , and the output voltage V 01 is greater than the reference voltage V ref , the output of comparator CMP1 is 0; after the flip-flop D receives the output 0 of comparator CMP1, the first output terminal of flip-flop D outputs 1. The logic AND gate AND1 receives the output 1 of the NOT gate NOT1 and the output 1 of the first output terminal of flip-flop D. After logical operation, the logic AND gate AND1 outputs 1; at this time, the logic selection circuit turns on the simple switch SS2 to connect the resistor R2 to the circuit, and the pulse generation circuit generates the high frequency pulse P H ;

[0036] When the resonant capacitor current I Cr is less than the reference current I ref , and the output voltage V 01 is less than the reference voltage V refWhen the comparator CMP1 outputs 1; after the flip-flop D receives the output 1 of the comparator CMP1, the second output terminal of the flip-flop D outputs 1. The logic AND gate AND2 receives the output 1 of the logic NOT gate NOT1 and the output 1 of the second output terminal of the flip-flop D, and outputs 1 after logical operation; at this time, the logic selection circuit turns on the simple switch SS3 to connect the resistor R3 to the circuit, and the pulse generation circuit generates a low-frequency pulse P L ;

[0037] Step 5: The power supply V DC1 Generates different currents through the resistors R1, R2, and R3. These different currents are output through the current-controlled current source ICCCS1, and the output current charges the charge and discharge capacitor C after passing through the switching transistor MOS1 OSC through the voltage detection circuit V sen collects the voltage across the charge and discharge capacitor C OSC and sends the voltage across the charge and discharge capacitor C OSC and the preset voltage reference value V DC2 to the comparator CMP3 for comparison;

[0038] When the voltage across the charge and discharge capacitor C OSC is less than the preset voltage reference value V DC2 , the comparator CMP3 outputs 0, otherwise it outputs 1; the output of the comparator CMP3 is a square wave pulse with the same charge and discharge frequency as the charge and discharge capacitor C OSC ; after passing through the time delay device TD1, this square wave pulse is converted into a clock pulse with the same frequency to control the conduction of the switching transistor MOS1, realizing the discharge of the charge and discharge capacitor C OSC ;

[0039] Send the voltage across the charge and discharge capacitor C OSC and the preset voltage reference value V DC3 to the comparator CMP4 for comparison. When the voltage across the charge and discharge capacitor C OSC is less than the preset voltage reference value V DC3 , the comparator CMP4 outputs 0, otherwise it outputs 1, obtaining a square wave pulse signal with a duty cycle of 0.5;

[0040] where V DC2 = 2V DC3 ;

[0041] Step 6: The square wave pulse signal generated by the pulse generation circuit is connected to the drive circuit DR1 to control the conduction and cutoff of the switching MOS transistors Q1 and Q4; the square wave pulse signal generated by the pulse generation circuit is sent to the input terminal of the logic NOT gate NOT2 of the dead zone generation circuit, and after passing through the time delay device TD2, it is connected to the drive circuit DR2 to control the cutoff and conduction of the switching MOS transistors Q1 and Q4.

[0042] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows:

[0043] 1. When the load and input voltage of the dual-output LLC resonant converter change, compared with the output current acquisition circuit, the capacitor current acquisition circuit of the present invention can quickly respond to the change of the capacitor current, can quickly adjust the control pulse of the switching MOS transistor, shorten the regulation time of the output voltage, and has a very fast load transient response speed.

[0044] 2. Compared with the traditional dual-frequency control, the present invention can effectively reduce the output voltage ripple of the dual-output LLC converter.

[0045] 3. The present invention has two control pulses of the dual-output LLC resonant converter and another control pulse for reducing the low-frequency oscillation of the output voltage, effectively improving the steady-state performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a circuit structure block diagram when the present invention adopts a control method for low output voltage ripple of a dual-output LLC resonant converter.

[0047] Figure 2 It is a system structure diagram of the present invention.

[0048] Figure 3 It is a control waveform diagram of the present invention.

[0049] Figure 4 It is a transient response waveform diagram when the output voltage of the present invention changes.

[0050] Figure 5 It is a transient response waveform diagram of the output voltage when the load of the present invention changes.

[0051] Figure 6 It is an output voltage ripple waveform diagram of a traditional dual-frequency control dual-output LLC resonant converter.

[0052] Figure 7 It is an output voltage ripple waveform diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0053] In order to make the technical means, features and effects achieved by the present invention easier to be understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with specific embodiments and the drawings in the embodiments of the present invention.

[0054] As Figures 1-7 shown, the optimal embodiment of the present invention is described as follows:

[0055] See Figure 1As shown in the figure, a low output voltage ripple control device for a dual-output LLC resonant converter includes a power supply, a power supply circuit TD, a feedback circuit, an output load R1, and an output load R2. The power supply circuit TD includes a full-bridge conversion circuit coupled to the power supply and having a drive circuit, a resonant network coupled to the full-bridge conversion circuit, an isolation transformer coupled to the resonant network, a first rectifier filter circuit and a second rectifier circuit coupled to the isolation transformer, a load output R1 coupled to the first rectifier filter circuit, and a load output R2 coupled to the second rectifier filter circuit;

[0056] See Figure 2 As shown in the figure, the drive circuit of the full-bridge conversion circuit includes a drive circuit DR1 and a drive circuit DR2; the full-bridge conversion circuit includes switching tubes Q1, Q2, Q3, and Q4 connected in a bridge; the drive circuit DR1 is connected to the gates of switching tubes Q1 and Q4, and the drive circuit DR2 is connected to the gates of switching tubes Q2 and Q3;

[0057] See Figure 2 As shown in the figure, a current acquisition point is provided on either side of the capacitor of the resonant cavity in the resonant network; a voltage acquisition point is provided on either side of the load output R1 of the first rectifier filter circuit;

[0058] See Figure 1 As shown in the figure, the feedback circuit includes an output voltage acquisition circuit, a capacitor current acquisition circuit, a logic selection circuit, a pulse generation circuit, and a dead zone generation circuit;

[0059] See Figure 1 As shown in the figure, the input end of the capacitor current acquisition circuit is connected to the current acquisition point; the input end of the output voltage acquisition circuit is connected to the voltage acquisition point; the first input end of the logic selection circuit is connected to the first output end of the capacitor current acquisition circuit, and the second input end of the logic selection circuit is connected to the output end of the output voltage acquisition circuit;

[0060] See Figure 1 As shown in the figure, the first input end of the pulse generation circuit is connected to the second output end of the capacitor current acquisition circuit, the second input end of the pulse generation circuit is connected to the first output end of the logic selection circuit, and the third input end of the pulse generation circuit is connected to the second output end of the logic selection circuit;

[0061] See Figure 1 As shown in the figure, the input end of the dead zone generation circuit is connected to the first output end of the pulse generation circuit; the drive circuit DR1 is connected to the second output end of the pulse generation circuit, and the drive circuit DR2 is connected to the output end of the dead zone generation circuit;

[0062] See Figure 1 As shown, the logic selection circuit includes a NOT gate NOT1 connected to the first output terminal of the capacitor current acquisition circuit, a D flip-flop connected to the output terminal of the output voltage acquisition circuit, an AND gate AND1, and an AND gate AND2. The input terminal of the AND gate AND1 is connected to the output terminal of the NOT gate NOT1 and the first output terminal of the D flip-flop. The input terminal of the AND gate AND2 is connected to the output terminal of the NOT gate NOT1 and the second output terminal of the D flip-flop. The output terminal of the AND gate AND1 forms the first output terminal of the logic selection circuit. The output terminal of the AND gate AND2 forms the second output terminal of the logic selection circuit.

[0063] See Figure 1 As shown, in this embodiment, the feedback circuit acquires current and voltage, selects through the logic selection circuit, enables the pulse generation circuit to generate three different frequency pulse signals, and adjusts the output of the power supply circuit TD through the duty cycle of the pulse signal, achieving a fast load transient response speed, a small output voltage ripple, and a wide load stable range.

[0064] See Figure 1 As shown, the output voltage acquisition circuit includes an output voltage detection circuit VS1 and a comparator CMP1. The output voltage detection circuit VS1 is connected to the voltage acquisition point. The negative input terminal of the comparator CMP1 is connected to the output terminal of the output voltage detection circuit VS1. The output terminal of the comparator CMP1 forms the output terminal of the output voltage acquisition circuit.

[0065] See Figure 1 As shown, the capacitor current acquisition circuit includes a capacitor current detection circuit IS1 and a comparator CMP2. The capacitor current detection circuit IS1 is connected to the current acquisition point. The positive input terminal of the comparator CMP2 is connected to the output terminal of the capacitor current detection circuit IS1. The first output terminal and the second output terminal of the comparator CMP2 respectively form the first output terminal and the second output terminal of the capacitor current acquisition circuit.

[0066] See Figure 1 As shown, in this embodiment, when the load and input voltage of the dual-output LLC resonant converter change, compared with the output current acquisition circuit, the capacitor current acquisition circuit of the present invention can quickly respond to the change of the capacitor current, can quickly adjust the control pulse of the switching MOS transistor, shorten the regulation time of the output voltage, and has a very fast load transient response speed.

[0067] See Figure 1 As shown, the pulse generation circuit includes a DC voltage source V connected in sequence DC1, a selection circuit, a current-controlled current source ICCCS1, a switching transistor MOS1, and a charge and discharge capacitor C OSC , and a comparator CMP4, wherein the current-controlled current source ICCCS1 is connected to the source of the switching transistor MOS1, and the charge and discharge capacitor C OSC is connected to the drain of the switching transistor MOS1;

[0068] Refer to Figure 1 As shown, the charge and discharge capacitor C OSC is connected to a voltage detection circuit V sen , the voltage detection circuit V sen is connected to a comparator CMP3, the comparator CMP3 is connected to a time delay device TD1, and the time delay device TD1 is connected to the gate of the switching transistor MOS1; the first output terminal and the second output terminal of the comparator CMP4 form the first output terminal and the second output terminal of the pulse generation circuit.

[0069] Refer to Figure 1 As shown, the selection circuit is composed of a first selection circuit, a second selection circuit, and a third selection circuit connected in parallel; the first selection circuit, the second selection circuit, and the third selection circuit are all composed of a simple switch and a resistor; the resistances of the resistor of the first selection circuit, the resistor of the second selection circuit, and the resistor of the third selection circuit are different;

[0070] Refer to Figure 1 As shown, the simple switch SS1 of the first selection circuit is connected to the second output terminal of the capacitor current acquisition circuit; the simple switch SS2 of the second selection circuit is connected to the first output terminal of the logic selection circuit; the simple switch SS3 of the third selection circuit is connected to the second output terminal of the logic selection circuit.

[0071] Refer to Figure 1 As shown, in this embodiment, by controlling the opening and closing of the simple switch, the selection circuit with different resistances is turned on, generating pulse signals with different frequencies; the principle is: the frequency of the pulse signal generated by the pulse generation circuit is related to the resistance, the capacitor C osc and the charging voltage across the capacitor. The greater the charging current of the capacitor C osc , the shorter the time to reach the voltage across the capacitor, and the shorter the time, the greater the pulse frequency; the resistance is one of R1, R2, or R3, the resistance value of R1 is less than the resistance value of R2, and the resistance value of R2 is less than the resistance value of R3.

[0072] Refer to Figure 1As shown, the dead zone generating circuit includes a logic NOT gate NOT2 and a time delay device TD2. The logic NOT gate NOT2 is connected to the first output terminal of the pulse generating circuit, and the time delay device TD2 is connected to the driving circuit DR2; the output terminal of the logic NOT gate NOT2 forms the output terminal of the pulse generating circuit.

[0073] See Figure 1 As shown, in this embodiment, within a certain period of time after the control signal flips until the feedback signal stabilizes, the time delay device TD2 shields the operation circuit of the feedback signal, avoiding the influence of spike noise.

[0074] In this embodiment, the resonant network is an LLC resonant network; in other embodiments, an LCC resonant network or a CLLC resonant network can be selected.

[0075] A method for controlling low output voltage ripple of a dual-output LLC resonant converter includes the following steps:

[0076] Step 1: The output voltage detection circuit detects the main output voltage V of the dual-output LLC resonant converter 01 , and sends it to the negative input terminal of the comparator CMP1. The preset voltage reference value V ref is sent to the positive input terminal of the comparator CMP1. The comparison result between V 01 and V ref is sent to the D terminal of the D flip-flop;

[0077] Step 2: The resonant capacitor current I is detected through the capacitor current detection circuit Cr , and the detected resonant capacitor current I Cr is sent to the positive input terminal of the comparator CMP2. The preset current reference value I ref is sent to the negative input terminal of the comparator CMP2;

[0078] Step 3: When the resonant capacitor current I Cr rises to the reference current I ref , the output result of the comparator CMP2 in the capacitor current acquisition circuit is 1. At this time, the logic selection circuit turns on the simple switch SS1 to connect the resistor R1 to the circuit, and the pulse generating circuit generates the highest frequency pulse P Hmax ;

[0079] Step 4: When the resonant capacitor current I Cr is less than the reference current I ref , the output result of the comparator CMP2 in the capacitor current acquisition circuit is 0. After receiving the output result of the comparator CMP2, the logic NOT gate NOT1 of the logic selection circuit outputs 1;

[0080] When the resonant capacitor current ICr less than the reference current I ref , and the output voltage V 01 is greater than the reference voltage V ref When, the output of comparator CMP1 is 0; after receiving the output 0 of comparator CMP1, the first output terminal of flip-flop D outputs 1. Logic AND gate AND1 receives the output 1 of logic NOT gate NOT1 and the output 1 of the first output terminal of flip-flop D. After logical operation, logic AND gate AND1 outputs 1; at this time, the logic selection circuit turns on the simple switch SS2 to connect the resistor R2 to the circuit, and the pulse generation circuit generates a high-frequency pulse P H ;

[0081] When the resonant capacitor current I Cr is less than the reference current I ref , and the output voltage V 01 is less than the reference voltage V ref When, the output of comparator CMP1 is 1; after receiving the output 1 of comparator CMP1, the second output terminal of flip-flop D outputs 1. Logic AND gate AND2 receives the output 1 of logic NOT gate NOT1 and the output 1 of the second output terminal of flip-flop D. After logical operation, logic AND gate AND2 outputs 1; at this time, the logic selection circuit turns on the simple switch SS3 to connect the resistor R3 to the circuit, and the pulse generation circuit generates a low-frequency pulse P L ;

[0082] Step 5: The power supply V DC1 generates different currents through the resistors R1, R2, and R3. These different currents pass through the current-controlled current source ICCCS1 to output a current. This output current passes through the switching transistor MOS1 and then charges the charge and discharge capacitor C OSC . The voltage across the charge and discharge capacitor C sen is collected through the voltage detection circuit V OSC . The voltage across the charge and discharge capacitor C OSC and the preset voltage reference value V DC2 are sent to the comparator CMP3 for comparison;

[0083] When the voltage across the charge and discharge capacitor C OSC is less than the preset voltage reference value V DC2 , the comparator CMP3 outputs 0, otherwise it outputs 1; the output of the comparator CMP3 is a square wave pulse with the same charge and discharge frequency as the charge and discharge capacitor C OSC . After passing through the time delay device TD1, this square wave pulse is converted into a clock pulse with the same frequency to control the conduction of the switching transistor MOS1, realizing the discharge of the charge and discharge capacitor C OSC ;

[0084] The voltage across the charge and discharge capacitor C OSC and the preset voltage reference value VDC3 is fed into comparator CMP4 for comparison. When the voltage across the charge-discharge capacitor C OSC is less than the preset voltage reference value V DC3 , comparator CMP4 outputs 0, otherwise it outputs 1, obtaining a square-wave pulse signal with a duty cycle of 0.5;

[0085] where V DC2 = 2V DC3 ;

[0086] Step 6: The square-wave pulse signal generated by the pulse generation circuit is connected to the drive circuit DR1 to control the conduction and cutoff of the switching MOS transistors Q1 and Q4; the square-wave pulse signal generated by the pulse generation circuit is fed into the input terminal of the logic NOT gate NOT2 of the dead-time generation circuit, and after passing through the time delay TD2, it is connected to the drive circuit DR2 to control the cutoff and conduction of the switching MOS transistors Q1 and Q4.

[0087] A method and device for controlling low output voltage ripple of a dual-output LLC resonant converter according to the present invention has the basic idea that: the low output voltage ripple control circuit of the dual-output LLC resonant converter includes an output voltage acquisition circuit, a capacitor current acquisition circuit, a logic selection circuit, a pulse generation circuit, and a dead-time generation circuit. The output voltage acquisition circuit compares the detected output voltage with the reference voltage, and the comparison result is used as the input of the logic selection circuit; the capacitor current acquisition circuit compares the detected capacitor current with the reference capacitor current, and the comparison result is used as the input of the logic selection circuit; the logic selection circuit realizes a three-way selection logic function through the input AND logic operation; the pulse generation circuit generates high and low pulses with three different frequencies, and the logic selection circuit selects the high and low pulses with three different frequencies. The selected frequency pulses pass through the dead-time generation circuit to control the conduction of the converter switching transistors. In addition, the selected frequency pulses are connected to the output voltage acquisition circuit to control the cutoff of the converter switching transistors. The low output voltage ripple control loop of the dual-output LLC resonant converter only has simple digital logic operations. Compared with the voltage-mode control and average current-mode control, the design of the compensation network of the control loop is reduced, so it has a fast transient response speed. And, the highest frequency pulse signal selected by the pulse generation circuit through the capacitor current acquisition circuit effectively reduces the low-frequency oscillation phenomenon of the output voltage of the converter and reduces the ripple of the output voltage of the converter.

[0088] The working principle of the invention will be further described below in conjunction with the accompanying drawings so that those skilled in the art can fully understand the present invention, specifically as follows:

[0089] As Figure 1As shown in the figure, a specific implementation of the present invention is as follows: A low output voltage ripple control method and device for a dual-output LLC resonant converter are composed of a dual-output LLC resonant converter and its control device. The control device consists of an output voltage acquisition circuit, a capacitor current acquisition circuit, a logic selection circuit, a pulse generation circuit, and a dead zone generation circuit. The output voltage acquisition circuit compares the main output voltage V 01 of the dual-output LLC resonant converter detected by the voltage sensor with the voltage reference value V ref , and the comparison result is used as the input of the logic selection circuit; the capacitor current acquisition circuit compares the resonant capacitor current I Cr detected by the current sensor with the current reference value I ref , and the comparison result is used as the input of the logic selection circuit; the logic selection circuit performs a logical AND operation on the two input signals to achieve the logic selection function; the output result of the logic selection circuit selects different frequency pulses generated by the pulse generation circuit, and the output pulse signal controls the on and off of the switching MOS tube of the switching converter through the dead zone generation circuit.

[0090] The TD converter of the present invention is a dual-output LLC resonant converter, and its working process and principle are as follows:

[0091] See Figure 1 As shown in the figure, the working process and principle of the control device using the low output voltage ripple control of the dual-output LLC resonant converter are as follows: From the relationship between the output voltage and the switching frequency of the LLC converter, it can be obtained that when the output voltage V 01 is greater than the reference voltage V ref , the high-frequency pulse P H is selected as the control pulse of the switching tube of the LLC converter to make the output voltage decrease; conversely, when the output voltage V 01 is less than the reference voltage V ref , the low-frequency pulse P L is selected as the control pulse of the switching tube of the LLC converter to make the output voltage increase. At the starting moment of any switching cycle, the output voltage acquisition circuit detects the main output voltage V 01 of the dual-output LLC resonant converter, and compares it with the voltage reference value V ref through the comparator CMP1. The comparison result passes through the D flip-flop; when the output voltage V 01 is greater than the reference voltage V ref , that is, the output of the comparator CMP1 is 0, the comparison result passes through the D flip-flop and performs a logical AND operation with the output result of the capacitor current acquisition circuit. At this time, the logic selection circuit selects the resistor R2 to be connected to the circuit to generate a larger current to charge and discharge the capacitor C osc ; since the frequency of the pulse signal is related to the resistor and the capacitor C oscis related to the size and the charging voltage across the capacitor. Therefore, capacitor C osc The larger the charging current of capacitor C is, the shorter the time to reach the voltage across the capacitor is. The shorter the time is, the higher the pulse frequency is. The pulse generating circuit generates a high-frequency pulse P H After passing through the dead-time generating circuit, two complementary-conducting square-wave signals are obtained. The driving circuit DR1 controls the conduction and cutoff of the converter switching MOS transistors Q1 and Q4. The driving circuit DR2 controls the conduction and cutoff of the converter switching MOS transistors Q2 and Q3. In addition, the square-wave frequency pulse generated by the pulse generating circuit is connected to the CP terminal of the D flip-flop, enabling the D flip-flop to be controlled by the clock level without constraint problems. Conversely, when the output voltage V 01 is less than the reference voltage V ref , that is, the output of the comparator CMP1 is 1. After passing through the D flip-flop, the comparison result is logically ANDed with the output result of the capacitor current acquisition circuit. At this time, the logic selection circuit selects the resistor R3 to be connected to the circuit, and the pulse generating circuit generates a low-frequency pulse P L After passing through the dead-time generating circuit, two complementary-conducting square-wave signals are obtained. The driving circuit DR1 controls the conduction and cutoff of the converter switching MOS transistors Q1 and Q4, and the driving circuit DR2 controls the conduction and cutoff of the converter switching MOS transistors Q2 and Q3, causing the output voltage to rise. When the resonant capacitor current I Cr rises to the reference current I ref , the output result of the capacitor current acquisition circuit is 1. At this time, the logic selection circuit causes the resistor R1 to be connected to the circuit, and the pulse generating circuit generates the highest-frequency pulse P Hmax , and the highest-frequency pulse P Hmax passes through the dead-time generating circuit to obtain two complementary-conducting square-wave signals. The driving circuit DR1 controls the conduction and cutoff of the converter switching MOS transistors Q1 and Q4, and the driving circuit DR2 controls the conduction and cutoff of the converter switching MOS transistors Q2 and Q3, causing the output voltage to decrease at a faster rate, thereby reducing the low-frequency oscillation phenomenon existing in the dual-frequency control and reducing the output voltage ripple.

[0092] Refer to Figure 3 As shown, at the starting moment of any switching cycle, the output voltage acquisition circuit detects the main output voltage V 01 of the dual-output LLC resonant converter and compares it with the voltage reference value V ref . Subsequently, through the logic selection circuit, the pulse generating circuit, and the dead-time generating circuit, control pulse signals of different frequencies are generated. When the output voltage is less than the reference voltage, the control loop selects the low-frequency pulse frequency P L to cause the output voltage to rise. When the output voltage is greater than the reference voltage, the control loop selects the high-frequency pulse frequency P H to cause the output voltage to decrease; the control pulse V fang generated by the pulse generating circuitThrough a dead-time generating circuit, a square-wave signal is converted into two complementary-conducting square-wave signals with a dead time of 300 ns to control the switching MOS transistors Q1, Q2, Q3, and Q4. Figure 3 Shown is the output voltage V 01 waveform, the resonant inductor current I r and the exciting inductor current I m waveform as well as the control pulse signal V fang waveform; during operation, the switching converter can achieve zero-voltage turn-on and zero-current turn-off of the secondary rectifier diode.

[0093] The time-domain simulation analysis of the method of the present invention is carried out using the PSIM simulation software, and the results are as follows:

[0094] Refer to Figure 4 Shown, the input voltage of the dual-output LLC resonant converter of the present invention changes from 360 V to 420 V at 0.05 s, and the output voltage V 01 reaches a new steady state after several switching cycles, having a very fast transient response speed.

[0095] Refer to Figure 5 Shown, the output current of the dual-output LLC resonant converter of the present invention changes from 4 A to 2 A at 0.05 s, the load is reduced by half, and the output voltage V 01 reaches a new steady state after several switching cycles, having a very fast transient response speed.

[0096] See Figure 6 and Figure 7 Shown, Figure 6 the output voltage ripple in Figure 7 is 65 mV, and the output voltage ripple in Figure 6 and Figure 7 is 35 mV. It can be seen that compared with the traditional dual-frequency control, the present invention reduces the output voltage ripple and has a fast transient response speed. in The simulation conditions of ref and ref are that the input voltage V r = 400 V, the voltage reference value V r = 48 V, the capacitor current reference value I m = 1 A, the resonant capacitor C

[0097] In the present invention, the converter TD can be any one of an LLC resonant converter, an LCC resonant converter, or a CLLC resonant converter.

[0098] ​​For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A low output voltage ripple control device for a dual-output LLC resonant converter, comprising a power supply, a power supply circuit TD, a feedback circuit, an output load R1 and an output load R2, characterized in that: The power supply circuit TD includes a full-bridge conversion circuit coupled to the power supply and having a drive circuit, a resonant network coupled to the full-bridge conversion circuit, an isolation transformer coupled to the resonant network, a first rectifier filter circuit and a second rectifier circuit coupled to the isolation transformer, a load output R1 coupled to the first rectifier filter circuit, and a load output R2 coupled to the second rectifier filter circuit; The drive circuit of the full-bridge conversion circuit includes a drive circuit DR1 and a drive circuit DR2; the full-bridge conversion circuit includes bridge-connected switching transistors Q1, Q2, Q3, and Q4; the drive circuit DR1 is connected to the gates of the switching transistors Q1 and Q4, and the drive circuit DR2 is connected to the gates of the switching transistors Q2 and Q3; A current acquisition point is provided on either side of the capacitor of the resonant cavity in the resonant network; a voltage acquisition point is provided on either side of the load output R1 of the first rectifier filter circuit; The feedback circuit includes an output voltage acquisition circuit, a capacitor current acquisition circuit, a logic selection circuit, a pulse generation circuit, and a dead zone generation circuit; The input end of the capacitor current acquisition circuit is connected to the current acquisition point; the input end of the output voltage acquisition circuit is connected to the voltage acquisition point; the first input end of the logic selection circuit is connected to the first output end of the capacitor current acquisition circuit, and the second input end of the logic selection circuit is connected to the output end of the output voltage acquisition circuit; The first input end of the pulse generation circuit is connected to the second output end of the capacitor current acquisition circuit, the second input end of the pulse generation circuit is connected to the first output end of the logic selection circuit, and the third input end of the pulse generation circuit is connected to the second output end of the logic selection circuit; The input end of the dead zone generation circuit is connected to the first output end of the pulse generation circuit; the drive circuit DR1 is connected to the first output end of the pulse generation circuit, and the drive circuit DR2 is connected to the output end of the dead zone generation circuit; The logic selection circuit includes a NOT gate NOT1 connected to the first output end of the capacitor current acquisition circuit, a D flip-flop connected to the output end of the output voltage acquisition circuit, an AND gate AND1, and an AND gate AND2; the input end of the AND gate AND1 is connected to the output end of the NOT gate NOT1 and the first output end of the D flip-flop, and the input end of the AND gate AND2 is connected to the output end of the NOT gate NOT1 and the second output end of the D flip-flop; the output end of the AND gate AND1 forms the first output end of the logic selection circuit; the output end of the AND gate AND2 forms the second output end of the logic selection circuit; The pulse generation circuit includes a DC voltage source VDC1, a selection circuit, a current-controlled current source ICCCS1, a switching transistor MOS1, a charge-discharge capacitor COSC, and a comparator CMP4 connected in sequence. The current-controlled current source ICCCS1 is connected to the source of the switching transistor MOS1, and the charge-discharge capacitor COSC is connected to the drain of the switching transistor MOS1; The charge-discharge capacitor COSC is connected to a voltage detection circuit Vsen, the voltage detection circuit Vsen is connected to a comparator CMP3, the comparator CMP3 is connected to a time delay unit TD1, and the time delay unit TD1 is connected to the gate of the switching transistor MOS1; the first output terminal and the second output terminal of the comparator CMP4 form the first output terminal and the second output terminal of the pulse generation circuit.

2. The low output voltage ripple control device for a dual-output LLC resonant converter according to claim 1, wherein: The output voltage acquisition circuit includes an output voltage detection circuit VS1 and a comparator CMP1. The output voltage detection circuit VS1 is connected to the voltage acquisition point. The negative input terminal of the comparator CMP1 is connected to the output terminal of the output voltage detection circuit VS1, and the output terminal of the comparator CMP1 forms the output terminal of the output voltage acquisition circuit. The capacitor current acquisition circuit includes a capacitor current detection circuit IS1 and a comparator CMP2. The capacitor current detection circuit IS1 is connected to the current acquisition point. The positive input terminal of the comparator CMP2 is connected to the output terminal of the capacitor current detection circuit IS1, and the first output terminal and the second output terminal of the comparator CMP2 respectively form the first output terminal and the second output terminal of the capacitor current acquisition circuit.

3. The low output voltage ripple control device for a dual-output LLC resonant converter according to claim 1, characterized in that: The selection circuit is composed of a first selection circuit, a second selection circuit, and a third selection circuit connected in parallel; the first selection circuit, the second selection circuit, and the third selection circuit are each composed of a simple switch and a resistor; the resistances of the resistor in the first selection circuit, the resistor in the second selection circuit, and the resistor in the third selection circuit are different. The simple switch SS1 of the first selection circuit is connected to the second output terminal of the capacitor current acquisition circuit; the simple switch SS2 of the second selection circuit is connected to the first output terminal of the logic selection circuit; the simple switch SS3 of the third selection circuit is connected to the second output terminal of the logic selection circuit.

4. A low output voltage ripple control device for a dual-output LLC resonant converter according to claim 1, characterized in that: The dead zone generation circuit includes a logic NOT gate NOT2 and a time delay unit TD2. The logic NOT gate NOT2 is connected to the first output terminal of the pulse generation circuit, and the time delay unit TD2 is connected to the drive circuit DR2; the output terminal of the logic NOT gate NOT2 forms the output terminal of the pulse generation circuit.

5. The low output voltage ripple control device for a dual-output LLC resonant converter according to claim 1, wherein: The resonant network is one of an LLC resonant network, an LCC resonant network, or a CLLC resonant network.

6. A control method for low output voltage ripple of a dual-output LLC resonant converter, characterized in that: It is realized by the low output voltage ripple control device of a dual-output LLC resonant converter according to any one of claims 1-5, and includes the following steps: Step 1: The output voltage detection circuit detects the main output voltage V of the dual-output LLC resonant converter 01 , and sends it to the negative input terminal of the comparator CMP1. The preset voltage reference value V ref is sent to the positive input terminal of the comparator CMP1. The comparison result between V 01 and V ref is sent to the D terminal of the D flip-flop; Step 2: Detect the resonant capacitor current I through the capacitor current detection circuit Cr , and send the detected resonant capacitor current I Cr to the positive input terminal of the comparator CMP2, and send the preset current reference value I ref to the negative input terminal of the comparator CMP2; Step 3: When the resonant capacitor current I Cr rises to the reference current I ref , the output result of the comparator CMP2 in the capacitor current acquisition circuit is 1. At this time, the logic selection circuit turns on the simple switch SS1 to connect the resistor R1 to the circuit, and the pulse generation circuit generates the highest frequency pulse P Hmax ; Step 4: When the resonant capacitor current I Cr is less than the reference current I ref , the output result of the comparator CMP2 in the capacitor current acquisition circuit is 0. After receiving the output result of the comparator CMP2, the logic NOT gate NOT1 of the logic selection circuit outputs 1; When the resonant capacitor current I Cr is less than the reference current I ref , and the output voltage V 01 is greater than the reference voltage V ref , the output of the comparator CMP1 is 0; after the flip-flop D receives the output 0 of the comparator CMP1, the first output terminal of the flip-flop D outputs 1. The logic AND gate AND1 receives the output 1 of the logic NOT gate NOT1 and the output 1 of the first output terminal of the flip-flop D. After logical operation, the logic AND gate AND1 outputs 1; at this time, the logic selection circuit turns on the simple switch SS2 to connect the resistor R2 to the circuit, and the pulse generation circuit generates a high-frequency pulse P H ; When the resonant capacitor current I Cr is less than the reference current I ref , and the output voltage V 01 is less than the reference voltage V ref , the output of the comparator CMP1 is 1; after the flip-flop D receives the output 1 of the comparator CMP1, the second output terminal of the flip-flop D outputs 1. The logic AND gate AND2 receives the output 1 of the logic NOT gate NOT1 and the output 1 of the second output terminal of the flip-flop D. After logical operation, the logic AND gate AND2 outputs 1; at this time, the logic selection circuit turns on the simple switch SS3 to connect the resistor R3 to the circuit, and the pulse generation circuit generates a low-frequency pulse P L ; Step 5: Power supply V DC1 Generate different currents through resistors R1, R2, and R3. The different currents pass through the current-controlled current source ICCCS1 to output a current, and the output current charges the charge and discharge capacitor C after passing through the switching transistor MOS1. OSC Charge, and collect the voltage across the charge and discharge capacitor C through the voltage detection circuit V sen Obtain the voltage across the charge and discharge capacitor C OSC Send the voltage across the charge and discharge capacitor C OSC And the preset voltage reference value V DC2 To the comparator CMP3 for comparison; When the voltage across the charge and discharge capacitor C OSC is less than the preset voltage reference value V DC2 , the comparator CMP3 outputs 0, otherwise it outputs 1; the output of the comparator CMP3 is a square wave pulse with the same charge and discharge frequency as that of the charge and discharge capacitor C OSC . After passing through the time delay TD1, this square wave pulse is converted into a clock pulse with the same frequency to control the conduction of the switching transistor MOS1, realizing the discharge of the charge and discharge capacitor C OSC . Send the voltage across the charge and discharge capacitor C OSC and a preset voltage reference value V DC3 to a comparator CMP4 for comparison. When the voltage across the charge and discharge capacitor C OSC is less than the preset voltage reference value V DC3 , the comparator CMP4 outputs 0, otherwise it outputs 1, obtaining a square wave pulse signal with a duty cycle of 0.5; Where V DC2 = 2V DC3 ; Step 6: The square wave pulse signal generated by the pulse generation circuit is connected to the drive circuit DR1 to control the conduction and cutoff of the switching MOS transistors Q1 and Q4; the square wave pulse signal generated by the pulse generation circuit is sent to the input terminal of the logic NOT gate NOT2 of the dead zone generation circuit, and after passing through the time delay unit TD2, it is connected to the drive circuit DR2 to control the cutoff and conduction of the switching MOS transistors Q1 and Q4.

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