Low-power power-on reset output driver

Abstract

The present invention relates to a low-power power-on reset output driver. Embodiments of the present disclosure provide an input-output (IO) structure in which complementary nodes of a level shifter are used to logically prevent the output of the IO structure from switching until both power supplies of the IO structure are powered. An exemplary level shifter includes: a pair of cross-coupled PFETs configured to output complementary voltage values ​​at a first node and a second node; a control circuit configured to select which of the complementary voltage values ​​are output to the first node and the second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and the third node and generating a level-shifted output.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to electronic circuits. More specifically, various embodiments of the present disclosure provide circuit structures for general purpose input and output (GPIO) output drivers with multiple voltage domains that can be powered up in any order. Background Art

[0002] General-purpose input / output (GPIO) generally refers to circuits and signal pins (or pads) on an integrated circuit (IC) that can function as either inputs or outputs. GPIO typically has two voltage domains that require two power supplies: a core voltage domain, such as 0.8 volts (V), for driving core transistors; and a higher output voltage domain, such as 1.8 V, for driving input / output (IO) transistors. During runtime, control circuitry determines which domain to use and interfaces with voltage level shifters to achieve the conversion from the low-voltage domain to the high-voltage domain, and with voltage level shifters to achieve the conversion from the high-voltage domain to the low-voltage domain.

[0003] During a system reset, the core voltage supply must typically be powered up first, followed by the high-voltage supply to avoid situations where, for example, the level-up shifter outputs power up in the wrong state and inadvertently turn on the main driver. To overcome this issue and allow the high-voltage supply to be turned on first, additional circuitry, such as a power-on-control (POC) mechanism, can be used to maintain the level-shifter outputs in a preferred, known state. However, this approach requires additional control inputs and additional power-on detection circuitry within the IC, which increases complexity, cost, and the potential for leakage current. Summary of the Invention

[0004] In some aspects of the present disclosure, a level-up shifter is provided, which is configured to shift an output node from a low voltage value VDD_L to a high voltage value VDD_H, the level-up shifter comprising: a first input for receiving VDD_H and a second input for receiving VDD_L; a cross-coupled pair of PFETs, which are configured to output complementary voltage values ​​at a first node and a second node, wherein the complementary voltage values ​​include ground and VDD_H; a control circuit, which is coupled to the cross-coupled pair of PFETs and is configured to select which of the complementary voltage values ​​are output to the first node and the second node; and protection logic, wherein the protection logic is configured to prevent the output node from switching states during a power-up phase in response to a detectable voltage at both the first node and the second node.

[0005] Other aspects of the present disclosure provide a general purpose input output (GPIO) comprising: a pad; and an output driver having at least one level up-shifter for shifting a voltage at the pad from a low voltage value VDD_L to a high voltage value VDD_H, wherein the level up-shifter comprises: a first input for receiving VDD_H and a second input for receiving VDD_L; a cross-coupled pair of PFETs configured to output complementary voltage values ​​at a first node and a second node, wherein the complementary voltage values ​​include ground and VDD_H; a control circuit coupled to the cross-coupled pair of PFETs and configured to select which of the complementary voltage values ​​are output to the first node and the second node; and protection logic, wherein the protection logic is configured to prevent the output node from switching states during a power-up phase in response to detectable voltages at both the first node and the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other features of the present disclosure will be more readily understood through a detailed description of various aspects of the present disclosure taken in conjunction with the accompanying drawings, which illustrate various embodiments of the present disclosure, in which:

[0007] Figure 1 A block diagram of a GPIO according to an embodiment of the present disclosure is provided.

[0008] Figure 2 A schematic diagram of an exemplary pull-down output driver with a level up-shifter is shown.

[0009] Figure 3 A schematic diagram of an exemplary pull-up output driver with a level up shifter is shown.

[0010] Figure 4 A schematic diagram of an improved pull-down output driver with a level up-shifter according to an embodiment of the present disclosure is shown.

[0011] Figure 5 A schematic diagram of an improved pull-up output driver with a level up-shifter according to an embodiment of the present disclosure is shown.

[0012] Figure 6 A schematic diagram of an alternative level up-shifter is shown.

[0013] Figure 7 A schematic diagram illustrating an improved alternative level up-shifter according to an embodiment of the present disclosure is shown.

[0014] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0015] In the description herein, reference is made to the accompanying drawings which form a part of the specification and which illustrate specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made within the scope of the present teachings. Therefore, the description herein is illustrative only.

[0016] Embodiments of the present disclosure provide circuits and related methods for a general-purpose input / output (GPIO) having a low voltage domain and a high voltage domain, wherein any power-up sequence can be used for the two voltage domains. The examples provided herein are described using voltage domains of 0.8 volts (V) and 1.8 V, however it should be understood that other voltage levels can be used. The GPIO described herein includes a level shifter with built-in protection logic that ensures that the main driver operates properly during power-up, regardless of which power supply is turned on first. The described level shifter does not require additional control inputs or power-up detection circuitry in the core or input / output (IO) ring area. Instead, an internal power-up voltage detector within the level shifter (referred to herein as "protection logic") pulls the level shifter to a known preferred state, thereby tri-stating the GPIO during power-up. In one illustrative embodiment, the complementary node of the level shifter is used as an input to the protection logic to logically prevent the level-shifted output from switching until both power supplies of the IO structure are powered on.

[0017] refer to Figure 1 , a simplified block diagram of an illustrative GPIO 10 is shown. The GPIO 10 can be embodied as any type of electronic circuit and, in various embodiments, can be provided in the form of, or included as part of, an integrated circuit (IC) structure. The GPIO 10 typically includes control circuitry 14, an output driver 12, and a pad 18. The GPIO 10 typically includes other components 16, such as input drivers, electrostatic discharge elements, data lines, control lines, etc., which have been omitted for brevity. In this illustrative embodiment, the output driver 12 is used to drive the pad 18 to a high voltage domain (e.g., 1.8V) using level up shifters 22, 28.

[0018] In this embodiment, two output paths are implemented, one for the PMOS pull-up 34 and the other for the NMOS pull-down 36. These two separate paths allow for better timing control and provide the ability to shut down the pull-up path 34 during open-drain operation. However, it should be understood that the GPIO 10 can be implemented with a single path. When data is being output from the core to the pad 18 during normal operation, the control logic 20 controls each path. In addition to the control logic 20, each path 34, 36 also includes a pre-driver 24, 30 and a main driver 26, 32, respectively. To perform level shifting, each level shifter 22, 28 includes power supplies from two voltage domains. As described above, in existing designs, if the higher voltage power supply is turned on before the lower voltage power supply, the level shifter may inadvertently cause the main driver 26, 32 to be driven to an undesirable state during power-up. The present method overcomes this problem through an improved level shifter design.

[0019] Figure 2 A configuration for the pull-down path 36 ( Figure 1 ) circuit design of a conventional level up-shifter 60. In the example shown, the main driver 32 includes an NFET driver N4, while in the pull-up path 34, the main driver 26 will include a PFET (see Figure 3 ). The level up-shifter 60 is coupled to both the high voltage domain power supply VDD_H (e.g., 1.8V) and the low voltage domain power supply VDD_L (e.g., 0.8V). The level up-shifter 60 generally includes a set of cross-coupled PFETs 60 (P0 and P2) that produce complementary outputs (e.g., 0V and 1.8V) at nodes A and AB, and a control circuit 62 coupled to VDD_L that determines, based on the level shifter input (LSI), whether nodes A and AB should output 0V and 1.8V, or 1.8V and 0V, respectively.

[0020] The control circuit includes a CMOS inverter (P4 and N3) powered by VDD_L, as well as NFETs N0 and N1. N0 connects node AB to ground and is gated by the LSI. N1 connects node A to ground and is gated by the output of the CMOS inverter. The additional PFETs P1 and P3 are included to improve the circuit's operating performance but can be omitted. During normal operation, when the LSI is low (e.g., 0V), N0 is off and N1 is on, so node A is 0V and node AB is 1.8V. The signal at node AB is then inverted to 0 by inverter 50 and output to pre-driver 30, which performs the inversion and outputs a 1.8V signal to main driver 32. When the LSI is high (e.g., 0.8V), N0 is on, node AB is pulled to 0V, and node A goes to 1.8V. This results in the output signal to main driver 32 being 0.

[0021] As described above, conventional implementations of level shifter 60 may exhibit undesirable behavior during power-up. When VDD_H is first turned on at power-up, VDD_H rises from 0V to 1.8V, while VDD_L remains at 0V. With both N0 and N1 turned off, nodes A and AB begin to pull up to a detectable voltage of approximately VDD_H – Vtp (where Vtp is the threshold voltage of P0 or P1). This causes inverter 50 to output 0V at node C. This turns on the output of pre-driver 30 and turns on main driver NFET N4, which can result in undesirable leakage current from pad 18 to ground (GRD), for example.

[0022] Figure 3 The pull-up path 34 ( Figure 1 ). In this case, the main driver 26 includes a PFET (P5) coupled to VDD_H.

[0023] Figure 4 An illustrative embodiment of an improved level up-shifter 28 is shown, wherein the inverter 50 ( Figure 2 and 3 ) is replaced with protection logic to prevent the aforementioned issues, in this case, inverter 51 and NAND gate 52. In this embodiment, NAND gate 52 receives a first input from node AB and a second input from inverter 51 (i.e., the inverted signal at node A). During normal operation, the circuit behaves identically to the prior art circuit. For example, when AB is 1.8V and A is 0V, node D is 1.8V and output O is 0V. Conversely, when AB is 0V and A is 1.8V, node D is 0V and output O is 1.8V.

[0024] During power-up operation, when VDD_H rises from 0V to 1.8V while VDD_L remains at 0V, both transistors N0 and N1 are turned off. This causes nodes A and AB to pull up to a detectable voltage of approximately VDDO-Vtp. However, in this case, node A, at a logic high, switches node D low, which in turn pulls the level-shifted output O of NAND gate 52 high. In response to the logic high input, inverter 54 in pre-driver 30 outputs a logic low. This result turns off main driver NFET N4 and maintains the output driver in tri-state mode.

[0025] Figure 5 shows a circuit with a pull-up path 34 ( Figure 1 ) is a similar circuit to the improved level up-shifter 22 of FIG. In this case, the pre-driver 24 includes a buffer 55, and the main driver 26 includes a PFET (P5) coupled to VDD_H.

[0026] Figure 6 An alternative to the conventional level up-shifter 70 is shown. In this circuit, instead of using an inverter (e.g. Figure 2 Instead of the inverter 50 in FIG, a NOR gate 72 is used to generate the level shifted output 0. This configuration reduces the logic transitions from low to high and from high to low to only two inversions, rather than the two inversions in the previous prior art level shifter 60 ( Figure 2 and 3 ) are used in the four inversions. However, the power-up issues are the same as in the previous embodiment. When VDD_H is first applied, both nodes AB and A float to logic high. Because VDD_L is low, node D is at logic low. P6 is off and P7 is on, N2 is off and N3 is on, pulling the level-shifted output O to logic low (i.e., ground).

[0027] Figure 7 Shown for Figure 6 8. A circuit diagram of an improved level up-shifter 80 is shown. In this case, protection logic is added, including a second CMOS inverter 82 and a NAND function 84 (instead of a full NAND gate). Inverter 82 is powered by VDD_H and gated by node A. NAND function 84 includes an additional PFET P8 that connects VDD_H to the level-shifted output O and is gated by inverter 82. Function 84 also includes an additional NFET N4 that connects the NOR gate to ground via NFET N3 and is also gated by the output of inverter 82.

[0028] At power-up, when both AB and A float to logic high and D is at logic low, P6 is off, P7 is on, N2 is off, and N3 is on. However, N4 is now off and P8 is on because node C is low after the inverter, pulling output O to logic high. This ensures that the NFET driver (not shown) is off during power-up.

[0029] In this improved level up-shifter design, during power up and power down operations (regardless of the order), the level shifted output will follow VDD_H to turn off the main driver.

[0030] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive and / or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art within the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, and / or technical improvements over technologies found in the marketplace, and / or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A general purpose input and output (GPIO), comprising: liner; as well as an output driver having at least one level up-shifter for shifting the voltage at said pad at an output node from a low voltage value VDD_L to a high voltage value VDD_H, wherein said level up-shifter comprises: a first input for receiving VDD_H and a second input for receiving VDD_L; a cross-coupled pair of PFETs configured to output complementary voltage values ​​at a first node and a second node, wherein the complementary voltage values ​​include ground and VDD_H; a control circuit coupled to the cross-coupled pair of PFETs and configured to select which of the complementary voltage values ​​are output to the first node and the second node; and protection logic, wherein the protection logic is configured to prevent the output node from switching states during a power-up phase in response to detectable voltages at both the first node and the second node, wherein the protection logic comprises: a logic inverter having an input coupled to the first node and an output coupled to a third node; and A NAND gate generates a level-shifted output in response to inputs including the second node and the third node.

2. The GPIO of claim 1 , wherein the output driver further comprises a pre-driver and a main driver, wherein the main driver comprises one of an NFET driver or a PFET driver. 3 . The GPIO according to claim 2 , wherein the output driver comprises a first level-up shifter for controlling a PMOS pull-up and a second level shifter for controlling an NMOS pull-down.

4. The GPIO of claim 1 , wherein the control circuit comprises a CMOS inverter powered by VDD_L and having an output coupled to a gate of an NFET connecting the first node to ground.

5. A general purpose input and output (GPIO), comprising: liner; as well as an output driver having at least one level up-shifter for shifting the voltage at said pad at an output node from a low voltage value VDD_L to a high voltage value VDD_H, wherein said level up-shifter comprises: a first input for receiving VDD_H and a second input for receiving VDD_L; a cross-coupled pair of PFETs configured to output complementary voltage values ​​at a first node and a second node, wherein the complementary voltage values ​​include ground and VDD_H; a control circuit coupled to the cross-coupled pair of PFETs and configured to select which of the complementary voltage values ​​are output to the first node and the second node, wherein the control circuit comprises a first CMOS inverter powered by VDD_L and having an output coupled to a gate of an NFET connecting the first node to ground; and protection logic, wherein the protection logic is configured to prevent the output node from switching states during a power-up phase in response to detectable voltages at both the first node and the second node, wherein at least one level up-shifter further comprises a NOR gate that produces a level-shifted output, wherein inputs of the NOR gate are coupled to the output of the first CMOS inverter and the second node, The protection logic includes: a second CMOS inverter powered by VDD_H and having an input coupled to the first node; and and non-functional elements, which include: an additional PFET connecting VDD_H to the level shift output and having a gate coupled to the output of the second CMOS inverter; and An additional NFET connects the NOR gate to ground and has a gate coupled to the output of the second CMOS inverter. 6 . The GPIO of claim 5 , wherein the output driver further comprises a pre-driver and a main driver, wherein the main driver comprises one of an NFET driver or a PFET driver. 7 . The GPIO according to claim 6 , wherein the output driver comprises a first level-up shifter for controlling a PMOS pull-up and a second level shifter for controlling an NMOS pull-down.

8. A level up-shifter configured to shift an output node from a low voltage value VDD_L to a high voltage value VDD_H, the level up-shifter comprising: a first input for receiving VDD_H and a second input for receiving VDD_L; a cross-coupled pair of PFETs configured to output complementary voltage values ​​at a first node and a second node, wherein the complementary voltage values ​​include ground and VDD_H; a control circuit coupled to the cross-coupled pair of PFETs and configured to select which of the complementary voltage values ​​are output to the first node and the second node; as well as protection logic, wherein the protection logic is configured to prevent the output node from switching states during a power-up phase in response to detectable voltages at both the first node and the second node, wherein the protection logic comprises: a logic inverter having an input coupled to the first node and an output coupled to a third node; as well as A NAND gate generates a level-shifted output in response to inputs including the second node and the third node.

9. The level up-shifter of claim 8, wherein the power-up phase comprises powering VDD_H before VDD_L. 10 . The level up-shifter of claim 8 , wherein the cross-coupled pairs of PFETs are respectively coupled to VDD_H.

11. The level up-shifter of claim 8, wherein the control circuit comprises a CMOS inverter powered by VDD_L and having an output coupled to a gate of an NFET connecting the first node to ground.

12. The level up-shifter of claim 8, wherein the control circuit receives a level shift input LSI coupled to an input of a CMOS inverter and to a gate of a second NFET connecting the second node to ground.

13. The level up-shifter of claim 12, wherein each of the cross-coupled pairs of PFETs is coupled to an additional PFET.

14. The level up-shifter of claim 13, wherein the LSI is further coupled to a gate of a first PFET among the additional PFETs.

15. The level up-shifter of claim 14, wherein the output of the CMOS inverter is further coupled to a gate of a second one of the additional PFETs.

16. The level up-shifter of claim 8, wherein VDD_L is 0.8 volts and VDD_H is 1.8 volts. The level up-shifter of claim 8 , wherein the level-shifted output is ground or VDD_H.

18. A level up-shifter configured to shift an output node from a low voltage value VDD_L to a high voltage value VDD_H, the level up-shifter comprising: a first input for receiving VDD_H and a second input for receiving VDD_L; a cross-coupled pair of PFETs configured to output complementary voltage values ​​at a first node and a second node, wherein the complementary voltage values ​​include ground and VDD_H; a control circuit coupled to the cross-coupled pair of PFETs and configured to select which of the complementary voltage values ​​are output to the first node and the second node, wherein the control circuit comprises a first CMOS inverter powered by VDD_L and having an output coupled to a gate of an NFET connecting the first node to ground; a NOR gate generating a level-shifted output, wherein an input of the NOR gate is coupled to the output of the first CMOS inverter and the second node; as well as protection logic, wherein the protection logic is configured to prevent the output node from switching states during a power-up phase in response to detectable voltages at both the first node and the second node; The protection logic includes: a second CMOS inverter powered by VDD_H and having an input coupled to the first node; and and non-functional elements, which include: an additional PFET connecting VDD_H to the level shift output and having a gate coupled to the output of the second CMOS inverter; and An additional NFET connects the NOR gate to ground and has a gate coupled to the output of the second CMOS inverter. The level up-shifter of claim 18 , wherein the power-up phase comprises powering VDD_H before VDD_L.

20. The level up-shifter of claim 18, wherein the cross-coupled pairs of PFETs are respectively coupled to VDD_H.

21. The level up-shifter of claim 18, wherein the control circuit receives a level shift input LSI coupled to an input of the first CMOS inverter and to a gate of a second NFET connecting the second node to ground.

22. The level up-shifter of claim 21, wherein each of the cross-coupled pairs of PFETs is coupled to an additional PFET.

23. The level up-shifter of claim 21, wherein the LSI is further coupled to a gate of a first one of the additional PFETs.

24. The level up-shifter of claim 23, wherein the output of the first CMOS inverter is further coupled to a gate of a second one of the additional PFETs.

25. The level up-shifter of claim 18, wherein VDD_L is 0.8 volts and VDD_H is 1.8 volts.

26. The level up-shifter of claim 18, wherein the level-shifted output is ground or VDD_H.

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