Stacked chip and method for detecting a stacked chip

Abstract

The application provides a stacked chip and a testing method of the stacked chip, the stacked chip comprising: at least two to-be-tested wafers, the at least two to-be-tested wafers comprising: a first to-be-tested wafer and a second to-be-tested wafer; the first to-be-tested wafer and the second to-be-tested wafer are arranged in layers and are interconnected through a connecting layer; a wiring layer, the wiring layer being located on a side of the first to-be-tested wafer away from the second to-be-tested wafer, the wiring layer comprising a conductive pad, the first to-be-tested wafer being connected to the conductive pad, and the second to-be-tested wafer being connected to the conductive pad through the connecting layer; and a comparison unit, the comparison unit being located on one of the at least two to-be-tested wafers, and being used for comparing first data written into the first to-be-tested wafer with second data written into the second to-be-tested wafer to determine whether the connecting layer is reliable; wherein the second data is written into the second to-be-tested wafer through the connecting layer. The application can detect whether the connecting layer between chips is reliable, and is not affected by the number of pads.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a stacked chip and a detection method for the stacked chip. Background Art

[0002] In the existing technology, after the chips are stacked and packaged, the function of the chips is closely related to the connection reliability between the chips. When there are many pins connecting the chips, it is difficult to test a large number of pads between the chips due to test conditions and cost limitations. Therefore, how to test the connection reliability between chips is still an urgent problem that needs to be solved. Summary of the Invention

[0003] The present invention provides a stacked chip and a testing method thereof, which can detect whether the connection layer between chips is reliable and is not affected by the number of pads.

[0004] To solve the above technical problems, the first technical solution provided by the present invention is: to provide a stacked chip, comprising: at least two wafers to be tested, the at least two wafers to be tested comprising: a first wafer to be tested and a second wafer to be tested; the first wafer to be tested and the second wafer to be tested are stacked and interconnected through a connecting layer; a wiring layer, the wiring layer is located on the side of the first wafer to be tested away from the second wafer to be tested, the wiring layer includes a conductive pad, the first wafer to be tested is connected to the conductive pad, and the second wafer to be tested is connected to the conductive pad through the connecting layer; a comparison unit, the comparison unit is located on one of the at least two wafers to be tested, and is used to compare the first data written into the first wafer to be tested with the second data written into the second wafer to be tested, so as to determine whether the connecting layer is reliable; wherein, the second data is written into the second wafer to be tested through the connecting layer.

[0005] Among them, the connection layer includes multiple connection keys; the second wafer to be tested is connected to the conductive pad through the connection keys; the second data is written through the connection keys, and the comparison unit compares the first data with the second data to determine whether each of the connection keys is reliable.

[0006] Among them, the first wafer to be tested includes multiple first units to be tested; the second wafer to be tested includes multiple second units to be tested; each second unit to be tested and each first unit to be tested are connected through one of the multiple connection keys; the first data is stored in each first unit to be tested and is also stored in the comparison unit; the second data is stored in each second unit to be tested, and the second data is the first data read from each first unit to be tested and written into each second unit to be tested through the corresponding connection key; the comparison unit obtains the second data stored in each second unit to be tested, and compares the second data stored in each second unit to be tested with the first data stored in each first unit to be tested, so as to determine whether the connection key corresponding to each first unit to be tested and each second unit to be tested is reliable.

[0007] Among them, the conductive pads include multiple first conductive pads and multiple second conductive pads; each of the first conductive pads is correspondingly connected to at least one of the first units to be tested, and each of the second conductive pads is correspondingly connected to at least one of the second units to be tested through one of the connecting keys, and the first conductive pads and the second conductive pads are interconnected.

[0008] Wherein, each of the first unit under test and / or the second unit under test includes at least one storage bit.

[0009] Among them, the stacked chip also includes: a data generating unit, which is arranged on one of the at least two wafers to be tested, or is arranged on each of the wafers to be tested, and is connected to the comparison unit; the data generating unit arranged on the first wafer to be tested generates first data, and writes the first data into the first wafer to be tested and the comparison unit; and the data generating unit arranged on the second wafer to be tested reads the second data from the second wafer to be tested, and writes it into the comparison unit.

[0010] Wherein, the comparison unit includes: an XOR gate, including a first input terminal, a second input terminal and an output terminal, the first input terminal of the XOR gate is connected to the data generating unit on the first wafer to be tested to receive the first data; the second input terminal of the XOR gate is connected to the data generating unit on the second wafer to be tested to obtain the second data; an OR gate, including a first input terminal, a second input terminal and an output terminal, the first input terminal of the OR gate is connected to the output terminal of the XOR gate; a register, including a first input terminal, a second input terminal and an output terminal, the first input terminal of the register is connected to the output terminal of the OR gate, the second input terminal of the register receives a data read signal, the output terminal of the register is connected to the second input terminal of the OR gate, and the output terminal of the register outputs a comparison result; the data read signal is generated after reading the second data, and the comparison result represents the position of the unreliable connection key.

[0011] The wafer to be tested is one or a combination of a memory wafer and a logic wafer.

[0012] To solve the above technical problems, the second technical solution provided by the present invention is: to provide a method for detecting a stacked chip, the method is based on the stacked chip described in any one of the above items, and the method includes: writing first data into a first wafer to be tested; writing the first data into a second wafer to be tested through a connection layer, so that the second data is stored in the second wafer to be tested; comparing the first data with the second data to determine whether the connection layer is reliable.

[0013] Among them, the step of writing the first data into the second wafer to be tested through the connection layer so that the second data is stored in the second wafer to be tested includes: reading the first data from the first wafer to be tested, and writing the first data into the second wafer to be tested through the connection layer so that the second data is stored in the second wafer to be tested.

[0014] Among them, the step of reading the first data from the first wafer to be tested and writing the first data into the second wafer to be tested through the connection layer so that the second data is stored in the second wafer to be tested includes: reading the first data from each of the first units to be tested in the first wafer to be tested, and writing the first data into the corresponding second units to be tested in the second wafer to be tested through the connection key connected to the first unit to be tested, so that each unit to be tested stores the second data.

[0015] The step of comparing the first data with the second data to determine whether the connection layer is reliable comprises: comparing the first data of each of the to-be-tested units with the second data of the second to-be-tested unit corresponding to the connection to determine whether the connection key between the first to-be-tested unit and the second to-be-tested unit is reliable; and in response to the first data and the second data not matching, outputting a comparison result, the comparison result representing the position of the unreliable connection key.

[0016] The stack chip of the present application is connected to the first to-be-tested unit and the second to-be-tested unit one by one through the pads on the wiring layer, so as to read out the first data stored in the first to-be-tested unit and write the first data into the second to-be-tested unit through the corresponding connection key, so that the second data is stored in the second to-be-tested unit. The comparison unit compares the first data with the second data, and then determines whether the corresponding connection key is reliable. The method of the present application can not be limited by the number of pins, and can well test a large number of pads between chips. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0018] Figure 1 The structure schematic diagram of an embodiment of the stack chip of the present application is shown in the figure.

[0019] Figure 2 The specific structure schematic diagram of an embodiment of the stack chip shown in the figure is shown in the figure. Figure 1

[0020] Figure 3 The specific structure schematic diagram of another embodiment of the stack chip shown in the figure is shown in the figure. Figure 1

[0021] The structure schematic diagram of an embodiment of the comparison unit is shown in the figure. Figure 4

[0022] The flowchart of an embodiment of the test method of the stack chip is shown in the figure. Figure 5 DETAILED DESCRIPTION

[0023] ​​With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0024] Please refer to Figure 1 , Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of the stacked chip of the present application, which specifically comprises: at least two to-be-tested wafers, in an embodiment, the at least two to-be-tested wafers comprise a first to-be-tested wafer 101 and a second to-be-tested wafer 102, and the first to-be-tested wafer 101 and the second to-be-tested wafer 102 are stacked.

[0025] The stacked chip further comprises a wiring layer 104, which is located on a side of the first to-be-tested wafer 101 away from the second to-be-tested wafer 102, and the wiring layer 104 comprises a conductive pad 107, the first to-be-tested wafer 101 is connected to the conductive pad 107, and the second to-be-tested wafer 102 is connected to the conductive pad 107 through the connecting layer 103.

[0026] The stacked chip further comprises a comparison unit 105, which is located on one of the at least two to-be-tested wafers, in the embodiment, the comparison unit 105 is located on the second to-be-tested wafer 102. The comparison unit 105 is used to compare first data written into the first to-be-tested wafer 101 with second data written into the second to-be-tested wafer 102, so as to determine whether the connecting layer 103 is reliable; wherein the second data is written into the second to-be-tested wafer through the connecting layer 103.

[0027] The stacked chip of the embodiment compares the first data written into the first to-be-tested wafer 101 with the second data written into the second to-be-tested wafer 102 through the comparison unit arranged in the to-be-tested wafer, and then determines whether the connecting layer 103 connecting the first to-be-tested wafer 101 and the second to-be-tested wafer 102 is reliable.

[0028] Please refer to Figure 2 , Figure 2 is Figure 1The schematic diagram of the specific structure of an embodiment of a stacked chip is shown. In this embodiment, the connection layer 103 includes multiple connection keys (such as 1 to 9 in the figure); the second wafer to be tested 102 is connected to the conductive pad 107 via the connection keys (such as 1 to 9 in the figure). The second data is written via the connection keys (such as 1 to 9 in the figure), and the comparison unit 105 compares the first data with the second data to determine whether each connection key (such as 1 to 9 in the figure) is reliable.

[0029] In one embodiment, the first wafer under test 101 includes a plurality of first units under test (such as A1 to A9 in the figure); the second wafer under test 102 includes a plurality of second units under test (such as B1 to B9 in the figure); each of the second units under test and each of the first units under test are connected via one of the plurality of connection keys. For example, the first unit under test A1 and the second unit under test B1 are connected via connection key 1, the first unit under test A2 and the second unit under test B2 are connected via connection key 2, the first unit under test A3 and the second unit under test B3 are connected via connection key 3, ..., the first unit under test A9 and the second unit under test B9 are connected via connection key 9.

[0030] First data is stored in each first unit under test and simultaneously stored in the comparison unit 105. Second data is stored in each second unit under test. The second data is the first data read from each first unit under test and written into each second unit under test via the corresponding connection key. For example, the first data read from the first unit under test A1 is then written to the second unit under test B1 via connection key 1, thereby causing the second data to be stored in the second unit under test B1. For another example, the first data read from the first unit under test A2 is then written to the second unit under test B2 via connection key 2, thereby causing the second data to be stored in the second unit under test B2.

[0031] The comparison unit 105 obtains the second data stored in each second unit under test and compares the second data stored in each second unit under test with the first data stored in each first unit under test to determine whether the connection key corresponding to each first unit under test and each second unit under test is reliable.

[0032] Specifically, assuming that the first data stored in the first units under test A1 to A9 is 1, the first data 1 stored in the first unit under test A1 is read out, and then the first data 1 is written to the second unit under test B1 through the connection key 1; the first data 1 stored in the first unit under test A2 is read out, and then the first data 1 is written to the second unit under test B2 through the connection key 2; the first data 1 stored in the first unit under test A3 is read out, and then the first data 1 is written to the second unit under test B3 through the connection key 3; the first data 1 stored in the first unit under test A4 is read out, and then the first data 1 is written to the second unit under test B4 through the connection key 4; the first data 1 stored in the first unit under test A5 is read out, and then the first data 1 is written to the second unit under test B5 through the connection key 5; ... the first data 1 stored in the first unit under test A9 is read out, and then the first data 1 is written to the second unit under test B9 through the connection key 9. The comparison unit obtains the second data from the second units to be tested B1 to B9 and compares the second data with the second data. If the second data read from the second units to be tested B1 to B9 are all 1, it means that the connection keys 1 to 9 are all normal; if the second data read from one of the second units to be tested is 0, it indicates that the connection key at the corresponding position is abnormal.

[0033] To implement the above process, please continue to refer to Figure 2 The conductive pads 107 include a plurality of first conductive pads 11 and a plurality of second conductive pads 12. Each of the first conductive pads 11 is connected to at least one of the first units under test (A1-A9), and each of the second conductive pads 12 is connected to at least one of the second units under test (B1-B9) via one of the connection keys (1-9). The first conductive pads 11 and the second conductive pads 12 are interconnected. In this way, first data can be read from the first units under test (A1-A9) via the first conductive pads 11 and the second conductive pads 12, and the first data can be written to the second units under test (B1-B9) via the connection keys (1-9).

[0034] It can be understood that in this embodiment, each first unit under test and / or each second unit under test includes at least one storage bit.

[0035] In this embodiment, the first data may be generated by an external device, and when the reliability is detected, the external device writes the first data to the first waiting unit in the stacked chip. In another embodiment, the first data may also be generated inside the stacked chip, specifically as follows Figure 3 As shown above Figure 2The difference between the embodiment and the prior art is that the embodiment further comprises a data generating unit 108. Specifically, the data generating unit 108 is arranged on one of the at least two to-be-tested wafers, for example, the data generating unit 108 is arranged on the first to-be-tested wafer 101. In another embodiment, the data generating unit 108 can also be arranged on each to-be-tested wafer, for example, the data generating unit 108 is arranged on the first to-be-tested wafer 101 and the second to-be-tested wafer 102.

[0036] The data generating unit 108 is connected to the comparison unit 105. The data generating unit 108 arranged on the first to-be-tested wafer 101 generates first data and writes the first data into the first to-be-tested wafer 101 and the comparison unit 108. Specifically, the data generating unit 108 arranged on the first to-be-tested wafer 101 writes the first data into the first to-be-tested units A1 to A9 and the comparison unit 108. In another embodiment, the second to-be-tested wafer 102 is also provided with a data generating unit, and the data generating unit 108 arranged on the second to-be-tested wafer 102 reads second data from the second to-be-tested wafer 102 and writes the second data into the comparison unit 105. Specifically, the data generating unit 108 arranged on the second to-be-tested wafer 102 reads the second data from the second to-be-tested units B1 to B9 and writes the second data into the comparison unit 105. Then, the comparison unit 105 compares the first data with the second data, and determines whether the connection keys at the corresponding positions are reliable.

[0037] Please refer to Figure 4 In an embodiment of the present application, the comparison unit 105 comprises an exclusive-OR gate XOR, an OR gate OR, and a register P. The exclusive-OR gate XOR comprises a first input end, a second input end, and an output end. The first input end of the exclusive-OR gate XOR is connected to the data generating unit 108 on the first to-be-tested wafer 101 to receive the first data. The second input end of the exclusive-OR gate XOR is connected to the data generating unit 108 on the second to-be-tested wafer 102 to obtain the second data. The OR gate OR comprises a first input end, a second input end, and an output end. The first input end of the OR gate OR is connected to the output end of the exclusive-OR gate XOR. The register P comprises a first input end, a second input end, and an output end. The first input end of the register P is connected to the output end of the OR gate OR. The second input end of the register P receives a data reading signal. The output end of the register P is connected to the second input end of the OR gate OR, and the output end of the register P outputs a comparison result.

[0038] The data read signal is generated after reading the second data, that is, the data read signal indicates that the second data has been successfully read. Specifically, the data generation unit 108 generates the data read signal after successfully reading the second data. The comparison result indicates the position of the unreliable connection key. Specifically, each first unit under test and each second unit under test corresponds to a connection key. When the comparison unit 105 compares the first data with the second data, it simultaneously records the storage bits where the comparison results do not match, thereby deducing the position of the connection key.

[0039] In the present application, the wafer to be tested is one or a combination of a memory wafer and a logic wafer. For example, in one embodiment, the first wafer to be tested 101 and the second wafer to be tested 102 are both memory wafers, such as DRAM (Dynamic Random Access Memory, dynamic random access memory), SRAM (Static Random-Access Memory, static random access memory), etc., which are not specifically limited. The first unit to be tested and the second unit to be tested are one of the storage arrays of the first wafer to be tested 101 and the second wafer to be tested 102. In another embodiment, the first wafer to be tested 101 is a memory wafer, and the second wafer to be tested 102 is a logic wafer. Alternatively, the first wafer to be tested 101 and the second wafer to be tested 102 are both logic wafers.

[0040] The stacked chip of the present application is provided with a wiring layer, and a first unit under test is connected to a second unit under test in a one-to-one correspondence via pads on the wiring layer, so that first data stored in the first unit under test is read out and written into the second unit under test via a corresponding connection key, so that the second unit under test stores second data. A comparison unit compares the first data with the second data, and then determines whether the corresponding connection key is reliable. The method of the present application is not limited by the number of pins and can well test a large number of pads between chips.

[0041] In a specific embodiment, the connection bonds include HB (Hybrid Bonding), RDL (Redistribution Layer) layer, TSV (Through Silicon Via), etc.

[0042] See Figure 5 , is a flow chart of an embodiment of the stacked detection method of the present invention. The detection method of this embodiment is based on the above Figures 1 to 4 The stacked chip shown, the detection method includes:

[0043] Step S51: writing first data into a first wafer to be tested.

[0044] Specifically, the first data is written into the first wafer to be tested. Figure 2, writing the first data into each first unit under test of the first wafer under test, so that each first unit under test stores the first data. For example, assuming that the first data is 1, each first unit under test stores 1.

[0045] Step S52: writing the first data into the second wafer to be tested through the connection layer, so that the second wafer to be tested stores second data.

[0046] Specifically, the first data is written into the second wafer to be tested through the connection layer, so that the second data is stored in the second wafer to be tested. For example, the first data is written into each second unit to be tested of the second wafer to be tested through the connection layer.

[0047] In one embodiment, the first data is read from the first wafer under test, and the first data is written to the second wafer under test via the connection layer, so that the second wafer under test stores the second data. For example, the first data is read from each first unit under test of the first wafer under test, and the first data is written to each second unit under test of the second wafer under test via the connection layer, so that the second unit under test stores the second data.

[0048] Specifically, the first data is read from each first unit under test in the first wafer under test, and the first data is written into the corresponding second unit under test in the second wafer under test through a connection key connected to the first unit under test, so that each unit under test stores the second data.

[0049] Step S53: Compare the first data with the second data to determine whether the connection layer is reliable.

[0050] Specifically, the first data of each unit under test is compared with the second data of the corresponding second unit under test to determine whether the connection key between the first unit under test and the second unit under test is reliable; in response to the first data and the second data not matching, a comparison result is output, and the comparison result represents the position of the unreliable connection key.

[0051] It is understandable that if the connection key is reliable, the second data stored in each second unit under test is still 1. That is, if the second data stored in a second unit under test is not 1, the connection key corresponding to the second unit under test is unreliable.

[0052] The stacked chip testing method of the present application provides a wiring layer, and connects a first unit under test to a second unit under test in a one-to-one correspondence via pads on the wiring layer, so as to read out first data stored in the first unit under test and write it into the second unit under test via a corresponding connection key, so that the second unit under test stores second data. A comparison unit compares the first data with the second data, and then determines whether the corresponding connection key is reliable. The method of the present application is not limited by the number of pins and can well test a large number of pads between chips.

[0053] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A stacked chip, characterized in that: include: At least two wafers to be tested, the at least two wafers to be tested comprising: a first wafer to be tested and a second wafer to be tested; the first wafer to be tested and the second wafer to be tested are stacked and interconnected via a connection layer, the connection layer comprising a plurality of connection keys; a wiring layer, the wiring layer being located on a side of the first wafer to be tested away from the second wafer to be tested, the wiring layer comprising conductive pads, the first wafer to be tested being connected to the conductive pads, and the second wafer to be tested being connected to the conductive pads via the connecting keys; a comparison unit, the comparison unit being located on one of the at least two wafers to be tested, and being configured to compare first data written into the first wafer to be tested with second data written into the second wafer to be tested, so as to determine whether the connection layer is reliable; wherein the first wafer to be tested includes a plurality of first units to be tested; the second wafer to be tested includes a plurality of second units to be tested; each of the second units to be tested and each of the first units to be tested are connected via one of the plurality of connection keys; The second data is the first data read out from each first unit under test and written into each second unit under test through the conductive pad and the corresponding connection key.

2. The stacked chip according to claim 1, wherein: The first data is stored in each of the first units to be tested and is also stored in the comparison unit; The second data is stored in each of the second units under test, The comparison unit obtains the second data stored in each second unit under test, and compares the second data stored in each second unit under test with the first data stored in each first unit under test to determine whether the connection key corresponding to each first unit under test and each second unit under test is reliable.

3. The stacked chip according to claim 2, wherein: The conductive pads include a plurality of first conductive pads and a plurality of second conductive pads; Each of the first conductive pads is correspondingly connected to at least one of the first units under test, and each of the second conductive pads is correspondingly connected to at least one of the second units under test via one of the connecting keys, and the first conductive pads and the second conductive pads are interconnected.

4. The stacked chip according to claim 2, wherein: Each of the first unit under test and / or the second unit under test includes at least one storage bit.

5. The stacked chip according to claim 2, wherein: Also includes: a data generating unit, disposed on one of the at least two wafers to be tested, or disposed on each of the wafers to be tested, and connected to the comparing unit; The data generating unit provided on the first wafer to be tested generates first data, and writes the first data into the first wafer to be tested and the comparing unit; The data generating unit disposed on the second wafer to be tested reads the second data from the second wafer to be tested and writes the second data into the comparing unit.

6. The stacked chip according to claim 5, wherein: The comparison unit includes: An XOR gate includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the XOR gate is connected to the data generating unit on the first wafer to be tested to receive the first data; the second input terminal of the XOR gate is connected to the data generating unit on the second wafer to be tested to obtain the second data; An OR gate, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the OR gate is connected to the output terminal of the XOR gate; a register comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the register is connected to the output terminal of the OR gate, the second input terminal of the register receives a data read signal, the output terminal of the register is connected to the second input terminal of the OR gate, and the output terminal of the register outputs a comparison result; The data read signal is generated after reading the second data, and the comparison result represents the position of the unreliable connection key.

7. The stacked chip according to claim 1, wherein: The wafer to be tested is one or a combination of a memory wafer and a logic wafer.

8. A method for detecting a stacked chip, characterized in that: The method is based on the stacked chip according to any one of claims 1 to 7, and the method comprises: Writing the first data into the first wafer to be tested; Writing the first data into the second wafer to be tested through the connection layer, so that the second wafer to be tested stores the second data; The first data is compared with the second data to determine whether the connection layer is reliable.

9. The detection method according to claim 8, characterized in that The step of writing the first data into the second wafer to be tested through the connection layer so that the second data is stored in the second wafer to be tested includes: The first data is read from the first wafer to be tested, and the first data is written into the second wafer to be tested through the connection layer, so that the second data is stored in the second wafer to be tested.

10. The detection method according to claim 9, characterized in that: The step of reading the first data from the first wafer to be tested and writing the first data into the second wafer to be tested through the connection layer so that the second data is stored in the second wafer to be tested includes: The first data is read from each first unit under test in the first wafer under test, and the first data is written into the corresponding second unit under test in the second wafer under test through a connection key connected to the first unit under test, so that each unit under test stores the second data.

11. The detection method according to claim 10, characterized in that: The step of comparing the first data with the second data to determine whether the connection layer is reliable includes: Comparing the first data of each unit under test with the second data of the corresponding second unit under test to determine whether the connection key between the first unit under test and the second unit under test is reliable; In response to the first data not matching the second data, a comparison result is output, wherein the comparison result indicates a position of the connection key that is unreliable.

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