Display panel and display device

Abstract

The present invention provides a display panel, comprising a first display area and a second display area surrounding the first display area; the display panel comprises: a substrate and a plurality of first pixel units and a plurality of second pixel units located on the substrate, the first pixel unit comprises a first light-emitting device and a first pixel circuit, the second pixel unit comprises a second light-emitting device and a second pixel circuit; the display panel further comprises: a first signal line and a second signal line, the first signal line is used to provide a first drive signal to the first pixel circuit; the second signal line is used to provide a second drive signal to the second pixel circuit; the load capacitance of the first signal line is equal to the load capacitance of the second signal line. The display panel provided by the embodiment of the present invention can effectively improve the uniformity of the display panel by making the load capacitance of the first signal line equal to the load capacitance of the second signal line.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the prior art, the data line used to provide data voltage to the pixel unit in the camera area under the screen adopts a bent design, and the newly added bent wiring increases the load capacitance on the data line (refer to Figure 1 ), resulting in uneven display of the panel, forming uneven vertical strips (reference Figure 2 ). Summary of the invention

[0003] The present invention provides a display panel and a display device, which can prevent uneven display of the panel and avoid the formation of longitudinal strip-shaped uneven display.

[0004] A first aspect of the present invention provides a display panel, comprising a display area and a frame area at least partially surrounding the display area, wherein the display area comprises a first display area and a second display area, and the second display area is at least located on one side of the first display area;

[0005] The display panel comprises: a substrate and a plurality of first pixel units and a plurality of second pixel units located on the substrate, the first pixel unit comprises a first light emitting device and a first pixel circuit, the second pixel unit comprises a second light emitting device and a second pixel circuit, the first light emitting device is located in the first display area, the first pixel circuit, the second light emitting device and the second pixel circuit are located in the second display area, the orthographic projection of the second light emitting device on the substrate and the orthographic projection of the second pixel circuit on the substrate at least partially overlap, and the first light emitting device and the first pixel circuit are connected via a connecting wire;

[0006] The display panel further includes: M first signal lines and N second signal lines located on the base substrate, N>M, and M and N are both positive integers;

[0007] The first signal line is located in the second display area and is configured to provide a first driving signal to the first pixel circuit;

[0008] The second signal line is located in the second display area and is configured to provide a second driving signal to the second pixel circuit;

[0009] An absolute value of a difference between a load capacitance of the first signal line and a load capacitance of the second signal line is smaller than a load capacitance of the first signal line or a load capacitance of the second signal line.

[0010] Optionally, the second signal line includes a main body portion extending along the first direction and a compensation portion connected to the main body portion;

[0011] The first signal line comprises an equivalent portion having the same length as the main portion of the second signal line and extending along the first direction and a newly added portion connected to the equivalent portion;

[0012] The length of the compensation portion is equal to that of the newly added portion.

[0013] Optionally, the second display area further includes: a plurality of virtual pixel circuits located on the base substrate;

[0014] At least part of the virtual pixel circuits are multiplexed as the first pixel circuits.

[0015] Optionally, each load capacitance of the M first signal lines is equal, and each load capacitance of the N second signal lines is equal; or

[0016] The load capacitance of at least one of the M first signal lines is equal to the load capacitance of at least one of the N second signal lines.

[0017] Optionally, the first pixel circuit at least includes a first storage capacitor, and the first storage capacitor includes a first electrode plate and a second electrode plate that are arranged opposite to each other;

[0018] The orthographic projection of the first signal line on the base substrate and the orthographic projection of the second electrode plate on the base substrate have a first overlapping area;

[0019] The display panel further comprises a compensation pattern located on the base substrate;

[0020] The orthographic projection of the second signal line on the base substrate and the orthographic projection of the compensation pattern on the base substrate have a second overlapping area;

[0021] An area of ​​the second overlapping region is greater than an area of ​​the first overlapping region.

[0022] Optionally, the compensation pattern includes: a body and a protruding portion extending from the body, and an orthographic projection of the second signal line on the base substrate and an orthographic projection of the protruding portion of the compensation pattern on the base substrate have a second overlapping area.

[0023] Optionally, the second pixel circuit includes at least one thin film transistor, a first planarization layer and a second storage capacitor;

[0024] The first planarization layer is located on a side of the thin film transistor away from the substrate to cover the thin film transistor;

[0025] The second light emitting device is located on a side of the first planarization layer away from the base substrate;

[0026] The thin film transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, a source electrode and a drain electrode located on a side of the gate away from the substrate, and a connecting electrode located on a side of the first planarization layer away from the substrate, wherein the connecting electrode is connected to one of the source electrode and the drain electrode through a via hole in the first planarization layer;

[0027] The second storage capacitor includes a third plate and a fourth plate that are arranged opposite to each other, the third plate is arranged in the same layer as the gate, and the fourth plate is located between the gate and the source.

[0028] Optionally, the compensation pattern is multiplexed as a fourth plate of the second storage capacitor.

[0029] Optionally, the first signal line and the second signal line are located in the same layer as the connection electrode.

[0030] Optionally, the display panel further comprises: a conductive connection portion located on the base substrate, and the fourth electrode plate of the second storage capacitor is coupled to the conductive connection portion through a via hole;

[0031] The display panel further comprises: a power line located on the base substrate, the power line is coupled to the conductive connection portion, and the conductive connection portion is located between the fourth electrode plate and the power line;

[0032] The compensation pattern is reused as the conductive connection portion.

[0033] Optionally, the compensation pattern is located in the same layer as one of the source or the drain.

[0034] Optionally, the border area includes at least an upper border area, and N compensation capacitors are arranged in the upper border area, and the N compensation capacitors correspond one-to-one to the N second signal lines, one end of each compensation capacitor is coupled to the corresponding second signal line, and the other end of each compensation capacitor is coupled to the voltage stabilization signal output end.

[0035] Optionally, the newly added portion of the first signal line includes at least a laterally added portion extending along the second direction, and the connecting line is at least parallel to the laterally added portion.

[0036] Optionally, the first signal line is a first data line configured to provide a first data signal to the first pixel circuit;

[0037] The second signal line is a second data line configured to provide a second data signal to the second pixel circuit.

[0038] A second aspect of the present invention provides a display device, comprising the above-mentioned display panel.

[0039] The display panel provided by the embodiment of the present invention can effectively improve the uniformity of the display panel by making the load capacitance of the first signal line equal to the load capacitance of the second signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of load capacitance on a data line in the related art;

[0041] Figure 2 It is a schematic diagram of uneven vertical strip display in the related art;

[0042] Figure 3 A schematic diagram of a load capacitor on a second signal line provided by an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of compensation design for a second signal line provided by an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of the connection between the virtual pixel circuit and the first light-emitting device provided in an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of the distance design between the pixel circuit and the light-emitting device provided in an embodiment of the present invention;

[0046] Figure 7 A circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0047] Figure 8 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0048] Fig. 9 A layout diagram of a first pixel circuit provided by an embodiment of the present invention;

[0049] Fig.10 A layout diagram of a second pixel circuit provided by an embodiment of the present invention;

[0050] Fig.11 A layout diagram of another second pixel circuit provided by an embodiment of the present invention;

[0051] Fig.12 for Fig.11 A layout diagram of the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer;

[0052] Fig.13 A schematic diagram of another load capacitor on a second signal line provided by an embodiment of the present invention.

[0053] Reference numerals

[0054] 1-display area 2-frame area 3-first display area 4-second display area

[0055] S1-first signal line S2-second signal line C1-new capacitor C2-compensation capacitor

[0056] 11-Equivalent part 111-First part 112-Second part 113-Third part

[0057] 12- New part 121- New part in horizontal direction 122- New part in vertical direction

[0058] 21-Main part 22-Compensation part

[0059] 41-Compensation pattern 411-Protruding part

[0060] 51-conductive connection part

[0061] 10- second pixel circuit 20- first pixel circuit

[0062] 30- second light emitting device 40- first light emitting device

[0063] L1-Connection wiring

[0064] 611- flexible substrate 612- barrier layer 613- buffer layer 614- first gate insulating layer

[0065] 615 - second gate insulating layer 616 - interlayer dielectric layer 617 - passivation layer

[0066] 618 - first planarization layer 619 - second planarization layer 620 - pixel definition layer

[0067] 621- spacer layer 622- light emitting layer 623- cathode 624- inorganic encapsulation layer

[0068] 6241-first inorganic encapsulation layer 6242-second inorganic encapsulation layer 625-organic encapsulation layer

[0069] 626 - anode layer 627 - connection electrode 627a - first connection electrode

[0070] 627b - second connection electrode 628 - source 629 - drain 630 - active layer

[0071] 631-Gate DETAILED DESCRIPTION

[0072] In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0073] With the trend of full screen, the display screen ratio of mobile phones is an important indicator. The Full Display with Camera (FDC) is to place the camera under the screen, and the display screen area above the camera can still display normally, thus realizing a full screen. In order to improve the light transmittance of the FDC area, it is usually avoided to design pixel circuits in the FDC area, and only the light-emitting device part is retained. The pixel circuit in the FDC area can use a virtual pixel circuit, which is a newly added pixel circuit after compressing the pixel circuit in the display area outside the FDC area.

[0074] Since there is a certain distance between the virtual pixel circuit and the light-emitting device in the FDC area, the virtual pixel circuit and the light-emitting device in the FDC area are connected through connecting wires. At the same time, the data line used to provide data signals to the virtual pixel circuit needs to adopt a meander line design, and the newly added meander line increases the load capacitance on the data line, resulting in uneven display of the panel and uneven display of longitudinal strips.

[0075] An embodiment of the present invention provides a display panel, comprising a display area and a frame area at least partially surrounding the display area, wherein the display area comprises a first display area and a second display area, and the second display area is at least located on one side of the first display area;

[0076] The display panel comprises: a base substrate and a plurality of first pixel units and a plurality of second pixel units located on the base substrate, wherein the first pixel unit comprises a first light emitting device and a first pixel circuit, and the second pixel unit comprises a second light emitting device and a second pixel circuit.

[0077] The first light-emitting device is located in the first display area, the first pixel circuit, the second light-emitting device and the second pixel circuit are located in the second display area, the orthographic projection of the second light-emitting device on the base substrate and the orthographic projection of the second pixel circuit on the base substrate at least partially overlap, and the first light-emitting device and the first pixel circuit are connected through a connecting wire; the display panel further includes: M first signal lines and N second signal lines located on the base substrate, N>M, and M and N are both positive integers;

[0078] The first signal line is located in the second display area and is configured to provide a first driving signal to the first pixel circuit;

[0079] The second signal line is located in the second display area and is configured to provide a second driving signal to the second pixel circuit;

[0080] An absolute value of a difference between a load capacitance of the first signal line and a load capacitance of the second signal line is smaller than a load capacitance of the first signal line or a load capacitance of the second signal line.

[0081] The display panel provided by the embodiment of the present invention can effectively improve the display uniformity of the display panel by keeping the absolute value of the difference between the load capacitance of the first signal line and the load capacitance of the second signal line within a relatively small range.

[0082] refer to Figure 3 and Figure 4 , wherein the border area 2 of the display panel provided by the embodiment of the present invention surrounds the display area 1, and the display area 1 includes a first display area 3 and a second display area 4, wherein the first display area 1 is an FDC area, and the second display area 4 is a non-FDC area.

[0083] The first pixel unit in the FDC area only retains the first light emitting device part, and the first pixel circuit part is located in the non-FDC area, so that the light transmittance of the FDC area can be guaranteed.

[0084] The first pixel circuit is connected to the first pixel unit through a lateral connection line, so that the FDC area can achieve a luminous display effect.

[0085] The non-FDC area is also provided with a second light emitting device and a second pixel circuit of a second pixel unit.

[0086] Figure 5 The second light emitting device 30, the first light emitting device 40, the second pixel circuit 10, the first pixel circuit 20, the connection electrode 627, the connection line L1, the first signal line S1 and the second signal line S2 are shown. Each pixel circuit is connected to the light emitting device through the connection electrode 627. That is, each pixel unit has a connection electrode 627. That is, the second pixel circuit 10 is connected to the second light emitting device 30 through the connection electrode 627 (the first connection electrode 627a), and the first pixel circuit 20 is connected to the first light emitting device 40 through the connection electrode 627 (the second connection electrode 627b).

[0087] For example, Figure 5 As shown, one end of the connection line L1 is connected to the first light emitting device 40, and the other end of the connection line L1 is connected to the first pixel circuit 20 through the connection electrode 627 (the second connection electrode 627b). For example, the connection electrode 627 can be formed by a single conductive component, or can include two different conductive components located in different layers. For example, the connection electrode 627 can include a conductive component located in one conductive layer and another conductive component located in another conductive layer.

[0088] like Figure 5As shown, a connecting line L1 passes through the area where the pixel circuit of the pixel unit is located to respectively connect the first pixel circuit 20 and the first light-emitting device 40 on both sides of the pixel unit. For example, the area where the pixel circuit of the pixel unit is located overlaps with a plurality of connecting lines L1 passing through the area. The area where the first pixel circuit 20 is arranged in the second display area 4 can be called an auxiliary area Ra, and the auxiliary area Ra can also be called a transition area. Figure 5 Taking the example that a second pixel circuit 10 overlaps with at most two connection lines L1, in other embodiments, a second pixel circuit 10 may also overlap with more connection lines L1. For example, in some embodiments, a second pixel circuit 10 may overlap with 5-15 connection lines L1. The number of connection lines L1 overlapped by a second pixel circuit 10 may be determined according to needs. Figure 5 As shown, the first pixel circuit 20 may also overlap with the connection line L1 which is not connected thereto.

[0089] In some embodiments, the area for disposing the first pixel circuit 20 can be obtained by compressing the size of the second pixel circuit 10 in the second direction. Figure 5 As shown, in the auxiliary area, a column of first pixel circuits 20 is provided for every set column of second pixel circuits 10. For example, the number of columns of second pixel circuits 10 between two adjacent columns of first pixel circuits 20 can be determined as required.

[0090] The first signal line S1 is connected to the column where the first pixel circuit 20 is located in a winding manner, and provides a first driving signal to the first pixel circuit 20 .

[0091] The second signal line S2 provides a second driving signal to a column of second pixel circuits 20 .

[0092] Figure 6 for Figure 4 The enlarged schematic diagram of part B in the figure, wherein the pixel unit of the embodiment of the present invention adopts an RGBG pixel arrangement method, and the second pixel circuit is close to the location of the second light-emitting device.

[0093] The second pixel circuit 10 and the second light emitting device 30 are designed with non-equidistant spacing. The spacing between the second pixel circuit 10 is smaller than that between the second light emitting devices 30. The virtual pixel circuit 20 newly added after compression can be used to drive the anode light emission in the FDC area, avoiding the design of circuit units in the FDC area and improving the light transmittance of the FDC area. Figure 5 As shown, the size of the three second pixel circuit units is equal to the distance between the two second light emitting devices. Figure 6 As shown, the size of the five second pixel circuit units is equal to the inter-electrode spacing of the four second light-emitting devices.

[0094] refer to Figure 5 , every two second pixel circuits compress one virtual pixel circuit.

[0095] refer to Figure 4 and Figure 6 , every 4 second pixel circuits are compressed into 1 virtual pixel circuit.

[0096] refer to Figure 3 , Figure 4 and Figure 5 The first signal line S1 is located in the second display area 4 and is configured to provide a first driving signal to the first pixel circuit; the second signal line S2 is configured to provide a second driving signal to the second pixel circuit.

[0097] The first signal line S1 adopts a winding design, so a new capacitor C1 is generated in the winding part, which causes uneven display of the panel and forms uneven display in the form of longitudinal strips.

[0098] In the embodiment of the present invention, in order to make the load capacitance on the second signal line S2 equal to the load capacitance on the first signal line S1 , load compensation is performed on the second signal line S2 .

[0099] Optionally, the second signal line includes a main body portion extending along the first direction and a compensation portion connected to the main body portion;

[0100] The first signal line comprises an equivalent portion having the same length as the main portion of the second signal line and extending along the first direction and a newly added portion connected to the equivalent portion;

[0101] The length of the compensation portion is equal to that of the newly added portion.

[0102] By making the length of the compensation part equal to that of the newly added part, the compensation capacitance of the compensation part and the newly added capacitance of the newly added part can be made equal, thereby avoiding the uneven display of longitudinal stripes caused by the newly added capacitance on the first signal line.

[0103] As an example, the second signal line S2 includes a main portion 21 and a compensation portion 22 , wherein the main portion 21 extends in the longitudinal direction, and the compensation portion 22 includes at least a portion of the second signal line S2 connected to the dummy pixel circuit.

[0104] It should be noted that Figure 4 and Figure 5 The wiring method of the compensation part shown is for illustration only. In actual production, various wiring methods may be used. Figure 4 and Figure 5 For illustration only.

[0105] like Figure 4As shown, the first signal line S1 includes an equivalent portion 11 and a new portion 12, wherein the equivalent portion 11 includes: a first portion 111, a second portion 112 and a third portion 113. The new portion 12 includes two transverse new portions 121 and one longitudinal new portion 122.

[0106] The sum of the lengths of the first portion 111, the second portion 112 and the third portion 113 of the first signal line S1 is equal to the length of the main portion 21 of the second signal line S2. The sum of the lengths of the two transversely added portions 121 is equal to the transverse portion of the compensation portion 22, and the length of the longitudinally added portion 122 is equal to the longitudinal portion of the compensation portion 22.

[0107] Likewise, it should be noted that the winding method of the first signal line S1 is only for illustration, and various routing methods may be used in the actual production process.

[0108] Optionally, the second display area further includes: a plurality of virtual pixel circuits located on the base substrate;

[0109] At least part of the virtual pixel circuits are multiplexed as the first pixel circuits.

[0110] By multiplexing the virtual pixel circuit as the first pixel circuit, it is possible to avoid setting up a pixel circuit in the FDC region, thereby improving the light transmittance of the FDC region.

[0111] As described above, each column of virtual pixel circuits is obtained by compressing 4 columns of RGBG pixel circuits.

[0112] In addition, the virtual pixel circuit can be obtained not only by a 4-to-1 method, but also by a 2-to-1 or 8-to-1 method.

[0113] Optionally, each load capacitance of the M first signal lines is equal; each load capacitance of the N second signal lines is equal; or the load capacitance of at least one of the M first signal lines is equal to the load capacitance of at least one of the N second signal lines.

[0114] By making the load capacitance of each of the M first signal lines equal; the load capacitance of each of the N second signal lines equal, or the load capacitance of at least one of the M first signal lines equal to the load capacitance of at least one of the N second signal lines, the load capacitances on the data lines of the entire display panel can be made equal, which can effectively improve the display uniformity of the display panel.

[0115] In order to ensure display uniformity of the display panel, it is necessary to make the load capacitances on all data lines in the panel equal, rather than just making the load capacitances on the M second signal lines equal to the load capacitances on the M first signal lines.

[0116] Optionally, the first pixel circuit at least includes a first storage capacitor, and the first storage capacitor includes a first electrode plate and a second electrode plate that are arranged opposite to each other;

[0117] The orthographic projection of the first signal line on the base substrate and the orthographic projection of the second electrode plate on the base substrate have a first overlapping area;

[0118] The display panel further comprises a compensation pattern located on the base substrate;

[0119] The orthographic projection of the second signal line on the base substrate and the orthographic projection of the compensation pattern on the base substrate have a second overlapping area;

[0120] An area of ​​the second overlapping region is greater than an area of ​​the first overlapping region.

[0121] The embodiment of the present invention increases the load capacitance on the second signal line by making the area of ​​the second overlapping region larger than the area of ​​the first overlapping region, so that the load capacitance on the second signal line is equal to the load capacitance on the first signal line, thereby effectively improving the display uniformity of the display panel.

[0122] Optionally,

[0123] The second pixel circuit includes at least one thin film transistor, a first planarization layer and a second storage capacitor;

[0124] The first planarization layer is located on a side of the thin film transistor away from the substrate to cover the thin film transistor;

[0125] The second light emitting device is located on a side of the first planarization layer away from the base substrate;

[0126] The thin film transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, a source electrode and a drain electrode located on a side of the gate away from the substrate, and a connecting electrode located on a side of the first planarization layer away from the substrate, wherein the connecting electrode is connected to one of the source electrode and the drain electrode through a via hole in the first planarization layer;

[0127] The second storage capacitor includes a third plate and a fourth plate that are arranged opposite to each other, the third plate is arranged in the same layer as the gate, and the fourth plate is located between the gate and the source.

[0128] Optionally, the compensation pattern is multiplexed as a fourth plate of the second storage capacitor.

[0129] refer to Figure 8The display panel provided by the embodiment of the present invention includes, from close to the base substrate to far away from the base substrate, the following:

[0130] Flexible substrate 611, barrier layer 612, buffer layer 613, active layer 630, first gate insulating layer 614, first gate metal layer, second gate insulating layer 615, second gate metal layer, interlayer dielectric layer 616, first source-drain metal layer, passivation layer 617, first planarization layer 618, second source-drain metal layer, second planarization layer 619, anode layer 626, pixel defining layer 620, spacer layer 621, light-emitting layer 622, cathode 623, first inorganic encapsulation layer 6241, organic encapsulation layer 625, second inorganic encapsulation layer 6242.

[0131] refer to Figure 8 , wherein at least one thin film transistor includes an active layer 630 , a gate 631 , a source 628 and a drain 629 , and the drain 629 is connected to the anode layer 626 of the light emitting element through a connecting electrode 627 .

[0132] The active layer 630 is a Poly-Si active layer, the source electrode 628 and the drain electrode 629 are made of a first source-drain metal layer, and the gate electrode 631 is made of a first gate metal layer.

[0133] refer to Fig.10 , the third electrode Cst3 is made of the first gate metal layer. The third electrode Cst3 is made of the same layer and the same material as the gate 631. The fourth electrode Cst4 is made of the second gate metal layer, the source 628 and the drain 629 are made of the first source-drain metal layer, the second gate metal layer is located between the first gate metal layer and the first source-drain metal layer, and the fourth electrode Cst4 is located between the gate 631 and the source 628.

[0134] The above key film layer design is not only applicable to the key film layer of low-temperature polycrystalline silicon (LTPS) backplane, but can also be applied to the backplane design of low-temperature polycrystalline oxide (LTPO) structure.

[0135] refer to Fig.10 By increasing the area of ​​the fourth electrode plate included in the second storage capacitor of the second pixel circuit in the non-FDC area, and then increasing the area of ​​the overlapping region between the second signal line and the fourth electrode plate, the load capacitance on the second signal line can be increased, so that the load capacitance on the second signal line is equal to the load capacitance on the first signal line, thereby effectively improving the display uniformity of the display panel.

[0136] Since the first signal line adopts a winding design, the load capacitance on the first signal line is increased, which is different from making the second signal line include a compensation part to obtain a compensation capacitance. In an embodiment of the present invention, the compensation capacitance is obtained by increasing the overlapping area of ​​one of the plates of the storage capacitor of the second signal line and at least part of the pixel units in the column.

[0137] Figure 7 A circuit diagram of a pixel circuit provided by an embodiment of the present invention; Fig. 9 A layout diagram of a first pixel circuit provided by an embodiment of the present invention; Fig.10 A layout diagram of a second pixel circuit provided by an embodiment of the present invention.

[0138] in, Fig. 9 A circuit diagram of a first pixel circuit in Fig.10 The circuit diagrams of the second pixel circuits in Figure 7 shown.

[0139] Since the first signal line adopts a winding design, the shapes of the first plate Cst1 and the second plate Cst2 of the first storage capacitor of the first pixel circuit are not adjusted.

[0140] In order to increase the load capacitance on the second signal line, refer to Fig.10 , the shape of the second plate Cst4 of the second storage capacitor of the second pixel circuit is changed. The compensation pattern 41 is the fourth plate Cst4 of the second storage capacitor. The shape of the first plate Cst3 of the second storage capacitor of the second pixel circuit is not changed.

[0141] refer to Figures 7 to 11 Each pixel circuit at least includes a first reset transistor T1 and a driving transistor T3. The second electrode of the first reset transistor T1 is coupled to the gate of the driving transistor T3.

[0142] The display substrate further includes: a plurality of first reset signal lines 14, and the gate of the first reset transistor T1 is coupled to the first reset signal line 14;

[0143] The initialization signal line includes a first initialization signal line 15 and a second initialization signal line 13;

[0144] A first electrode of the first reset transistor T1 is coupled to the first initialization signal line 15 .

[0145] The display substrate further comprises:

[0146] A plurality of power signal lines 16, a plurality of light emission control signal lines 17, a plurality of data lines 11 and a plurality of second reset signal lines 18;

[0147] The scanning lines include a first scanning line 10 and a second scanning line 12;

[0148] The pixel circuit further includes a compensation transistor T2, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst;

[0149] The first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and the gate of the compensation transistor T2 is coupled to the first scanning line 10;

[0150] The first electrode of the data writing transistor T4 is coupled to the corresponding data line 11, the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3, and the gate of the data writing transistor T4 is coupled to the second scanning line 12;

[0151] The gate of the first light-emitting control transistor T5 is coupled to the corresponding light-emitting control signal line 17, the first electrode of the first light-emitting control transistor T5 is coupled to the power signal line 16, and the second electrode of the first light-emitting control transistor T5 is coupled to the first electrode of the driving transistor T3;

[0152] The gate of the second light emitting control transistor T6 is coupled to the corresponding light emitting control signal line 17, the first electrode of the second light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, the second electrode of the second light emitting control transistor T6 is coupled to the anode of the light emitting element EL, and the cathode of the light emitting element EL receives the negative power supply signal VSS;

[0153] The gate of the second reset transistor T7 is coupled to the second reset signal line 18, the second electrode of the second reset transistor T7 is coupled to the second electrode of the second light emitting control transistor T6, and the first electrode of the second reset transistor T7 is coupled to the second initialization signal line 13;

[0154] Exemplarily, the second reset signal line 18 coupled to the gate of the second reset transistor T7 in the current pixel circuit is the same line as the first scan line 10 coupled to the gate of the data writing transistor T4 in the pixel circuit adjacent to the first direction.

[0155] refer to Figure 8 The first reset signal line 14 is made of the same layer and material as the gate electrode of the thin film transistor. The second initialization signal line 13 or the first initialization signal line 15 is made of the second gate metal layer.

[0156] Optionally, the first signal line and the second signal line are located in the same layer as the connection electrode.

[0157] The first signal line and the second signal line are located in the same layer as the connection electrode, and the first signal line, the second signal line and the connection electrode can be formed through a single patterning process, thereby reducing the mask patterning process.

[0158] Optionally, the first signal line, the second signal line, and the connecting electrode are made of a second source-drain metal layer; and the second electrode plate of the first storage capacitor is made of a second gate metal layer.

[0159] The first signal line and the second electrode plate are made of different film layers, so that a load capacitor can be formed between the first signal line and the second electrode plate. The second signal line and the fourth electrode plate are made of different film layers, so that a load capacitor can be formed between the second signal line and the fourth electrode plate. The area of ​​the fourth electrode plate can be adjusted according to the size of the load capacitor on the first signal line, and then the load capacitor on the second signal line can be adjusted, so that the load capacitor on the second signal line is equal to the load capacitor on the first signal line, thereby effectively improving the display uniformity of the display panel.

[0160] Optionally, the compensation pattern includes: a body and a protruding portion extending from the body, and an orthographic projection of the second signal line on the base substrate and an orthographic projection of the compensation pattern on the base substrate have a second overlapping area, including:

[0161] The orthographic projection of the second signal line on the base substrate and the orthographic projection of the protruding portion of the compensation pattern on the base substrate have a second overlapping area.

[0162] The compensation pattern of the embodiment of the present invention includes a protruding portion, and the size of the second overlapping region can be adjusted by changing the area of ​​the protruding portion.

[0163] refer to Fig. 9 and Fig.10 The compensation pattern 41 is the second electrode plate Cst4 of the second storage capacitor. The compensation pattern 41 is close to the second signal line ( Figure 8 The protruding portion 411 on one side of the data line 11) is closer to the first signal line ( Figure 7 If the protruding portion of one side of the data line 11) is larger, the overlapping area of ​​the second signal line and the second plate Cst4 of the second storage capacitor is larger than the overlapping area of ​​the first signal line and the second plate Cst2 of the first storage capacitor.

[0164] Optionally, the display panel further comprises: a conductive connection portion located on the base substrate, the fourth electrode plate of the second storage capacitor is coupled to the conductive connection portion through a via hole, and the conductive connection portion is located between the fourth electrode plate and the power line;

[0165] The display panel further comprises: a power line located on the base substrate, the power line being coupled to the conductive connection portion;

[0166] The compensation pattern is reused as the conductive connection portion.

[0167] The embodiments of the present invention increase the load capacitance on the second signal line by adding a conductive connection portion, thereby increasing the overlapping area between the orthographic projection of the second signal line on the substrate and the orthographic projection of the conductive connection portion on the substrate, so that the load capacitance on the second signal line is equal to the load capacitance on the first signal line, thereby effectively improving the display uniformity of the display panel.

[0168] refer to Fig.11 , Fig.11 A layout diagram of another second pixel circuit provided by an embodiment of the present invention, Fig.11 Different from Fig.10 The place is that Fig.10 The shape of the second electrode plate Cst4 of the second storage capacitor is changed to distinguish it from Fig. 9 The shape of the second plate Cst2 of the first storage capacitor. Fig.11 In the embodiment, the shape of the second electrode plate Cst2 of the second storage capacitor is not changed, but the area of ​​the conductive connection portion 51 is increased in the first source-drain metal layer.

[0169] Optionally, the first signal line and the second signal line are made of a second source-drain metal layer; the second plate of the first storage capacitor and the fourth plate of the second storage capacitor are both made of a second gate metal layer; and the compensation pattern is made of a first source-drain metal layer.

[0170] The embodiments of the present invention can increase the load capacitance on the second signal line by forming a load capacitance between the second signal line located in the second source-drain metal layer and the conductive connection portion located in the first source-drain metal layer, so that the load capacitance on the second signal line is equal to the load capacitance on the first signal line, thereby effectively improving the display uniformity of the display panel.

[0171] Fig. 9 Different from Figure 7 The difference is that the area of ​​the conductive connection part 51 is increased, so that the overlapping area of ​​the second signal line and the conductive connection part 51 is increased, forming a compensation capacitor to ensure that the load capacitance on the first signal line is equal to that on the first signal line, thereby ensuring the display uniformity of the display panel.

[0172] Optionally, the compensation pattern is located in the same layer as one of the source or the drain.

[0173] refer to Fig.11 and Fig.12The compensation pattern 41 is obtained after the area of ​​the source or drain of the first light emitting control transistor T5 is increased.

[0174] Fig.12 for Fig.11 The layout diagram of the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer is as shown in Fig.11 and Fig.12 As shown, the increased area of ​​the source or drain of the first light emission control transistor T5 forms a compensation pattern 41.

[0175] Optionally, the border area includes at least an upper border area, and N compensation capacitors are arranged in the upper border area, and the N compensation capacitors correspond one-to-one to the N second signal lines, one end of each compensation capacitor is coupled to the corresponding second signal line, and the other end of each compensation capacitor is coupled to the voltage stabilization signal output end.

[0176] The embodiment of the present invention can increase the load capacitance on the second signal line by setting a compensation capacitor in the upper frame area of ​​the display panel, so that the load capacitance on the second signal line is equal to the load capacitance on the first signal line, effectively improving the display uniformity of the display panel.

[0177] refer to Fig.13 , Fig.13 A schematic diagram of another load capacitance on a second signal line provided by an embodiment of the present invention, wherein the compensation capacitor C2 is disposed in the upper frame region of the frame region 2 of the display panel. The purpose of the present application is to increase the load capacitance on the second signal line. According to the foregoing content, the following methods are adopted: increasing the length of the second signal line, increasing the overlapping area between the second signal line and the capacitor plate, increasing the overlapping area between the second signal line and the conductive connection portion, etc., and Fig.13 The improved method shown is to directly connect the second signal line to a compensation capacitor, and set the compensation capacitor in the upper frame area.

[0178] Optionally, the newly added portion of the first signal line includes at least a transversely added portion extending along a first direction, and the connecting line is parallel to the transversely added portion.

[0179] The first signal line of the embodiment of the present invention adopts a winding design, wherein the first signal line is connected to the virtual pixel circuit through a laterally newly added part.

[0180] Optionally, the first signal line is a first data line configured to provide a first data signal to the first pixel circuit;

[0181] The second signal line is a second data line configured to provide a second data signal to the second pixel circuit.

[0182] refer to Figure 5The first signal line S1 of the embodiment of the present invention is a first data line. The first data line adopts a winding design, which can prevent the first data line from passing through the FDC area and improve the light transmittance of the FDC area.

[0183] A second aspect of the present invention further provides a display device, comprising the above-mentioned display panel.

[0184] The display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will appreciate that the structure of the above-mentioned display device does not constitute a limitation on the display device, and the display device may include more or less of the above-mentioned components, or a combination of certain components, or different component arrangements. In an embodiment of the present invention, the display device includes but is not limited to a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0185] The display device may be any product or component with a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board and a backplane.

[0186] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0187] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.

[0188] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0189] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0190] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0191] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: comprising a display area and a frame area at least partially surrounding the display area, the display area comprising a first display area and a second display area, the second display area being located at least on one side of the first display area; The display panel comprises: a base substrate and a plurality of first pixel units and a plurality of second pixel units located on the base substrate, wherein the first pixel unit comprises a first light emitting device and a first pixel circuit, and the second pixel unit comprises a second light emitting device and a second pixel circuit; The first light emitting device is located in the first display area, the first pixel circuit, the second light emitting device and the second pixel circuit are located in the second display area, the orthographic projection of the second light emitting device on the base substrate and the orthographic projection of the second pixel circuit on the base substrate at least partially overlap, and the first light emitting device and the first pixel circuit are connected via a connecting wire; The display panel further includes: M first signal lines and N second signal lines located on the base substrate, N>M, and M and N are both positive integers; The first signal line is located in the second display area and is configured to provide a first driving signal to the first pixel circuit; The second signal line is located in the second display area and is configured to provide a second driving signal to the second pixel circuit; An absolute value of a difference between a load capacitance of the first signal line and a load capacitance of the second signal line is smaller than a load capacitance of the first signal line or a load capacitance of the second signal line; The second signal line includes A main body portion extending along a first direction and a compensation portion connected to the main body portion; The first signal line comprises an equivalent portion having the same length as the main portion of the second signal line and extending along the first direction and a newly added portion connected to the equivalent portion; The length of the compensation portion is equal to that of the newly added portion.

2. The display panel according to claim 1, characterized in that: The second display area further includes: a plurality of virtual pixel circuits located on the base substrate; At least part of the virtual pixel circuits are multiplexed as the first pixel circuits.

3. The display panel according to claim 1, characterized in that: Each load capacitance of the M first signal lines is equal, and each load capacitance of the N second signal lines is equal; or A load capacitance of at least one of the M first signal lines is equal to a load capacitance of at least one of the N second signal lines.

4. The display panel according to claim 1, characterized in that: The first pixel circuit at least includes a first storage capacitor, and the first storage capacitor includes a first electrode plate and a second electrode plate that are arranged opposite to each other; The orthographic projection of the first signal line on the base substrate and the orthographic projection of the second electrode plate on the base substrate have a first overlapping area; The display panel further comprises a compensation pattern located on the base substrate; The orthographic projection of the second signal line on the base substrate and the orthographic projection of the compensation pattern on the base substrate have a second overlapping area; An area of ​​the second overlapping region is greater than an area of ​​the first overlapping region.

5. The display panel according to claim 4, characterized in that: The compensation pattern includes: a body and a protruding portion extending from the body, and an orthographic projection of the second signal line on the base substrate and an orthographic projection of the protruding portion of the compensation pattern on the base substrate have a second overlapping area.

6. The display panel according to claim 4, characterized in that: The second pixel circuit includes at least one thin film transistor, a first planarization layer and a second storage capacitor; The first planarization layer is located on a side of the thin film transistor away from the substrate to cover the thin film transistor; The second light emitting device is located on a side of the first planarization layer away from the base substrate; The thin film transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, a source electrode and a drain electrode located on a side of the gate away from the substrate, and a connecting electrode located on a side of the first planarization layer away from the substrate, wherein the connecting electrode is connected to one of the source electrode and the drain electrode through a via hole in the first planarization layer; The second storage capacitor includes a third plate and a fourth plate that are arranged opposite to each other, the third plate is arranged in the same layer as the gate, and the fourth plate is located between the gate and the source.

7. The display panel according to claim 6, characterized in that: The compensation pattern is multiplexed as the fourth plate of the second storage capacitor.

8. The display panel according to claim 6, characterized in that: The first signal line and the second signal line are located in the same layer as the connection electrode.

9. The display panel according to claim 6, characterized in that: The display panel further comprises: a conductive connection portion located on the base substrate, the fourth electrode plate of the second storage capacitor being coupled to the conductive connection portion through a via hole; The display panel further comprises: a power line located on the base substrate, the power line is coupled to the conductive connection portion, and the conductive connection portion is located between the fourth electrode plate and the power line; The compensation pattern is reused as the conductive connection portion.

10. The display panel according to claim 9, characterized in that: The compensation pattern is located at the same layer as one of the source electrode or the drain electrode.

11. The display panel according to claim 1, characterized in that: The border area at least includes an upper border area, and N compensation capacitors are arranged in the upper border area. The N compensation capacitors correspond one-to-one to the N second signal lines. One end of each compensation capacitor is coupled to the corresponding second signal line, and the other end of each compensation capacitor is coupled to the voltage stabilization signal output end.

12. The display panel according to claim 1, characterized in that: The newly added portion of the first signal line at least includes a transversely added portion extending along the second direction, and the connecting line is parallel to at least the transversely added portion.

13. The display panel according to any one of claims 1 to 12, characterized in that: The first signal line is a first data line configured to provide a first data signal to the first pixel circuit; The second signal line is a second data line configured to provide a second data signal to the second pixel circuit.

14. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-13.

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