Multi-phase clock generation method, multi-phase clock generation circuit and multi-phase switching circuit

Abstract

The present invention discloses a multi-phase clock generation method, a multi-phase clock generation circuit, and a multi-phase switching circuit, which generate a high-frequency clock signal whose frequency is proportional to n; divide the high-frequency clock signal to generate n-phase clock signals, wherein the period of each phase clock signal in the n-phase clock signal is n times the period of the high-frequency clock signal, and the phase difference between each adjacent two-phase clock signal is 360 / n degrees; compare the m-th phase clock signal with a standard clock signal, and adjust the period of the high-frequency clock signal according to the comparison result, so that the period of the n-phase clock signal is consistent with the period of the standard clock signal; wherein n is an integer greater than 1, and m is a positive integer less than or equal to n. The present invention can achieve a consistent phase difference between each adjacent two-phase clock signal of the multi-phase clock, and the period of each phase clock signal is consistent with the period of the standard clock signal.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a multi-phase clock generation method, a multi-phase clock generation circuit and a multi-phase switching circuit. Background Art

[0002] Multi-phase clocks are required in many applications, such as in multi-phase interleaved parallel switching circuits. A traditional method for generating multi-phase clocks is to divide a system high-frequency clock with a fixed frequency and output multiple relatively low-frequency clock signals. For example, assuming the period of the system high-frequency clock is 10ns, when a two-phase clock signal with a period of 1μs is required, the two-phase clock signals can be set to differ by 0.5μs, that is, a difference of 50 system high-frequency clock periods. However, when a three-phase clock signal with a period of 1μs is required, the theoretical difference between each two adjacent phases of the three-phase clock signal should be 1 / 3μs, but this is difficult to achieve in practice because the difference between each two adjacent phases is required to be 100 / 3 system high-frequency clock periods, which is obviously impossible to achieve with a non-integer number of system high-frequency clock periods. Therefore, this traditional method of generating multi-phase clocks is prone to the problem of inconsistent phase differences between each two adjacent phase clock signals when certain phase numbers are required. Another traditional method of generating a multi-phase clock is to use multiple delay units to delay the clock signal and generate a multi-phase clock signal. However, as the number of multi-phase clocks required increases, adaptation problems inevitably arise between the delay units. The delay times of the delay units may be inconsistent, causing the phases of the clocks that rely on these delay units to be advanced or delayed, and the phase difference between each two adjacent phase clock signals may be inconsistent. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a multi-phase clock generation method, a multi-phase clock generation circuit and a multi-phase switching circuit to solve the technical problem of inconsistent phase difference between each adjacent two-phase clock signal of the multi-phase clock in the prior art, and to achieve that the period of each phase clock signal is consistent with the period of the standard clock signal.

[0004] The technical solution of the present invention is to provide a multi-phase clock generation method for generating an n-phase clock signal, the multi-phase clock generation method comprising:

[0005] Generate a high-frequency clock signal whose frequency is proportional to n;

[0006] Dividing the high-frequency clock signal to generate n-phase clock signals, wherein the period of each phase clock signal in the n-phase clock signals is n times the period of the high-frequency clock signal;

[0007] Comparing the m-th phase clock signal with the standard clock signal, and adjusting the period of the high-frequency clock signal according to the comparison result, so that the period of the n-phase clock signal is consistent with the period of the standard clock signal;

[0008] Wherein, n is an integer greater than 1, and m is a positive integer less than or equal to n.

[0009] Optionally, the phase difference between each two adjacent phase clock signals in the n-phase clock signals is 360 / n degrees.

[0010] Optionally, when the period of the m-th phase clock signal is greater than the period of the standard clock signal, reducing the period of the high-frequency clock signal;

[0011] When the period of the m-th phase clock signal is smaller than the period of the standard clock signal, the period of the high-frequency clock signal is increased.

[0012] Optionally, the method for generating the high-frequency clock signal includes:

[0013] obtaining a ramp signal according to the first controlled current;

[0014] The ramp signal is reset when the high-frequency clock signal is valid;

[0015] The ramp signal is compared with a reference voltage, and the high-frequency clock signal is output according to the comparison result.

[0016] Optionally, the current value of the first controlled current is proportional to n and proportional to the first current.

[0017] Optionally, the m-th phase clock signal is compared with a standard clock signal, and the reference voltage is adjusted according to the comparison result to adjust the period of the high-frequency clock signal.

[0018] Optionally, the m-th phase clock signal is compared with a standard clock signal, and the first current is adjusted according to the comparison result to adjust the period of the high-frequency clock signal.

[0019] Optionally, the step of dividing the high-frequency clock signal and generating the n-phase clock signal further includes:

[0020] obtaining a counting signal according to the high-frequency clock signal, wherein the counting signal is incremented by 1 whenever the high-frequency clock signal reaches an effective level, wherein the counting signal is reset once after n cycles of the high-frequency clock signal;

[0021] The counting signals are logically combined, and the n-phase clock signal is obtained according to the logical combination result.

[0022] In a second aspect, the present invention further provides a multi-phase clock generation circuit for generating an n-phase clock signal, the multi-phase clock generation circuit comprising:

[0023] A frequency multiplication clock generating circuit receives a control signal representing the phase number n and outputs a high-frequency clock signal having a frequency proportional to n;

[0024] a frequency division and multiplication circuit, receiving the high-frequency clock signal and the control signal, dividing the frequency of the high-frequency clock signal to output the n-phase clock signal, wherein the period of each phase clock signal in the n-phase clock signal is n times the period of the high-frequency clock signal, and the phase difference between each two adjacent phase clock signals is 360 / n degrees;

[0025] a period correction circuit receiving and comparing the m-th phase clock signal and the standard clock signal, and outputting a correction signal based on the comparison result; the frequency multiplication clock generation circuit receiving the correction signal to adjust the period of the high-frequency clock signal, thereby making the period of the n-phase clock signal consistent with the period of the standard clock signal;

[0026] Wherein, n is an integer greater than 1, and m is a positive integer less than or equal to n.

[0027] Optionally, the period correction circuit includes:

[0028] a logic circuit receiving the m-th phase clock signal and the standard clock signal and comparing them, and outputting a judgment result by indicating that the period of the high-frequency clock signal needs to be reduced when the period of the m-th phase clock signal is greater than the period of the standard clock signal; and increasing the period of the high-frequency clock signal when the period of the m-th phase clock signal is less than the period of the standard clock signal;

[0029] The adjustment circuit receives the judgment result and outputs the correction signal according to the judgment result.

[0030] Optionally, the frequency multiplier clock generating circuit includes:

[0031] a first controlled current source receiving the control signal and the first current to output a first controlled current, wherein a current value of the first controlled current is proportional to n and proportional to a current value of the first current;

[0032] a first capacitor connected to the first controlled current source;

[0033] a first switch connected in parallel with the first capacitor, the first switch being controlled by the high-frequency clock signal; when the high-frequency clock signal is invalid, the first switch is turned off, the first controlled current charges or discharges the first capacitor, and a ramp signal is output from a common end of the first capacitor and the first controlled current; and when the high-frequency clock signal is valid, the first switch is turned on, and the ramp signal is reset;

[0034] The comparison circuit receives the ramp signal and a reference voltage, performs comparisons therebetween, and outputs the high-frequency clock signal according to the comparison result.

[0035] Optionally, the frequency-multiplied clock generating circuit receives the correction signal as the reference voltage to adjust the period of the high-frequency clock signal.

[0036] Optionally, the frequency-multiplied clock generating circuit receives the correction signal as the first current to adjust the period of the high-frequency clock signal.

[0037] Optionally, the frequency division and multiplication circuit includes:

[0038] a counter receiving the high-frequency clock signal and the control signal, generating a counting signal, wherein the counting signal is incremented by 1 whenever the high-frequency clock signal reaches an effective level, and the counting signal is reset every n cycles of the high-frequency clock signal;

[0039] The clock distribution circuit receives the counting signal, performs logical combination on the counting signal, and outputs the n-phase clock signal according to the logical combination result.

[0040] In a third aspect, the present invention further provides a multi-phase switching circuit, wherein the multi-phase switching circuit includes n switching circuits, and the multi-phase switching circuit includes the multi-phase clock generating circuit.

[0041] The n-phase clocks generated by the multi-phase clock generating circuit are respectively clock signals of the n switching circuits.

[0042] The circuit structure of the present invention has the following advantages compared with the prior art: the phase difference between each two adjacent phase clock signals of the multi-phase clock is consistent, and the period of each phase clock signal is consistent with the period of the standard clock signal. In practical applications, when the number of working phases changes, the frequency of the multi-phase clock can be quickly locked. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a circuit block diagram of a multi-phase clock generation circuit according to an embodiment of the present invention;

[0044] Figure 2 is a waveform diagram of a ramp signal and a clock signal according to an embodiment of the present invention;

[0045] Figure 3 1 is a schematic diagram of the circuit structure of a multi-phase clock generating circuit according to a first embodiment of the present invention;

[0046] Figure 4 FIG. 1 is a schematic diagram of the circuit structure of a multi-phase clock generating circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments and covers any substitution, modification, equivalent method and solution made within the spirit and scope of the present invention.

[0048] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can also fully understand the present invention without description of these details.

[0049] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are simplified and not to exact proportions, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0050] refer to Figure 1 The multi-phase clock generation circuit of the embodiment of the present invention includes a frequency multiplication clock generation circuit 10, a frequency division and multiplication circuit 20, and a period correction circuit 30. The frequency multiplication clock generation circuit 10 receives a control signal representing the number of phases n to output a high-frequency clock signal clkH with a frequency proportional to n, where n is an integer greater than 1. The frequency division and multiplication circuit 20 receives the high-frequency clock signal clkH and the control signal, divides the high-frequency clock signal clkH to output the n-phase clock signals clk1, clk2...clkn. Figure 2 , wherein the period of each phase clock signal in the n-phase clock signals clk1, clk2...clkn is n times the period of the high-frequency clock signal clkH, and the phase difference between each two adjacent phase clock signals is 360 / n degrees. The period correction circuit 30 receives the m-th phase clock signal clkm and the standard clock signal clk0 and compares them, and outputs a correction signal based on the comparison result. The multiplied clock generation circuit 10 receives the correction signal to adjust the period T of the high-frequency clock signal clkH. H , so that the period of the m-th phase clock signal clkm is n·T H It is consistent with the period T0 of the standard clock signal, so that the periods of the n-phase clock signals are consistent with the period of the standard clock signal, where m is a positive integer less than or equal to n.

[0051] It should be noted that in Figure 2In the embodiment, the high-frequency clock signal and the n-phase clock signal are both active at high level. In other embodiments, the high-frequency clock signal or the n-phase clock signal may also be active at low level.

[0052] Example 1

[0053] refer to Figure 1 and Figure 3 The frequency multiplication clock generation circuit 10 in the multi-phase clock generation circuit of the first embodiment of the present invention includes a first controlled current source U01, a first capacitor C01, a first switch K01 and a comparison circuit U02. The first controlled current source U01 receives a control signal and a first current I1 to output a first controlled current. The control signal can represent the number of phases n, where n is an integer greater than 1. The current value of the first controlled current is proportional to n and proportional to the current value of the first current. For ease of understanding, Figure 3 The value of the first controlled current is set to n·I1. In other embodiments, the value of the first controlled current can also be k·n·I1, where k is any positive number. The first end of the first capacitor C01 is connected to the first controlled current source U01, and the second end is grounded. A first switch K01 is connected in parallel with the first capacitor C01. The control end of the first switch K01 receives a high-frequency clock signal clkH, which controls the first switch K01. When the high-frequency clock signal is invalid, the first switch K01 is turned off, and the first controlled current charges the first capacitor C01. The common end of the first capacitor C01 and the first controlled current outputs a ramp signal Vramp, which increases at a slope proportional to the first controlled current. When the high-frequency clock signal clkH is valid, the first switch K01 is turned on, and the ramp signal Vramp is reset. The first input terminal of the comparison circuit U02 receives the ramp signal Vramp, and the second input terminal receives the reference voltage Vref, and performs comparison to output the high-frequency clock signal clkH according to the comparison result. When the ramp signal Vramp is greater than the reference voltage Vref, the level of the high-frequency clock signal clkH jumps to a valid level. The waveforms of the corresponding ramp signal Vramp and high-frequency clock signal clkH can be referred to Figure 2 The ramp signal Vramp increases at a slope proportional to the first controlled current during each rising period, and whenever the ramp signal Vramp exceeds the reference voltage Vref, the high-frequency clock signal clkH transitions to an active level. Since the first controlled current is proportional to n, it is easy to conclude that the period of the high-frequency clock signal clkH is inversely proportional to n, and accordingly, its frequency is proportional to n. Furthermore, it should be noted that the high-frequency clock signal clkH can be active high, and in other examples, the high-frequency clock signal clkH can also be active low.

[0054] In this embodiment, the frequency division and multiplication circuit 20 includes a counter 201 and a clock distribution circuit 202. The counter 201 receives the high-frequency clock signal clkH and the control signal to generate a count signal, wherein the control signal can represent the number of phases n. The count signal is incremented by 1 whenever the high-frequency clock signal clkH reaches an active level, and is reset every n cycles of the high-frequency clock signal. The clock distribution circuit 202 receives the count signal, performs a logical combination on the count signal, and outputs the n-phase clock signal based on the result of the logical combination. Taking the counter 20 generating a 2-bit binary count signal A2A1 as an example, whenever the high-frequency clock signal clkH reaches an effective level, the count signal A2A1 is incremented by 1. When a 4-phase clock signal is required, the counter 20 cyclically generates the count signal A2A1: 00, 01, 10, 11, and resets to 00 whenever A2A1 reaches 11. When a 3-phase clock signal is required, the counter 20 cyclically generates the count signal A2A1: 00, 01, 10, and resets to 00 whenever A2A1 reaches 10. The corresponding clock distribution circuit 202 receives the 2-bit binary count signal A2A1 and performs a logical combination on the count signal A2A1. When That is, when A2A1=00, the first phase clock signal clk1 outputs a valid level pulse; when That is, when A2A1=01, the second phase clock signal clk2 outputs a valid level pulse; when That is, when A2A1=10, the third-phase clock signal clk3 outputs a valid level pulse; when A2·A1=1, that is, A2A1=11, the fourth-phase clock signal clk4 outputs a valid level pulse. Therefore, when a four-phase clock signal is required, the corresponding clock distribution circuit 202 can output valid four-phase clock signals: clk1, clk2, clk3, and clk4, wherein the period of each phase clock signal in the four-phase clock signal is four times the period of the high-frequency clock signal clkH, and the phase difference between each two adjacent phase clock signals is 90 degrees. When a three-phase clock signal is required, the corresponding clock distribution circuit 202 can output valid three-phase clock signals: clk1, clk2, and clk3, wherein the period of each phase clock signal in the three-phase clock signal is three times the period of the high-frequency clock signal, and the phase difference between each two adjacent phase clock signals is 120 degrees. From the above two specific examples, it can be known that the counter 201 can be a counter that generates any multi-bit binary counting signal or any other type of counter. The counter 201 resets the counting signal every n cycles of the high-frequency clock signal according to the requirements of any phase number n, and can be combined with a matching clock distribution circuit to obtain any number of phases of n-phase clock signals clk1, clk2...clkn. The waveforms of the high-frequency clock signal clkH and the n-phase clock signal can be referred to. Figure 2 The period of each phase clock signal in the n-phase clock signal is n times the period of the high-frequency clock signal, and the phase difference between each two adjacent phase clock signals is 360 / n degrees. It should be noted that the n-phase clock signal can be active high, and in other examples, the n-phase clock signal can also be active low.

[0055] In this embodiment, the period correction circuit 30 includes a logic circuit 301 and an adjustment circuit 302. The logic circuit 301 receives the m-th phase clock signal clkm and the standard clock signal clk0, where m is a positive integer less than or equal to n. The logic circuit 301 compares the period of the m-th phase clock signal clkm with the period of the standard clock signal clk0 to output a judgment result: when the period of the m-th phase clock signal clkm is greater than the period of the standard clock signal clk0, indicating that the period of the high-frequency clock signal clkH needs to be reduced, the INC signal is invalidated and the DEC signal is valid. When the period of the m-th phase clock signal clkm is less than the period of the standard clock signal clk0, indicating that the period of the high-frequency clock signal clkH needs to be increased, the INC signal is validated and the DEC signal is invalidated. The adjustment circuit 302 receives the judgment result and outputs the correction signal based on the judgment result. The adjustment circuit 302 specifically includes: a second current source U03, a third current source U04, a second switch K02, a third switch K03, and a second capacitor C02. The control end of the second switch K02 is connected to the INC signal output end of the logic circuit 301, and the control end of the third switch K03 is connected to the DEC signal output end of the logic circuit 301. The second current source U03 and the second switch K02 are connected in series to form a first series circuit. The third current source U04 and the third switch K03 are connected in series and in parallel with the second capacitor C02 to form a second parallel circuit. The first series circuit and the second parallel circuit are connected in series, and the connection point serves as the output end of the period correction circuit 30, which outputs a correction signal.

[0056] When the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be reduced, the INC signal is deactivated and the DEC signal is activated. The deactivated INC signal turns off the second switch K02, while the activated DEC signal turns on the third switch K03 for a period of time and then turns off, thereby partially discharging the charge on the second capacitor C02 and reducing the voltage of the correction signal. When the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be increased, the INC signal is activated and the DEC signal is deactivated. The deactivated DEC signal turns off the third switch K03, while the activated INC signal turns on the second switch K02 for a period of time and then turns off, thereby increasing the charge on the second capacitor C02 and increasing the voltage of the correction signal. Optionally, the on-time of the second switch K02 or the third switch K03 can be set to be related to the difference between the period of the m-th phase clock signal clkm and the period of the standard clock signal clk0, as well as the number of phases n.

[0057] The multiplier clock generation circuit 10 of this embodiment receives the correction signal as the reference voltage Vref. m is a positive integer less than or equal to n. When the period of the m-th phase clock signal clkm is greater than the period of the standard clock signal clk0, the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be reduced. The adjustment circuit 302 causes the voltage of the correction signal output by the period correction circuit 30 to decrease. In other words, the reference voltage Vref received by the second input terminal of the comparison circuit U02 in the multiplier clock generation circuit 10 is reduced, and the period of the high-frequency clock clkH is correspondingly reduced. When the period of the m-th phase clock signal clkm is less than the period of the standard clock signal clk0, the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be increased. The adjustment circuit 302 causes the voltage of the correction signal output by the period correction circuit 30 to increase. In other words, the reference voltage Vref received by the second input terminal of the comparison circuit U02 in the multiplier clock generation circuit 10 is increased, and the period of the high-frequency clock clkH is correspondingly increased. Because the period of each phase clock signal in the n-phase clock signal is n times the period of the high-frequency clock signal clkH, the period of each phase clock signal in the n-phase clock signal will increase as the period of the high-frequency clock clkH increases, and decrease as the period of the high-frequency clock decreases, thereby achieving the period of the n-phase clock signal being consistent with the period of the standard clock signal clk0.

[0058] It should be noted that, for ease of implementation, in this embodiment, the second end of the first capacitor is grounded. That is, the voltage at the second end of the first capacitor is constantly zero. The period of the high-frequency clock signal clkH is adjusted by adjusting the reference voltage Vref, thereby ensuring that the periods of the n-phase clock signals are consistent with those of the standard clock signal. In other embodiments, the second end of the first capacitor may not be grounded, but may instead receive a first voltage. For example, in one embodiment, the second end of the first capacitor receives a first voltage, where the first voltage is less than the reference voltage Vref. When the high-frequency clock signal clkH is inactive, the first switch is turned off, the first controlled current charges the first capacitor, and the common end of the first capacitor and the first controlled current outputs a rising ramp signal Vramp. When the high-frequency clock signal clkH is active, the first switch K01 is turned on, resetting the ramp signal Vramp to the first voltage. When the ramp signal Vramp is greater than the reference voltage Vref, the high-frequency clock signal clkH transitions to an active level. In another embodiment, the reference voltage Vref can be set to be less than the first voltage V1. When the high-frequency clock signal is invalid, the first switch is turned off, the first controlled current discharges the first capacitor, and the common terminal of the first capacitor and the first controlled current outputs a decreasing ramp signal Vramp. When the high-frequency clock signal clkH is valid, the first switch K01 is turned on, and the ramp signal Vramp is reset to the first voltage. When the ramp signal Vramp is less than the reference voltage Vref, the level of the high-frequency clock signal clkH jumps to a valid level. In these embodiments, the period of the high-frequency clock signal clkH can be adjusted by adjusting either the reference voltage Vref or the first voltage, thereby ensuring that the periods of the n-phase clock signals are consistent with the period of the standard clock signal clk0.

[0059] The multiphase clock generation circuit of this embodiment can be used to generate a multiphase clock signal with a consistent phase difference between each two adjacent phase clock signals. Furthermore, the period of the high-frequency clock signal can be adjusted by adjusting the reference voltage received by the comparison circuit in the frequency-multiplied clock generation circuit, thereby ensuring that the period of each phase clock signal is consistent with that of the standard clock signal. In practical applications, when the number of operating phases changes, the frequency of the multiphase clock can be quickly locked by rapidly adjusting the current value of the first controlled current.

[0060] Example 2

[0061] refer to Figure 1 and Figure 4The frequency multiplication clock generating circuit 10 in the multi-phase clock generating circuit of the second embodiment of the present invention is basically the same as the frequency multiplication clock generating circuit of the first embodiment. The difference is that the frequency multiplication clock generating circuit 10 of this embodiment receives the correction signal output by the period correction circuit 30 as the first current I1, which will not be repeated here.

[0062] The frequency division and multiplication circuit 20 of this embodiment is identical to the frequency division and multiplication circuit of the first embodiment, and will not be described again here.

[0063] The period correction circuit 30 of this embodiment includes a logic circuit 301 and a regulation circuit 302. The logic circuit 301 of this embodiment is identical to the logic circuit of the first embodiment and is not described in detail here. The regulation circuit 302 of this embodiment includes a voltage regulation circuit 3021 and a voltage-to-current conversion circuit 3022. The voltage regulation circuit 3021 of this embodiment includes a second current source U03, a third current source U04, a second switch K02, a third switch K03, and a second capacitor C02. The control end of the second switch K02 is connected to the DEC signal output end of the logic circuit 301, and the control end of the third switch K03 is connected to the INC signal output end of the logic circuit 301. The second current source U03 and the second switch K02 are connected in series to form a first series circuit. The third current source U04 and the third switch K03 are connected in series to form a second parallel circuit in parallel with the second capacitor C02. The first series circuit and the second parallel circuit are connected in series, and the connection point is connected to the input end of the voltage-to-current circuit 3022. The output end of the voltage-to-current circuit 3022 serves as the output end of the regulation circuit 302, outputting a correction signal, which is a current signal. For example, the regulation circuit 302 includes a voltage-controlled current source U05, whose first input end receives the voltage at the connection point, whose second input end is grounded, and whose output end outputs the correction signal.

[0064] When the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be reduced, the INC signal is deactivated and the DEC signal is activated. The deactivated INC signal turns off the third switch K03, while the DEC signal turns on the second switch K02 for a period of time and then turns it off, thereby increasing the charge on the second capacitor C02 and raising the connection point voltage. The voltage-controlled current source U05 converts the connection point voltage into a correction signal at a certain ratio, thereby increasing the current value of the correction signal. When the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be increased, the INC signal is activated and the DEC signal is deactivated. The deactivated DEC signal turns off the second switch K02, while the activated INC signal turns on the third switch K03 for a period of time and then turns it off, thereby discharging a portion of the charge on the second capacitor C02 and reducing the connection point voltage. The voltage-controlled current source U05 converts the connection point voltage into a correction signal at a certain ratio, thereby reducing the current value of the correction signal. Optionally, the on-time of the second switch K02 or the third switch K03 may be set to be related to the difference between the period of the m-th phase clock signal clkm and the period of the standard clock signal clk0 , and to the phase number n.

[0065] The frequency multiplication clock generation circuit 10 of this embodiment receives the correction signal as the first current I1. m is a positive integer less than or equal to n. When the period of the m-th phase clock signal clkm is greater than the period of the standard clock signal clk0, the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be reduced. The adjustment circuit 302 increases the current value of the correction signal output by the period correction circuit 30. The first current I1 received by the first controlled current source U01 in the frequency multiplication clock generation circuit 10 increases, and the first controlled current output by the first controlled current source U01 increases. The absolute value of the slope of the ramp signal Vramp also increases. Accordingly, the high-frequency clock When the period of the m-th phase clock signal clkm is less than the period of the standard clock signal clk0, the logic circuit 301 determines that the period of the high-frequency clock signal clkH needs to be increased. The adjustment circuit 302 reduces the current value of the correction signal output by the period correction circuit 30, reduces the first current I1 received by the first controlled current source U01 in the frequency-multiplied clock generation circuit 10, reduces the first controlled current output by the first controlled current source U01, and reduces the absolute value of the slope of the ramp signal. Correspondingly, the period of the high-frequency clock signal clkH increases. Because the period of each phase clock signal in the n-phase clock signal is n times the period of the high-frequency clock signal clkH, the period of each phase clock signal in the n-phase clock signal increases as the period of the high-frequency clock signal clkH increases and decreases as the period of the high-frequency clock signal clkH decreases, thereby achieving the period of each phase clock signal being consistent with the period of the standard clock signal clk0.

[0066] The multiphase clock generation circuit of this embodiment can be used to generate a multiphase clock signal with a consistent phase difference between each two adjacent phase clock signals. Furthermore, the slope of the ramp signal can be adjusted by adjusting the first current received by the first controlled current source in the frequency-multiplied clock generation circuit, thereby adjusting the period of the high-frequency clock signal. This ensures that the period of each phase clock signal is consistent with that of the standard clock signal. In practical applications, when the number of operating phases changes, the frequency of the multiphase clock can be quickly locked by rapidly adjusting the current value of the first controlled current.

[0067] The above-described embodiments do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the above-described embodiments shall be included in the scope of protection of this technical solution.

Claims

1. A multi-phase clock generation method for generating n-phase clock signals, characterized in that: include: Generate a high-frequency clock signal whose frequency is proportional to n; Dividing the high-frequency clock signal to generate n-phase clock signals, wherein the period of each phase clock signal in the n-phase clock signals is n times the period of the high-frequency clock signal; Comparing the m-th phase clock signal with the standard clock signal, and adjusting the period of the high-frequency clock signal according to the comparison result, so that the period of the n-phase clock signal is consistent with the period of the standard clock signal; Wherein, n is an integer greater than 1, and m is a positive integer less than or equal to n; the method for generating the high-frequency clock signal includes: obtaining a ramp signal according to the first controlled current; The ramp signal is reset when the high-frequency clock signal is valid; The ramp signal is compared with a reference voltage, and the high-frequency clock signal is output according to the comparison result.

2. The clock generation method according to claim 1, wherein: The phase difference between each two adjacent phase clock signals in the n-phase clock signals is 360 / n degrees.

3. The clock generation method according to claim 1, wherein: When the period of the m-th phase clock signal is greater than the period of the standard clock signal, reducing the period of the high-frequency clock signal; When the period of the m-th phase clock signal is smaller than the period of the standard clock signal, the period of the high-frequency clock signal is increased.

4. The clock generation method according to claim 1, wherein: The current value of the first controlled current is proportional to n and proportional to the first current.

5. The clock generation method according to claim 4, wherein: The m-th phase clock signal is compared with a standard clock signal, and the reference voltage is adjusted according to the comparison result to adjust the period of the high-frequency clock signal.

6. The clock generation method according to claim 4, wherein: The m-th phase clock signal is compared with a standard clock signal, and the first current is adjusted according to the comparison result to adjust the period of the high-frequency clock signal.

7. The clock generation method according to claim 1, wherein: The step of dividing the high-frequency clock signal and generating the n-phase clock signal further includes: obtaining a counting signal according to the high-frequency clock signal, wherein the counting signal is incremented by 1 whenever the high-frequency clock signal reaches an effective level, wherein the counting signal is reset once after n cycles of the high-frequency clock signal; The counting signals are logically combined, and the n-phase clock signal is obtained according to the logical combination result.

8. A multi-phase clock generating circuit, generating n-phase clock signals, characterized in that: include: A frequency multiplication clock generating circuit receives a control signal representing the phase number n and outputs a high-frequency clock signal having a frequency proportional to n; a frequency division and multiplication circuit, receiving the high-frequency clock signal and the control signal, dividing the frequency of the high-frequency clock signal to output the n-phase clock signal, wherein the period of each phase clock signal in the n-phase clock signal is n times the period of the high-frequency clock signal, and the phase difference between each two adjacent phase clock signals is 360 / n degrees; a period correction circuit receiving and comparing the m-th phase clock signal and the standard clock signal, and outputting a correction signal based on the comparison result; the frequency multiplication clock generation circuit receiving the correction signal to adjust the period of the high-frequency clock signal, thereby making the period of the n-phase clock signal consistent with the period of the standard clock signal; Wherein, n is an integer greater than 1, and m is a positive integer less than or equal to n; the frequency multiplier clock generating circuit includes: a first controlled current source receiving the control signal and the first current to output a first controlled current, wherein a current value of the first controlled current is proportional to n and proportional to a current value of the first current; a first capacitor connected to the first controlled current source; a first switch connected in parallel with the first capacitor, the first switch being controlled by the high-frequency clock signal; when the high-frequency clock signal is invalid, the first switch is turned off, the first controlled current charges or discharges the first capacitor, and a ramp signal is output from a common end of the first capacitor and the first controlled current; and when the high-frequency clock signal is valid, the first switch is turned on, and the ramp signal is reset; The comparison circuit receives the ramp signal and a reference voltage, performs comparisons therebetween, and outputs the high-frequency clock signal according to the comparison result.

9. The clock generating circuit according to claim 8, wherein: The period correction circuit comprises: a logic circuit receiving the m-th phase clock signal and the standard clock signal and comparing them, and outputting a judgment result by indicating that the period of the high-frequency clock signal needs to be reduced when the period of the m-th phase clock signal is greater than the period of the standard clock signal; and increasing the period of the high-frequency clock signal when the period of the m-th phase clock signal is less than the period of the standard clock signal; The adjustment circuit receives the judgment result and outputs the correction signal according to the judgment result.

10. The clock generating circuit according to claim 8, wherein: The frequency-multiplied clock generating circuit receives the correction signal as the reference voltage to adjust the period of the high-frequency clock signal.

11. The clock generating circuit according to claim 8, wherein: The frequency-multiplied clock generating circuit receives the correction signal as the first current to adjust the period of the high-frequency clock signal.

12. The clock generating circuit according to claim 8, wherein: The frequency division and multiplication circuit comprises: a counter receiving the high-frequency clock signal and the control signal, generating a counting signal, wherein the counting signal is incremented by 1 whenever the high-frequency clock signal reaches an effective level, and the counting signal is reset every n cycles of the high-frequency clock signal; The clock distribution circuit receives the counting signal, performs logical combination on the counting signal, and outputs the n-phase clock signal according to the logical combination result.

13. A multi-phase switching circuit, comprising n switching circuits, wherein the multi-phase switching circuit comprises the multi-phase clock generating circuit according to any one of claims 8 to 12, The n-phase clocks generated by the multi-phase clock generating circuit are respectively clock signals of the n switching circuits.

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