Chip failure analysis method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose a chip failure analysis method and device, electronic equipment and a storage medium. The method comprises: inputting a plurality of real drop postures of a mainboard to a trained chip failure analysis model; the mainboard comprises one or more test chips; outputting a predicted stress value of each test chip under each real drop posture by the chip failure analysis model, and generating a predicted stress value array corresponding to each real drop posture according to the predicted stress value of each test chip under each real drop posture; when one or more failed chips are detected from the mainboard, determining a target drop posture causing the failure of the failed chip according to the predicted stress value in the predicted stress value array corresponding to each real drop posture of each failed chip. By implementing the embodiments of the present application, the failure scenario of the chip can be accurately and efficiently reproduced, thereby realizing the failure analysis of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of fault diagnosis, in particular to a chip failure analysis method and device, electronic equipment and storage medium. BACKGROUND

[0002] In recent years, with the development of the consumer electronics industry, people's requirements for the quality and reliability of electronic devices are increasing, so the failure analysis of electronic components has become more and more important. In the production, testing and use of electronic components, failure analysis can find out the failure causes and failure mechanisms of electronic components, which is beneficial to timely correct errors in design and development.

[0003] In the current consumer electronics industry, drop reliability test is often used for failure analysis of electronic components. According to whether the drop posture is determined, the drop reliability test can be divided into directional drop test and random drop test. Among them, for mobile phone products, the tumble drop test is a typical random drop test, which is used to evaluate the impact resistance of the mobile phone.

[0004] The tumble drop test is a repeated automated drop test, and the drop posture is uncertain. After a certain number of drop tests, the whole machine chip with poor structural reliability has a de-soldering behavior, and the de-soldering of the chip will cause a functional failure problem. At the first time of problem exposure, the failure mechanism of chip de-soldering needs to be analyzed. In the whole failure mechanism reproduction and scheme rectification process, the confirmation of the failure scene is undoubtedly a key link. Correct reasoning of the failure scene can effectively assist in solving the problem and shortening the development cycle. After the failure scene is reproduced, the structure and hardware engineers will issue a scheme for reliability optimization according to the failure mechanism reproduced by the simulation engineer, and close the problem.

[0005] The existing method for reproducing the failure scene is that the analyst quickly locates the problem reason based on solid mechanics theory and rich failure analysis experience, and directly analyzes the failure scene according to the failure phenomenon. However, the key of this method lies in the analysis ability and technical ability of engineers, but for most engineers, a large amount of project experience and solid theoretical foundation are needed to make good speculation. Even for very excellent engineers, there is a great possibility of misjudgment. Therefore, how to accurately and efficiently reason out the failure scene according to the failure condition has become a key technical problem in tumble drop failure analysis. SUMMARY

[0006] The embodiments of the present application disclose a chip failure analysis method and device, electronic equipment and storage medium, which can accurately and efficiently reproduce the failure scene of the chip, thereby realizing the failure analysis of the chip.

[0007] The chip failure analysis method disclosed by the embodiments of the present application is characterized in that the method comprises:

[0008] a plurality of real drop postures of a mainboard are input into the trained chip failure analysis model; the mainboard comprises one or more test chips;

[0009] the chip failure analysis model outputs a predicted stress value borne by each test chip under each real drop posture, and generates a predicted stress value array corresponding to each real drop posture according to the predicted stress value borne by each test chip under each real drop posture;

[0010] when one or more failed chips are detected from the mainboard, a target drop posture causing the failure of each failed chip is determined according to the predicted stress value in the predicted stress value array corresponding to each real drop posture of each failed chip.

[0011] As an optional implementation, the determination of the target drop posture causing the failure of each failed chip comprises:

[0012] the real drop posture corresponding to the maximum predicted stress value is determined as the target drop posture causing the failure of the failed chip; the maximum predicted stress value is determined according to the predicted stress value in the predicted stress value array corresponding to each real drop posture of the failed chip.

[0013] As an optional implementation, the method further comprises:

[0014] each predicted stress value in each predicted stress value array is sorted in descending order, and a recurrence matrix is determined according to the sorting result and each real drop posture; each row of the recurrence matrix comprises a real drop posture and the predicted stress value corresponding to the real drop posture after sorting;

[0015] and the determination of the real drop posture corresponding to the maximum predicted stress value as the target drop posture causing the failure of the failed chip comprises:

[0016] for each failed chip, each column included in the recurrence matrix is sequentially queried until the first predicted stress value corresponding to the failed chip is queried as the maximum predicted stress value;

[0017] the real drop posture included in the row where the maximum predicted stress value is located is determined as the target drop posture causing the failure of the failed chip.

[0018] As an optional implementation, the method further comprises:

[0019] Each of the predicted stress values in each of the predicted stress value arrays is sorted in descending order, and a recurrence matrix is determined according to the sorting result and the real drop posture; each row of the recurrence matrix includes a real drop posture and the predicted stress value corresponding to the real drop posture after sorting;

[0020] Each of the predicted stress values in the recurrence matrix is mapped to the number of the test chip corresponding to each of the predicted stress values;

[0021] And the real drop posture corresponding to the maximum predicted stress value is determined as the target drop state causing the failure of the failed chip, comprising:

[0022] For each of the failed chips, each column included in the recurrence matrix is sequentially queried until the first number corresponding to the failed chip is queried out; the first queried number is the number of the test chip corresponding to the maximum predicted stress value;

[0023] The real drop posture included in the row where the first queried number is located is determined as the target drop state causing the failure of the failed chip.

[0024] As an optional implementation, the method further comprises:

[0025] Based on the predicted stress value array corresponding to each of the real drop postures, the test chip corresponding to the minimum stress value in the predicted stress value array is selected as a candidate reliable chip;

[0026] The test chip with the most repeated words in the candidate reliable chip is selected as a reliable chip.

[0027] As an optional implementation, the method further comprises:

[0028] The reliable chip is stored into a reference optimization scheme library; the reference optimization scheme library includes the project number corresponding to the reliable chip and the structure information of the reliable chip;

[0029] A solution including the structure information of the reliable chip is sent to the equipment corresponding to the project number through the reference optimization scheme library.

[0030] As an optional implementation, the method further comprises:

[0031] A plurality of sample drop postures of the mainboard and sample stress values received by each of the test chips under each of the sample drop postures are obtained.

[0032] inputting the sample drop posture and the sample stress value borne by each test chip under each sample drop posture into the chip failure analysis model to be trained to obtain a training stress value output by the chip failure analysis model to be trained;

[0033] calculating a training loss according to the sample stress value and the training stress value, and adjusting a weight parameter of the chip failure analysis model to be trained according to the training loss to obtain a trained chip failure analysis model.

[0034] The chip failure analysis device disclosed in the embodiments of the present application comprises:

[0035] an input module configured to input a plurality of real drop postures of a mainboard into the trained chip failure analysis model, wherein the mainboard comprises one or more test chips;

[0036] a prediction module configured to output a predicted stress value borne by each test chip under each real drop posture through the chip failure analysis model, and generate a predicted stress value array corresponding to each real drop posture according to the predicted stress value borne by each test chip under each real drop posture;

[0037] a determination module configured to, when one or more failed chips are detected from the mainboard, determine a target drop posture causing the failure of each failed chip according to the predicted stress value in the predicted stress value array corresponding to each real drop posture of each failed chip.

[0038] The embodiments of the present application disclose an electronic device, comprising a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to make the processor implement any chip failure analysis method disclosed in the embodiments of the present application.

[0039] The embodiments of the present application disclose a computer readable storage medium storing a computer program, wherein the computer program makes a computer execute any chip failure analysis method disclosed in the embodiments of the present application.

[0040] Compared with the related art, the embodiments of the present application have the following beneficial effects:

[0041] The multiple real drop postures of the mainboard are input into the trained chip failure analysis model to output predicted stress values of one or more test chips included in the mainboard under each real drop posture, and a predicted stress value array corresponding to each real drop posture is generated according to the predicted stress values of the test chips under each real drop posture; when a failure chip is detected from the mainboard, the real drop posture corresponding to the failure chip is queried from the predicted stress value array as a target drop posture causing the failure of the failure chip. The chip failure analysis model outputs the predicted stress values of the test chips under each real drop posture in the embodiments of the present application, to obtain the predicted stress value array corresponding to each real drop posture, and the target drop posture of the failure chip is quickly determined according to the predicted stress value array, so that the failure scene of the chip can be accurately and efficiently reproduced, thereby realizing the failure analysis of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0043] Figure 1 is a structural schematic diagram of a chip failure analysis system disclosed by the embodiments of the present application;

[0044] Figure 2 is a flowchart of a chip failure analysis method disclosed by the embodiments of the present application;

[0045] Figure 3 is a schematic diagram of a drum drop scene disclosed by the embodiments of the present application;

[0046] Figure 4 is a flowchart of another chip failure analysis method disclosed by the embodiments of the present application;

[0047] Figure 5 is a flowchart of another chip failure analysis method disclosed by the embodiments of the present application;

[0048] Figure 6 is a flowchart of an expert system architecture disclosed by the embodiments of the present application;

[0049] Figure 7 is a flowchart of another chip failure analysis method disclosed by the embodiments of the present application;

[0050] Figure 8 is a flowchart of a neural network training and prediction instance disclosed by the embodiments of the present application;

[0051] Figure 9 is a structural schematic diagram of a chip failure analysis device disclosed by an embodiment of the present application.

[0052] Figure 10 is a structural schematic diagram of an electronic device disclosed by an embodiment of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0054] It should be noted that the terms “include” and “have” and any variations thereof in the embodiments of the present application and the drawings are intended to cover the inclusions without the exclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed or optionally further includes other steps or units inherent to the process, method, product or device.

[0055] The embodiments of the present application disclose a chip failure analysis method and device, an electronic device and a storage medium, which can accurately and efficiently reproduce the failure scenario of a chip. The following will be described in detail respectively.

[0056] Figure 1 is a structural schematic diagram of a chip failure analysis system disclosed by an embodiment of the present application. The chip failure analysis method provided by the embodiments of the present application can be applied to the chip failure analysis system as shown in Figure 1 The chip failure analysis system includes an electronic device 101, a mainboard 102, a test chip 103 and a server 104.

[0057] The electronic device 101 can be a personal computer, a notebook computer, a smart phone, a tablet computer, a wearable device and the like, but is not limited thereto.

[0058] The mainboard 102 is one of the most important components in the electronic device 101. The mainboard 102 can be the main circuit board in the electronic device such as a personal computer, a notebook computer, a smart phone, a tablet computer and a wearable device.

[0059] The test chip 103 can be any one of a plurality of chips in the mainboard 102. The test chip 103 can be a power management chip, a storage chip, a radio frequency chip and the like, but is not limited thereto.

[0060] The server 104 can be a stand-alone server or a server cluster composed of multiple servers.

[0061] The electronic device 101 can communicate wirelessly with the server 104.

[0062] The electronic device 101 can input the plurality of real drop postures of the mainboard 102 into the trained chip failure analysis model. Alternatively, the chip failure analysis model can be trained in the server 104 and stored in the server 104. The electronic device 101 can input the plurality of real drop postures of the mainboard 102 into the chip failure analysis model in the server 104, output the predicted stress values of each test chip 103 under each real drop posture through the chip failure analysis model of the server 104, and generate a predicted stress value array according to the predicted stress values of each test chip 103 under each real drop posture. The server 104 can transmit the predicted stress value array back to the electronic device 101. When the electronic device 101 detects one or more failed chips from the mainboard 102, the electronic device 101 determines the target drop posture that causes the failure of the failed chip according to the predicted stress values of each failed chip in the predicted stress value array corresponding to the plurality of real drop postures, respectively.

[0063] In some alternative embodiments, the chip failure analysis model can be trained in the server 104, and the electronic device 101 can download the trained chip failure analysis model from the server 104; or the chip failure analysis model can be trained directly in the electronic device 101 and stored in the electronic device 101. The electronic device 101 can input the plurality of real drop postures of the mainboard 102 into the chip failure analysis model in the electronic device 101, output the predicted stress values of each test chip 103 under each real drop posture through the chip failure analysis model of the electronic device 101, and generate a predicted stress value array according to the predicted stress values of each test chip 103 under each real drop posture. When the electronic device 101 detects one or more failed chips from the mainboard 102, the electronic device 101 determines the target drop posture that causes the failure of the failed chip according to the predicted stress values of each failed chip in the predicted stress value array corresponding to the plurality of real drop postures, respectively.

[0064] Please refer to Figure 2 , Figure 2 is a flowchart of a chip failure analysis method disclosed in an embodiment of the present application. Failure analysis includes reproducing the failure cause of a chip, failure mechanism, and giving reference suggestions. Among them, Figure 2 The chip failure analysis method described is applicable to electronic devices such as mobile phones, notebook computers, wearable devices, and fields related to impact analysis, and the embodiments of the present application are not limited.

[0065] As Figure 2 shown, the chip failure analysis method can include the following steps:

[0066] 201, input a plurality of real drop postures of the mainboard to the trained chip failure analysis model.

[0067] The mainboard can be a main circuit board of an electronic device such as a mobile phone, a notebook computer, and a wearable device. The mainboard includes one or more test chips. The test chips can be power management chips, memory chips, radio frequency chips, etc. on the mainboard, but are not limited thereto.

[0068] For electronic devices, a drop reliability test can use a drum drop test. The drum drop test is a repeated automatic drop test, and in each drum drop, the drop posture of the electronic device is uncertain, so the drum drop test is a random drop test. The drum drop can be used to evaluate the impact resistance of the mobile phone. After a certain number of drop tests, the chips with poor structural reliability in the mainboard of the electronic device have a de-soldering behavior, and the de-soldering of the chips causes functional failure. Because the failure mechanism of the chip de-soldering can be analyzed, the failure scenario of the chip can be reproduced.

[0069] As Figure 3 described, Figure 3 is a drum drop scene schematic diagram disclosed by an embodiment of the present application. The drum drop scene can be defined as that the electronic device is impacted with the floor with the front down or the back down, and one corner of the four corners of the electronic device first contacts the floor. To parameterize the drop scene, a coordinate system composed of an x-axis, a y-axis, and a z-axis can be established, and the x-axis, the y-axis, and the z-axis are perpendicular to each other. The coordinate system takes the geometric center of the electronic device as the origin, the z-axis is perpendicular to the ground, and the drop posture of the mainboard of the electronic device can be represented by the rotation angle b around the x-axis and the rotation angle a around the y-axis of the entire electronic device. Therefore, the real drop posture can include the rotation angle b around the x-axis and the rotation angle a around the y-axis when the mainboard in the electronic device drops onto the ground.

[0070] Chip de-soldering mainly comes from two types of impact modes: the screen face of the mobile phone impacts the ground and the back cover face of the mobile phone impacts the ground. For the same type of impact mode, different drop postures, i.e., the rotation angles (a, b) of the whole machine around the geometric center in the x-axis and the y-axis, determine the de-soldering risk of the mainboard chip. Therefore, for the same type of impact mode, the failure scene can be expressed by the real drop posture (a, b), and the feasible region of the two rotation angles is [-c, c], and the real drop posture can be discretized. It is assumed that there are m drop postures, and the real drop posture can be represented as: (a j ,b j ), where j ∈ [1, m], j is an integer; a j ,b j ∈ [-c, c].

[0071] Typical chip packaging methods include round solder balls and square solder balls. For the same type of packaging method, the stress value of the chip solder ball under drop conditions can be calculated to represent the whole machine. The stress value can be a MISES stress. For drop posture (a, b), assuming that there are n chips on the motherboard, the stress value of the chip solder ball can be represented as: mise i (a j ,b j ), where i ∈ [1, n], i is an integer. The stress value can be used to evaluate fatigue, damage, etc., and is a mechanical concept in elastic-plastic mechanics, which means that when the shape of the unit changes and the strain energy reaches a certain level, the material begins to be damaged. Therefore, the stress value can be used to represent the failure phenomenon of the chip.

[0072] Alternatively, the stress value can be obtained by a stress sensor, strain analysis software, and manual calculation.

[0073] In some embodiments, the stress value can be obtained by finite element analysis. Finite element analysis (FEA) is a process for predicting stress effects. Finite element analysis can divide an actual continuous three-dimensional model into finite elements to obtain the stress value of each element. Finite element modeling (FEM) can divide a geometric model into a grid using correct and appropriate finite elements to obtain a finite element model. The finite element model is a simulation model used to simulate the mechanical properties of the structure.

[0074] In an alternative embodiment, a parameterized finite element simulation model can be established with sample drop postures (a, b) as independent variables. The sample stress values of each test chip in the motherboard under each sample drop posture can be obtained by finite element analysis. Finite element analysis can accurately obtain the sample stress values of each test chip under each sample drop posture, and a large number of training sample sets can be obtained by a small amount of calculation, saving the calculation cost.

[0075] 202. Output the predicted stress values of each test chip under each real drop posture by the chip failure analysis model, and generate a predicted stress value array corresponding to each real drop posture according to the predicted stress values of each test chip under each real drop posture.

[0076] Each real drop posture corresponds to a predicted stress value array, and each predicted stress value array includes the predicted stress values of each test chip in the motherboard under the same real drop posture. The predicted stress value can be used to describe the failure phenomenon of the test chip. Alternatively, the predicted stress value can be a predicted MISES stress value.

[0077] The chip failure analysis model can be a neural network model. The sample drop posture and the sample stress value borne by each test chip under each sample drop posture are taken as a training sample set of the chip failure analysis model, and the training sample set includes an input data set and an output data set. The input data set is (a j ,b j ), where j is an integer, and a j ,b j ∈[-c,c]; the output data set is mise i (a j ,b j ), where i is an integer. Since there is a high nonlinearity between the drop posture and the stress value in the drum drop test, a neural network can be used for function approximation to obtain the mapping relationship between the motherboard drop posture and the stress value. By inputting the real drop posture into the trained chip failure analysis model, the predicted stress value borne by each test chip under each real drop posture can be predicted.

[0078] 203. When one or more failed chips are detected from the motherboard, the target drop posture causing the failure of the failed chip is determined according to the predicted stress value in the predicted stress value array corresponding to each failed chip under a plurality of real drop postures.

[0079] The failed chip can be a test chip that fails due to delamination. Assuming that each test chip of the same type of package form on the motherboard is numbered and identified, the test chip name can be represented by chip i , that is, the name of the i th test chip is chip i , and for the failure scenario (a j ,b j ), the stress value of the i th chip is mise i (a j ,b j ).

[0080] Since delamination occurs in the s th test chip during the drum drop test, the predicted stress value representing the s th test chip is the maximum, that is: mise i (a j ,b j ) max =mise s (a j ,b j ) (1)

[0081] wherein, is the real drop posture, and mise i (a j ,b j ) maxThe maximum value of the predicted stress value of each test chip under the real drop posture mise s (a j ,b j ) is the predicted stress value of the s-th test chip under the real drop posture.

[0082] Suppose that two test chips are simultaneously delaminated, which is less likely to occur. If the s-th and h-th test chips are simultaneously delaminated, both of the two test chips are marked as the maximum value, without distinguishing the size. When multiple test chips are delaminated, the representation method is consistent, and there is: mise i (a j ,b j ) max = mise s (a j ,b j ), mise h (a j ,b j ) (2)

[0083] That is, under a drop posture, which chip delaminates first indicates that the stress value of the chip is the largest.

[0084] In some embodiments, when one or more failed chips are detected from the mainboard, a real drop posture corresponding to the maximum predicted stress value is determined as a target drop state causing the failed chips to fail. The maximum predicted stress value is determined according to the predicted stress values in the array of predicted stress values respectively corresponding to the multiple real drop postures.

[0085] For example, when a failed chip is detected, the predicted stress value of the failed chip under each real drop posture is queried from the array of predicted stress values respectively corresponding to the multiple real drop postures, and the real drop posture corresponding to the maximum predicted stress value is determined as the target drop state causing the failed chip to fail. When N failed chips are detected, the above steps are repeated N times. N is a positive integer greater than or equal to 1.

[0086] ​In an optional embodiment, a stress value threshold can be used to determine the target drop posture that causes the failed chip to fail. For example, the predicted stress values of the failed chip corresponding to each real drop posture are compared with the stress value threshold, and one or more real drop postures corresponding to the predicted stress values greater than the stress value threshold are determined as the target drop postures that cause the failed chip to fail. That is, the failed chip can be caused by multiple real drop postures, and the stress value threshold can be used to determine multiple failure scenarios. Optionally, the stress value threshold is adjusted to a suitable value, and the real drop posture corresponding to the only predicted stress value greater than the stress value threshold can be determined as the target drop posture that causes the failed chip to fail.

[0087] The embodiment of the present application outputs the predicted stress values of each test chip under each real drop posture through the chip failure analysis model, to obtain an array of predicted stress values corresponding to each real drop posture, and quickly determines the target drop posture corresponding to the failed chip according to the predicted stress value of the failed chip in the array of predicted stress values, so as to accurately and efficiently reproduce the failure scenario of the chip and realize the failure analysis of the chip.

[0088] In the related art, in order to reproduce the failure scenario, the most likely scenario can also be modeled and calculated, and the failure scenario can be derived by comparing the simulation analysis calculation result with the failure phenomenon. However, the key of the modeling calculation lies in the data coverage, and a small amount of calculation is not enough to cover the failure scenario, but a large amount of calculation to cover the failure scenario brings huge calculation cost. According to the supercomputing center billing standard-0.06 yuan / cpu / h, 48 cpu, 22 h are consumed for a single scene calculation, and the simulation calculation cost of a single scene is 63 yuan. If a is used for data coverage, if 1 degree is used for coverage, the calculation amount is 121, and the calculation cost is about 0.7 million yuan. If 0.1 degree is used for coverage, the calculation amount is 12100, and the calculation cost is about 700 thousand yuan. The data coverage is too small, the coverage accuracy is insufficient, and the data coverage amount increases, which requires huge calculation cost.

[0089] Therefore, the embodiment of the present application takes the drop posture as the failure scenario and takes the stress value as the failure phenomenon, establishes the functional relationship between the failure scenario and the failure phenomenon through the chip failure analysis model, parameterizes the failure scenario and the failure phenomenon, saves a large amount of calculation cost, and can accurately, efficiently and at low cost infer the failure scenario of the chip according to the failure phenomenon of the chip.

[0090] It should be noted that in some possible embodiments, the foregoing chip failure analysis method is not only applicable to chip delamination, but also applicable to delamination of other electronic devices, such as capacitors, transistors, relays, sensors, etc.

[0091] Please refer toFigure 4 , Figure 4 is a flowchart of another chip failure analysis method disclosed in embodiments of the present application. As shown in Figure 4 , the method comprises the following steps:

[0092] 401. Input a plurality of real drop postures of a mainboard to the trained chip failure analysis model.

[0093] The chip failure analysis model can be a neural network model.

[0094] 402. Output the predicted stress values of each test chip under each real drop posture by the chip failure analysis model, and generate a predicted stress value array corresponding to each real drop posture according to the predicted stress values of each test chip under each real drop posture.

[0095] There are N test chips on the mainboard. The normalized predicted stress value of the i-th test chip under the real drop posture (a j ,b j ) can be obtained by the chip failure analysis model. The a j in the real drop posture is the rotation angle around the y-axis when the mainboard falls to the ground, and the b j is the rotation angle around the x-axis when the mainboard falls to the ground.

[0096] 403. Sort each predicted stress value in each predicted stress value array in descending order, and determine a recurrence matrix according to the sorting result and each real drop posture.

[0097] Each row of the recurrence matrix includes a real drop posture and the sorted predicted stress value corresponding to the real drop posture. Optionally, the predicted stress value can be a normalized predicted stress value.

[0098] Considering the test result of single test chip delamination, when only the k-th test chip delaminates, the real predicted stress value of the k-th test chip is the largest among all test chips under the real drop posture (a j ,b j ), and mise i (a j ,b j ) max = mise k (a j ,b j ).

[0099] To realize the failure scenario recurrence, the is sorted in descending order with the name of the test chip as the independent variable, and stored in the predicted stress value array: failrefn (a j ,b j ), have:

[0100] failref1(a j ,b j )>failref2(a j ,b j )>failref3(a j ,b j )>....>failref n (a j ,b j ) (3)

[0101]

[0102]

[0103] Wherein, failref n (a j ,b j ) is a single row n column array, each failref n (a j ,b j ) corresponds to a real drop posture, and the elements of each column in the array include the predicted stress values of each test chip under the real drop posture.

[0104] In order to efficiently reproduce the failure scenario, a reproduction matrix can be generated.

[0105] For m real drop postures, an m row n+2 column reproduction matrix failref m,n+2 can be constructed:

[0106]

[0107] It can be seen that, since the real drop posture includes two rotation angles a j and b j of the mainboard falling to the ground, the first column of the reproduction matrix can include the rotation angle a j in the real drop posture, and the second column can include the rotation angle b j in the real drop posture.

[0108] According to formulas (3), (4) and (5), the data in (6) can be equivalently transformed, as shown in formula (7):

[0109]

[0110] In some embodiments, after determining the reproduction matrix through steps 301 to 303, the predicted stress values ​​in the reproduction matrix can be mapped to the test chip numbers corresponding to each predicted stress value; for each failed chip, each column of the reproduction matrix is ​​queried in sequence until the first number corresponding to the failed chip is found; the first number found is the number of the test chip corresponding to the maximum predicted stress value; the actual drop posture included in the row of the first number found is taken as the target drop state that caused the failed chip to fail.

[0111] Mapping predicted stress values ​​to the test chip's serial number improves the efficiency of reproducing the failure scenario of the failed chip. When applying the chip failure analysis method of this application to small devices with limited computing power, mapping predicted stress values ​​to test chip serial numbers can achieve faster computation speed; alternatively, when each failure analysis requires searching a large amount of data, mapping predicted stress values ​​to test chip serial numbers can also achieve faster computation speed. Based on the test chip's serial number, the serial number corresponding to the failed chip can be more intuitively and quickly looked up in the reproduction matrix, thereby efficiently determining the failure scenario corresponding to the failed chip, i.e., the target drop posture.

[0112] For example, the mapping relationship shown in formula (1) is further used to map formula (7) to the specific test chip number. The mapping relationship is shown in formula (8).

[0113]

[0114] Where w1 and w2 are the positions of elements in the predicted stress value array.

[0115] Combining formulas (7) and (8), we obtain formula (9):

[0116]

[0117] Where s, e, h, o, u, v ∈ [1, n], and n is an integer.

[0118] For example, for a single failed chip, assuming the chip number is k, the failure scenario reproduction process is as follows:

[0119] 1) A failed chip was detected during the drop test, and the chip number k was obtained;

[0120] 2) Iterate through failref2 m,3 That is, traversing the third column of the reproduction matrix, the third column includes the test chip number corresponding to the maximum predicted stress value under each actual drop posture;

[0121] 3)failref2 m,3=k; in the third column, query whether there is a test chip numbered k, and determine the test chip numbered k as a failed chip;

[0122] 4) failure scenario: a m ,b m ; after querying that there is a number k in the third column, the row in which k is located in the recurrence matrix corresponds to the failure scenario a m ,b m , that is, the failure scenario.

[0123] For multiple failed chips, assuming the number of failed chips is q, then traverse formula (10), and extract the failure scenario that matches the number of failed chips and formula (10), which is similar to the failure scenario recurrence process of a single failed chip.

[0124] failref2 m,3 , failref2 m,4 ..... failref2 m,q+2 (10)

[0125] 404, for each failed chip, query each column included in the recurrence matrix in order until the first predicted stress value corresponding to the failed chip is queried as the maximum predicted stress value.

[0126] According to formula (7), each predicted stress value in each predicted stress value array is sorted in descending order. It can be seen that the third column of the recurrence matrix includes the maximum predicted stress value corresponding to each real drop posture, the fourth column includes the second largest predicted stress value corresponding to each real drop posture, and so on. Therefore, for each failed chip, the column including the maximum predicted stress value can be queried, that is, the third column of the recurrence matrix is queried, until the first predicted stress value corresponding to the failed chip is queried as the maximum predicted stress value.

[0127] In some optional embodiments, each predicted stress value in each predicted stress value array can be sorted in descending order, and a stress value matrix can be determined according to the sorting result. The stress value matrix can not include a real drop posture, but each row of the stress value matrix corresponds to a real drop posture. Optionally, each row of the stress value matrix can be labeled, and each label of each row corresponds to each real drop posture. Each row of the stress value matrix includes the predicted stress values of each test chip in descending order under the same real drop posture. For each failed chip, each column included in the stress value matrix is sequentially queried until the first predicted stress value corresponding to the failed chip is found as a maximum predicted stress value. Therefore, the first column of the stress value matrix can be queried until the first predicted stress value corresponding to the failed chip is found as the maximum predicted stress value.

[0128] 405、The real drop posture included in the row where the maximum predicted stress value is located is taken as a target drop state causing the failure of the failed chip.

[0129] The real drop posture corresponding to the row where the maximum predicted stress value is located in the recurrence matrix is taken as a target drop state causing the failure of the failed chip. The target drop state is the drop state of the failed chip.

[0130] According to the real drop postures and the predicted stress value arrays corresponding to each real drop posture, the recurrence matrix is determined in the embodiments of the present application, the recurrence matrix includes each real drop posture and the predicted stress value array corresponding to each real drop posture, by sorting each predicted stress value in each predicted stress value array in descending order, when detecting a failed chip, each column of the recurrence matrix can be sequentially traversed until the predicted stress value corresponding to the failed chip is found, and the efficiency of chip failure scene recurrence and failure analysis is improved.

[0131] Please refer to Figure 5 , Figure 5 is a flowchart of another chip failure analysis method disclosed in the embodiments of the present application.

[0132] 501、The plurality of real drop postures of the mainboard are input to the trained chip failure analysis model.

[0133] 502、The predicted stress values borne by each test chip under each real drop posture are output by the chip failure analysis model, and a predicted stress value array corresponding to each real drop posture is generated according to the predicted stress values borne by each test chip under each real drop posture.

[0134] 503. When one or more failed chips are detected from the motherboard, the target drop posture that caused the failure of the chip is determined based on the predicted stress value in the predicted stress value array corresponding to each failed chip in multiple real drop postures.

[0135] 504. Based on the array of predicted stress values ​​corresponding to each actual drop posture, the test chip corresponding to the minimum stress value in the array of predicted stress values ​​is selected as the candidate reliable chip.

[0136] The candidate reliable chip is the test chip with the lowest stress value in each array of predicted stress values.

[0137] 505. The test chip with the most repeated characters among the candidate reliable chips is selected as the reliable chip.

[0138] The lowest predicted stress value indicates that the test chip is least likely to desolder. Therefore, the test chip with the most repeated tests can be selected as the reliable chip from the pool of candidate reliable chips. Among the candidate reliable chips, the test chip with the most repeated tests experiences the lowest predicted stress value under the most real drop postures, and is therefore reliable.

[0139] In some embodiments, a recurrence matrix can also be used to determine reliable chips. The (n+2)th column of the recurrence matrix in formula (9) is processed, i.e., the last column. The test chip in this column has the highest reliability under the failure scenario. For example, the test chip numbered h in formula (9) is the test chip with the highest reliability under the failure scenario (a1, b1), the test chip numbered o is the test chip with the highest reliability under the failure scenario (a2, b2), and so on. The test chip with the most repetitions in the last column is identified as the reliable chip. The reliable chip has a better local structural design and hardware layout.

[0140] The following process can be used to analyze chips that exhibit superior reliability across multiple failure scenarios:

[0141] 1) Extract formula (9) The last column in;

[0142] 2) Get the last column:

[0143] 3) Repeatability statistics: Count the test chip numbers that are repeated the most times in the last column;

[0144] 4) Match the test chip's serial number to its name;

[0145] 5) Store in the reference optimization scheme library, labeled as: project number + chip name

[0146] 506. Store reliable chips in the reference optimization scheme library.

[0147] The reference optimization scheme library can include the name of the reliable chip, the corresponding project number of the reliable chip, and the structural information of the reliable chip. The structural information can include the hardware layout, local structural layout, mounting structure, and circuit layout in the entire circuit board of the reliable chip.

[0148] 507. Send a solution, including the structural information of a reliable chip, to the device corresponding to the project number through the reference optimization solution library.

[0149] In some embodiments, the embodiments of this application can be embedded into a LINUX cluster computing monitoring and submission platform to solve the failure reproduction problem of test chip desoldering in roller drop testing; simultaneously, an expert system can be embedded into the LINUX cluster computing monitoring and submission platform, leveraging the platform's computing, monitoring, and submission capabilities to derive an expert system module for handling specific problems. An expert system is a computer program system that can simulate human experts solving domain-specific problems.

[0150] Optionally, the project number can correspond to one electronic device or multiple electronic devices; the project number can also be the number corresponding to each project created in the expert system project pool.

[0151] Optionally, in the expert system, the failure scenario of the failed chip can be sent to the project number corresponding to the failed chip. Then, a solution can be sent to the device corresponding to the project number containing the failed chip through a reference optimization solution library. The solution can address the failure scenario of the failed chip and the problems existing in the structural design of the failed chip, and provide an optimized structural design scheme for the failed chip based on the structural information of reliable chips. The expert system can not only reproduce the failure scenario, but also provide reference optimization solutions, effectively promoting the project progress of solving the chip desoldering failure problem.

[0152] Please see Figure 6 , Figure 6 This is a flowchart illustrating an expert system architecture disclosed in an embodiment of this application. The expert system's project pool contains multiple projects named pro_1, pro_2, ..., pro_n. When a chip failure is detected in each project, the chip desoldering problem for all projects can be solved by establishing a scenario-parametric finite element model to calculate initial training samples. Then, a neural network is used for function approximation to obtain prediction data, which can be predicted stress values. The prediction data can be used in two ways: firstly, to reproduce the failure scenario of the failed chip detected in the current project; secondly, to export the installation structure of excellent local chips to the resource pool, while the resource pool pushes reference solutions to the current project based on the names of the excellent local chips.

[0153] The existing processing scheme has problems of over-reliance on individual engineering analysis ability of designers, possibility of misjudgment, and high cost of calculation, which hinders the promotion of the project process. After the failure scenario is reproduced, the reliability optimization scheme is proposed for the failure mechanism to solve the failure problem, which also over-reliance on individual engineering analysis ability of designers, because the number of experts in the field is limited. Therefore, the expert system for chip failure analysis based on neural network in the embodiments of the present application can not only accurately reproduce the failure scenario with low calculation cost, but also provide rich and excellent reference optimization scheme for the failure problem.

[0154] Please refer to Figure 7 , Figure 7 is another flowchart of a chip failure analysis method disclosed in the embodiments of the present application.

[0155] 701, a plurality of sample drop postures of a mainboard and sample stress values of each test chip under each sample drop posture are obtained.

[0156] The sample drop posture can include a rotation angle b around the x-axis and a rotation angle a around the y-axis when the mainboard falls to the ground. Optionally, the sample stress value of each test chip under each sample drop posture can be obtained by finite element analysis. The sample drop posture and the sample stress value of each test chip under each sample drop posture are used as a training sample set of a chip failure analysis model. The chip failure analysis model can be a neural network model, and the training sample set includes an input sample set and an output sample set. The input sample set is the sample drop posture (a j ,b j ), where j is an integer; a j ,b j ∈[-c,c]; and the output sample set is the sample stress value mise i (a j ,b j ), where i is an integer.

[0157] For example, assuming c=5, the feasible region is [-5, 5], the rotation angle interval d=2 degrees, and the sample drop posture m=36, the initial training sample number is 36, the sample drop posture is shown in Table 1, and a parameterized finite element simulation model with rotation angle (a, b) as the independent variable is established. For example, the finite element software can be used to establish it.

[0158]

[0159]

[0160] Table 1 sample drop posture instantiation

[0161] The training method is as shown in Figure 8 Figure 8 is a flowchart of a neural network training and prediction example disclosed in embodiments of the present application.

[0162] In order to more intuitively perform reverse mapping on the input sample set, the training sample set can be normalized to the interval [-1, 1], and the sample drop posture and sample stress value in the training sample set are normalized, as shown in the following formulas (11), (12), and (13):

[0163]

[0164]

[0165]

[0166] wherein a j and b j are two rotation angles in the sample drop posture (a j , b j ), wherein j [1, m] and j is an integer, representing the number of sample drop postures; a j , b j [−c, c], and c is the interval of the rotation angles a j and b j in the sample drop posture; and are normalized results of the rotation angles a j and b j in the sample drop posture, and the interval is [-1, 1]; mise i (a j , b j ) is the sample stress value, wherein i [1, n] and i is an integer; mise i (a j , b j ) mid is the intermediate value of the sample stress value of each test chip under each sample drop posture; mise i (a j , b j ) max is the maximum value of the sample stress value of each test chip under each sample drop posture; and mise i (a j , b j ) min is the minimum value of the sample stress value of each test chip under each sample drop posture. is the normalized result of the sample stress value, and the interval is [-1, 1]. ​

[0167] According to formulas (11), (12), and (13), the normalized input sample set is: The normalized output sample set is: During training, normalizing the sample drop posture and sample stress value can shorten the training speed of the neural network and make the data more intuitive.

[0168] 702. Input the sample drop posture and the sample stress value of each test chip under each sample drop posture into the chip failure analysis model to be trained, and obtain the training stress value output by the chip failure analysis model to be trained.

[0169] In some embodiments, the normalized input sample set can be... and the normalized output sample set The training sample set is input into the chip failure analysis model to be trained.

[0170] 703. Calculate the training loss based on the sample stress value and the training stress value, and adjust the weight parameters of the chip failure analysis model to be trained according to the training loss to obtain the trained chip failure analysis model.

[0171] Because of the highly nonlinear relationship between the drop posture and stress value in the roller drop test, a neural network can be used to approximate the function and obtain the mapping relationship between the motherboard drop posture and stress value.

[0172] As an optional implementation, a minimum-scale neural network can be built. The input layer of the neural network has two neurons, and the output layer has n neurons, which is the same as the number of test chips. To ensure the high nonlinearity of the fitted model, it includes at least one hidden layer. The actual number of hidden layers and the number of neurons in the hidden layer can be adjusted according to the actual training situation. The activation function adopts the classic sigmoid function, and the backpropagation method adopts the classic method - steepest descent method. The neural network can be quickly built using open source libraries such as scikit-leam in Python, and there is no specific limitation.

[0173] The calculated loss can be L1 loss, L2 loss, cross-entropy loss, etc., but is not limited to these.

[0174] The neural network is trained using a training sample set to approximate the functional relationship between the input and output sample sets, thus obtaining the weight parameters of the neural network. This functional relationship is then used to describe the chip failure analysis model, resulting in the mapping equation:

[0175]

[0176] Where f is a functional relationship; The normalized falling posture, This is the normalized stress value.

[0177] 704. Input multiple real drop postures of the motherboard into the trained chip failure analysis model.

[0178] In some embodiments, the angle values ​​of the sample drop postures during training can be refined and used as a prediction dataset input into the trained chip failure analysis model. For example, when the input sample set is the sample drop posture (a j ,b j ), where j∈[1,m], and j is an integer; a j ,b j ∈[-c,c]; The output sample set is the sample stress values. i (a j ,b j ), where i∈[1,n], and i is an integer. Where c=5, the feasible region is [-5,5], the angle interval d=2 degrees, the sample fall posture m=36, then the initial training sample size is 36, and the sample fall postures are shown in Table 1. In order to perform detailed prediction of the entire feasible region, the angle interval d=2 degrees can be changed to the angle interval d=0.1 degrees. Therefore, the true fall posture used for prediction is (a j ,b j ), where j∈[1,m], m=3600, that is, the prediction input sample set input to the completed training includes 3600 fall postures.

[0179] 705. Output the predicted stress value of each test chip under each real drop posture through the chip failure analysis model, and generate an array of predicted stress values ​​corresponding to each real drop posture based on the predicted stress value of each test chip under each real drop posture.

[0180] The normalized true fall posture can be Input into the trained chip failure analysis model as shown in formula (14): The normalized predicted stress values ​​of each test chip under each actual drop posture were obtained. Where i∈[1,n], and i is an integer.

[0181] In some embodiments, various real-world fall postures can be considered. Perform the reverse mapping, that is, according to formula (11), we obtain In other words, a large amount of prediction dataset can be obtained by using the trained chip failure analysis model.

[0182]

[0183] wherein a j and b j are real angle values in the real drop posture (a j , b j ); a normalized predicted stress value, representing a normalized predicted stress value of the i-th chip under the real drop posture (a j , b j ) is wherein i∈[1, n], i is an integer, and n is a number of test chips on the mainboard. The real drop postures and the normalized predicted stress values of the test chips under each real drop posture can be used to generate a predicted stress value array corresponding to each real drop posture.

[0184] 706. When one or more failed chips are detected from the mainboard, a target drop posture causing the failed chips to fail is determined according to the predicted stress values of each failed chip in the predicted stress value arrays corresponding to the multiple real drop postures respectively.

[0185] The embodiments of the present application construct a training sample set through a small amount of finite element calculation, train a chip failure analysis model, and obtain a mapping relationship between a mainboard drop posture and a stress value based on the trained chip failure analysis model, to obtain predicted stress values of the test chips under each real drop posture, thereby saving a large amount of calculation cost. The predicted stress value arrays are generated according to the real drop postures and the predicted stress values, the predicted stress values corresponding to the failed chips are queried from the predicted stress value arrays, and thus the real drop postures corresponding to the failed chips, i.e., the failure scenarios, are obtained, thereby improving the efficiency of chip failure analysis.

[0186] Please refer to Figure 9 , Figure 9 is a structural schematic diagram of a chip failure analysis device disclosed by the embodiments of the present application. The device can be applied to electronic devices such as mobile phones, notebook computers, wearable devices, and the like, and is not specifically limited. As shown in Figure 9 , the chip failure analysis device 900 can include an input module 910, a prediction module 920, and a determination module 930.

[0187] The input module 910 is configured to input multiple real drop postures of a mainboard to a trained chip failure analysis model; the mainboard includes one or more test chips.

[0188] The prediction module 920 is configured to predict, by the chip failure analysis model based on a mapping relationship between a mainboard drop posture and a stress value, predicted stress values of the test chips under each real drop posture, to obtain a predicted stress value array corresponding to each real drop posture.

[0189] The determining module 930 is configured to determine a target drop state causing the failure of the failed chip according to a predicted stress value in each predicted stress value array corresponding to each real drop state when the one or more failed chips are detected from the motherboard.

[0190] In an embodiment, the determining module 930 is further configured to determine a real drop state corresponding to a maximum predicted stress value as the target drop state causing the failure of the failed chip, wherein the maximum predicted stress value is determined according to the predicted stress value in each predicted stress value array corresponding to each real drop state.

[0191] In an embodiment, the determining module 930 is further configured to sort each predicted stress value in each predicted stress value array in descending order, and determine a recurrence matrix according to the sorting result and the real drop states, wherein each row of the recurrence matrix includes a real drop state and a sorted predicted stress value corresponding to the real drop state.

[0192] In addition, the determining module 930 is further configured to, for each failed chip, sequentially query each column included in the recurrence matrix until a first predicted stress value corresponding to the failed chip is queried as a maximum predicted stress value, and determine a real drop state corresponding to the maximum predicted stress value as the target drop state causing the failure of the failed chip.

[0193] In an embodiment, the determining module 930 is further configured to sort each predicted stress value in each predicted stress value array in descending order, and determine a recurrence matrix according to the sorting result and the real drop states, wherein each row of the recurrence matrix includes a real drop state and a sorted predicted stress value corresponding to the real drop state, and map the predicted stress value in the recurrence matrix to a number of a test chip.

[0194] In addition, the determining module 930 is further configured to, for each failed chip, sequentially query each column included in the recurrence matrix until a first number corresponding to the failed chip is queried from the number of the test chip as a number of a maximum predicted stress value, and determine a real drop state corresponding to the number of the maximum predicted stress value as the target drop state causing the failure of the failed chip.

[0195] In an embodiment, the chip failure analysis device 900 is further configured to count a test chip with a maximum repetition number as a reliable chip from each test chip with a minimum predicted stress value under each real drop state.

[0196] In an embodiment, the chip failure analysis device 900 is further configured to store the reliable chip into a reference optimization scheme library; the reference optimization scheme library comprises a project number corresponding to the reliable chip and structure information of the reliable chip; and the reference optimization scheme library is configured to send a solution comprising the structure information of the reliable chip to the project number corresponding to the reliable chip.

[0197] In an embodiment, the chip failure analysis device 900 further comprises a training unit.

[0198] The training unit is configured to obtain a plurality of sample drop postures of a mainboard and sample stress values of each test chip under each sample drop posture.

[0199] The sample drop postures and the sample stress values of each test chip under each sample drop posture are input into the chip failure analysis model to be trained to obtain training stress values output by the chip failure analysis model to be trained.

[0200] The training loss is calculated according to the sample stress values and the training stress values, and the weight parameters of the chip failure analysis model to be trained are adjusted according to the training loss to obtain the trained chip failure analysis model.

[0201] Please refer to Figure 10 , Figure 10 is a structural schematic diagram of an electronic device disclosed by an embodiment of the present application. As shown in Figure 10 , the electronic device 1000 can include:

[0202] a memory 1010 storing executable program codes;

[0203] a processor 1020 coupled with the memory 1010;

[0204] The processor 1020 calls the executable program codes stored in the memory 1010 to execute any chip failure analysis method disclosed by an embodiment of the present application.

[0205] An embodiment of the present application discloses a computer readable storage medium storing a computer program, wherein the computer program is executed by the processor to enable the processor to implement any chip failure analysis method disclosed by an embodiment of the present application.

[0206] It should be understood that the term "one embodiment" or "an embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It will also be appreciated by those of skill in the art that references to a structure or feature that is

[0207] In various embodiments of the present application, it should be understood that the magnitude of the serial number of the above-mentioned processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0208] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e. they can be located in one place, or they can be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0209] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0210] The integrated unit described above, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer accessible memory. Based on such understanding, the technical solutions of the present application, essentially or the part that makes a contribution to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product, which is stored in a memory and includes a number of steps for causing a computer device (which can be a personal computer, a server or a network device, etc., and specifically can be a processor in the computer device) to execute the methods of the embodiments of the present application described above.

[0211] Those skilled in the art can understand that all or part of the steps of various methods in the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer readable storage medium, including Read-Only Memory (ROM), Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), One-time Programmable Read-Only Memory (OTPROM), Electrically-Erasable Programmable Read-Only Memory (EEPROM), Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, magnetic disk storage, magnetic tape storage, or any other medium that can be used to carry or store data in a computer readable manner.

[0212] The above describes in detail a chip failure analysis method and device, an electronic device and a storage medium disclosed in the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples. The above embodiment descriptions are only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method of chip failure analysis, characterized by, The method comprises: inputting a plurality of real drop postures of a mainboard into a trained chip failure analysis model; the mainboard comprises one or more test chips; outputting, by the chip failure analysis model, a predicted stress value of each test chip under each real drop posture, and generating a predicted stress value array corresponding to each real drop posture according to the predicted stress value of each test chip under each real drop posture; sorting each predicted stress value in each predicted stress value array in descending order, and determining a recurrence matrix according to the sorting result and each real drop posture; each row of the recurrence matrix comprises a real drop posture and the sorted predicted stress value corresponding to the real drop posture; when one or more failed chips are detected from the mainboard, for each failed chip, sequentially querying each column included in the recurrence matrix until a first predicted stress value corresponding to the failed chip is queried as a maximum predicted stress value; a real drop posture included in a row where the maximum predicted stress value is located is taken as a target drop state causing the failure of the failed chip; the maximum predicted stress value is determined according to the predicted stress value in the predicted stress value array corresponding to each real drop posture of the failed chip.

2. The method of claim 1, wherein, The method further comprises: based on the predicted stress value array corresponding to each real drop posture, taking a test chip corresponding to a minimum stress value in the predicted stress value array as a candidate reliable chip; taking a test chip with the largest number of repeated words in the candidate reliable chip as a reliable chip.

3. The method of claim 2, wherein, The method further comprises: storing the reliable chip into a reference optimization scheme library; the reference optimization scheme library comprises a project number corresponding to the reliable chip and structure information of the reliable chip; sending, by the reference optimization scheme library, a solution comprising the structure information of the reliable chip to a device corresponding to the project number.

4. The method of claim 1, wherein, The method further comprises: obtaining a plurality of sample drop postures of the mainboard and sample stress values of each test chip under each sample drop posture; inputting the sample drop postures and the sample stress values of each test chip under each sample drop posture into a chip failure analysis model to be trained to obtain training stress values output by the chip failure analysis model to be trained; calculating a training loss according to the sample stress values and the training stress values, and adjusting weight parameters of the chip failure analysis model to be trained according to the training loss to obtain a trained chip failure analysis model.

5. A method of chip failure analysis, characterized by, The method comprises: inputting a plurality of real drop postures of a mainboard into a trained chip failure analysis model; the mainboard comprises one or more test chips; outputting, by the chip failure analysis model, a predicted stress value of each test chip under each real drop posture, and generating a predicted stress value array corresponding to each real drop posture according to the predicted stress value of each test chip under each real drop posture; each of the predicted stress values in each of the predicted stress value arrays is sorted in descending order, and a recurrence matrix is determined according to the sorting result and the real drop posture; each row of the recurrence matrix includes a real drop posture and the sorted predicted stress value corresponding to the real drop posture; each of the predicted stress values in the recurrence matrix is mapped to the number of the test chip corresponding to the predicted stress value; when one or more failed chips are detected from the mainboard, for each of the failed chips, each column included in the recurrence matrix is sequentially queried until the first number corresponding to the failed chip is queried out, the first queried number is the number of the test chip corresponding to the maximum predicted stress value, the maximum predicted stress value is determined according to the predicted stress values in the predicted stress value arrays corresponding to the failed chip under a plurality of real drop postures respectively; and the real drop posture included in the row where the first queried number is located is taken as the target drop state causing the failure of the failed chip.

6. A chip failure analysis apparatus characterized by comprising: comprise: an input module configured to input a plurality of real drop postures of a mainboard to a trained chip failure analysis model; the mainboard comprises one or more test chips; a prediction module configured to output, by the chip failure analysis model, a predicted stress value borne by each of the test chips under each of the real drop postures, and generate a predicted stress value array corresponding to each of the real drop postures according to the predicted stress value borne by each of the test chips under each of the real drop postures; a determination module configured to sort each of the predicted stress values in each of the predicted stress value arrays in descending order, and determine a recurrence matrix according to the sorting result and each of the real drop postures; each row of the recurrence matrix includes a real drop posture and the sorted predicted stress value corresponding to the real drop posture; the determination module is further configured to, when one or more failed chips are detected from the mainboard, for each of the failed chips, sequentially query each column included in the recurrence matrix until the first predicted stress value corresponding to the failed chip is queried out as the maximum predicted stress value; and take the real drop posture included in the row where the maximum predicted stress value is located as the target drop state causing the failure of the failed chip; the maximum predicted stress value is determined according to the predicted stress values in the predicted stress value arrays corresponding to the failed chip under a plurality of real drop postures respectively.

7. A chip failure analysis apparatus characterized by comprising: comprise: an input module configured to input a plurality of real drop postures of a mainboard to a trained chip failure analysis model; the mainboard comprises one or more test chips; a prediction module configured to output, by the chip failure analysis model, a predicted stress value borne by each of the test chips under each of the real drop postures, and generate a predicted stress value array corresponding to each of the real drop postures according to the predicted stress value borne by each of the test chips under each of the real drop postures; The determination module is configured to sort each of the predicted stress values in each of the predicted stress value arrays in descending order, determine a recurrence matrix according to a sorting result and the real drop attitudes, and map each of the predicted stress values in the recurrence matrix to a number of the test chip corresponding to each of the predicted stress values. The determination module is further configured to, when one or more failed chips are detected from the motherboard, for each of the failed chips, sequentially query each of columns included in the recurrence matrix until a first number corresponding to the failed chip is queried out, the first queried number is a number of a test chip corresponding to the maximum predicted stress value, the maximum predicted stress value is determined according to predicted stress values in a plurality of predicted stress value arrays corresponding to the real drop attitudes of the failed chip respectively, and take a real drop attitude included in a row where the first queried number is located as a target drop attitude causing the failed chip to fail.

8. An electronic device, comprising: A computer program is stored in a memory and executed by a processor, and the computer program causes the processor to implement steps of the chip failure analysis method according to any one of claims 1 to 5.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement steps of the chip failure analysis method according to any one of claims 1 to 5.

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