Built-in self-test circuit and method for physical unclonable function quality check

Abstract

A built-in self-test circuit and method for physical unclonable function (PUF) quality check are disclosed. The built-in self-test circuit includes a PUF array, a readout circuit, and a first comparison circuit. The PUF array includes a plurality of PUF cells, each of which includes a first storage cell and a second storage cell, and the readout circuit outputs an output bit from the first storage cell and a parity bit from the second storage cell. The first comparison circuit compares an output bit string and a parity bit string to generate a parity check result, where the output bit string includes output bits read from a plurality of selected PUF cells of the plurality of PUF cells, and the parity bit string includes parity bits read from the plurality of selected PUF cells. The present invention can improve the efficiency of checking PUF quality without or with less side effects.

Description

TECHNICAL FIELD

[0001] The present application relates to a physical unclonable function (PUF), and in particular, to a built-in self-test (BIST) circuit and method for PUF quality inspection. BACKGROUND

[0002] A PUF can be considered as a fingerprint on a wafer, as the physical characteristics of different wafers will have slight differences due to some uncontrollable factors in the manufacturing process, and these differences cannot be copied or predicted, and thus can be used as static entropy for security-related applications. In some embodiments of the PUF, some elements in the PUF pool need to be enrolled to convert some physical characteristics of the elements into random bits. However, the enrollment action can be accidentally skipped or have some defects, and thus the random bits read from the PUF pool need to be detected for quality inspection, which greatly increases the manufacturing time and labor cost.

[0003] Therefore, a novel method and related device are needed to inspect the quality of the random bits provided by the PUF pool without or with less side effects. SUMMARY

[0004] An object of the present application is to provide a built-in self-test (BIST) circuit and method for PUF quality inspection to improve the efficiency of inspecting the quality of a PUF pool without greatly increasing additional costs.

[0005] At least one embodiment of the present disclosure provides a built-in self-test circuit for physically unclonable function quality check. The built-in self-test circuit can include a physically unclonable function array, a readout circuit coupled to the physically unclonable function array, and a first comparison circuit coupled to the readout circuit. The physically unclonable function array can include a plurality of physically unclonable function units, wherein each physically unclonable function unit of the plurality of physically unclonable function units includes a first memory cell and a second memory cell. The readout circuit can be configured to output an output string including a plurality of output bits read from the first memory cells of a plurality of selected physically unclonable function units and a parity string including a plurality of parity bits read from the second memory cells of the plurality of selected physically unclonable function units. The first comparison circuit can be configured to generate a parity check result based on a hamming distance between the output string and the parity string.

[0006] At least one embodiment of the present disclosure provides a built-in self-test method for physically unclonable function quality check. The built-in self-test method can include providing physically unclonable function values using a physically unclonable function array, wherein the physically unclonable function array includes a plurality of physically unclonable function units, and each physically unclonable function unit of the plurality of physically unclonable function units includes a first memory cell and a second memory cell; outputting an output string including a plurality of output bits read from a plurality of first memory cells of a plurality of selected physically unclonable function units and a parity string including a plurality of parity bits read from a plurality of second memory cells of the plurality of selected physically unclonable function units using a readout circuit; and generating a parity check result based on a hamming distance between the output string and the parity string using a first comparison circuit.

[0007] At least one embodiment of the present disclosure provides a built-in self-test circuit for physical unclonable function quality inspection. The built-in self-test circuit can include a physical unclonable function array and a comparison circuit. The physical unclonable function array can include a plurality of physical unclonable function units. The comparison circuit can receive a first horizontal string, a first vertical string, and a first skew string from the physical unclonable function array, calculate a horizontal hamming weight of the first horizontal string, a vertical hamming weight of the first vertical string, and a skew hamming weight of the first skew string, and determine whether the horizontal hamming weight, the vertical hamming weight, and the skew hamming weight meet predetermined criteria to generate a health degree inspection result.

[0008] Embodiments of the present disclosure provide a built-in self-test circuit and a built-in self-test method for checking the quality of physical unclonable functions by means of built-in circuits. Therefore, external measuring instruments are not required, and the testing time cost and the labor cost can be greatly reduced. In addition, embodiments of the present disclosure do not greatly increase additional hardware. Therefore, the present disclosure can improve the efficiency of checking the quality of physical unclonable functions without or with less side effects. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of a physical unclonable function unit according to an embodiment of the present disclosure.

[0010] Figure 2 A schematic diagram of a physical unclonable function array according to an embodiment of the present disclosure.

[0011] Figure 3 A schematic diagram of a built-in self-test circuit for physical unclonable function quality inspection according to an embodiment of the present disclosure.

[0012] Figure 4 A schematic diagram of a built-in self-test circuit for physical unclonable function quality inspection according to an embodiment of the present disclosure. Figure 3 Some details of the readout circuit shown.

[0013] Figure 5 A schematic diagram of a workflow of a built-in self-test method for physical unclonable function quality inspection according to an embodiment of the present disclosure.

[0014] Figure 6 A schematic diagram of a workflow of a parity check for a group of physical unclonable function units in a physical unclonable function array according to an embodiment of the present disclosure.

[0015] Figure 7This is a schematic diagram of the distribution of readout voltages for each physically non-replicable unit in a group of selected physically non-replicable functional units from a physically non-replicable functional array according to an embodiment of the present invention.

[0016] Figure 8 This is a schematic diagram of a decoding scheme for a physically non-replicable functional array according to an embodiment of the present invention.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 10, 210, 220 Physically Non-Replicable Functional Units

[0019] 20 Physically Non-Replicable Functional Arrays

[0020] Transistors M0, M1, and T1 to T12

[0021] WL0~WL3 letter lines

[0022] FL0~FL3 Follower lines

[0023] AF0~AF3 control lines

[0024] 30 Built-in self-test circuit

[0025] 30C Controller

[0026] 30P power supply

[0027] 300 Physically Unreplicable Functional Devices

[0028] 301 Physically Non-Replicable Functional Array

[0029] 302-line decoder

[0030] 303 drive

[0031] 304 Readout Circuit

[0032] 305-column decoder

[0033] 306 Sensing Amplifier

[0034] 307 bias circuit

[0035] 310 Register

[0036] Register 311

[0037] 312 X Decoder

[0038] 313 Y decoder

[0039] 314 Z decoder

[0040] 320 multiplexer

[0041] 330 and 350 comparator circuits

[0042] 351 Accumulator

[0043] 352 comparator

[0044] 360 Register

[0045] ADDR ROW line address

[0046] ADDR COLUMN column address

[0047] 305C Switch Control

[0048] 305W switching circuit

[0049] BL0~BL31 bit lines

[0050] DL0~DL31 switches

[0051] SA0~SA31 Amplifier Circuit

[0052] DATA0~DATA31 bits of data

[0053] S510~S530, S610~S660 Steps

[0054] ONNR enables normal read distribution.

[0055] OFFNR disables the distribution for normal reading.

[0056] ONMR opening margin distribution

[0057] OFFMR Closure Margin Distribution

[0058] ONMVREF Enable margin level

[0059] OFFMVREF Turn off margin level

[0060] PX(0)~PX(31) Horizontal String

[0061] PY(0)~PY(31) Vertical strings

[0062] PZ(0) skewed string

[0063] D 0,0 ~D 31,31 data Detailed Implementation

[0064] Figure 1This is a schematic diagram illustrating the registration of a Physically Unclonable Function (PUF) unit 10 according to an embodiment of the present invention. Figure 1 As shown, the PUF unit 10 may include at least two PUF memory units, such as a first memory unit and a second memory unit, wherein the first memory unit may include transistor M0, and the second memory unit may include transistor M1. In this embodiment, a high voltage may be applied to the gate terminals of transistors M0 and M1, causing transistors M0 and M1 to be registered simultaneously, meaning that transistors M0 and M1 will be initialized to generate a random code. Specifically, after the energy accumulated on the gate terminals of transistors M0 and M1 reaches a certain level, one of transistors M0 and M1 will undergo quantum tunneling, and the energy accumulated on the gate terminals of transistors M0 and M1 will be released through the gate leakage path of the transistor undergoing quantum tunneling. Therefore, one of transistors M0 and M1 (e.g., transistor M0) will generate a quantum tunneling current greater than a predetermined threshold, while the other of transistors M0 and M1 (e.g., transistor M1) will generate a quantum tunneling current less than the predetermined threshold or will not undergo quantum tunneling. The quantum tunneling mechanism described above can be similar to gate oxide breakdown, but is not limited to hard / destructive breakdown. For example, quantum tunneling can be soft breakdown using trap-assisted tunneling, but the present invention is not limited thereto. For ease of understanding, a transistor that generates a quantum tunneling current greater than the predetermined threshold can be called a "broken" transistor, while a transistor that generates a quantum tunneling current less than the predetermined threshold (or does not undergo quantum tunneling) can be called an "unbroken" transistor. In this embodiment, the quantum tunneling mechanism occurring in transistor M0 and / or transistor M1 is inherently random. In addition, transistors M0 and M1 are not perfectly symmetrical or mutually consistent in physical characteristics due to process variations. Therefore, which of transistors M0 and M1 will break is random. For example, transistors M0 and M1 may have the same probability (e.g., 50% each) of becoming broken transistors, but the present invention is not limited thereto.

[0065] Figure 2 This is a schematic diagram of a PUF array 20 according to an embodiment of the present invention. In this embodiment, a 2x2 PUF array is shown for illustrative purposes, but this is not a limitation of the invention, and PUF arrays of different sizes can be derived accordingly. In this embodiment, each PUF cell of the PUF array 20 contains six transistors connected in series, wherein... Figure 1The registration operation shown can be employed in this embodiment, and in particular, can be applied to each PUF cell of PUF array 20. For example, PUF cell 210 may include transistors T1 to T6 connected in series, wherein the gate terminals of transistors T1 to T6 are respectively connected to a word line WL0, a following line FL0, a control line AF0, a control line AF1, a following line FL1, and a word line WL1. Additionally, PUF cell 220 may include transistors T7 to T12 connected in series, wherein the gate terminals of transistors T7 to T12 are respectively connected to a word line WL2, a following line FL2, a control line AF2, a control line AF3, a following line FL3, and a word line WL3. In this embodiment, transistors T3 and T4 of PUF cell 210 can respectively serve as… Figure 1 The examples shown are transistors M0 and M1, while transistors T9 and T10 of PUF unit 220 can be respectively used as... Figure 1 Examples of transistors M0 and M1 are shown.

[0066] like Figure 2 As shown, the first group of PUF cells in PUF array 20 (e.g. Figure 2 The upper half of the PUF cell shown is coupled to a bit line BL0, and the second group of PUF cells in the PUF array 20 (e.g., Figure 2 The lower half of the PUF cell shown is coupled to a bit line BL1. For simplicity, the following description focuses on the operation of the first group of PUF cells (e.g., PUF cells 210 and 220), with similar details for the second group of PUF cells deduced accordingly. Regarding PUF cell 210, transistors T3 and T4, after registration, can be considered as two resistors with different resistance values, where a broken transistor in T3 and T4 will have a relatively low resistance value (corresponding to a relatively high gate leakage current), and an unbroken transistor in T3 and T4 will have a relatively high resistance value (corresponding to a relatively low gate leakage current). Transistors T1 and T6 are used to control the readout of PUF data, while transistors T2 and T5 are used to prevent transistors T1 and T6 from being damaged during the registration of T3 and T4 (e.g., ensuring that the voltage difference across each transistor of T1 and T6 falls within a tolerable range). In some embodiments, transistors T2 and T5 may be omitted, meaning that transistor T1 may be directly connected to transistor T3 and transistor T6 may be directly connected to transistor T4. Details of PUF unit 220 are similar to those of PUF unit 210 and will not be repeated here for the sake of brevity.

[0067] Table 1

[0068] AF0 AF1 FL0 FL1 WL0 WL1 BL0 Register VPP VPP VX VX VPR VPR 0 Data extraction (M0) VSEN 0 VDD 0 VDD 0 0 Data extraction (M1) 0 VSEN 0 VDD 0 VDD 0

[0069] Table 1 illustrates the control of transistors in selected PUF cells, such as PUF cell 210, during registration and data retrieval (e.g., voltages applied to their gate terminals, such as those applied to word line WL0, follower line FL0, control line AF0, control line AF1, follower line FL1, and word line WL1). Assuming PUF cell 210 is selected and PUF cell 220 is not selected, a zero voltage (e.g., ground voltage) can be applied to the gate terminals of all transistors in the unselected PUF cell (e.g., transistors T7-T12 in PUF cell 220) to disable the unselected PUF cell, but the invention is not limited thereto. During registration of PUF cell 210, voltages VPP are applied to control lines AF0 and AF1, voltages VX are applied to follower lines FL0 and FL1, and voltages VPR are applied to word lines WL0 and WL1, wherein the zero voltage (labeled "0" in Table 1) is applied to bit line BL0. Assuming that after registration of PUF cell 210, transistor T3 breaks while transistor T4 does not, in order to extract data from transistor T3 of PUF cell 210 (labeled "Data Extraction (M0)" in Table 1), a sensing voltage VSEN can be applied to control line AF0 and the zero voltage (labeled "0" in Table 1) can be applied to control line AF1. The word line WL0 and follower line FL0 will be applied with voltage VDD, while the word line WL1 and follower line FL1 will be applied with the zero voltage, and the bit line BL0 will be applied with the zero voltage. Because the broken transistor T3 has a relatively high gate leakage current, a relatively low readout voltage can be detected on the bit line BL0, and the data from transistor T3 of PUF cell 210 can be judged as the logic value "0". To extract data from transistor T4 of PUF cell 210 (labeled "Data Extraction (M1)" in Table 1), a sensing voltage VSEN is applied to control line AF1 and the zero voltage is applied to control line AF0. A voltage VDD is applied to word line WL1 and follower line FL1, while the zero voltage is applied to word line WL0 and follower line FL0, and the zero voltage is applied to bit line BL0. Because the unbroken transistor T4 has a relatively low gate leakage current, a relatively low readout voltage can be detected on bit line BL0, and the data from transistor T4 of PUF cell 210 can be determined as a logic value "1". The data extraction operation can be deduced similarly for the case where transistor T3 is unbroken but transistor T4 is broken after PUF cell 210 registration, and will not be elaborated here. The above data extraction scheme can be called a single-ended sensing scheme, for example, where data readout of transistor T3 and transistor T4 operates separately. The relevant details for selecting PUF unit 220 can be deduced similarly, and will not be repeated here for the sake of brevity.

[0070] Figure 3 This is a schematic diagram of a built-in self-test (BIST) circuit 30 for PUF quality inspection according to an embodiment of the present invention. In this embodiment, the BIST circuit 30 may include a power supply 30P, a controller 30C, and a PUF device 300 coupled to the power supply 30P and the controller 30C. The power supply 30P may be a high-voltage system to provide power to the components within the BIST circuit 30, while the controller 30C can be used to control the workflow of BIST operation. The PUF device 300 may include a PUF array 301, a row decoder 302, a driver 303 coupled between the PUF array 301 and the row decoder 302, and a readout circuit 304 coupled to the PUF array 301, wherein the readout circuit 304 may include a column decoder 305 coupled to the PUF array 301, and a sense amplifier 306 coupled to the column decoder 305. The PUF device 300 may further include a bias circuit 307 coupled to a sense amplifier 306 within the readout circuit 304. In this embodiment, the PUF array 301 may include a plurality of PUF units, each of which may include Figure 1 The diagram shows a first memory cell (containing transistor M0) and a second memory cell (containing transistor M1). Specifically, the first memory cell may contain... Figure 2 The transistors T1 to T3 of the PUF unit 210 shown are (or Figure 2 The transistors T7 to T9 of the PUF unit 220 shown, and the second memory unit may include Figure 2 The transistors T4 to T6 of the PUF unit 210 shown are (or Figure 2 The transistors T10 to T12 of the PUF unit 220 shown are illustrated, but the present invention is not limited thereto.

[0071] Ideally, for each PUF cell within the PUF array 301, transistors M0 (e.g., transistor T3 of PUF cell 210 or transistor T9 of PUF cell 220) and M1 (e.g., transistor T4 of PUF cell 210 or transistor T10 of PUF cell 220) should, after registration, have one transistor broken and the other intact. Therefore, for a single PUF cell, the data from transistor M0 (referred to as the "output bit") and the data from transistor M1 (referred to as the "parity bit") are expected to have opposite logic values ​​(e.g., if one is "1", the other is "0"). In practice, the registration of one or more PUF cells within the PUF array 301 may be defective. For example, both transistors M0 and M1 in a single PUF cell may be broken, resulting in both its output bit and parity bit being "0". For example, if both transistors M0 and M1 in a single PUF unit are intact, both the output bit and the parity bit will be "1".

[0072] The readout circuit 304 can be used to output an output bit from the first memory cell, such as transistor M0, and an even / parity bit from the second memory cell, such as transistor M1. Specifically, the line decoder 302 can output a parity bit based on the line address ADDR. ROW Control signals are generated to select a row of PUF cells, and driver 303 can drive PUF array 301 using the drive voltage provided by power supply 30P according to these control signals (e.g., drive the PUF array 301). Figure 2 The word lines WL0 and WL1 shown allow the readout circuit 304 to extract data (e.g., the output bits and / or the parity bits) from each PUF cell of a selected row of PUF cells. Additionally, the column decoder 305 can be used to retrieve data based on the column address ADDR. COLUMNAt least one column of PUF cells is selected to sense the readout voltage from at least one column of selected PUF cells in PUF array 301. Sensing amplifier 304 can determine whether the logic value of the data from the selected PUF cells is "0" or "1," wherein sensing amplifier 304 can operate according to the bias voltage provided by bias circuit 307. For ease of understanding, this embodiment can use a 32×32 PUF array as an example of PUF array 301, but the invention is not limited thereto. It should be noted that PUF array 301 does not necessarily have to be a square array (for example, the number of rows in PUF array 301 may be different from the number of columns), and column decoder 305 does not necessarily have to select an entire column of PUF cells for readout. In some embodiments, the PUF array 301 may be a 2×512 PUF array, wherein the row decoder 302 may select a row of PUF units (e.g., 512 PUF units) from this 2×512 PUF array, and the column decoder 305 may select only 32 PUF units from these 512 PUF units to extract 32 bits of data, but the present invention is not limited thereto.

[0073] Figure 4 According to an embodiment of the present invention Figure 3 Some details of the readout circuit 304 shown (e.g., the column decoder 305 and the sense amplifier 306 within it). In this embodiment, Figure 3 The column decoder 305 shown may include a switch control circuit 305C (denoted as "switch control" for simplicity) and a switch circuit 305W, wherein the switch circuit 305W may include multiple switches such as DL0, DL1, DL2, ... and DL31, and the switch control circuit 305C may be based on the column address ADDR COLUMN 32 switch control signals are generated to control switches DL0, DL1, DL2, ..., and DL31 respectively. Additionally, Figure 3 The shown sensing amplifier 306 can be used to output the output bit based on the readout voltage read from the transistor M0 of the selected PUF cell and to output the parity bit based on the readout voltage read from the transistor M1 of the selected PUF cell. In particular, Figure 3The sensing amplifier 306 shown may include one or more amplifier circuits such as SA0, SA1, SA2, ... and SA31 to output bit data DATA0, DATA1, DATA2, ... and DATA31 respectively. In this embodiment, switch DL0 may be coupled between bit line BL0 of PUF array 301 and amplifier circuit SA0; switch DL1 may be coupled between bit line BL1 of PUF array 301 and amplifier circuit SA1; switch DL2 may be coupled between bit line BL2 of PUF array 301 and amplifier circuit SA2; and so on, for example, switch DL31 may be coupled between bit line BL31 of PUF array 301 and amplifier circuit SA31; but the invention is not limited thereto. In some embodiments, the switching circuit 305W may include two or more layers of switches to implement more flexible switching control schemes, but the invention is not limited thereto.

[0074] exist Figure 4 In the embodiments described, each of the amplifier circuits SA0, SA1, SA2, ..., SA31 can operate as a comparator. In the following description, amplifier circuit SA0 is used as an example, while the operation of other amplifier circuits such as amplifier circuits SA1, SA2, ..., SA31 is similar to that of amplifier circuit SA0 and will not be repeated here. When the read voltage from the selected PUF cell (e.g., transistor M0 within it) is less than the reference voltage VREF, the voltage difference between the read voltage and the reference voltage VREF can be amplified to make the output of amplifier circuit SA0 a high voltage (e.g., voltage VDD), and the output bit can be determined to have a first logic value such as "1". When the read voltage from the selected PUF cell (e.g., transistor M0 within it) is greater than the reference voltage VREF, the voltage difference between the read voltage and the reference voltage VREF can be amplified to make the output of amplifier circuit SA0 a low voltage (e.g., the zero voltage), and the output bit can be determined to have a second logic value such as "0". The operation of extracting the parity bit from transistor M1 by sensing amplifier 306 is similar to the operation of extracting the output bit from transistor M0, and the relevant details will not be repeated here.

[0075] To check the quality of the PUF device 300 (especially the PUF array 301 within it), the BIST circuit 30 can be used to check the authenticity, reliability, and randomness of the PUF data provided by the PUF device 300. In addition to the above components, the BIST circuit 30 may further include a register 310 coupled to the PUF device 300, a multiplexer 320 coupled to the register 310, a comparator circuit 330 coupled to the PUF device 300 and the multiplexer 320, a comparator circuit 350 coupled to the multiplexer 320, and a register 360 coupled to the multiplexer 320 and the comparator circuit 330, such as... Figure 3 As shown. In particular, register circuitry 310 may include register 311 coupled to PUF device 300, a horizontal decoder such as X decoder 312 coupled between register 311 and multiplexer 320, a vertical decoder such as Y decoder 313 coupled between register 311 and multiplexer 320, and a skew decoder such as Z decoder 314 coupled between register 311 and multiplexer 320. Multiplexer 320 is used to select one of X decoder 312, Y decoder 313, and Z decoder 314 for outputting data / strings from register 311.

[0076] In this embodiment, the readout circuit 304 can extract 32 bits of data (e.g., data from a row of PUF cells in the PUF array 301) from the PUF device 300 at a time and store it in register 311, but the invention is not limited thereto. After extracting data from all rows of PUF cells in the PUF array 301, all PUF data in the PUF array 301 (e.g., 32×32 output bits extracted from the PUF device 300) can be dumped into register 311, but the invention is not limited thereto. Additionally, the X decoder 312 can be used to extract data from register 311 and generate a horizontal string by collecting multiple output bits read from a group of horizontal PUF cells in the PUF array 301 into a group, wherein the PUF cells in the group of horizontal PUF cells are arranged horizontally in the PUF array 301. Y decoder 313 can be used to extract data from register 311 and generate a vertical string by collecting multiple output bits read from a set of vertical PUF units in PUF array 301 into a group, wherein the PUF units in the set of vertical PUF units are arranged vertically in PUF array 301. Z decoder 314 can be used to extract data from register 311 and generate a skewed string by collecting multiple output bits read from a set of skewed PUF units in PUF array 301 into a group, wherein the PUF units in the set of skewed PUF units are arranged skewed in PUF array 301.

[0077] Figure 5 This is a schematic diagram illustrating the workflow of a BIST method for PUF quality inspection according to an embodiment of the present invention, wherein... Figure 5 The workflow shown can be achieved through Figure 3 The BIST circuit 30 shown is used to execute this. It should be noted that... Figure 5 The workflow shown is for illustrative purposes only and is not intended to limit the invention. Furthermore, one or more steps may be added, deleted, or modified in this workflow. These steps do not necessarily need to be strictly followed if the same result is obtained. Figure 5 Execute in the order shown. For ease of understanding, please refer to... Figure 3 For reference Figure 5 .

[0078] In step S510, the BIST circuit 30 may use the PUG array 301 to provide PUF values, wherein the PUF array 301 includes a plurality of PUF cells (e.g., 32×32 PUF cells), and each of the plurality of PUF cells may include a first memory cell such as transistor M0 and a second memory cell such as transistor M1.

[0079] In step S520, the BIST circuit 30 may use the readout circuit 304 to output an output bit from the first memory cell, such as transistor M0, and to output a parity bit from the second memory cell, such as transistor M1.

[0080] In step S530, the BIST circuit 30 may use the comparison circuit 330 to compare an output string with a parity string to generate a parity check result, wherein the output string includes a plurality of output bits read from a plurality of selected PUF units, and the parity string includes a plurality of parity bits read from the plurality of selected PUF units.

[0081] In detail, when a first row of PUF cells in the PUF array 301 is selected, the multiplexer 320 can select the X decoder 312 to output an output string from the first row of storage cells in register 311, wherein the output bits in the output string are extracted from the first row of PUF cells. The readout circuit 304 can output a parity string from the first row of PUF cells, wherein the parity bits in the parity string are extracted from the first row of PUF cells. For each PUF cell in the first row of PUF cells, a comparison circuit 330 (e.g., a 32-bit comparison circuit) can check whether the output bit and parity bit of each PUF cell have opposite logical values ​​to produce a comparison result, wherein the comparison circuit 330 may include multiple exclusive OR (XOR) logic circuits to compare the two strings bit by bit. The comparison result indicates which PUF cells in the first row of PUF cells passed the parity check (i.e., their output bits and parity bits have opposite logical values). Comparator circuit 330 may include a counter to count how many PUF cells in the first row of PUF cells passed the parity check. For example, the counter of comparator circuit 330 may calculate the Hamming distance between the output string and the parity string as the parity check result for the first row of PUF cells, and send this parity check result back to controller 30C for further judgment. The parity check for other rows of PUF cells in PUF array 301 can be performed in the same manner, and will not be elaborated here for the sake of simplicity.

[0082] To better understand the parity check described above, please refer to [link / reference]. Figure 6 This is a schematic diagram illustrating the workflow of parity checking for a group of PUF cells in a PUF array 301 according to an embodiment of the present invention. It should be noted that... Figure 6 The workflow shown is for illustrative purposes only and is not intended to limit the invention. Furthermore, one or more steps may be added, deleted, or modified in this workflow. These steps do not necessarily need to be strictly followed if the same result is obtained. Figure 6 Execute in the order shown.

[0083] In step S610, PUF data (e.g., multiple output bits) is extracted from transistor M0 using a single-ended sensing scheme.

[0084] In step S620, PUF data (e.g., multiple parity bits) is extracted from transistor M1 using a single-ended sensing scheme.

[0085] In step S630, the BIST circuit 30 (e.g., comparator circuit 330) checks the Hamming distance (in [the distance between the PUF data from transistor M0 and the PUF data from transistor M1)). Figure 6 The label is written as "Check HD between M0 and M1" for brevity.

[0086] In step S640, the controller 30C can determine whether the calculation result of the Hamming distance (e.g., indicating a parity check result of the Hamming distance) meets a predetermined standard (e.g., determining whether the Hamming distance is greater than a predetermined value). For simplicity, this step is... Figure 6 The indicator is "Does the HD result meet the standard?". For example, when the plurality of output bits and the plurality of parity bits are all 32-bit strings, the predetermined value can be set to 30. If the judgment result is "yes", the workflow proceeds to step S650; if the judgment result is "no", the workflow proceeds to step S660. For example, for a single row of PUF cells in PUF array 301, the controller 30C can determine whether the calculated result of the Hamming distance corresponding to this single row of PUF cells meets the standard. As another example, after calculating the Hamming distances of PUF cells corresponding to all rows in PUF array 301, the controller 30C can determine whether the entire PUF array 301 meets the standard based on the summary / sum of these calculation results.

[0087] In step S650, the BIST circuit 30 can output PUF data from transistor M0 or M1 using the PUF device 300. For example, when the PUF data is used as a final random code, the PUF data is extracted only from transistor M0 and not from transistor M1 (e.g., only the output bits are output from the PUF array 301, while the parity bits are not output). As another example, when the PUF data is used as the final random code, the PUF data is extracted only from transistor M1 and not from transistor M0 (e.g., only the parity bits are output from the PUF array 301, while the output bits are not output).

[0088] In step S660, the BIST circuit 30 may output an alarm signal to notify the user or the electronic device coupled to the BIST circuit 30 that the parity check result of the PUF device 300 fails to meet the standard.

[0089] In the above description, a row of PUF cells can be used as an example of a unit for performing parity checks, but the invention is not limited thereto. In other embodiments, different numbers of PUF cells can be grouped together as a unit for performing the above-described parity checks, and the number of bits in the comparison circuit 330 can be varied accordingly. As mentioned above, the output bits and parity bits from the same PUF cell are expected to have opposite logic values. In practice, when the number of defective PUF cells in the PUF array 301 is less than a tolerable number, the PUF array 301 can still be considered to have passed the parity check. Therefore, the implementation details of the criteria for determining whether the PUF array 301 passes the parity check can vary according to the manufacturer's needs and are not limited to any specific rule described above.

[0090] Figure 7 This is a schematic diagram illustrating the distribution of readout voltage (or readout current) of each PUF cell in a selected group of PUF cells from a PUF array 301 according to an embodiment of the present invention, wherein... Figure 7 The horizontal axis represents the readout voltage (or readout current) from transistor M0 or M1, while Figure 7 The vertical axis represents the number of hits corresponding to these readout voltages (or readout currents). When the sense voltage VSEN is set to the normal sense level V... NS And the reference voltage VREF is set to the normal reference level V. NR At that time, the distribution of readout voltages from the broken transistors within the selected PUF cells of the group can be determined by... Figure 7 The curve labeled "ON normal read (ONNR)" represents the reading voltage distribution from the unbroken transistors within the selected PUF cells. Figure 7 The curve labeled "OFF normal read (OFFNR)" represents this. To check the reliability of the PUF device 300, the BIST circuit 30 can shift the sense voltage VSEN or the reference voltage VREF to make the readout operation more critical or threshold. If the data extracted from the selected PUF cells in the group remains unchanged, it indicates that the amount of shift applied to the sense voltage VSEN or the reference voltage VREF is tolerable.

[0091] In one embodiment, the BIST circuit 30 can use an offset voltage ΔV R The reference voltage VREF is varied to a turn-on margin level ONMVREF (e.g., ONMVREF = V). NR +ΔV RThis makes the operation of judging the read voltage from the broken transistor as "0" more thresholded. With the reference voltage VREF set to the on-margin level ONMVREF, all PUF data in the PUF array 301 (32×32 output bits extracted from the PUF device 300) can first be poured to register 311. When the first row of PUF cells in the PUF array 301 is selected, the multiplexer 320 can select the X decoder 312 to output a reference voltage on-margin string from the first row of storage cells in register 311, wherein the output bits in the reference voltage on-margin string are extracted from the first row of PUF cells. The BIST circuit 30 can use the offset voltage ΔV R The reference voltage VREF is varied to adjust the reference voltage VREF to an off-margin level OFFMVREF (e.g., OFFMVREF = V). NR –ΔV R This makes the operation of judging the read voltage from an unbroken transistor as "1" more thresholded. The readout circuit 304 can output a reference voltage off margin string from the first row of PUF cells, wherein the output bits within the reference voltage off margin string are extracted from the first row of PUF cells. The comparator circuit 330 can check whether the reference voltage on margin string and the reference voltage off margin string are consistent to produce a reference voltage margin check result, wherein the on margin level ONMVREF is greater than the off margin level OFFMVREF. The comparator circuit 330 may include a counter to count how many PUF cells in the first row of PUF cells pass the margin check. For example, the counter of the comparator circuit 330 can produce the reference voltage margin check result, indicating how many PUF cells in the first row of PUF cells can tolerate this variation (i.e., offset voltage ΔV). R The reference voltage margin check result is then sent back to the controller 30C for further judgment. For example, when the reference voltage margin check result indicates that the reference voltage enable margin string and the reference voltage disable margin string are consistent, the controller 30C can determine that the first row of PUF units has passed the reference voltage margin check.

[0092] In one embodiment, the BIST circuit 30 can be used with an offset voltage ΔV S The sensing voltage VSEN is varied to adjust the sensing voltage VSEN to a turn-on margin level V. ONMS (e.g. V) ONMS =V NS –ΔV S This causes the distribution of the read voltage from the broken transistor to be shifted to the left. Figure 7The distribution is labeled ONMR, and the operation where the read voltage from the broken transistor is judged as "0" becomes more threshold-sensitive. The sensing voltage VSEN is set to the turn-on margin level V. ONMS In this case, all PUF data in PUF array 301 (32×32 output bits extracted from PUF device 300) can be first poured into register 311. When the first row of PUF units in PUF array 301 is selected, multiplexer 320 can select X decoder 312 to output a sensed voltage enable margin string from the first row of storage units in register 311, wherein the output bits in the sensed voltage enable margin string are extracted from the first row of PUF units. BIST circuit 30 can use offset voltage ΔV S The sensing voltage VSEN is varied to adjust the sensing voltage VSEN to a shutdown margin level V. OFFMS (e.g. V) OFFMS =V NS +ΔV S This shifts the distribution of the readout voltage from the unbroken transistor to the right. Figure 7 The distribution marked as OFFMR, and the operation where the read voltage from the unbroken transistor is judged as "1", becomes more thresholded. The readout circuit 304 can output a sensed voltage turn-off margin string from the first row of PUF cells, wherein the output bits within the sensed voltage turn-off margin string are extracted from the first row of PUF cells. The comparator circuit 330 can check whether the sensed voltage turn-on margin string and the sensed voltage turn-off margin string are consistent to generate a sensed voltage margin check result, wherein the turn-on margin level V... ONMS Less than the off margin level V OFFMS The counter in the comparator circuit 330 operates similarly to the counter for the sensed voltage margin check result as it does for the reference voltage margin check result, and will not be described further here for the sake of simplicity.

[0093] It should be noted that margin checks (e.g., reference voltage margin checks and sense voltage margin checks) for PUF cells in other rows of PUF array 301 can be performed similarly, and the relevant details will not be repeated here. Furthermore, in the above description, a row of PUF cells can be used as an example of a unit for performing margin checks, but the invention is not limited to this. In other embodiments, different numbers of PUF cells can be grouped together as a unit for performing the aforementioned margin checks, and the number of bits in the comparison circuit 330 can be varied accordingly. Additionally, the implementation details of the criteria used to determine whether PUF array 301 passes the margin check (e.g., the acceptable number of PUF cells that cannot tolerate an offset applied to the sense voltage VSEN or reference voltage VREF) can vary according to manufacturer requirements and are not limited to any specific rule described above. In some embodiments, when the margin check (e.g., either the reference voltage margin check or the sense voltage margin check) fails, the controller 30C can reduce the offset voltage ΔV. R and / or ΔV S Until the PUF array 301 passes the margin check, the reliability of a corresponding degree of the PUF array 301 can be determined based on the reduced offset voltage ΔV. R and / or ΔV S It is estimated that, but the present invention is not limited thereto.

[0094] Figure 8 This is a schematic diagram of a decoding scheme for a PUF array 301 according to an embodiment of the present invention, wherein all PUF data in the PUF array 301 (e.g., 32×32 output bits from the PUF device 300) can be transferred to register 311. For ease of understanding, the data stored in register 311 can be represented as D. RA,CA Let RA represent the row address and CA represent the column address. For example, the data stored in the first row of register 311 could be {D}. 0,0 D 0,1 D 0,2 ,…,D 0,30 D 0,31}; The data stored in the second row of register 311 can be {D 1,0 D 1,1 D 1,2 ,…,D 1,30 D 1,31}; The data stored in the third row of register 311 can be {D 2,0 D 2,1 D 2,2 ,…,D 2,30 D 2,31}; and the rest can be deduced similarly. For example, the data stored in the thirty-second row of register 311 could be {D 31,0 D31,1 D 31,2 ,…,D 31,30 D 31,31 Additionally, the X decoder 312 can generate each of the horizontal strings PX(0), PX(1), PX(2), ..., PX(31) by collecting the output bits read from a set of horizontally arranged PUF units into a group, where these horizontal strings {PX(nx)|nx=0,1,2,…,31}={D nx,0 D nx,1 D nx,2 ,…,D nx,30 D nx,31 The Y decoder 313 can generate each of the vertical strings PX(0), PX(1), PX(2), ..., PX(31) by collecting the output bits read from a set of vertically arranged PUF units into a set, where these vertical strings {PY(ny)|ny=0,1,2,…,31}={D 0,ny D 1,ny D 2,ny ,…,D 30,ny D 31,ny}. The Z decoder 314 can generate each of the skewed strings PZ(0), PZ(1), PZ(2), ... and PZ(31) by collecting the output bits read from a set of skewed PUF units arranged in the skew direction into a set, where PZ(0) = {D 0,0 D 1,1 D 2,2 ,…,D 30,30 D 31,31}、PZ(1)={D 0,1 D 1,2 D 2,3 ,…,D 30,31 D 31,0}, and PZ(2)={D 0,2 D 1,3 D 2,4 ,…,D 30,0 D 31,1}, and so on, for example PZ(30)={D 0,30 D 1,31 D 2,0 ,…,D 30,28 D 31,29}, and PZ(31)={D 0,31 D 1,0 D 2,1 ,…,D 30,29 D 31,30In this embodiment, the BIST circuit 30 can generate at least one health check result based on at least one of the horizontal string {PX(nx)|nx=0,1,2,…,31}, the vertical string {PY(ny)|ny=0,1,2,…,31}, and / or the skewed string {PZ(nz)|nz=0,1,2,…,31} (e.g., a combination thereof).

[0095] In the first part of the health check, the comparison circuit 250 may use its internal accumulator 351 (e.g., a 5-bit accumulator) to calculate a horizontal Hamming weight for each of the horizontal strings {PX(nx)|nx=0,1,2,…,31}, a vertical Hamming weight for each of the vertical strings {PY(ny)|ny=0,1,2,…,31}, and a skew Hamming weight for each of the skew strings {PZ(nz)|nz=0,1,2,…,31}. The comparison circuit 250 may further use its internal comparator 352 (e.g., a 5-bit comparator) to determine whether the horizontal Hamming weights, the vertical Hamming weights, and the skew Hamming weights meet predetermined criteria (e.g., whether they fall within a predetermined range) to produce the result of the first part of the health check. It should be noted that the Hamming weight of a string is the number of non-zero bits (e.g., logic "1") in that string, while the number of zero bits in a set of random bits is expected to be approximately the same as the number of non-zero bits. Based on the aim of ensuring that the difference between the number of zero bits and the number of non-zero bits extracted from a set of PUF cells in PUF array 301 is less than a tolerable value, the implementation details of the predetermined criteria used to determine whether PUF array 301 passes the health check can vary according to manufacturer requirements and are not limited to any specific rule described above. For example, a set of PUF cells (e.g., any or each of the horizontal string PX(nx), vertical string PY(ny), and skew string PZ(nz)) can be judged to have passed the health test when the Hamming weight of this set of PUF cells (e.g., any or each of the aforementioned horizontal Hamming weight, vertical Hamming weight, and skew Hamming weight) equals an ideal value (e.g., when the Hamming weight of a 32-bit string equals 16). For example, a group of PUF units (e.g., any one or each of the horizontal string PX(nx), vertical string PY(ny), and skewed string PZ(nz)) can be judged to have passed the health test if the error of the Hamming weight (e.g., any one or each of the aforementioned horizontal Hamming weight, vertical Hamming weight, and skewed Hamming weight) relative to the ideal value falls within a tolerable range, such as ±4% (e.g., when the Hamming weight of a 32-bit string falls between 14 and 18). It should be noted that the predetermined standard (e.g., the tolerable range) can be determined based on calculations from a statistical distribution model and can be adjusted in practice according to requirements (e.g., acceptable randomness).

[0096] In the second part of the health check, the BIST circuit 30 can, with the aid of the comparison circuit 330, calculate a horizontal Hamming distance between horizontal strings PX(m1) and PX(m2), a vertical Hamming distance between vertical strings PY(m1) and PY(m2), and a skewed Hamming distance between skewed strings PZ(m1) and PZ(m2) to generate the result of the second part of the health check based on the horizontal Hamming distance, the vertical Hamming distance, and / or the skewed Hamming distance (e.g., a combination thereof), where m1 and m2 are two distinct values ​​in the range of 0 to 31. Furthermore, this embodiment preferably selects two physically adjacent sets of PUF bits (e.g., m2 = m1 + 1) for the above calculation, but the invention is not limited thereto. In some embodiments, m2 = m1 + n, where n is any suitable integer.

[0097] For example, the X decoder 312 and the multiplexer 320 can first output the horizontal string PX(0) to the register 360 (e.g., a 32-bit register), and then output the horizontal string PX(1) to the comparator circuit 330. The comparator circuit 330 can perform a bit-by-bit comparison between the horizontal string PX(0) and the horizontal string PX(1), and can calculate (e.g., by means of a counter) the horizontal Hamming distance between the horizontal strings PX(0) and PX(1) based on the comparison result. The rest can be deduced in the same way. For example, the horizontal Hamming distance between horizontal strings PX(2) and PX(3), the horizontal Hamming distance between horizontal strings PX(4) and PX(5), ... and the horizontal Hamming distance between horizontal strings PX(30) and PX(31) can be calculated in the above manner, that is, m1 = 0, 2, 4, ... and 30 and m2 = 1, 3, 5, ... and 31, but the present invention is not limited thereto. Similarly, the Y decoder 313 and the multiplexer 320 can first output the vertical string PY(0) to the register 360 (e.g., a 32-bit register), and then output the vertical string PY(1) to the comparator circuit 330. The comparison circuit 330 can perform a bit-by-bit comparison between the vertical string PY(0) and the vertical string PY(1), and can calculate (e.g., by a counter) the vertical Hamming distance between the vertical strings PY(0) and PY(1) based on the comparison result. The rest can be calculated similarly. For example, the vertical Hamming distance between the vertical strings PY(2) and PY(3), the vertical Hamming distance between the vertical strings PY(4) and PY(5), ... and the vertical Hamming distance between the vertical strings PY(30) and PY(31) can be calculated in the above manner, i.e., m1 = 0, 2, 4, ... and 30 and m2 = 1, 3, 5, ... and 31, but the invention is not limited thereto. Similarly, the Z decoder 314 and the multiplexer 320 can first output the skewed string PZ(0) to the register 360 (e.g., a 32-bit register), and then output the skewed string PZ(1) to the comparator circuit 330. The comparator circuit 330 can perform a bit-by-bit comparison between the skewed string PZ(0) and the skewed string PZ(1), and can calculate (e.g., by a counter) the skewed Hamming distance between the skewed string PZ(0) and the skewed string PZ(1) based on the comparison result. The rest can be deduced in the same way. For example, the skew Hamming distance between skewed string PZ(2) and skewed string PZ(3), the skew Hamming distance between skewed string PZ(4) and skewed string PZ(5), ... and the skew Hamming distance between skewed string PZ(30) and skewed string PZ(31) can be calculated in the above way, that is, m1 = 0, 2, 4, ... and 30 and m2 = 1, 3, 5, ... and 31, but the present invention is not limited to this.In some embodiments, m1 = 0, 1, 2, ..., and 30, while m2 = 1, 2, 3, ..., and 31. In some embodiments, m1 = 0, 4, 8, 12, ..., and 28, while m2 = 1, 5, 9, ..., and 29. These design variations are all within the scope of this invention.

[0098] It should be noted that any two strings extracted from a set of random bits are expected to be as different from each other as possible, and the Hamming distance between these two strings is expected to be greater than a predetermined value. Based on this, the implementation details of the predetermined criteria used to determine whether the PUF array 301 passes the second part of the health check can vary according to the manufacturer's requirements and are not limited to any specific rule described above. Furthermore, after the controller 30C receives the results of the first part and the second part of the health check, the controller 30C can summarize these results to determine whether the PUF array 301 passes the health check. For example, the controller 30C may only determine that the PUF array 301 passes the health check if both the first part and the second part of the health check meet the predetermined criteria, but the present invention is not limited to this.

[0099] In summary, embodiments of the present invention provide a BIST circuit and a BIST method that ensure authenticity, reliability, and randomness through parity checks, margin checks, and health checks proposed in this invention. The aforementioned parity checks, margin checks, and health checks can be performed separately or together. Furthermore, since the relevant test circuitry is built into the PUF device, no external measurement equipment is required, significantly reducing testing time and labor costs. Additionally, embodiments of the present invention do not significantly increase additional hardware; therefore, the present invention can improve the efficiency of PUF quality checks with little or no side effects.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A built-in self-test circuit for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable functional array includes multiple physically non-replicable functional units, wherein each of the multiple physically non-replicable functional units includes a first storage unit and a second storage unit, the first storage unit includes a first transistor, the second storage unit includes a second transistor, the first transistor and the second transistor are connected in series, and the first transistor and the second transistor are registered simultaneously during initialization. A readout circuit, coupled to the physically non-replicable functional array, is used to output an output string containing multiple output bits read from a first storage cell of multiple selected physically non-replicable functional units, and a parity string containing multiple parity bits read from a second storage cell of the multiple selected physically non-replicable functional units. as well as A first comparison circuit, coupled to the readout circuit, is used to generate a parity check result based on a Hamming distance between the output string and the parity string. For each of the plurality of selected physically non-replicable functional units, the first comparison circuit checks whether the output bit and parity bit of each of the plurality of selected physically non-replicable functional units have opposite logic values.

2. The built-in self-test circuit as described in claim 1, characterized in that, Also includes: A controller, coupled to the first comparison circuit, is used to determine whether the parity check result meets a predetermined standard.

3. The built-in self-test circuit as described in claim 1, characterized in that, The readout circuit includes: A sensing amplifier is configured to output the output bit based on a readout voltage read from a first storage cell of each of the plurality of selected physically non-replicable functional units, wherein the output bit has a first logic value when the readout voltage is less than a reference voltage, and the output bit has a second logic value when the readout voltage is greater than the reference voltage.

4. A built-in self-test circuit for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable functional array includes multiple physically non-replicable functional units, wherein each of the multiple physically non-replicable functional units includes a first storage unit and a second storage unit. A readout circuit, coupled to the physically non-replicable functional array, is used to output an output string containing a plurality of output bits read from a first storage cell of a plurality of selected physically non-replicable functional units, and a parity string containing a plurality of parity bits read from a second storage cell of the plurality of selected physically non-replicable functional units, wherein the readout circuit comprises: A sensing amplifier is configured to output an output bit based on a readout voltage read from a first storage cell of each of the plurality of selected physically non-replicable functional units, wherein the output bit has a first logic value when the readout voltage is less than a reference voltage, and has a second logic value when the readout voltage is greater than the reference voltage; and A first comparison circuit, coupled to the readout circuit, is used to generate a parity check result based on a Hamming distance between the output string and the parity string. The readout circuit outputs an enable margin string from the plurality of selected physical non-replicable functional units by setting the reference voltage to an enable margin level, and outputs a disable margin string from the plurality of selected physical non-replicable functional units by setting the reference voltage to a disable margin level. The first comparison circuit checks whether the enable margin string and the disable margin string are consistent to generate a margin check result; wherein the enable margin level is greater than the disable margin level.

5. A built-in self-test circuit for checking the quality of physically unreplicable functions, characterized in that, Include: A physically non-replicable functional array includes multiple physically non-replicable functional units, wherein each of the multiple physically non-replicable functional units includes a first storage unit and a second storage unit. A readout circuit, coupled to the physically non-replicable functional array, is used to output an output string containing a plurality of output bits read from a first storage cell of a plurality of selected physically non-replicable functional units, and a parity string containing a plurality of parity bits read from a second storage cell of the plurality of selected physically non-replicable functional units, wherein the readout circuit comprises: A sensing amplifier is configured to output an output bit based on a readout voltage read from a first storage cell of each of the plurality of selected physically non-replicable functional units, wherein the output bit has a first logic value when the readout voltage is less than a reference voltage, and has a second logic value when the readout voltage is greater than the reference voltage; and A first comparison circuit, coupled to the readout circuit, is used to generate a parity check result based on a Hamming distance between the output string and the parity string. When the readout circuit reads the readout voltage from the first storage cell, a sensing voltage is applied to the first storage cell; The readout circuit outputs an enable margin string from the plurality of selected physical non-replicable functional units by setting the sensing voltage to an enable margin level, and outputs a disable margin string from the plurality of selected physical non-replicable functional units by setting the sensing voltage to a disable margin level. The first comparison circuit checks whether the enabled margin string and the disabled margin string are consistent, so as to generate a margin check result. The enable margin level is less than the disable margin level.

6. A built-in self-test circuit for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable functional array includes multiple physically non-replicable functional units, wherein each of the multiple physically non-replicable functional units includes a first storage unit and a second storage unit. A readout circuit, coupled to the physically non-replicable functional array, is used to output an output string containing multiple output bits read from a first storage cell of multiple selected physically non-replicable functional units, and a parity string containing multiple parity bits read from a second storage cell of the multiple selected physically non-replicable functional units. A first comparison circuit, coupled to the readout circuit, is used to generate a parity check result based on a Hamming distance between the output string and the parity string. A horizontal decoder, coupled to the physically non-copyable functional array, is used to generate a first horizontal string by collecting multiple output bits read from a first group of horizontally arranged physically non-copyable functional units into a group. A vertical decoder, coupled to the physically non-copyable functional array, is used to generate a first vertical string by collecting multiple output bits read from a first group of vertically arranged physically non-copyable functional units into a group. as well as A skew decoder, coupled to the physically non-copyable functional array, is used to generate a first skewed string by collecting multiple output bits read from a first group of skewed physically non-copyable functional units arranged in the skew direction into a group. One of the health check results is generated based on the first horizontal string, the first vertical string, the first skewed string, or a combination thereof.

7. The built-in self-test circuit as described in claim 6, characterized in that, Also includes: A second comparison circuit is configured to receive one or more of the first horizontal string, the first vertical string, and the first skewed string, and calculate one or more of the first horizontal Hamming weight of the first horizontal string, the first vertical Hamming weight of the first vertical string, and the first skewed Hamming weight of the first skewed string, and determine whether the one or more of the first horizontal Hamming weight, the first vertical Hamming weight, and the first skewed Hamming weight meet a predetermined standard, so as to generate the health check result.

8. The built-in self-test circuit as described in claim 6, characterized in that, The horizontal decoder generates a second horizontal string by collecting multiple output bits read from a second set of horizontally physically non-copyable functional units arranged in the horizontal direction into a group; the vertical decoder generates a second vertical string by collecting multiple output bits read from a second set of vertically physically non-copyable functional units arranged in the vertical direction into a group. The skew decoder generates a second skewed string by collecting multiple output bits read from a second set of skewed physically non-replicable functional units arranged in the skew direction; wherein a horizontal Hamming distance between the first horizontal string and the second horizontal string is calculated using the first comparison circuit, a vertical Hamming distance between the first vertical string and the second vertical string is calculated using the first comparison circuit, and a skewed Hamming distance between the first skewed string and the second skewed string is calculated using the first comparison circuit, to generate the health check result based on the horizontal Hamming distance, the vertical Hamming distance, the skewed Hamming distance, or a combination thereof.

9. The built-in self-test circuit as described in claim 8, characterized in that, The first group of horizontally physically non-replicable functional units is physically adjacent to the second group of horizontally physically non-replicable functional units, the first group of vertically physically non-replicable functional units is physically adjacent to the second group of vertically physically non-replicable functional units, and the first group of skewed physically non-replicable functional units is substantially adjacent to the second group of skewed physically non-replicable functional units.

10. A built-in self-testing method for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable functional array is used to provide physically non-replicable functional values. The array comprises multiple physically non-replicable functional units, each of which includes a first storage unit and a second storage unit. The first storage unit includes a first transistor. The second memory cell includes a second transistor, the first transistor and the second transistor are connected in series, and the first transistor and the second transistor are registered simultaneously during initialization; An output string containing multiple output bits read from multiple first storage cells of multiple selected physically non-copyable functional units and a parity string containing multiple parity bits read from multiple second storage cells of the multiple selected physically non-copyable functional units are output using a readout circuit. as well as A parity check result is generated using a first comparison circuit based on a Hamming distance between the output string and the parity string. The generation of the parity check result using the first comparison circuit based on the Hamming distance between the output string and the parity string includes: For each of the plurality of selected physically non-replicable functional units, check whether the output bit and parity bit of each of the plurality of selected physically non-replicable functional units have opposite logical values.

11. The built-in self-testing method as described in claim 10, characterized in that, Also includes: Determine whether the parity check result meets the predetermined standard.

12. The built-in self-testing method as described in claim 10, characterized in that, The output of the plurality of output bits from the first storage cell using the readout circuit includes: A sense amplifier using the readout circuit outputs the output bit based on a readout voltage read from a first storage cell of each of the plurality of selected physically non-replicable functional units; When the readout voltage is less than a reference voltage, the output bit has a first logic value, and when the readout voltage is greater than the reference voltage, the output bit has a second logic value.

13. A built-in self-testing method for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable function value is provided using a physically non-replicable function array, wherein the physically non-replicable function array includes a plurality of physically non-replicable function units, and each of the plurality of physically non-replicable function units includes a first storage unit and a second storage unit. An output string containing multiple output bits read from multiple first storage cells of multiple selected physically non-copyable functional units, and a parity string containing multiple parity bits read from multiple second storage cells of the multiple selected physically non-copyable functional units, wherein the multiple output bits output from the first storage cells by the read circuit include: A sense amplifier using the readout circuit outputs the output bit based on a readout voltage read from a first storage cell of each of the plurality of selected physically non-replicable functional units; When the readout voltage is less than a reference voltage, the output bit has a first logic value, and when the readout voltage is greater than the reference voltage, the output bit has a second logic value. A parity check result is generated using a first comparison circuit based on a Hamming distance between the output string and the parity string. The readout circuit uses the reference voltage to set to an enable margin level to output an enable margin string from the plurality of selected physical non-replicable functional units, and uses the readout circuit to set the reference voltage to a disable margin level to output a disable margin string from the plurality of selected physical non-replicable functional units. as well as The first comparison circuit is used to check whether the enabled margin string and the disabled margin string are consistent, so as to generate a margin check result. The enable margin level is greater than the disable margin level.

14. A built-in self-testing method for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable function value is provided using a physically non-replicable function array, wherein the physically non-replicable function array includes a plurality of physically non-replicable function units, and each of the plurality of physically non-replicable function units includes a first storage unit and a second storage unit. An output string containing multiple output bits read from multiple first storage cells of multiple selected physically non-copyable functional units, and a parity string containing multiple parity bits read from multiple second storage cells of the multiple selected physically non-copyable functional units, wherein the multiple output bits output from the first storage cells by the read circuit include: A sense amplifier using the readout circuit outputs the output bit based on a readout voltage read from a first storage cell of each of the plurality of selected physically non-replicable functional units; When the readout voltage is less than a reference voltage, the output bit has a first logic value, and when the readout voltage is greater than the reference voltage, the output bit has a second logic value. as well as A parity check result is generated using a first comparison circuit based on a Hamming distance between the output string and the parity string. When the readout circuit reads the readout voltage from the first memory cell, a sensing voltage is applied to the first memory cell, and the built-in self-test method further includes: The readout circuit is used to set the sensing voltage to an enable margin level to output an enable margin string from the plurality of selected physical non-replicable functional units, and the readout circuit is used to set the sensing voltage to a disable margin level to output a disable margin string from the plurality of selected physical non-replicable functional units. as well as The first comparison circuit is used to check whether the enabled margin string and the disabled margin string are consistent, so as to generate a margin check result. The enable margin level is less than the disable margin level.

15. A built-in self-testing method for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable function value is provided using a physically non-replicable function array, wherein the physically non-replicable function array includes a plurality of physically non-replicable function units, and each of the plurality of physically non-replicable function units includes a first storage unit and a second storage unit. An output string containing multiple output bits read from multiple first storage cells of multiple selected physically non-copyable functional units and a parity string containing multiple parity bits read from multiple second storage cells of the multiple selected physically non-copyable functional units are output using a readout circuit. A parity check result is generated using a first comparison circuit based on a Hamming distance between the output string and the parity string. A first horizontal string is generated by using a horizontal decoder to collect multiple output bits read from a first group of horizontally arranged, physically non-copyable functional units into a group. A first vertical string is generated by using a vertical decoder to collect multiple output bits read from a first group of vertically physically non-copyable functional units arranged in a vertical direction into a group. A first skewed string is generated by using a skewed decoder to collect multiple output bits read from a first group of skewed physically non-copyable functional units arranged in the skew direction into a group. as well as A health check result is generated based on the first horizontal string, the first vertical string, the first skewed string, or a combination thereof.

16. The built-in self-testing method as described in claim 15, characterized in that, Also includes: A second comparison circuit is used to receive one or more of the first horizontal string, the first vertical string, and the first skewed string, and to calculate one or more of the following: a first horizontal Hamming weight for the first horizontal string, a first vertical Hamming weight for the first vertical string, and a first skewed Hamming weight for the first skewed string; and Determine whether one or more of the first horizontal Hamming weight, the first vertical Hamming weight, and the first skewed Hamming weight meet a predetermined standard to generate the health check result.

17. The built-in self-testing method as described in claim 15, characterized in that, Also includes: The horizontal decoder uses multiple output bits read from a second set of horizontally physically non-copyable functional units arranged in a horizontal direction to generate a second horizontal string. The vertical decoder uses multiple output bits read from a second set of vertically physically non-copyable functional units arranged in a vertical direction to generate a second vertical string. as well as The skew decoder uses multiple output bits read from a second set of skew physically non-copyable functional units arranged in the skew direction to generate a second skewed string. The first comparison circuit is used to calculate a horizontal Hamming distance between the first horizontal string and the second horizontal string; A vertical Hamming distance between the first vertical string and the second vertical string is calculated using the first comparison circuit. as well as The first comparison circuit is used to calculate a skewed Hamming distance between the first skewed string and the second skewed string, so as to generate the health check result based on the horizontal Hamming distance, the vertical Hamming distance, the skewed Hamming distance, or a combination thereof.

18. The built-in self-testing method as described in claim 17, characterized in that, The first group of horizontally physically non-replicable functional units is physically adjacent to the second group of horizontally physically non-replicable functional units, the first group of vertically physically non-replicable functional units is physically adjacent to the second group of vertically physically non-replicable functional units, and the first group of skewed physically non-replicable functional units is physically adjacent to the second group of skewed physically non-replicable functional units.

19. A built-in self-test circuit for quality inspection of physically unreplicable functions, characterized in that, Include: A physically non-replicable functional array, containing multiple physically non-replicable functional units; A comparison circuit is used to receive a first horizontal string, a first vertical string, and a first skew string from the physically non-replicable functional array, to calculate a horizontal Hamming weight of the first horizontal string, a vertical Hamming weight of the first vertical string, and a skew Hamming weight of the first skew string, and to determine whether the horizontal Hamming weight, the vertical Hamming weight, and the skew Hamming weight meet a predetermined standard, so as to generate a health check result. A horizontal decoder, coupled to the physically non-copyable functional array, is used to generate the first horizontal string by collecting multiple output bits read from a first group of horizontally arranged physically non-copyable functional units into a group. A vertical decoder, coupled to the physically non-copyable functional array, is used to generate the first vertical string by collecting multiple output bits read from a first group of vertically arranged physically non-copyable functional units into a group. as well as A skewed decoder, coupled to the physically non-copyable function array, is used to generate the first skewed string by collecting multiple output bits read from a first group of skewed physically non-copyable function units arranged in the skew direction into a group. One of the health check results is generated based on the first horizontal string, the first vertical string, the first skewed string, or a combination thereof.

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