Wafer dicing method

Abstract

The application provides a wafer dicing method, comprising the following steps: providing a wafer; performing a first cutting to cut a medium layer along a thickness direction of the wafer to stop at a side surface of a substrate close to a metal layer, and forming a first groove at the cutting position; forming a hybrid bonding structure on a side surface of the substrate far from the metal layer; performing a second cutting to cut the hybrid bonding structure to stop at the side surface of the substrate far from the metal layer, and forming a second groove at the cutting position; and taking a patterned photoresist layer as a mask, penetrating the substrate exposed by the second groove, and connecting the second groove with the first groove. Through the first cutting, the second cutting, and taking the patterned photoresist layer as the mask, penetrating the substrate exposed by the second groove, and connecting the second groove with the first groove, the wafer is cut in a sequential and phased manner along the thickness direction, so that the wafer is prevented from being split and the chips are prevented from being damaged in the dicing process; the surface of the hybrid bonding structure is not polluted and damaged due to the protection of the patterned photoresist layer, and effective wafer dicing is achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a wafer dicing method. Background Technology

[0002] As the microelectronics industry enters the post-Moore's Law era, chip structures are evolving towards three-dimensionality to further meet the demands for high integration, small size, and superior performance. Compared to wafer-to-wafer (W2W) stacking, chip-to-wafer (C2W) heterogeneous integration can achieve interconnection between chips of different technology nodes and sizes, offering greater flexibility. Furthermore, C2W can significantly improve yield by selecting known good dies (KGD) for bonding with wafers. C2W has become an important development direction for 3D-IC technology. Currently, C2W mass production solutions primarily utilize micro-bump packaging processes, with a minimum interconnect unit size of approximately 40μm. Moreover, the underfill between bumps hinders heat dissipation. Current research is moving towards bumpless processes with even smaller interconnect unit sizes. Bumpless processes utilize hybrid bonding technology to bond chips (C) formed after dicing one wafer to another (W).

[0003] Dicing a wafer is a crucial step, especially in protecting the hybrid bonding structure and bonding interfaces from damage. There are typically two dicing methods: blade dicing or laser dicing. Blade dicing can cause severe cleaving, while laser dicing, although effectively avoiding cleaving, cannot cut through in one pass due to thermal effects and requires blade dicing in conjunction with laser dicing. Furthermore, the test cells within the dicing channels of the first wafer contain materials such as copper, tungsten, or aluminum that are difficult to remove by dry etching or produce byproducts that are difficult to remove during dry etching, making plasma dicing unsuitable. Therefore, conventional dicing methods are not suitable for C2W 3D stacking processes based on hybrid bonding. Summary of the Invention

[0004] The purpose of this invention is to provide a wafer dicing method that protects the hybrid bonding structure and its surface (bonding interface) and avoids chip splitting and damage during the dicing process.

[0005] This invention provides a wafer dicing method, comprising:

[0006] A wafer is provided, the wafer including a substrate, a dielectric layer on the substrate, and a metal layer embedded in the dielectric layer;

[0007] The first cut is performed, cutting the dielectric layer along the thickness direction of the wafer and stopping on the side surface of the substrate near the metal layer, forming a first trench at the cut point;

[0008] A hybrid bonding structure is formed on the surface of the substrate away from the metal layer;

[0009] A second cut is performed, cutting at least the hybrid bonding structure along the thickness direction of the wafer to the side of the substrate away from the metal layer, forming a second trench at the cut; the second trench and the first trench have the same projection on the substrate;

[0010] A patterned photoresist layer is formed on the hybrid bonding structure, the patterned photoresist layer having an opening that is identical to the projection of the second trench onto the substrate;

[0011] Using the patterned photoresist layer as a mask, the second trench is connected to the first trench by penetrating the substrate exposed by the opening and the second trench.

[0012] Furthermore, after performing the first cut but before forming the hybrid bonding structure, the process also includes:

[0013] One side of the first cut wafer is bonded to the carrier wafer using bonding adhesive, which fills the first trench.

[0014] Furthermore, the process includes the following steps prior to forming the hybrid bonding structure:

[0015] The surface of the substrate away from the metal layer is thinned.

[0016] Furthermore, after the substrate is thinned but before the hybrid bonding structure is formed, the process includes:

[0017] An insulating layer is formed on the thinned substrate surface;

[0018] A through-silicon via is formed, the through-silicon via penetrating the insulating layer, the substrate, and a portion of the thickness of the dielectric layer to expose the metal layer;

[0019] An interconnect layer is formed, which fills the through-silicon via and is electrically connected to the metal layer.

[0020] Furthermore, after forming the interconnect layer, the method further includes:

[0021] A redistribution layer is formed, which covers the insulating layer and the interconnect layer. The redistribution layer includes a redistribution dielectric layer and a redistribution metal layer embedded in the redistribution dielectric layer. The redistribution metal layer is electrically connected to the interconnect layer.

[0022] Furthermore, forming the hybrid bonding structure includes:

[0023] A bonding dielectric layer is formed, which covers an insulating layer or the redistribution layer; an opening is made in the bonding dielectric layer, and a bonding metal layer is filled in the opening, the bonding metal layer being electrically connected to the interconnect layer or the redistribution metal layer; the bonding dielectric layer and the bonding metal layer constitute the hybrid bonding structure.

[0024] Furthermore, both the first and second cuts are performed using laser cutting or plasma cutting.

[0025] Furthermore, using the patterned photoresist layer as a mask, the substrate exposed by the opening and the second trench is etched using a dry etching method or a plasma cutting method.

[0026] Furthermore, the dielectric layer is also embedded with pads, which are electrically connected to the metal layer, and a passivation layer is formed on the dielectric layer, exposing the pads.

[0027] Furthermore, the top surfaces of the bonding dielectric layer and the bonding metal layer serve as a hybrid bonding interface.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] This invention provides a wafer dicing method, comprising: providing a wafer, the wafer including a substrate, a dielectric layer on the substrate, and a metal layer embedded in the dielectric layer; performing a first dicing, cutting the dielectric layer along the thickness direction of the wafer and stopping at a point on the substrate near the metal layer, forming a first trench at the dicing point; forming a hybrid bonding structure on a point on the substrate away from the metal layer; performing a second dicing, cutting the hybrid bonding structure along the thickness direction of the wafer and stopping at a point on the substrate away from the metal layer, forming a second trench at the dicing point; forming a patterned photoresist layer on the hybrid bonding structure, the patterned photoresist layer having an opening; using the patterned photoresist layer as a mask, penetrating the substrate exposed by the opening and the second trench, connecting the second trench with the first trench. This invention uses a first cut, a second cut, and a patterned photoresist layer as a mask to penetrate the substrate exposed by the opening and the second trench, connecting the second trench with the first trench. It cuts sequentially and in stages along the wafer thickness direction, avoiding splitting and chip damage during the dicing process. The surface of the hybrid bonding structure is protected from contamination and damage by the patterned photoresist layer formed by wafer-level exposure and development, thus achieving effective wafer dicing. Attached Figure Description

[0030] Figure 1 This is a schematic flowchart of a wafer dicing method according to an embodiment of the present invention.

[0031] Figures 2 to 11 This is a schematic diagram of each step in the wafer dicing method according to an embodiment of the present invention.

[0032] The accompanying figure is labeled as follows:

[0033] 10-Wafer; 11-Substrate; 12-Dielectric layer; 13a-Metal layer; 13b-Pad; 14-Passivation layer; 15-Bonding adhesive; 16-Insulating layer; 16a-Interconnect layer; 17-Redistribution layer; 17a-Redistribution metal layer; 18-Hybrid bonding structure; 18a-Bonding metal layer; 19-Patterned photoresist layer; 20-Carrier wafer. Detailed Implementation

[0034] Based on the above research, embodiments of the present invention provide a wafer dicing method. The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] This invention provides a wafer dicing method, such as... Figure 1 As shown, it includes:

[0036] S1. A wafer is provided, the wafer including a substrate, a dielectric layer on the substrate and a metal layer embedded in the dielectric layer;

[0037] S2. Perform the first cut, cut the dielectric layer along the thickness direction of the wafer and stop on the side surface of the substrate near the metal layer, forming a first trench at the cut;

[0038] S3. A hybrid bonding structure is formed on the surface of the substrate away from the metal layer;

[0039] S4. Perform a second cut, cutting the hybrid bonding structure along the thickness direction of the wafer and stopping at the side of the substrate away from the metal layer, forming a second trench at the cut; the second trench and the first trench have the same projection on the substrate;

[0040] S5. A patterned photoresist layer is formed on the hybrid bonding structure, the patterned photoresist layer having an opening that is the same as the projection of the second trench on the substrate;

[0041] S6. Using the patterned photoresist layer as a mask, penetrate the substrate exposed by the opening and the second trench to connect the second trench with the first trench.

[0042] The following is combined with Figures 2 to 6The steps of the wafer dicing method according to embodiments of the present invention are described.

[0043] like Figure 2 As shown, a wafer 10 is provided, the wafer 10 including a substrate 11, the substrate 11 having opposing first surfaces f1 and second surfaces f2, a dielectric layer 12 formed on the second surface f2 of the substrate, the dielectric layer 12 embedding a metal layer 13a and pads 13b. It should be understood that each chip on the wafer 10 is configured with one or more (≥2) pads 13b as needed. The number and position of the metal layers 13a in each chip on the wafer 10 are configured according to actual needs and are not limited. The pads 13b are electrically connected to the metal layers 13a as needed, and the pads 13b lead out the electrical signals of the chips on the wafer 10. A passivation layer 14 is formed on the dielectric layer 12, the passivation layer 14 exposing the pads 13b. The wafer 10 is tested and marked as a known good die (KGD). The dielectric layer 12 is not limited to a single-layer dielectric layer, but can also be a multi-layer composite dielectric layer, such as a composite dielectric layer including silicon dioxide layers and silicon nitride layers.

[0044] like Figure 3 As shown, the first cut is performed by cutting the dielectric layer 12 along the thickness direction of the wafer 10, stopping at the second surface f2 on the substrate 11 near the metal layer 13a, forming a first trench V1 at the cut. If a passivation layer 14 is formed on the dielectric layer 12, the passivation layer 14 and the dielectric layer 12 are cut along the dicing path, stopping at the second surface f2. The first cut can be performed by laser cutting or plasma cutting.

[0045] like Figure 4 As shown, the wafer 10 and the carrier wafer 20 are temporarily bonded. Bonding adhesive can be used for temporary bonding, forming a bonding adhesive 15 between the wafer 10 and the carrier wafer 20. The bonding adhesive 15 also fills the first trench V1 to provide support and protection.

[0046] like Figures 5 to 7 As shown, the surface of the substrate 11 away from the metal layer 13a (first surface f1) is thinned to form a hybrid bonding structure. An insulating layer 16 is formed on the thinned substrate 11 surface. The insulating layer is made of, for example, a silicon oxide layer and / or a silicon nitride layer. A through-silicon via (TSV) T1 is formed, penetrating the insulating layer 16, the substrate 11, and a portion of the dielectric layer 12 to expose the metal layer 13a. An interconnect layer 16a is formed in the TSV T1. The interconnect layer 16a is made of a metal, such as copper or tungsten. When the interconnect layer 16a is made of copper, it can be formed by electroplating. The interconnect layer 16a is electrically connected to the metal layer 13a. It should be understood that, for clarity of view, Figure 7Only one through-silicon via (TSV) and the interconnect layer 16a located within the TSV are shown. In practical applications, the number of TSVs in wafer 10 is not limited and can be configured in multiple ways as needed. The interconnect layer 16a fills the TSV and covers the surface of the insulating layer 16. A chemical mechanical polishing (CMP) process is performed to planarize the surfaces of the interconnect layer 16a and the insulating layer 16.

[0047] like Figure 8 As shown, a redistribution layer 17 is formed, which covers the insulating layer 16 and the interconnect layer 16a. The redistribution layer 17 includes a redistribution dielectric layer and a redistribution metal layer 17a embedded in the redistribution dielectric layer. The redistribution metal layer 17a is electrically connected to the interconnect layer 16a. The redistribution metal layer 17a enables the connection of electrical signals within the wafer.

[0048] A hybrid bonding structure 18 is formed, comprising a bonding dielectric layer and a bonding metal layer 18a embedded in the bonding dielectric layer. Specifically, a bonding dielectric layer is formed, which covers a redistribution layer 17. An opening is formed in the bonding dielectric layer, and the opening is filled with the bonding metal layer 18a, which is electrically connected to the redistribution metal layer 17a. The top surface of the bonding dielectric layer and the bonding metal layer 18a serves as the hybrid bond interface. Preferably, for ease of design, the hybrid bonding structure 18 may comprise a multi-layer structure, such as two layers.

[0049] In another embodiment, the redistribution layer 17 can be omitted, i.e., a hybrid bonding structure 18 can be formed directly on the insulating layer 16. Specifically, a bonding dielectric layer is formed, covering the insulating layer 16 and the interconnect layer 16a. An opening is formed in the bonding dielectric layer, and the opening is filled with a bonding metal layer 18a, which is electrically connected to the interconnect layer 16a. The top surfaces of the bonding dielectric layer and the bonding metal layer 18a serve as the hybrid bond interface. Preferably, for ease of design, the hybrid bonding structure 18 can comprise a multi-layer structure, such as two layers.

[0050] like Figure 8 and Figure 9 As shown, a second dicing is performed, cutting at least the hybrid bonding structure 18 along the thickness direction of the wafer, stopping at the surface of the thinned substrate 11. Specifically, the hybrid bonding structure 18, the redistribution layer 17, and the insulating layer 16 are cut sequentially at the surface of the thinned substrate 11, forming a second trench V2 at the cut. The projections of the second trench V2 and the first trench V1 on the substrate 11 are the same. The second dicing can be performed using laser cutting or plasma cutting. It should be understood that each chip after wafer dicing may include the redistribution layer 17 and the hybrid bonding structure 18. For clarity of illustration, Figure 9The redistribution metal layer 17a in the redistribution layer 17 and the bonding metal layer 18a in the hybrid bonding structure 18 are omitted.

[0051] like Figure 10 As shown, a patterned photoresist layer 19 is formed using an exposure and development process, and the patterned photoresist layer 19 covers the hybrid bonding structure 18. The patterned photoresist layer 19 has an opening V3 corresponding to the second trench V2. The opening V3, viewed from above, is, for example, grid-shaped, and the projection of the opening V3 onto the substrate 11 is the same as that of the second trench V2. The opening V3 and the second trench V2 expose dicing lines on the substrate 11.

[0052] like Figure 11 As shown, using the patterned photoresist layer 19 as a mask, wafer-level dry etching or plasma cutting is used to penetrate the substrate 11 exposed by the opening V3 and the second trench. The second trench is connected to the first trench, and the entire wafer is cut into multiple independent chips. This method does not require additional equipment.

[0053] A bonding adhesive 15 is formed between the wafer 10 and the carrier wafer 20. The bonding adhesive 15 fills the first trench and plays a supporting and protective role during the second dicing to form the second trench and through the substrate 11 exposed by the opening and the second trench. If the first trench is not filled with bonding adhesive 15, the gap at the first trench can easily lead to splitting or damage to the chip during the dicing process.

[0054] The patterned photoresist layer 19 protects the bonding interface of the wafer during dry etching or plasma dicing. This bonding interface is the top surface of the bonding dielectric layer and the bonding metal layer 18a. The patterned photoresist layer 19 can then be removed using an ashing process. The ashing process itself does not oxidize the metal (e.g., copper) at the bonding interface because it lacks a humid atmosphere. A cleaning process is added after the ashing process; an HF-containing solution can remove any possible CuO without damaging the bonding interface, for example, containing copper (Cu). A carrier film, such as a blue film or a UV film, is attached to the surface of the wafer containing the hybrid bonding structure 18. The carrier wafer 20 is debonded to the diced wafer, and the carrier wafer 20 is removed. The carrier wafer 20 is made of, for example, glass. Laser irradiation penetrates the carrier wafer 20 to the bonding adhesive 15, causing the bonding adhesive 15 to lose its adhesiveness, thereby peeling off (removing) the carrier wafer 20. The wafer is then cleaned to remove the bonding adhesive and dicing defects. The bonding adhesive 15 can be removed using a stripper. After the chip diced on the blue film is expanded, the chip (C) can be picked up from the blue film and bonded to another wafer (W) to achieve chip-to-wafer (C2W) three-dimensional stacking. Specifically, the side containing the hybrid bonding structure 18 is bonded to the other wafer to be bonded.

[0055] Chip-to-wafer (C2W) bonding involves bonding one or more known good dies (KGDs) to a wafer. Specifically, the picked-up dies can be fixed on a carrier (e.g., an electrostatic chuck) and pre-bonded directly to another wafer as a whole. Afterward, the carrier (e.g., the electrostatic chuck) releases the dies, the carrier is removed, the die surface is cleaned, and the pre-bonded dies and wafer are annealed to complete the hybrid bonding. Direct bonding methods can be used, such as low-temperature direct bonding methods below 450°C, or thermal load bonding methods. In these methods, a load is applied to multiple dies located on a carrier, and the multiple dies and the other wafer to be bonded are heated under vacuum to facilitate the formation of atomic bonds between their surfaces (usually metal surfaces, such as metal contact pads).

[0056] In summary, this invention provides a wafer dicing method, comprising: providing a wafer; performing a first dicing, cutting a dielectric layer along the thickness direction of the wafer and stopping at the side surface of the substrate near the metal layer, forming a first trench at the dicing point; forming a hybrid bonding structure on the side surface of the substrate away from the metal layer; performing a second dicing, cutting the hybrid bonding structure and stopping at the side surface of the substrate away from the metal layer, forming a second trench at the dicing point; using a patterned photoresist layer as a mask, penetrating the substrate exposed by the second trench, connecting the second trench to the first trench. Through the first dicing, the second dicing, and using a patterned photoresist layer as a mask to penetrate the substrate exposed by the second trench and connect the second trench to the first trench, dicing is performed sequentially and in stages along the wafer thickness direction, avoiding splitting and chip damage during the dicing process; the surface of the hybrid bonding structure is protected from contamination and damage by the patterned photoresist layer, achieving effective wafer dicing.

[0057] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0058] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A wafer dicing method, characterized in that, include: A wafer is provided, the wafer including a substrate, a dielectric layer on the substrate, and a metal layer embedded in the dielectric layer; The first cut is performed, cutting the dielectric layer along the thickness direction of the wafer and stopping on the side surface of the substrate near the metal layer, forming a first trench at the cut point; A hybrid bonding structure is formed on the surface of the substrate away from the metal layer; A second cut is performed, cutting at least the hybrid bonding structure along the thickness direction of the wafer to stop on the side of the substrate away from the metal layer, forming a second trench at the cut; The second trench and the first trench have the same projection on the substrate; A patterned photoresist layer is formed on the hybrid bonding structure, the patterned photoresist layer having an opening that is identical to the projection of the second trench onto the substrate; Using the patterned photoresist layer as a mask, the second trench is connected to the first trench by penetrating the substrate exposed by the opening and the second trench.

2. The wafer dicing method as described in claim 1, characterized in that, After the first cut is performed, but before the formation of the hybrid bonding structure, the process includes: One side of the first cut wafer is bonded to the carrier wafer using bonding adhesive, which fills the first trench.

3. The wafer dicing method as described in claim 1, characterized in that, The process further includes, prior to forming the hybrid bonding structure: The surface of the substrate away from the metal layer is thinned.

4. The wafer dicing method as described in claim 3, characterized in that, After the substrate is thinned but before the hybrid bonding structure is formed, the following steps are included: An insulating layer is formed on the thinned substrate surface; A through-silicon via is formed, the through-silicon via penetrating the insulating layer, the substrate, and a portion of the thickness of the dielectric layer to expose the metal layer; An interconnect layer is formed, which fills the through-silicon via and is electrically connected to the metal layer.

5. The wafer dicing method as described in claim 4, characterized in that, After forming the interconnect layer, it also includes: A redistribution layer is formed, which covers the insulating layer and the interconnect layer. The redistribution layer includes a redistribution dielectric layer and a redistribution metal layer embedded in the redistribution dielectric layer. The redistribution metal layer is electrically connected to the interconnect layer.

6. The wafer dicing method as described in claim 5, characterized in that, Forming the hybrid bonding structure includes: A bonding dielectric layer is formed, which covers the insulating layer or the redistribution layer; an opening is made in the bonding dielectric layer, and a bonding metal layer is filled in the opening, the bonding metal layer being electrically connected to the interconnect layer or the redistribution metal layer; the bonding dielectric layer and the bonding metal layer constitute the hybrid bonding structure.

7. The wafer dicing method according to any one of claims 1 to 6, characterized in that, Both the first and second cuts are performed using laser cutting or plasma cutting.

8. The wafer dicing method according to any one of claims 1 to 6, characterized in that, Using the patterned photoresist layer as a mask, the substrate exposed by the opening and the second trench is etched using either dry etching or plasma cutting.

9. The wafer dicing method according to any one of claims 1 to 6, characterized in that, The dielectric layer is further embedded with pads, which are electrically connected to the metal layer. A passivation layer is formed on the dielectric layer, exposing the pads.

10. The wafer dicing method as described in claim 6, characterized in that, The top surfaces of the bonding medium layer and the bonding metal layer serve as a hybrid bonding interface.

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