Chip backside connected packaging substrate and manufacturing method thereof

Abstract

The invention discloses a method for manufacturing a chip back-connected package substrate, comprising: preparing a polymer support frame with a device placement opening frame; mounting a chip at the bottom of the device placement opening frame to form a package layer; applying a reinforcing plate; forming a first insulating layer and a first copper foil on its surface, forming a first circuit layer on the surface of the first insulating layer to communicate with the first terminal surface of the chip; removing the reinforcing plate; forming a groove in part of the package layer; thinning the package layer by the groove to form a window to expose the second terminal surface of the chip or the back of the chip by plasma etching; forming a via hole in the first insulating layer, forming a second circuit layer on the surface of the first copper foil, forming a third circuit layer on the upper surface of the polymer support frame with the bottom and sidewall of the window, the first circuit layer and the second circuit layer are connected through the via hole, and the second terminal surface or the back of the chip is connected with the third circuit layer. Also disclosed is a chip back-connected package substrate.

Description

Technical Field

[0001] The invention relates to an electronic device packaging structure, in particular to a packaging substrate connected with the back side of a chip and a manufacturing method thereof. Background Art

[0002] With the continuous development of electronic technology, electronic products tend to be highly functional and high-density integrated. Since the miniaturization of components such as chips has faced a bottleneck and it is difficult to further effectively reduce the size, how to package chips and other components more reasonably to achieve high functionality and high-density integration has become a very important topic in the current semiconductor packaging field. After continuous development and evolution, panel-level embedded packaging technology has been increasingly used and plays an increasingly important role in the field of semiconductor packaging. With the continuous development and improvement of panel-level embedded packaging technology, panel-level embedded packaging has now formed an industrialization with a certain scale, but there are still certain limitations, which limit the widespread application of panel-level embedded packaging technology.

[0003] Existing panel-level embedded packaging solutions can already realize embedded packaging of components such as chips, such as the board-level embedded packaging solution disclosed in Chinese patent CN109686669B. Figure 1 As shown, the component 11 is embedded in the support frame 10 with a cavity. However, the support frame with a cavity has a thickness of more than 200 μm, and is usually used for embedded packaging of chips with a thickness of more than 150 μm. There is a lack of effective solutions for embedded packaging with thinner frames and thinner chip thickness, and it can only meet the chip / component embedded packaging of single-sided I / O.

[0004] In the prior art, for the embedded packaging structure with circuits led out on both sides of the chip, the window opening of the packaging material on the back of the chip is performed by laser. Since the laser beam energy is concentrated and high temperature is generated during the laser process, the chip is greatly damaged. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a chip backside connected packaging substrate and a manufacturing method thereof.

[0006] Based on the above purpose, the first aspect of the present invention provides a method for manufacturing a packaging substrate with a chip back surface connected, comprising the following steps:

[0007] (a) preparing a polymer support frame, wherein the polymer support frame comprises a device placement frame penetrating the polymer support frame in a height direction;

[0008] (b) mounting a chip on the bottom of the device placement frame, and forming a packaging layer in the gap between the chip and the device placement frame and on the upper surface of the polymer support frame;

[0009] (c) applying a reinforcing plate on the surface of the encapsulation layer;

[0010] (d) forming a first insulating layer on the lower surface of the polymer support frame, forming a first copper foil on the lower surface of the first insulating layer, and forming a first circuit layer in the upper surface of the first insulating layer, wherein the first circuit layer is connected to the first terminal surface of the chip;

[0011] (e) removing the reinforcing plate;

[0012] (f) removing part of the encapsulation layer in the area where the window needs to be opened on the second terminal surface or the back surface of the chip to form a groove, and the distance from the bottom of the groove to the second terminal surface or the back surface of the chip is similar to the thickness of the encapsulation layer on the upper surface of the polymer support frame;

[0013] (g) thinning the packaging layer on the upper surface of the polymer support frame by plasma etching to expose the first conductive copper pillar layer in the polymer support frame, and thinning the packaging layer at the bottom and sidewalls of the groove to form a window exposing the second terminal surface or back surface of the chip;

[0014] (h) forming a via hole in the first insulating layer, forming a second circuit layer on the surface of the first copper foil, and forming a third circuit layer on the upper surface of the polymer support frame and on the bottom and side walls of the window, the first circuit layer and the second circuit layer are connected through the via hole, and the second terminal surface or back surface of the chip is connected to the third circuit layer.

[0015] In some embodiments, the thickness of the encapsulation layer at the sidewall of the groove is reduced to the same as the distance from the bottom of the groove to the second terminal surface or the back surface of the chip.

[0016] In some embodiments, the reinforcement plate comprises a copper clad laminate having at least one side covered with a double-layer copper foil, wherein the copper clad laminate comprises a core layer, a first copper layer on a surface of the core layer, and a second copper layer on the first copper layer, wherein the first copper layer and the second copper layer are attached together by physical pressing.

[0017] In some embodiments, step (e) includes removing the stiffener plate by physically separating the first copper layer and the second copper layer.

[0018] In some embodiments, step (f) includes first etching a portion of the second copper layer to expose an area on the second terminal surface or back side of the chip where a window is required, and then removing a portion of the packaging layer exposed in the area to form a groove.

[0019] In some embodiments, step (g) includes first etching the remaining second copper layer, then using 5 plasma etching to thin the packaging layer on the upper surface of the polymer support frame to expose the end of the first conductive copper column layer within the polymer support frame, and thinning the packaging layer at the bottom and side walls of the groove to form a window exposing the second terminal surface or back side of the chip.

[0020] In some embodiments, step (c) includes first forming a temporary insulating layer on the surface of the encapsulation layer, and then applying a reinforcing plate on the surface of the temporary insulating layer.

[0021] 10 In some embodiments, step (f) includes first etching a portion of the second copper layer to expose the chip

[0022] The area where the window needs to be opened is located on the second terminal surface or the back surface, and then the temporary insulating layer and part of the packaging layer exposed in the area are removed to form a groove.

[0023] In some embodiments, step (g) comprises first etching the remaining second copper layer and removing the temporary

[0024] The insulating layer is then thinned by plasma etching to expose the end of the first conductive copper column layer in the polymer support frame, and the bottom and bottom of the groove are thinned.

[0025] The packaging layer of the side wall forms an opening to expose the second terminal surface or the back surface of the chip.

[0026] In some embodiments, step (b) includes mounting the chip on the bottom of the device placement frame by applying an adhesive layer on the lower surface of the polymer support frame and then attaching the first terminal surface of the chip to the adhesive layer exposed in the device placement frame.

[0027] 20 In some embodiments, the adhesive layer comprises a single-sided tape.

[0028] In some embodiments, step (d) comprises:

[0029] (d1) removing the adhesive layer;

[0030] (d2) forming a first metal seed layer on the lower surface of the polymer support frame;

[0031] (d3) applying a first photoresist layer on the first metal seed layer, exposing and developing the first photoresist layer to form a first characteristic pattern;

[0032] (d4) plating copper in the first characteristic pattern to form a first circuit layer;

[0033] (d5) removing the first photoresist layer and etching the exposed first metal seed layer;

[0034] (d6) laminating an insulating material on the first wiring layer to form a first insulating layer;

[0035] (d7) Forming a first copper foil on the lower surface of the first insulating layer.

[0036] 30 In some embodiments, step (h) comprises:

[0037] (h1) forming a blind hole in the first insulating layer to expose the first wiring layer, wherein the blind hole vertically penetrates the first copper foil;

[0038] (h2) forming a second metal seed layer on the bottom and sidewalls of the blind hole, and forming a third metal seed layer on the upper surface of the polymer support frame and on the bottom and sidewalls of the open window;

[0039] (h3) applying a second photoresist layer on the lower surface of the first insulating layer, applying a third photoresist layer on the third metal seed layer, exposing and developing the second photoresist layer to form a second characteristic pattern exposing the blind hole and the first copper foil, and exposing and developing the third photoresist layer to form a third characteristic pattern exposing the window and the end of the first conductive copper column layer;

[0040] (h4) forming a via hole and a second circuit layer by electroplating in the second characteristic pattern, and forming a third circuit layer by electroplating in the third characteristic pattern;

[0041] (h5) removing the second photoresist layer and the third photoresist layer, and etching the exposed second metal seed layer and the third metal seed layer.

[0042] In some embodiments, the polymer support framework has a thickness of 100 μm or less.

[0043] In some embodiments, the insulating layer includes pure resin or resin containing glass fibers.

[0044] In some embodiments, the polymer support frame includes a second insulating layer and a third insulating layer, the second insulating layer includes a fourth circuit layer within the lower surface of the second insulating layer and the first conductive copper pillar layer on the fourth circuit layer, the third insulating layer includes a second conductive copper pillar layer, a third conductive copper pillar layer and a fifth circuit layer located between the second conductive copper pillar layer and the third conductive copper pillar layer, the first circuit layer and the fifth circuit layer are conductively connected through the third conductive copper pillar layer, the fourth circuit layer and the fifth circuit layer are conductively connected through the second conductive copper pillar layer, the third circuit layer and the fourth circuit layer are conductively connected through the first conductive copper pillar layer, and the device placement port frame passes through the second insulating layer and the third insulating layer.

[0045] Based on the same purpose, the second aspect of the present invention provides a chip back-side connected packaging substrate, which is prepared by the method for preparing a chip back-side connected packaging substrate according to the first aspect of the present invention.

[0046] In some embodiments, it includes a polymer support frame and a first insulating layer located below the polymer support frame, the polymer support frame includes a device placement frame that penetrates the polymer support frame in the height direction, a chip is mounted on the bottom of the device placement frame, a packaging layer is filled in the gap between the chip and the device placement frame, a window is formed in the packaging layer to expose the second terminal surface or back side of the chip, a third circuit layer is arranged on the upper surface of the polymer support frame and on the bottom and side walls of the window, the second terminal surface or back side of the chip is connected to the third circuit layer, the first insulating layer includes a first circuit layer in the upper surface of the first insulating layer and a via hole located on the first circuit layer, a second circuit layer is arranged on the lower surface of the first insulating layer, and the first circuit layer and the second circuit layer are connected through the via hole.

[0047] In some embodiments, the polymer support frame includes a second insulating layer and a third insulating layer arranged in the longitudinal direction, the third insulating layer is located above the first insulating layer, the second insulating layer includes a fourth circuit layer within the lower surface of the second insulating layer and a first conductive copper pillar layer on the fourth circuit layer; the third insulating layer includes a second conductive copper pillar layer, a third conductive copper pillar layer and a fifth circuit layer located between the second conductive copper pillar layer and the third conductive copper pillar layer, the first circuit layer and the fifth circuit layer are conductively connected through the third conductive copper pillar layer, the fourth circuit layer and the fifth circuit layer are conductively connected through the second conductive copper pillar layer, the third circuit layer and the fourth circuit layer are conductively connected through the first conductive copper pillar layer, and the device placement port frame passes through the second insulating layer and the third insulating layer.

[0048] From the above description, it can be seen that the present invention provides a packaging substrate connected to the back side of the chip and a manufacturing method thereof. When manufacturing the packaging substrate, the polymer support frame used is a multi-layer substrate structure with a device placement frame. The thickness of the polymer support frame is less than or equal to 100μm, which can be suitable for embedded packaging of chips less than 100μm; after the chip is embedded and packaged, a reinforcement plate is stacked for reinforcement. When the polymer support frame is layered on one side, the reinforcement plate can provide support for the polymer support frame to avoid the scrapping of the thin plate during the manufacturing process; the I / O position of the embedded chip is opened by plasma etching to avoid damage to the chip caused by traditional window opening methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] For a better understanding of the invention and to illustrate embodiments of the invention, reference is made below, purely by way of example, to the accompanying drawings.

[0050] With specific reference to the drawings, it must be emphasized that certain illustrations are exemplary and are intended only for the purpose of illustrative discussion of the preferred embodiments of the invention and are presented for the purpose of providing what are believed to be the most useful and understandable illustrations for the description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to illustrate the structural details of the invention in more detail than is necessary for a basic understanding of the invention; the description with reference to the drawings enables those skilled in the art to recognize how several forms of the invention may be practically embodied. In the drawings:

[0051] Figure 1 A cross-sectional schematic diagram of an integrated circuit packaging method and packaging structure in the prior art;

[0052] Figure 2 A schematic cross-sectional view of a package substrate with back-side connection of a chip according to an embodiment of the present invention;

[0053] Figures 3(a) to 3(j) A schematic cross-sectional view showing intermediate structures in various steps of a method for manufacturing a chip backside-connected packaging substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] Reference Figure 2 , showing a cross-sectional schematic diagram of a packaging substrate 100 connected to the back side of a chip; the packaging substrate 100 includes a polymer support frame and a first insulating layer 101 located below the polymer support frame; the polymer support frame is a multi-layer substrate structure, preferably, the thickness of the polymer support frame is less than or equal to 100μm, so that it can be suitable for embedded packaging of chips less than 100μm.

[0055] The polymer support frame includes a second insulating layer 102 and a third insulating layer 103 arranged in the longitudinal direction. The third insulating layer 103 is located above the first insulating layer 101 , and the second insulating layer 102 is located above the third insulating layer 103 .

[0056] The first insulating layer 101, the second insulating layer 102 and the third insulating layer 103 may include the same material or different materials; the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103 may be selected from pure resin or resin containing glass fiber respectively; preferably, the third insulating layer 103 is selected from pure resin.

[0057] The polymer support frame further includes a device placement opening frame 104 penetrating the second insulating layer 102 and the third insulating layer 103 along the height direction, and a chip 105 is mounted on the bottom of the device placement opening frame 104 .

[0058] Generally, the chip 105 can be a double-sided I / O chip or a single-sided I / O chip. The single-sided I / O chip can use the package substrate structure to realize the circuit lead-out of the chip I / O side and the production of the heat dissipation copper surface of the non-I / O side. This embodiment only takes the double-sided I / O chip as an example for illustration.

[0059] The first terminal surface of the chip 105 is mounted on the bottom of the device placement opening frame 104 , and the gap between the chip 105 and the device placement opening frame 104 is filled with a packaging layer 106 . A window 1062 is formed in the packaging layer 106 to expose the second terminal surface of the chip.

[0060] The encapsulation layer 106 may be selected from pure resin, and the encapsulation layer 106 may fix the chip 105 to prevent the chip 105 from shifting.

[0061] A third circuit layer 1026 is disposed on the upper surface of the second insulating layer 102 and on the bottom and sidewalls of the opening 1062. The second terminal surface of the chip 105 is connected to the third circuit layer 1026. It should be noted that the upper surface and lower surface mentioned in this embodiment are subject to the drawings.

[0062] The first insulating layer 101 includes a first circuit layer 1011 on the upper surface of the first insulating layer 101 and a via hole 1013 located on the first circuit layer 1011 . A second circuit layer 1014 is arranged on the lower surface of the first insulating layer 101 . The first circuit layer 1011 and the second circuit layer 1014 are connected through the via hole 1013 .

[0063] The second insulating layer 102 includes a fourth circuit layer 1022 in the lower surface of the second insulating layer 102 and a first conductive copper pillar layer 1024 on the fourth circuit layer 1022 . The third circuit layer 1026 and the fourth circuit layer 1022 are conductively connected via the first conductive copper pillar layer 1024 .

[0064] The third insulating layer 103 includes a second conductive copper pillar layer 1032, a third conductive copper pillar layer 1036 and a fifth circuit layer 1034 located between the second conductive copper pillar layer 1032 and the third conductive copper pillar layer 1036. The first circuit layer 1011 and the fifth circuit layer 1034 are conductively connected through the third conductive copper pillar layer 1036, and the fourth circuit layer 1022 and the fifth circuit layer 1034 are conductively connected through the second conductive copper pillar layer 1032.

[0065] The conductive copper pillar layer mentioned in this embodiment may include at least one copper through-hole pillar as an IO channel to achieve conduction between layers. The sizes and / or shapes of the multiple copper through-hole pillars may be the same or different. The copper through-hole pillars may be solid copper pillars or hollow pillars with copper plating on the surface. Preferably, the conductive copper pillar layer includes multiple copper through-hole pillars as IO channels, and the ends of the conductive copper pillar layer may be flush with the insulating layer or higher than the insulating layer.

[0066] Reference Figures 3(a) to 3(j) , a schematic cross-sectional view of the intermediate structure of each step of a method for manufacturing a chip back-side-connected packaging substrate 100 according to an embodiment of the present invention is shown.

[0067] The manufacturing method comprises the following steps: preparing a polymer support frame, as shown in Fig. 3(a). The polymer support frame comprises a second insulating layer 102, a third insulating layer 103 below the second insulating layer 102, and a device placement frame 104 penetrating the second insulating layer 102 and the third insulating layer 103 in the height direction.

[0068] The second insulating layer 102 includes a fourth circuit layer 1022 within the lower surface of the second insulating layer 102 and a first conductive copper pillar layer 1024 on the fourth circuit layer 1022. The third insulating layer 103 includes a second conductive copper pillar layer 1032, a third conductive copper pillar layer 1036 and a fifth circuit layer 1034 located between the second conductive copper pillar layer 1032 and the third conductive copper pillar layer 1036. The fourth circuit layer 1022 and the fifth circuit layer 1034 are conductively connected via the second conductive copper pillar layer 1032.

[0069] The end of the first conductive copper pillar layer 1024 can be flush with the upper surface of the second insulating layer 102, or it can be higher than the upper surface of the second insulating layer 102; the end of the second conductive copper pillar layer 1032 can be flush with the upper surface of the third insulating layer 103, or it can be higher than the upper surface of the third insulating layer 103; the end of the third conductive copper pillar layer 1036 can be flush with the lower surface of the third insulating layer 103, or it can be higher than the lower surface of the third insulating layer 103, which is not limited here.

[0070] Usually, multiple device placement opening frames can be provided for subsequent chip mounting, and their sizes can be the same or different, depending on the shape and size of the chip to be embedded, which is not limited here.

[0071] Typically, the method for manufacturing a polymer support frame comprises the following sub-steps:

[0072] obtaining a sacrificial carrier;

[0073] applying a copper seed layer on a sacrificial carrier;

[0074] applying a resist layer on a sacrificial carrier;

[0075] applying another copper seed layer;

[0076] applying a photoresist layer;

[0077] The patterned photoresist layer is a pattern having copper through holes and loop-shaped strip through holes;

[0078] Electroplating copper in the pattern forms a third conductive copper pillar layer 1036 and a first loop strip copper pillar layer;

[0079] Stripping the photoresist layer;

[0080] etching the exposed copper seed layer;

[0081] The third conductive copper pillar layer 1036 and the first loop strip copper pillar layer are laminated with insulating material;

[0082] Thinning and flattening the insulating material to expose the third conductive copper pillar layer 1036 and the end of the first loop-shaped copper pillar layer to form the lower portion of the third insulating layer 103;

[0083] Repeat the steps of applying a copper seed layer, a photoresist layer, patterning, copper plating in the pattern, stripping the photoresist layer, and etching the exposed copper seed layer to form an upper portion of the third insulating layer 103, wherein the upper portion of the third insulating layer 103 includes a fifth circuit layer 1034, a second conductive copper pillar layer 1032 located on the fifth circuit layer 1034, and a second loop-shaped copper pillar layer, and the second loop-shaped copper pillar layer is vertically aligned with the first loop-shaped copper pillar layer;

[0084] Repeat the above steps to form a second insulating layer 102, wherein the second insulating layer 102 includes a fourth circuit layer 1022, a first conductive copper pillar layer 1024 and a third loop-shaped strip copper pillar layer located on the fourth circuit layer 1022, wherein the third loop-shaped strip copper pillar layer and the second loop-shaped strip copper pillar layer and the first loop-shaped strip copper pillar layer are aligned in the longitudinal direction;

[0085] removing the sacrificial carrier;

[0086] Etching the resist layer;

[0087] An upper photoresist layer and a lower photoresist layer are respectively applied on the upper surface of the second insulating layer 102 and the lower surface of the third insulating layer 103, and the upper photoresist layer and the lower photoresist layer are exposed and developed to expose the loop strip copper pillars in the first loop strip copper pillar layer, the second loop strip copper pillar layer and the third loop strip copper pillar layer;

[0088] The loop-shaped copper pillars are etched back and the dielectric material therein is removed to form a device placement opening frame 104, and the upper photoresist layer and the lower photoresist layer are removed to obtain a polymer support frame.

[0089] It should be noted that the polymer support frame can be a polymer substrate having more insulating layers. This embodiment is subsequently demonstrated with the polymer support frame including two insulating layers, but the manufacturing method is not limited to being applicable only to the polymer support frame having two insulating layers. Preferably, the thickness of the polymer support frame is less than or equal to 100 μm, which is convenient for embedding and packaging of chips less than 100 μm.

[0090] The second insulating layer 102 and the third insulating layer 103 can be selected from pure resin or resin containing glass fiber respectively; preferably, the third insulating layer 103 is selected from pure resin.

[0091] Next, an adhesive layer 1037 is provided at the bottom of the third insulating layer 103, and the first terminal surface of the chip 105 is attached to the adhesive layer 1037 exposed in the device placement opening frame 104, as shown in FIG3(b). Generally, the adhesive layer 1037 can be a single-sided tape, which is usually a commercially available transparent film that can be decomposed by heat or under ultraviolet irradiation; the adhesive layer 1037 can temporarily support and fix the chip 105.

[0092] The chip 105 can be a double-sided I / O chip or a single-sided I / O chip. The subsequent operations are only demonstrated using the double-sided I / O chip as an example, and the manufacturing method of this embodiment is not limited to being applicable only to double-sided I / O chips.

[0093] Then, a packaging layer 106 is formed in the gap between the chip 105 and the device placement opening frame 104 and on the upper surface of the second insulating layer 102, as shown in Fig. 3(c). Generally, the packaging layer 106 can be selected from pure resin.

[0094] Next, a temporary insulating layer 107 is formed on the surface of the encapsulation layer 106, and a reinforcing plate is applied on the surface of the temporary insulating layer 107, as shown in FIG3(d). Generally, the temporary insulating layer 107 can be selected from pure resin or resin containing glass fiber, and preferably, the temporary insulating layer 107 is selected from pure resin. The temporary insulating layer 107 can combine the reinforcing plate and the encapsulation layer 106.

[0095] The reinforcing plate can provide support force when the polymer support frame is subsequently subjected to single-sided layer addition, thereby avoiding the scrapping of the polymer support frame during the manufacturing process.

[0096] The reinforcing plate can be any metal plate or glass substrate with a separation layer applied on the surface, such as a copper plate, an aluminum plate, a stainless steel plate or an aluminum alloy plate, etc., or a sacrificial copper foil or a surface copper-clad plate. Preferably, the reinforcing plate in this embodiment is a copper-clad plate with a double-layer copper foil on at least one side, wherein the copper-clad plate includes a core layer 1081, a first copper layer 1082 on the surface of the core layer 1081, and a second copper layer 1083 on the first copper layer 1082, wherein the first copper layer 1082 and the second copper layer 1083 are attached together by physical pressing, and the second copper layer 1083 is in contact with the temporary insulating layer 107.

[0097] Then, the adhesive layer 1037 is removed, a first metal seed layer is formed on the lower surface of the third insulating layer 103, a first photoresist layer is applied on the first metal seed layer, the first photoresist layer is exposed and developed to form a first feature pattern, copper is plated in the first feature pattern to form a first circuit layer 1011, the first photoresist layer is removed, the exposed first metal seed layer is etched, an insulating material is laminated on the first circuit layer 1011 to form a first insulating layer 101, and a first copper foil 1012 is formed on the lower surface of the first insulating layer 101, as shown in FIG. 3(e). The first circuit layer 1011 is connected to the first terminal surface of the chip 105, and the first circuit layer 1011 is conductively connected to the fifth circuit layer 1034 through the third conductive copper pillar layer 1036.

[0098] Generally, the adhesive layer 1037 can be removed by ultraviolet irradiation or thermal decomposition. The first insulating layer 101 can be selected from pure resin or pure resin containing glass fiber, which is not limited here. The first copper foil 1012 can be formed on the lower surface of the first insulating layer 101 by lamination.

[0099] Next, the first copper layer 1082 and the second copper layer 1083 are physically separated, and the reinforcing plate is removed, as shown in FIG. 3( f ).

[0100] Then, a portion of the second copper layer 1083 is etched to expose the area of ​​the second terminal surface of the chip 105 where a window needs to be opened, as shown in FIG. 3( g ).

[0101] Typically, the steps include:

[0102] applying a fourth photoresist layer on the surface of the second copper layer 1083;

[0103] exposing and developing the fourth photoresist layer to form a fourth characteristic pattern exposing the area where the second terminal surface of the chip 105 needs to be opened;

[0104] Etching the exposed second copper layer 1083 in the fourth feature pattern;

[0105] The fourth photoresist layer is removed.

[0106] Next, the temporary insulating layer 107 and part of the encapsulation layer 106 exposed in the region are removed to form a groove 1061, as shown in FIG3(h). Generally, the distance from the bottom of the groove 1061 to the second terminal surface of the chip 105 is the same as the thickness of the encapsulation layer 106 on the upper surface of the second insulating layer 102, which provides a basis for the subsequent preparation of the opening by the groove in a plasma etching manner.

[0107] It can be understood that there is still a certain distance from the bottom of the groove 1061 to the second terminal surface of the chip 105, so the temporary insulating layer 107 and part of the packaging layer 106 exposed in the area can be removed by plasma etching. For cost and efficiency considerations, laser can also be used to remove the temporary insulating layer 107 and part of the packaging layer 106 exposed in the area; preferably, the temporary insulating layer 107 and part of the packaging layer 106 exposed in the area are removed by plasma etching.

[0108] Then, the remaining second copper layer 1083 is etched and the temporary insulating layer 107 is removed. The packaging layer 106 on the upper surface of the second insulating layer 102 is thinned by plasma etching to expose the end of the first conductive copper pillar layer 1024, and the packaging layer 106 at the bottom and sidewall of the groove 1061 is thinned to form a window 1062 exposing the second terminal surface of the chip 105, as shown in Figure 3 (i). Generally, the thickness of the thinned packaging layer on the sidewall of the groove 1061 is the same as the distance from the bottom of the groove 1061 to the second terminal surface of the chip 105. By thinning the packaging layer by plasma etching and preparing the window 1062 exposing the second terminal surface of the chip 105, damage to the chip 105 when opening the window by conventional laser method can be avoided.

[0109] Next, a via hole 1013 is formed in the first insulating layer 101, a second circuit layer 1014 is formed on the surface of the first copper foil 1012, and a third circuit layer 1026 is formed on the upper surface of the second insulating layer 102 and on the bottom and sidewalls of the opening 1062. The first circuit layer 1011 and the second circuit layer 1014 are connected through the via hole 1013, and the second terminal surface of the chip 105 is connected to the third circuit layer 1026, thereby obtaining a package substrate 100, as shown in FIG3(j). The third circuit layer 1026 and the fourth circuit layer 1022 are connected through the first conductive copper pillar layer 1024.

[0110] Typically, the following steps may be included:

[0111] A blind hole exposing the first circuit layer 1011 is formed in the first insulating layer 101, wherein the blind hole vertically penetrates the first copper foil 1012;

[0112] A second metal seed layer is formed on the bottom and sidewalls of the blind hole 1013 , and a third metal seed layer is formed on the upper surface of the second insulating layer 102 and on the bottom and sidewalls of the opening 1062 ;

[0113] A second photoresist layer is applied on the lower surface of the first insulating layer 101, and a third photoresist layer is applied on the third metal seed layer. The second photoresist layer is exposed and developed to form a second characteristic pattern exposing the blind hole and the first copper foil 1012, and the third photoresist layer is exposed and developed to form a third characteristic pattern exposing the window 1062 and the end of the first conductive copper pillar layer 1024;

[0114] The via hole 1013 and the second circuit layer 1014 are formed by electroplating in the second characteristic pattern, and the third circuit layer 1026 is formed by electroplating in the third characteristic pattern;

[0115] The second photoresist layer and the third photoresist layer are removed, and the exposed second metal seed layer and the third metal seed layer are etched.

[0116] Typically, the blind hole 1013 may be processed by laser.

[0117] Optionally, the following steps may also be included:

[0118] A blind hole exposing the first circuit layer 1011 is formed in the first insulating layer 101, wherein the blind hole vertically penetrates the first copper foil 1012;

[0119] A second metal seed layer is formed on the bottom and sidewalls of the blind hole 1013 and the lower surface of the first insulating layer 101, and a third metal seed layer is formed on the upper surface of the second insulating layer 102 and the bottom and sidewalls of the window 1062;

[0120] Electroplating to form a third copper layer on the second metal seed layer and the first copper foil 1012, and electroplating to form a fourth copper layer on the third metal seed layer;

[0121] applying a second photoresist layer on the third copper layer, and applying a third photoresist layer on the fourth copper layer;

[0122] The second photoresist layer is exposed and developed to form a second characteristic pattern covering the blind hole and the first copper foil 1012 , and the third photoresist layer is exposed and developed to form a third characteristic pattern covering the end of the first conductive copper pillar layer 1024 and the open window 1062 ;

[0123] The third copper layer exposed in the second characteristic pattern is etched to form a second circuit layer 1014, and the fourth copper layer exposed in the third characteristic pattern is etched to form a third circuit layer 1026;

[0124] The second photoresist layer and the third photoresist layer are removed, and the exposed second metal seed layer and the third metal seed layer are etched.

[0125] Those skilled in the art will recognize that the present invention is not limited to the contents specifically illustrated and described in the context. Moreover, the scope of the present invention is defined by the appended claims, including combinations and sub-combinations of the various technical features described above, as well as variations and improvements thereof, which will be foreseen by those skilled in the art after reading the foregoing description.

[0126] In the claims, the term "comprise" and variations such as "comprising", "including", etc., mean that listed components are included, but generally do not exclude other components.

Claims

1. A method for manufacturing a packaging substrate with a chip backside connection, comprising the following steps: (a) preparing a polymer support frame, wherein the polymer support frame comprises a device placement frame penetrating the polymer support frame in a height direction; (b) mounting a chip on the bottom of the device placement frame, and forming a packaging layer in the gap between the chip and the device placement frame and on the upper surface of the polymer support frame; (c) applying a reinforcing plate on the surface of the encapsulation layer; (d) forming a first insulating layer on the lower surface of the polymer support frame, and forming a first copper foil on the lower surface of the first insulating layer, wherein the first insulating layer includes a first circuit layer located within the upper surface of the first insulating layer, and the first circuit layer is connected to the first terminal surface of the chip; (e) removing the reinforcing plate; (f) removing part of the encapsulation layer in the area where the window needs to be opened on the second terminal surface or the back surface of the chip to form a groove, and the distance from the bottom of the groove to the second terminal surface or the back surface of the chip is the same as the thickness of the encapsulation layer on the upper surface of the polymer support frame; (g) thinning the packaging layer on the upper surface of the polymer support frame by plasma etching to expose the first conductive copper pillar layer in the polymer support frame, and thinning the packaging layer at the bottom and sidewalls of the groove to form a window exposing the second terminal surface or back surface of the chip; (h) forming a via hole in the first insulating layer, forming a second circuit layer on the surface of the first copper foil, and forming a third circuit layer on the upper surface of the polymer support frame and on the bottom and side walls of the window, wherein the first circuit layer and the second circuit layer are connected through the via hole, and the second terminal surface or back surface of the chip is connected to the third circuit layer; The thickness of the encapsulation layer thinned on the side wall of the groove is the same as the distance from the bottom of the groove to the second terminal surface or the back surface of the chip; The reinforcing plate comprises a copper-clad laminate having at least one side covered with a double-layer copper foil, wherein the copper-clad laminate comprises a core layer, a first copper layer on a surface of the core layer, and a second copper layer on the first copper layer, wherein the first copper layer and the second copper layer are attached together by physical pressing; wherein step (e) comprises removing the reinforcing plate by physically separating the first copper layer and the second copper layer; The step (f) includes firstly etching a portion of the second copper layer to expose the area where the window needs to be opened on the second terminal surface or the back surface of the chip, and then removing the portion of the packaging layer exposed in the area to form a groove.

2. The manufacturing method according to claim 1, wherein step (g) comprises first etching the remaining second copper layer, then using plasma etching to thin the packaging layer on the upper surface of the polymer support frame to expose the end of the first conductive copper column layer in the polymer support frame, and thinning the packaging layer at the bottom and sidewall of the groove to form a window exposing the second terminal surface or back side of the chip. 3 . The manufacturing method according to claim 1 , wherein step (c) comprises first forming a temporary insulating layer on the surface of the encapsulation layer, and then applying a reinforcing plate on the surface of the temporary insulating layer.

4. The manufacturing method according to claim 3, wherein step (f) comprises first etching a portion of the second copper layer to expose the area where the second terminal surface or the back surface of the chip needs to be opened, and then removing the temporary insulating layer and a portion of the packaging layer exposed in the area to form a groove.

5. The manufacturing method according to claim 4, wherein step (g) comprises first etching the remaining second copper layer and removing the temporary insulating layer, then using plasma etching to thin the packaging layer on the upper surface of the polymer support frame to expose the end of the first conductive copper column layer in the polymer support frame, and thinning the packaging layer at the bottom and sidewall of the groove to form a window exposing the second terminal surface or back side of the chip.

6. The manufacturing method according to claim 1, wherein step (b) includes mounting the chip on the bottom of the device placement frame by applying an adhesive layer on the lower surface of the polymer support frame and then attaching the first terminal surface of the chip to the adhesive layer exposed in the device placement frame. The manufacturing method according to claim 6 , wherein the adhesive layer comprises a single-sided tape.

8. The method according to claim 6, wherein step (d) comprises: (d1) removing the adhesive layer; (d2) forming a first metal seed layer on the lower surface of the polymer support frame; (d3) applying a first photoresist layer on the first metal seed layer, and exposing and developing the first photoresist layer to form a first characteristic pattern; (d4) plating copper in the first characteristic pattern to form a first circuit layer; (d5) removing the first photoresist layer, and etching the exposed first metal seed layer; (d6) laminating an insulating material on the first wiring layer to form a first insulating layer; (d7) Forming a first copper foil on the lower surface of the first insulating layer.

9. The method according to claim 1, wherein step (h) comprises: (h1) forming a blind hole in the first insulating layer to expose the first wiring layer, wherein the blind hole vertically penetrates the first copper foil; (h2) forming a second metal seed layer on the bottom and sidewalls of the blind hole, and forming a third metal seed layer on the upper surface of the polymer support frame and on the bottom and sidewalls of the open window; (h3) applying a second photoresist layer on the lower surface of the first insulating layer, applying a third photoresist layer on the third metal seed layer, exposing and developing the second photoresist layer to form a second characteristic pattern exposing the blind hole and the first copper foil, and exposing and developing the third photoresist layer to form a third characteristic pattern exposing the window and the end of the first conductive copper pillar layer; (h4) forming a via hole and a second circuit layer by electroplating in the second characteristic pattern, and forming a third circuit layer by electroplating in the third characteristic pattern; (h5) removing the second photoresist layer and the third photoresist layer, and etching the exposed second metal seed layer and the third metal seed layer. 10 . The manufacturing method according to claim 1 , wherein the thickness of the polymer support frame is less than or equal to 100 μm.

11. The manufacturing method according to claim 1 or 3, wherein the insulating layer comprises pure resin or resin containing glass fiber.

12. The manufacturing method according to claim 1, wherein the polymer support frame includes a second insulating layer and a third insulating layer, the second insulating layer includes a fourth circuit layer within the lower surface of the second insulating layer and the first conductive copper pillar layer on the fourth circuit layer, the third insulating layer includes a second conductive copper pillar layer, a third conductive copper pillar layer and a fifth circuit layer located between the second conductive copper pillar layer and the third conductive copper pillar layer, the first circuit layer and the fifth circuit layer are conductively connected through the third conductive copper pillar layer, the fourth circuit layer and the fifth circuit layer are conductively connected through the second conductive copper pillar layer, the third circuit layer and the fourth circuit layer are conductively connected through the first conductive copper pillar layer, and the device placement frame passes through the second insulating layer and the third insulating layer.

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