Vertical transistor

Abstract

A vertical transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region. The channel region is crystalline, and its grains have an average grain size of less than 20 nanometers. The channel region at the top interface or the bottom interface has a horizontal texture larger than the volume of the grains in the channel region vertically located between the grains at the top and bottom interfaces. Other embodiments and aspects are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to vertical transistors. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as an array of one or more individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention period of at least approximately 10 years. Volatile memory dissipates energy and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention period of a few milliseconds or less. In any case, memory cells are configured to hold or store the memory in at least two different selectable states. In binary systems, these states are considered "0" or "1". In other systems, at least some individual memory cells may be configured to store information in more than two levels or states.

[0004] A field-effect transistor (FET) is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions through the channel region to the other. When the voltage is removed from the gate, current flow is largely blocked through the channel region. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. FETs are also used, of course, in integrated circuit systems outside of memory circuitry. Summary of the Invention

[0005] On one hand, this disclosure relates to a vertical transistor comprising: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region, wherein the top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size of less than 20 nanometers; and the channel region at the top interface or the bottom interface has a horizontal texture larger than the volume of the grains in the channel region vertically located between the grains at the top and bottom interfaces.

[0006] On the other hand, this disclosure relates to a vertical transistor comprising: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region, the top source / drain region having a top interface with the channel region, and the bottom source / drain region having a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size from 5 nanometers to 10 nanometers; and the channel region at the top interface has a horizontal texture larger in volume than the grains in the channel region vertically located between the top and bottom interfaces.

[0007] Furthermore, this disclosure relates to a vertical transistor comprising: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region, wherein the top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size of 5 nanometers to 10 nanometers; and the channel region at the bottom interface has a horizontal texture larger in volume than the grains in the channel region vertically located between the grains at the top and bottom interfaces.

[0008] On the other hand, this disclosure relates to a vertical transistor comprising: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region, the top source / drain region having a top interface with the channel region, and the bottom source / drain region having a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size from 5 nanometers to 10 nanometers; and at least some of the grains in the channel region at the top interface, at least some of the grains in the channel region at the bottom interface, and at least some of the grains in the channel region vertically located between the top and bottom interfaces have a horizontal texture; the channel region at the top and bottom interfaces has a horizontal texture larger in volume than the grains vertically located between the top and bottom interfaces. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of a vertical transistor according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a grain.

[0011] Figures 3 to 17 This is a schematic cross-sectional view of a vertical transistor according to an embodiment of the present invention. Detailed Implementation

[0012] Figure 1 An example of a vertical transistor 14 as part of a construction 10 according to an embodiment of the present invention is shown. Construction 10 includes a base substrate 11 having any one or more of a plurality of conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulating (i.e., electrically) materials 12. Various materials have been vertically formed on the base substrate 11. The materials may be... Figure 1 The material depicted may be adjacent to, vertically inside, or vertically outside the substrate. For example, other parts of the integrated circuit system or fully fabricated components may be disposed somewhere above, around, or inside the base substrate 11. Only one vertical transistor 14 is shown, but configuration 10 may include, for example, multiple vertical transistors of the same or different configurations fabricated to include an array of multiple vertical transistors according to the invention.

[0013] The vertical transistor 14 includes a top source / drain region 16, a bottom source / drain region 18, a channel region 20 vertically located between the top and bottom source / drain regions 16 and 18, respectively, and a gate 22 (i.e., a conductive material) operably laterally adjacent to (e.g., laterally beside) the channel region 20. A gate insulator 24 (e.g., silicon dioxide, silicon nitride, a high-k material, and / or a ferroelectric material) is located between the gate 22 and the channel region 20. For simplicity and clarity, the exemplified component is depicted only in... Figure 1 The middle section is shown as a vertical cross-section. Example source / drain regions and channel regions may be, for example, extending inwards and outwards. Figure 1 The form of a longitudinally extending line that is a common extension of the page plane. Alternatively, and by way of example only, the horizontal cross-section of the example source / drain region and channel region may be circular, rectangular, elliptical, triangular, etc. (not shown). The gate insulator 24 and / or the gate 22 may surround such a structure or, by way of example only, partially surround such a structure or be located on only one lateral side in the vertical cross-section (not shown). The top source / drain region 16 and channel region 20 may be considered to have a top interface 38 and the bottom source / drain region 18 and channel region 20 may be considered to have a bottom interface 40. Interfaces 38 and / or 40 are shown as flat and horizontal, but other oriented interfaces may be used, such as diagonal, sawtooth and / or wavy interfaces, combinations of straight and curved segments, etc.

[0014] For example only, regions 16, 18, and 20 may comprise one or more of appropriately doped crystalline semiconductor materials, such as silicon, germanium, and one or more so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN), wherein source / drain regions 16 and 18 are sufficiently doped to be conductive and channel region 20 is undoped or sufficiently doped to be semiconductive to conduct in the "on" state of the transistor and not conduct in the "off" state. Alternatively, channel region 20 may comprise an oxide semiconductor material, such as zinc tin oxide (ZnO). x Sn y O, commonly referred to as "ZTO"), indium zinc oxide (In) x Zn y O, commonly referred to as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly referred to as "IGZO"), indium gallium silicon oxide (In) x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In) x W y O, commonly referred to as "IWO"), indium oxide (In) xO), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), Zirconia zinc tin (Si) x In y Zn z One or more of O and other similar materials. A chemical formula containing at least one of "x", "y", "z" and "a" (e.g., Zn). x Sn y O、In x Zn y O、In x Ga y Zn z O、In x W y O、In x Ga y Si z O, Al x Sn y In z Zn aThe term O represents a composite material containing, for each oxygen atom (O), an average ratio of "x" atoms of one element, "y" atoms of another element (if any), "z" atoms of an additional element (if any), and "a" atoms of a further element (if any) throughout one or more regions. Since the chemical formula represents relative atomic ratios rather than strict chemical structures, the channel material of channel region 20 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", "z", and "a" may be integers or non-integers. As used herein, the term "non-stoichiometric" means and includes compounds having elemental compositions that cannot be expressed by ratios of well-defined natural numbers and violate the law of definite proportions.

[0015] The channel region 20 is crystalline and has an average grain size of less than 20 nanometers (the average value of the straight-line dimension cut through the grain center along the grain). In this document, “crystalline” without immediately following a numerical percentage or other quantitative adjective means a material, region, and / or structure that is at least 90% crystalline by volume (i.e., has at least 90% grains by volume). In one embodiment, the average grain size of the channel region 20 is no greater than 15 nanometers, in another embodiment no greater than 10 nanometers, in another embodiment no less than 5 nanometers, and in another embodiment from 5 nanometers to 10 nanometers. The channel region 20 at the top interface 38 or the channel region 20 at the bottom interface 40 (considered individually located at either interface) has a horizontal texture larger than the volume of the grains vertically located between the grains at the top and bottom interfaces 38 and 40, respectively.

[0016] For example, Figure 1 The channel region 20 is presented as having individual grains, individually designated as 30 or 29. Grain 30 is characterized by having at least one portion of an edge or grain boundary at one of the top interface 38 or the bottom interface 40, while grain 29 is located vertically between grains 30 and does not have any portion of an edge or grain boundary located at the top interface 38 or the bottom interface 40. Figure 2 The examples schematically illustrate individual and isolated grains 25 and 50, which may include... Figure 1 The grains 30 and 29 (indicating that grains 30 and 29 may internally be grains 25 or 50) are shown to include lattice points 52, which may individually include atoms, ions, or molecules from the respective grain 25 or 50 and are arranged in crystal planes 54. The crystal planes 54 in grain 50 are relative to... Figure 2 The plane of the page is horizontally oriented, while crystal plane 54 in grain 25 is not.

[0017] Figure 3 Is with Figure 1The structure shown is the same as the one depicted, however, numbers 30 and 29 have been removed from the interior of the individual grains depicted in channel region 20. The asterisks are those that make its crystal planes appear as shown. Figure 2 In the example of the grain 50, the grain is horizontally oriented, and such crystal planes are therefore orthogonal / normal to the vertical line of the vertical transistor 14. Figure 3 An example embodiment is shown in which the channel region 20 at the top interface 38 has a horizontal texture larger than the volume of the grains 29 vertically located between the grains 30 at the top and bottom interfaces 38 and 40, respectively, regardless of whether the total volume of the grains 29 is greater than or less than the total volume of the grains 30 at either interface 38 or 40. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0018] Figure 3 An example embodiment is also shown in which the channel area 20 at only one of the top interface 38 and the bottom interface 40 has a larger horizontal texture (at the top interface 38). Furthermore, in one example, Figure 3 An embodiment is shown in which all grains 30 in the channel region 20 at the top interface 38 have horizontal texture / horizontal crystal planes. Figure 4 The example alternative embodiment construction 10a is shown, wherein, for example, less than all of the grains 30 in the channel region 20a at the top interface 38 have a horizontal texture / horizontal crystal plane. Similar designations from the above embodiments are used where appropriate, with some construction differences indicated by the suffix "a" or different designations. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0019] Figure 5 and 6 Showing the above information respectively Figure 3 and 4 The described constructions are similar to those of embodiments 10b and 10c, wherein channel regions 20b and 20c at the bottom interface 40 each have a larger horizontal texture. Similar designations from the above embodiments are used where appropriate, with some construction differences indicated by the suffix "b" or "c". Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0020] Figure 7 , 8Alternative embodiments 20d, 20e, 10f, and 10g are illustrated in 10d, 10e, 10f, and 10g, respectively, wherein the channel regions 20d, 20e, 20f, and 20g at both the top interface 38 and the bottom interface 40 individually have greater horizontal texture. Similar designations from the above embodiments are used where appropriate, with some construction differences indicated by the suffixes “d,” “e,” “f,” or “g,” respectively. In some such embodiments, the amount of texture in the channel region 20* at the top interface 38 (* is used as a suffix to encompass all such identical numerically designated components, which may or may not have other suffixes) and the amount of horizontal texture in the channel region 20* at the bottom interface 40 are relatively the same. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0021] The above examples demonstrate that none of the grains 29 in the channel region 20* between the grains 30 located vertically at the top interface 38 and the bottom interface 40 have a horizontal texture / horizontal crystal plane. Figure 11 , 12 Examples 10h, 10i, 10j, 10k, 10m, 10n, and 10p are shown, respectively, of alternative example embodiments, wherein some grains 29 in the channel region 20* located vertically between grains 30 at the top interface 38 and the bottom interface 40 have horizontal textures / horizontal crystal planes. Similar designations from the above embodiments are used where appropriate, with some structural differences indicated by the suffixes “h”, “i”, “j”, “k”, “m”, “n”, and “p”, respectively. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0022] Setting a larger horizontal texture in the channel region 20* at interface 38 or 40 can improve the conductivity between the corresponding source / drain region and the channel region (i.e., across this interface).

[0023] Any suitable method can be used to generate the channel region as shown above, and the method can be performed before or after (ideally before) the formation of the top source / drain / region 16. One example includes laser annealing. For example only, laser annealing can use wavelengths between 200 nm and 700 nm, at a speed of 0.1 J / cm². 2 Up to 2J / cm 2 (Ideally, 0.5 J / cm) 2 Up to 2J / cm 2The laser power, pulse width from 5 nanoseconds to 250 nanoseconds, number of laser emissions from 1 to 100, and substrate temperature from room temperature to 450°C are all specified in this document. The laser power for all annealing processes described herein can be varied according to the selection of a person skilled in the art. Additionally, the substrate temperature and laser pulse width may vary for different laser emissions. Multiple spatiotemporal laser annealing steps can be used. Alternatively, for example, annealing may include microwave annealing. Example microwave annealing conditions include microwave power from 500 watts to 10,000 watts, substrate temperature from room temperature to 600°C, an inert environment (e.g., N2, inert gas, etc.), pressure from 1 mTorr to atmospheric pressure, and time from 1 second to 12 hours. Multiple spatiotemporal microwave annealing steps can be used. Annealing may include any two or more of the above example annealing methods.

[0024] (Several) of the above processing or construction can be considered as relating to an array of components formed as a single stack or single layer of such components or formed within a single stack or single layer of such components, such components being above or as part of an underlying substrate (although a single stack / layer may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the completed construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional stacks / layers of this type may be positioned or fabricated above and / or below the locations shown in the figures or described above. Furthermore, (several) component arrays may be identical or different relative to each other in different stacks / layers and different stacks / layers may have the same or different thicknesses relative to each other. Intermediate structures may be disposed between vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Moreover, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / layers can be manufactured substantially simultaneously.

[0025] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting fixtures, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0026] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “below,” “under,” “upper,” and “lower” generally refer to a vertical direction. “Horizontal” means a direction along the surface of the main substrate (i.e., within 10 degrees) and relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal to the horizontal. “Completely horizontal” means a direction along the surface of the main substrate (i.e., not at an angle to it) and relative to the direction in which the substrate is processed during manufacturing, and “completely vertical” is 90° to the complete horizontal. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular directions relative to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending / extend(ing)elevationally” means a direction at an angle of at least 45° to the complete horizontal. Furthermore, in relation to field-effect transistors, "extending vertically" and "extending horizontally" refer to the orientation of the transistor channel length along which current flows between the source and drain regions during operation. For bipolar junction transistors, "extending vertically" and "extending horizontally" refer to the direction of the base length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within 10° of the vertical line.

[0027] Furthermore, the terms "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) between the two stated areas / materials / components. Moreover, the use of "above" without preceding "direct" only requires that a portion of the stated area / material / component above another stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, the use of "below" and "under" without preceding "direct" only requires that a portion of the stated area / material / component below / under another stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0028] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any material they cover. Where one or more example compositions are provided for any material, that material may comprise, consist substantially of, or be composed of such compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0029] Furthermore, “thickness” itself (without the preceding directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or adjacent regions with different compositions, passing through a given material or region. Additionally, the various materials or regions described herein may have substantially constant or variable thicknesses. If the thickness is variable, then unless otherwise indicated, the thickness refers to the average thickness, and due to the variable thickness, this material or region will have a minimum thickness and a maximum thickness. As used herein, “different compositions” only requires that the portions of two stated materials or regions that can directly touch each other are chemically and / or physically different, for example, provided that such materials or regions are not homogeneous. If two stated materials or regions do not directly touch each other, then “different compositions” only requires that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different, provided that such materials or regions are not homogeneous. In this document, a stated material, region, or structure is “directly touching” each other when there is at least some physical contact between them. In contrast, the preceding words “above,” “upon,” “adjacent,” “along,” and “against” do not include “directly against” and constructions in which (some) intermediate materials, (some) areas, or (some) structures result in the stated materials, areas, or structures not being in physical contact with each other.

[0030] In this paper, the premise of “electrical coupling” between zone-material-components is that current can flow continuously from one to the other during normal operation, and this flow is mainly achieved by moving subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be located between and electrically coupled to the zone-material-component. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0031] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features that have or may form components. "Row" and "column" are used synonymously with respect to any series of areas, components, and / or features, independent of function. In any case, rows may be straight and / or curved and / or relatively parallel and / or non-parallel to each other, as may columns. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than right angles).

[0032] Combinations of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds, or combinations thereof.

[0033] In this document, any use of "selective" in relation to etching, removal, deposition, and / or forming is an action in which a stated material is acted relative to another stated material(s) at a volume ratio of at least 2:1. Furthermore, any use of selective deposition, selective growth, or selective forming is directed at the deposition, growth, or formation of a material relative to another stated material(s) at a volume ratio of at least 2:1 for at least the first 75 angstroms.

[0034] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0035] in conclusion

[0036] In some embodiments, a vertical transistor includes: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region. The channel region is crystalline, and its grains have an average grain size of less than 20 nanometers. The channel region at the top interface or the bottom interface has a horizontal texture larger than the volume of the grains in the channel region vertically located between the grains at the top and bottom interfaces.

[0037] In some embodiments, a vertical transistor includes: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region. The channel region is crystalline, and its grains have an average grain size from 5 nanometers to 10 nanometers. The channel region at the top interface has a horizontal texture larger than the grains in the channel region vertically located between the top and bottom interfaces.

[0038] In some embodiments, a vertical transistor includes: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region. The channel region is crystalline, and its grains have an average grain size of 5 nanometers to 10 nanometers. The channel region at the bottom interface has a horizontal texture larger than the grains in the channel region vertically located between the grains at the top and bottom interfaces.

[0039] In some embodiments, a vertical transistor includes: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region. The channel region is crystalline, and its grains have an average grain size of 5 nanometers to 10 nanometers. At least some of the grains in the channel region at the top interface, at least some of the grains in the channel region at the bottom interface, and at least some of the grains in the channel region vertically located between the top and bottom interfaces have a horizontal texture. The channel region at the top and bottom interfaces has a horizontal texture larger in volume than the grains vertically located between the top and bottom interfaces.

[0040] In accordance with regulations, the subject matter disclosed herein has been described in language that is more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the means disclosed herein include exemplary embodiments. Therefore, the claims should be given the full scope expressed literally and should be appropriately interpreted in accordance with the principle of equivalence.

Claims

1. An upright transistor comprising: a top source / drain region, a bottom source / drain region, a channel region uprightly between the top and bottom source / drain regions, and a gate operatively laterally adjacent the channel region, the top source / drain region having a top interface with the channel region, the bottom source / drain region having a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size of less than 20 nanometers; and the channel region at the top interface or at the bottom interface has a horizontal texture that is greater than the volume of the grains in the channel region uprightly between the grains at the top and bottom interfaces.

2. The upright transistor of claim 1, wherein the average grain size of the channel region is no greater than 15 nanometers.

3. The upright transistor of claim 2, wherein the average grain size of the channel region is no greater than 10 nanometers.

4. The upright transistor of claim 1, wherein the average grain size of the channel region is no less than 5 nanometers.

5. The upright transistor of claim 1, wherein the average grain size of the channel region is from 5 nanometers to 15 nanometers.

6. The upright transistor of claim 1, wherein the top and bottom source / drain regions are crystalline.

7. The upright transistor of claim 1, wherein all of the grains in the channel region at the top interface or at the bottom interface have a horizontal texture.

8. The upright transistor of claim 1, wherein less than all of the grains in the channel region at the top interface or at the bottom interface have a horizontal texture.

9. The upright transistor of claim 1, wherein the channel region at the top interface has a greater horizontal texture.

10. The upright transistor of claim 1, wherein the channel region at the bottom interface has a greater horizontal texture.

11. The upright transistor of claim 1, wherein the channel region at only one of the top and bottom interfaces has a greater horizontal texture.

12. The upright transistor of claim 11, wherein the channel region at the top interface has a greater horizontal texture.

13. The upright transistor of claim 11, wherein the channel region at the bottom interface has a greater horizontal texture.

14. The upright transistor of claim 1, wherein the channel region at both the top and bottom interfaces has a greater horizontal texture.

15. The upright transistor of claim 1, wherein some of the grains in the volume of the channel region uprightly between the grains at the top and bottom interfaces have a horizontal texture.

16. The upright transistor of claim 1, wherein none of the grains in the volume of the channel region uprightly between the grains at the top and bottom interfaces have a horizontal texture.

17. The vertical transistor of claim 1, wherein the greater horizontal texture is perfectly horizontal, and the vertical transistor is perfectly vertical.

18. A vertical transistor, comprising: a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate operatively laterally adjacent the channel region, the top source / drain region having a top interface with the channel region, the bottom source / drain region having a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size from 5 nanometers to 10 nanometers; and the channel region at the top interface has a horizontal texture greater than a volume of the grains in the channel region vertically between the grains at the top and bottom interfaces.

19. The vertical transistor of claim 18, wherein all of the grains in the channel region at the top interface have a horizontal texture.

20. The vertical transistor of claim 18, wherein less than all of the grains in the channel region at the top interface have a horizontal texture.

21. The vertical transistor of claim 18, wherein the greater horizontal texture is perfectly horizontal, and the vertical transistor is perfectly vertical.

22. A vertical transistor, comprising: a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate operatively laterally adjacent the channel region, the top source / drain region having a top interface with the channel region, the bottom source / drain region having a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size from 5 nanometers to 10 nanometers; and the channel region at the bottom interface has a horizontal texture greater than a volume of the grains in the channel region vertically between the grains at the top and bottom interfaces.

23. The vertical transistor of claim 22, wherein all of the grains in the channel region at the bottom interface have a horizontal texture.

24. The vertical transistor of claim 22, wherein less than all of the grains in the channel region at the bottom interface have a horizontal texture.

25. The vertical transistor of claim 22, wherein the greater horizontal texture is perfectly horizontal, and the vertical transistor is perfectly vertical.

26. A vertical transistor, comprising: a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate operatively laterally adjacent the channel region, the top source / drain region having a top interface with the channel region, the bottom source / drain region having a bottom interface with the channel region; the channel region is crystalline, and its grains have an average grain size from 5 nanometers to 10 nanometers; and the channel region at the bottom interface has a horizontal texture greater than a volume of the grains in the channel region vertically between the grains at the top and bottom interfaces. At least some of the grains in the channel region at the top interface, at least some of the grains in the channel region at the bottom interface, and at least some of the grains of the channel region vertically between the grains at the top and bottom interfaces have horizontal texture; the channel region at the top and bottom interfaces has more horizontal texture than the volume of the grains vertically between the top and bottom interfaces.

27. The vertical transistor of claim 26, wherein the amount of horizontal texture in the channel region at the top interface is the same as the amount of horizontal texture in the channel region at the bottom interface relative to each other.

28. The vertical transistor of claim 26, wherein the greater horizontal texture is perfectly horizontal, and the vertical transistor is perfectly vertical.

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