Differential Signal Detection Circuit, Detection Method and Electronic Device

Abstract

The present application provides a differential signal detection circuit, a detection method and an electronic device, including: a voltage threshold generation unit, a pre-comparison unit, a rectification comparison unit and a detection processing unit; the voltage threshold generation unit provides an adjustable voltage threshold according to a reference voltage value and an adjustable symbol sequence; the pre-comparison unit compares the voltage value of the differential signal with the adjustable voltage threshold to provide a first comparison result; the rectification comparison unit performs rectification and comparison processing on the first comparison result to provide a signal to be detected; when the detection processing unit detects that the signal to be detected is at a high level, it determines that the differential signal is a valid signal; when it detects that the signal to be detected is at a low level, it subtracts a preset value from the adjustable symbol sequence and provides the adjustable symbol sequence after subtracting the preset value to the voltage threshold generation unit to obtain a new signal to be detected. The differential signal detection circuit, detection method and electronic device provided by the present application are used to improve the accuracy of detecting whether a differential signal is a valid signal.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a differential signal detection circuit, a detection method, and an electronic device. Background Art

[0002] SerDes (serializer / deserializer) is a transceiver IC (integrated circuit) that converts serial data and parallel data mutually. The SerDes includes a receiving end, and the receiving end includes an equalization circuit, a clock data recovery circuit, a deserialization circuit, etc. The equalization circuit is used to equalize differential signals to eliminate losses and inter-symbol interference during the transmission of differential signals. The clock data recovery circuit is used to sample the signal output by the equalization circuit, thereby extracting clock information and re-timing the data. The deserialization circuit deserializes the serial high-speed data output by the clock data recovery circuit into parallel data. Usually, after detecting that the differential signal is a valid signal, the equalization circuit, the clock data recovery circuit, the deserialization circuit, etc. are controlled to start working.

[0003] In the related art, an analog front-end circuit (as shown in Figure 1 ) includes: an impedance matching unit 110, a differential amplifier 120, and an amplitude detection and judgment unit 130. The impedance matching unit 110 is used to adapt differential signals (inp, inn) with different amplitudes and implement multi-path output of differential signals; the differential amplifier 120 is used to amplify the signal to be detected of the impedance matching unit 110 and provide it to the amplitude detection and judgment unit 130; the amplitude detection and judgment unit 130 is used to detect the amplitudes of the signals to be detected (outp, outn) of the differential amplifier 120, judge whether the amplitudes of the signals to be detected (outp, outn) are greater than a preset amplitude threshold to obtain a detection signal, and further judge whether the detection signal is a pulse signal. If so, it is determined that the differential signal is a valid signal.

[0004] In practical applications, when the transmission rate of the differential signals (inp, inn) is relatively high, the amplitude values of the differential signals (inp, inn) are relatively low, and at the same time, the amplitude values jitter greatly. There may be a process in which the amplitude of the differential signal suddenly becomes larger and then becomes smaller. Therefore, by using the above analog front-end circuit to obtain a detection signal, the detection signal may be misjudged as a pulse signal, resulting in poor accuracy in detecting whether the differential signal is a valid signal. Summary of the Invention

[0005] The present application provides a differential signal detection circuit, a detection method, and an electronic device to solve the problem of poor accuracy in detecting whether a differential signal is a valid signal.

[0006] In a first aspect, the present application provides a detection circuit for differential signals, including: a voltage threshold generation unit, a pre-comparison unit, a rectification comparison unit, and a detection processing unit; wherein,

[0007] The voltage threshold generation unit is configured to provide an adjustable voltage threshold to the pre-comparison unit according to an input reference voltage value and an adjustable symbol sequence;

[0008] The pre-comparison unit is configured to compare the voltage value of the input differential signal with the adjustable voltage threshold, and provide a first comparison result to the rectification comparison unit;

[0009] The rectification comparison unit is configured to perform rectification and comparison processing on the first comparison result, and provide a signal to be detected to the detection processing unit;

[0010] The detection processing unit is configured to determine that the differential signal is a valid signal when the signal to be detected is detected as a high level; when the signal to be detected is detected as a low level, subtract a preset value from the adjustable symbol sequence, and provide the adjustable symbol sequence after subtracting the preset value to the voltage threshold generation unit to obtain a new signal to be detected.

[0011] In this design, when the detection processing unit detects that the signal to be detected is a low level (indicating that the differential signal is an invalid signal), it reduces the value of the adjustable symbol sequence, so that the value of the adjustable voltage threshold becomes smaller, ensuring that the pre-comparison unit can compare the voltage value of the input differential signal with the reduced adjustable voltage threshold again to obtain a new first comparison result, and enabling the rectification comparison unit to provide a new signal to be detected to the detection processing unit again based on the new first comparison result, realizing cyclic detection of the differential signal and improving the accuracy of detecting whether the differential signal is a valid signal.

[0012] In a possible design, the voltage threshold generation unit includes: a decoder, a first-stage operational amplifier, and a second-stage operational amplifier;

[0013] The decoder is configured to perform decoding processing on the adjustable symbol sequence to obtain a switch control sequence;

[0014] The first-stage operational amplifier is configured to amplify the feedback voltage provided by the second-stage operational amplifier and the reference voltage value to obtain an amplified reference voltage value;

[0015] The second-stage operational amplifier is configured to output an adjustable voltage threshold according to the amplified reference voltage value and the switch control sequence, and provide a feedback voltage to the first-stage operational amplifier.

[0016] In this design, the adjustable symbol sequence is decoded by a decoder to obtain a switch control sequence, which can reduce the number of input control words, and further reduce the number of pins of the test circuit. Moreover, the adjustable symbol sequence can be flexibly configured, and the test circuit provided in this application can adapt to SerDes in different working scenarios.

[0017] In a possible design, the first-stage operational amplifier includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, NMOS transistor M4, and NMOS transistor M5;

[0018] The source of PMOS transistor M1 is connected to the source of PMOS transistor M2, the gate of PMOS transistor M1 is connected to the gate of PMOS transistor M2, and the source of NMOS transistor M3 is connected to the source of NMOS transistor M4;

[0019] The sources of PMOS transistor M1 and PMOS transistor M2 receive a first voltage;

[0020] The drain of NMOS transistor M3 is respectively connected to the drain and gate of PMOS transistor M1, and the gate of NMOS transistor M3 is connected to the first output terminal of the second-stage operational amplifier;

[0021] The drain of NMOS transistor M4 is respectively connected to the drain of PMOS transistor M2 and the input terminal of the second-stage operational amplifier, and the gate of NMOS transistor M4 receives a reference voltage value;

[0022] The gate of NMOS transistor M5 receives a second voltage, the source of NMOS transistor M5 is grounded, and the drain of NMOS transistor M5 is connected between the sources of NMOS transistor M3 and NMOS transistor M4.

[0023] In a possible design, the second-stage operational amplifier includes: PMOS transistor M6, NMOS transistor M7, resistor Rc, capacitor Cc, resistor array RA1, and resistor array RA2;

[0024] The source of PMOS transistor M6 receives a first voltage;

[0025] The drain of PMOS transistor M6 is connected to the drain of NMOS transistor M7 through the series-connected resistor array RA1 and resistor array RA2. The source of NMOS transistor M7 is grounded, and the gate of NMOS transistor M7 receives a second voltage;

[0026] The gate of PMOS transistor M6 is connected to the first-stage operational amplifier and is also connected to the drain of PMOS transistor M6 through the series-connected resistor Rc and capacitor Cc;

[0027] The resistor array RA1 outputs the maximum adjustable voltage threshold in the adjustable voltage threshold, and the resistor array RA2 outputs the minimum adjustable voltage threshold in the adjustable voltage threshold;

[0028] The gate of NMOS transistor M3 is connected between resistor array RA1 and resistor array RA2.

[0029] In a possible design, resistor arrays RA1 and RA2 have the same structure;

[0030] Resistor array RA1 includes N resistors connected in series and switches connected to each resistor.

[0031] In this design, resistor array RA1 includes N resistors connected in series and switches connected to each resistor. The switches can be controlled to conduct or cut off, flexibly select the resistors, so as to obtain the maximum adjustable voltage threshold and the minimum adjustable voltage threshold whose values can change.

[0032] In a possible design, the differential signal includes: a first signal and a second signal;

[0033] The adjustable voltage threshold includes: a maximum adjustable voltage threshold and a minimum adjustable voltage threshold;

[0034] The first comparison result includes: a first voltage difference, a first common-mode voltage, a second voltage difference, and a second common-mode voltage;

[0035] The pre-comparison unit includes: a first amplifier and a second amplifier;

[0036] The first amplifier is configured to output a first voltage difference and a first common-mode voltage according to the first signal, the second signal, and the maximum adjustable voltage threshold and the minimum adjustable voltage threshold in the adjustable voltage threshold;

[0037] The second amplifier is configured to output a second voltage difference and a second common-mode voltage according to the first signal, the second signal, and the maximum adjustable voltage threshold and the minimum adjustable voltage threshold in the adjustable voltage threshold.

[0038] In a possible design, the first amplifier and the second amplifier have the same structure;

[0039] The first amplifier includes: resistor R2, resistor R3, resistor R4, resistor R5, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, NMOS transistor M11, NMOS transistor M12, and NMOS transistor M13; wherein,

[0040] The series-connected resistor R2 and resistor R4 are in parallel with the series-connected resistor R3 and resistor R5; resistor R2 and resistor R3 receive the first voltage, and the first common-mode voltage is output between resistor R4 and resistor R5;

[0041] The source of NMOS transistor M8 is connected to the source of NMOS transistor M9, and the source of NMOS transistor M11 is connected to the source of NMOS transistor M12;

[0042] The gate of NMOS transistor M10 receives a second voltage, the source of NMOS transistor M10 is grounded, the drain of NMOS transistor M10 is connected between the source of NMOS transistor M8 and the source of NMOS transistor M9, the gate of NMOS transistor M8 receives the minimum adjustable voltage threshold, the drain of NMOS transistor M8 is respectively connected to the drain of NMOS transistor M11, and resistors R2 and R4, the gate of NMOS transistor M9 receives a second signal, and the drain of NMOS transistor M9 outputs a first voltage difference;

[0043] The gate of NMOS transistor M13 is connected to a second voltage, the source of NMOS transistor M13 is grounded, the drain of NMOS transistor M13 is connected between the source of NMOS transistor M11 and the source of NMOS transistor M12, the gate of NMOS transistor M11 receives a first signal, and the drain of NMOS transistor M12 is respectively connected to the drain of the said NMOS transistor M9, and the said resistors R3 and R5.

[0044] In a possible design, the rectifying and comparing unit includes: a rectifying module and a comparator module;

[0045] The rectifying module is used for rectifying the first comparison result and providing a first rectifying signal and a second rectifying signal to the comparator module;

[0046] The comparator module is used for comparing the first voltage value of the first rectifying signal and the second voltage value of the second rectifying signal and providing a signal to be detected to the detection processing unit.

[0047] In a possible design, the rectifying module includes: a first rectifier and a second rectifier;

[0048] The first rectifier is used for outputting a second rectifying signal according to the first common-mode voltage and the second common-mode voltage in the first comparison result;

[0049] The second rectifier is used for outputting a first rectifying signal according to the first voltage difference and the second voltage difference in the first comparison result.

[0050] In a possible design, the structures of the first rectifier and the second rectifier are the same;

[0051] The first rectifier includes: resistor R6, resistor R7, NMOS transistor M14, NMOS transistor M15 and NMOS transistor M16; wherein,

[0052] Resistor R6 and resistor R7 are connected, and resistor R6 and resistor R7 receive a first voltage;

[0053] The source of NMOS transistor M14 and the source of NMOS transistor M15 are connected;

[0054] The drain of NMOS transistor M14 is connected to resistor R6, and the gate of NMOS transistor M14 receives the first common-mode voltage;

[0055] The drain of NMOS transistor M15 is connected to resistor R7, and the gate of NMOS transistor M17 receives the second common-mode voltage;

[0056] The gate of NMOS transistor M16 receives the second voltage. The source of NMOS transistor M16 is grounded, and the drain of NMOS transistor M16 is connected between the source of NMOS transistor M14 and the source of NMOS transistor M15, and a second rectified signal is output between the source of NMOS transistor M14 and the source of NMOS transistor M15.

[0057] In a possible design, the comparator module includes: a first comparator and a second comparator;

[0058] The first comparator is configured to compare the first voltage value and the second voltage value, and provide a second comparison result to the second comparator;

[0059] The second comparator is configured to perform a conversion process on the second comparison result, and provide a signal to be detected to the detection processing unit.

[0060] In a possible design, the first comparator includes: NMOS transistors M17, M18, M19, PMOS transistors M20, M21, M22, and M23;

[0061] The sources of NMOS transistors M17 and M18 are connected, and the sources of PMOS transistors M20, M21, M22, and M23 are connected. The drains of PMOS transistors M20 and M21 are connected, and the drains of PMOS transistors M22 and M23 are connected;

[0062] The gate of PMOS transistor M20 receives the third voltage, and the gate of PMOS transistor M21 is connected between the drains of PMOS transistors M22 and M23;

[0063] The gate of PMOS transistor M23 receives the third voltage, and the gate of PMOS transistor M22 is connected between the drains of PMOS transistors M20 and M21;

[0064] The gate of NMOS transistor M17 receives the second rectified signal, and the drain of NMOS transistor M17 is connected between the drains of PMOS transistors M20 and M21;

[0065] The gate of NMOS transistor M18 receives the first rectified signal, and the drain of NMOS transistor M18 is connected between the drains of PMOS transistors M22 and M23;

[0066] The gate of NMOS transistor M19 receives the fourth voltage, the source of NMOS transistor M19 is grounded, and the drain of NMOS transistor M19 is connected between the sources of NMOS transistors M17 and M18.

[0067] In a possible design, the second comparator includes: PMOS transistor M24, PMOS transistor M25, NMOS transistor M26, NMOS transistor M27, NMOS transistor M28, and NMOS transistor M29;

[0068] The sources of PMOS transistor M24 and PMOS transistor M25 are connected, and the sources of PMOS transistor M24 and PMOS transistor M25 receive the first voltage;

[0069] The sources of NMOS transistor M26, NMOS transistor M27, NMOS transistor M28, and NMOS transistor M29 are grounded;

[0070] The gate of PMOS transistor M24 is connected between the drains of PMOS transistors M20 and M21, the drain of PMOS transistor M24 is connected to the drain of NMOS transistor M27, and the gate of NMOS transistor M27 is connected to the drains and gates of NMOS transistors M29 and M28 respectively;

[0071] The gate of PMOS transistor M25 is connected between the drains of PMOS transistors M23 and M22, the drain of PMOS transistor M25 is connected between the drains of NMOS transistors M28 and M29, and the gate of NMOS transistor M28 is connected to the drains and gates of NMOS transistors M26 and M27 respectively;

[0072] The signal to be detected is output between the drain of PMOS transistor M25 and the drain of NMOS transistor M28.

[0073] In a second aspect, the present application provides a method for detecting a differential signal, which is applied to the differential signal detection circuit described in any item of the first aspect; the method includes:

[0074] Receiving a reference voltage value and an adjustable symbol sequence,

[0075] Outputting an adjustable voltage threshold according to the reference voltage value and the adjustable symbol sequence;

[0076] Receiving a differential signal;

[0077] Output a first comparison result according to the differential signal and the adjustable voltage threshold;

[0078] Rectify and compare the first comparison result to obtain a signal to be detected;

[0079] If the signal to be detected is at a high level, determine that the differential signal is a valid signal;

[0080] If the signal to be detected is at a low level, subtract a preset value from the adjustable symbol sequence, and obtain a new signal to be detected according to the adjustable symbol sequence after subtracting the preset value.

[0081] In a third aspect, the present application provides an electronic device, including: a detection circuit for the differential signal according to any one of the first aspects.

[0082] The present application provides a detection circuit, a detection method and an electronic device for a differential signal. The detection circuit for the differential signal includes: a voltage threshold generation unit, a pre-comparison unit, a rectification and comparison unit, and a detection and processing unit. Among them, the voltage threshold generation unit is configured to provide an adjustable voltage threshold to the pre-comparison unit according to an input reference voltage value and an adjustable symbol sequence; the pre-comparison unit is configured to compare the voltage value of the input differential signal with the adjustable voltage threshold, and provide a first comparison result to the rectification and comparison unit; the rectification and comparison unit is configured to rectify and compare the first comparison result, and provide a signal to be detected to the detection and processing unit; the detection and processing unit is configured to determine that the differential signal is a valid signal when detecting that the signal to be detected is at a high level; when detecting that the signal to be detected is at a low level, subtract a preset value from the adjustable symbol sequence, and provide the adjustable symbol sequence after subtracting the preset value to the voltage threshold generation unit to obtain a new signal to be detected. In the detection circuit, detection method and electronic device for a differential signal provided by the present application, when the detection and processing unit detects that the signal to be detected is at a low level (indicating that the differential signal is an invalid signal), the value of the adjustable symbol sequence is reduced, so that the value of the adjustable voltage threshold becomes smaller, ensuring that the pre-comparison unit can compare the voltage value of the input differential signal with the reduced adjustable voltage threshold again to obtain a new first comparison result, and enabling the rectification and comparison unit to provide a new signal to be detected to the detection and processing unit again based on the new first comparison result, realizing cyclic detection of the differential signal and improving the accuracy of detecting whether the differential signal is a valid signal. Description of the Drawings

[0083] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0084] Figure 1 It is a schematic structural diagram of an analog front-end circuit provided in the related art;

[0085] Figure 2 Schematic structure of the differential signal detection circuit provided by this application Figure 1 ;

[0086] Figure 3 Schematic diagram of the correspondence between the adjustable symbol sequence and the adjustable voltage threshold provided by this application;

[0087] Figure 4 Flowchart of the working method of the detection circuit 20 provided by this application;

[0088] Figure 5 Schematic structure diagram of the voltage threshold generation unit 21 provided by this application;

[0089] Figure 6 Schematic structure diagram of the pre - comparison unit 22 provided by this application;

[0090] Figure 7 Schematic illustration of the relationship between inp, inn, vthp, and vthn in AMP1 provided by this application Figure 1 ;

[0091] Figure 8 Schematic illustration of the relationship between inp, inn, vthp, and vthn in AMP1 provided by this application Figure 2 ;

[0092] Figure 9 Schematic illustration of the relationship between outn1, outn2, vcmn1, and vcmn2 in the pre - comparison unit 22 provided by this application Figure 1 ;

[0093] Figure 10 Schematic illustration of the relationship between outn1, outn2, vcmn1, and vcmn2 in the pre - comparison unit 22 provided by this application Figure 2 ;

[0094] Figure 11 Schematic structure of the differential signal detection circuit provided by this application Figure 2 ;

[0095] Figure 12 Schematic structure diagram of the rectification module 231 provided by this application;

[0096] Figure 13 Schematic structure diagram of the comparator module 232 provided by this application.

[0097] Through the above - mentioned drawings, specific embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. Detailed Implementation Modes

[0098] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation modes described in the following exemplary embodiments do not represent all implementation modes consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0099] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and above-mentioned accompanying drawings of the present application are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data may be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0100] Figure 1 is a schematic structural diagram of an analog front-end circuit provided in the related art. As Figure 1 shown, the analog front-end circuit 10 includes: an impedance matching unit 110, a differential amplifier 120, and an amplitude detection and judgment unit 130. The impedance matching unit 110, the differential amplifier 120, and the amplitude detection and judgment unit 130 are connected in sequence.

[0101] The impedance matching unit 110 is used to adapt differential signals (inp, inn) with different amplitudes and implement multi-path output of the differential signals. The differential amplifier 120 is used to amplify the signal to be detected of the impedance matching unit 110 and provide it to the amplitude detection and judgment unit 130. The amplitude detection and judgment unit 130 is used to detect the amplitude of the signal to be detected (outp, outn) of the differential amplifier 120, judge whether the amplitude of the signal to be detected (outp, outn) is greater than a preset amplitude threshold to obtain a detection signal, and further judge whether the detection signal is a pulse signal. If so, it is determined that the differential signal is a valid signal.

[0102] In practical applications, when the transmission rate of the differential signals (inp, inn) is relatively high, the amplitude value of the differential signals (inp, inn) is relatively low, and at the same time, the amplitude value jitters greatly. There may be a process in which the amplitude value of the differential signal suddenly becomes larger and then smaller. At this time, the detection signal should be a non-pulse signal. However, if throughFigure 1 The provided analog front-end circuit obtains a detection signal, which may misjudge the detection signal as a pulse signal, resulting in poor accuracy in detecting whether the differential signal is a valid signal.

[0103] In this application, in order to improve the accuracy of detecting whether a differential signal is a valid signal, the inventor designed a detection circuit for differential signals, and designed a voltage threshold generation unit, a pre-comparison unit, a rectification comparison unit, and a detection processing unit in the detection circuit. The voltage threshold generation unit can generate an adjustable voltage threshold with a variable voltage value. The pre-comparison unit can provide a first comparison result to the rectification comparison unit according to the voltage value of the differential signal and the adjustable voltage threshold. The rectification comparison unit provides a signal to be detected to the detection processing unit according to the first comparison result. When the detection processing unit detects that the signal to be detected is at a high level, it determines that the differential signal is a valid signal. When the detection processing unit detects that the signal to be detected is at a low level, it causes the voltage threshold generation unit to generate a new adjustable voltage threshold, and again provides a new first comparison result according to the voltage value of the differential signal and the new adjustable voltage threshold. In this application, the value of the adjustable voltage threshold can change. Therefore, by changing the magnitude of the adjustable voltage threshold, the voltage value of the differential signal and the adjustable voltage threshold can be processed repeatedly, thereby improving the accuracy of detecting whether the differential signal is a valid signal.

[0104] The following uses specific embodiments to detail the technical solution of this application and how the technical solution of this application solves the above technical problems. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the drawings.

[0105] Figure 2 Structural schematic of the detection circuit for differential signals provided by this application Figure 1 As Figure 2 shown, the detection circuit 20 includes: a voltage threshold generation unit 21, a pre-comparison unit 22, a rectification comparison unit 23, and a detection processing unit 24.

[0106] The voltage threshold generation unit 21 is respectively connected to the pre-comparison unit 22 and the detection processing unit 24, the pre-comparison unit 22 is connected to the rectification comparison unit 23, and the rectification comparison unit 23 is also connected to the detection processing unit 24.

[0107] The voltage threshold generation unit 21 is configured to provide an adjustable voltage threshold to the pre-comparison unit 22 according to the input reference voltage value and adjustable symbol sequence;

[0108] The pre-comparison unit 22 is configured to compare the voltage value of the input differential signal with the adjustable voltage threshold and provide a first comparison result to the rectification comparison unit 23;

[0109] A rectifying and comparing unit 23, configured to rectify and compare the first comparison result and provide a signal to be detected to a detection processing unit 24;

[0110] The detection processing unit 24 is configured to determine that the differential signal is a valid signal when the signal to be detected is detected as a high level; when the signal to be detected is detected as a low level, subtract a preset value from the adjustable symbol sequence, and provide the adjustable symbol sequence after subtracting the preset value to a voltage threshold generating unit 21 to obtain a new signal to be detected.

[0111] The adjustable symbol sequence is provided by the detection processing unit 24. When the signal to be detected is detected as a low level, subtract a preset value from the previously output adjustable symbol sequence, and provide the adjustable symbol sequence after subtracting the preset value to the voltage threshold generating unit 21.

[0112] Optionally, the adjustable symbol sequence is TH <m:0>Any one of the symbol sequences. For example, M can be 2, 3, etc.

[0113] For example, when M is equal to 2, TH<2:0> includes 8 adjustable symbol sequences, which are in turn: 000, 001, 010, 011, 100, 101, 110, 111.

[0114] For example, when M is equal to 3, TH<3:0> includes 16 adjustable symbol sequences, which are in turn: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111.

[0115] The adjustable voltage threshold includes the maximum adjustable voltage threshold vthp and the minimum adjustable voltage threshold vthn.

[0116] In this application, the SerDes includes a receiving end, and the receiving end includes the detection circuit for the differential signal provided by this application. The differential signal is the signal sent from the sending end to the receiving end, where the sending end and the receiving end are not in the same SerDes.

[0117] The differential signal includes a first signal inp and a second signal inp. The amplitudes of the first signal inp and the second signal inp are the same and the phases are opposite.

[0118] The following combines Figure 3 to illustrate the correspondence between the adjustable symbol sequence and the adjustable voltage threshold. Figure 3 is a schematic diagram of the correspondence between the adjustable symbol sequence and the adjustable voltage threshold provided by this application. As Figure 3 shown, in the two-dimensional coordinate system, it includes: the X-axis and the Y-axis. The X-axis represents the adjustable symbol sequence, and the Y-axis represents the adjustable voltage threshold. It should be noted that Figure 3 is illustrated by taking TH<2:0> as an example. In Figure 3 , as the value of the adjustable symbol sequence increases, vthp increases in turn, and vthn decreases in turn.

[0119] The following takes TH<2:0> as an example and combines Figure 4 to illustrate the working process of the detection circuit 20.

[0120] Figure 4 is a flowchart of the detection method for the differential signal provided by this application. Figure 4 The detection method for the differential signal shown can be executed by the detection circuit 20. As Figure 4 shown, the method includes:

[0121] In S401, the voltage threshold generation unit 21 receives the reference voltage value vcm and the adjustable symbol sequence i, and outputs the maximum adjustable voltage threshold vthp and the minimum adjustable voltage threshold vthn.

[0122] Initially, the adjustable symbol sequence i is the symbol sequence 111 with the largest value among the values in TH<2:0>.

[0123] In S402, the pre-comparison unit 22 receives the differential signal, vthp and vthn, and outputs the first comparison result.

[0124] In S403, the rectifying and comparing unit 23 receives the first comparison result, and performs rectifying and comparing processing on the first comparison result to obtain the signal to be detected.

[0125] In S404, the detection processing unit 24 receives the signal to be detected, and determines whether the signal to be detected is at a high level.

[0126] If so, S405 is executed; otherwise, S406 is executed.

[0127] In S405, the detection processing unit 24 determines that the differential signal is a valid signal.

[0128] In S406, the detection processing unit 24 determines whether the adjustable symbol sequence i is 000.

[0129] If so, S407 is executed; otherwise, S408 is executed.

[0130] In S407, the detection processing unit 24 determines that the differential signal is an invalid signal.

[0131] In S408, the detection processing unit 24 subtracts a preset value from the adjustable symbol sequence i to obtain the adjustable symbol sequence i-1, updates the adjustable symbol sequence i to the adjustable symbol sequence i-1, and repeats the execution of S401 to S407.

[0132] Optionally, the preset value can be binary 1.

[0133] In Figure 2 In the detection circuit 20 provided in the embodiment, when the detection processing unit 24 detects that the signal to be detected is at a low level (indicating that the differential signal is an invalid signal), it reduces the value of the adjustable symbol sequence, so that the value of the adjustable voltage threshold becomes smaller, ensuring that the pre-comparison unit 22 can compare the voltage value of the input differential signal with the adjustable voltage threshold with a smaller value again to obtain a new first comparison result, and enabling the rectifying and comparing unit 23 to provide a new signal to be detected to the detection processing unit 24 again based on the new first comparison result, realizing the cyclic detection of the differential signal and improving the accuracy of detecting whether the differential signal is a valid signal.

[0134] Further, in the present application, the signal to be detected provided by the rectification comparison unit 23 to the detection processing unit 24 is a high level or a low level, rather than a pulse signal. Therefore, when the transmission rate of the differential signals (inp, inn) is relatively high (the amplitude values of the differential signals (inp, inn) are relatively low and the jitter is relatively large), the detection processing unit 24 can also accurately detect whether the differential signal is a valid signal, avoiding misdetecting the signal to be detected that should be at a high level as a low level, and improving the accuracy of detecting whether the differential signal is a valid signal.

[0135] In the prior art, in order to accurately determine whether a detection signal is a pulse signal, a counter is usually added in the analog front-end circuit to count the detected pulse signals within a certain clock cycle. When the number of pulse signals reaches a threshold value, the detection signal is considered to be a pulse signal. Since the above-mentioned related technology requires adding a counter, the complexity of the circuit is increased and the design area of the circuit is increased.

[0136] In the present application, the signal to be detected is a high level or a low level, rather than a pulse signal. Therefore, there is no need to add a counter in the detection circuit, reducing the complexity of the detection circuit and the design area of the detection circuit.

[0137] Based on the above embodiments, the voltage threshold generation unit 21 provided by the present application will be described below in conjunction with Figure 5 FIG.

[0138] Figure 5 FIG. Figure 5 is a schematic structural diagram of the voltage threshold generation unit 21 provided by the present application. As

[0139] shown, the voltage threshold generation unit 21 includes: a decoder 210, a first-stage operational amplifier 211, and a second-stage operational amplifier 212.

[0140] The decoder 210 is configured to perform operations on the adjustable symbol sequence TH <m:0>Perform decoding processing to obtain the switch control sequence GP <n:0>Optionally, when the detection circuit 20 includes a detection processing unit 24, the adjustable symbol sequence TH can be adjusted by the detection processing unit 24 <m:0>, when the detection circuit 20 does not include the detection processing unit 24, the adjustable symbol sequence TH can be manually adjusted <m:0>。

[0141] The first - stage operational amplifier 211 amplifies the feedback voltage value and the reference voltage value provided by the second - stage operational amplifier 212 to obtain an amplified reference voltage value.

[0142] The second - stage operational amplifier 212 outputs an adjustable voltage threshold according to the amplified reference voltage value and the switch control sequence, and provides a feedback voltage value to the first - stage operational amplifier 211.

[0143] Among them, M and N have the following relationship: 2 M+1 -1 = N. For example, when M = 2, N is equal to 7. For example, when M = 3, N is equal to 15.

[0144] For example, when the adjustable symbol sequence is TH<2:0>, the decoder 210 decodes the adjustable symbol sequence TH<2:0> to obtain the switch control sequence GP<7:0>.

[0145] It should be noted that GP<7:0> is a switch control sequence with only one bit being 0, and the switch control sequence GP<7:0> can be any one of 1111 1110, 1111 1101, 1111 1011, 1111 0111, 1110 1111, 1101 1111, 1011 1111, 0111 1111.

[0146] It should be noted that the position of which bit of GP<7:0> is 0 corresponds to TH<2:0>, GP <n:0>The right side is the least significant bit, and the left side is the most significant bit.

[0147] For example, when TH<2:0> is 000, it indicates that the first bit in GP<7:0> is 0, that is, GP<7:0> is 1111 1110.

[0148] For example, when TH<2:0> is 001, it indicates that the second bit in GP<7:0> is 0, that is, GP<7:0> is 1111 1101.

[0149] For example, when TH<2:0> is 111, it indicates that the eighth bit in GP<7:0> is 0, that is, GP<7:0> is 0111 1111.

[0150] In a possible design, the first-stage operational amplifier 211 includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, NMOS transistor M4, and NMOS transistor M5;

[0151] The sources of PMOS transistor M1 and PMOS transistor M2 are connected, the gates of PMOS transistor M1 and PMOS transistor M2 are connected, and the sources of NMOS transistor M3 and NMOS transistor M4 are connected;

[0152] The sources of PMOS transistor M1 and PMOS transistor M2 receive the first voltage VDD;

[0153] The drain of NMOS transistor M3 is respectively connected to the drain and gate of PMOS transistor M1, and the gate of NMOS transistor M3 is connected to the first output terminal of the second-stage operational amplifier (for outputting the feedback voltage value vcm_out);

[0154] The drain of NMOS transistor M4 is respectively connected to the drain of PMOS transistor M2 and the input terminal of the second-stage operational amplifier 212, and the gate of NMOS transistor M4 receives the reference voltage value vcm;

[0155] The gate of NMOS transistor M5 receives the second voltage Vb, the source of NMOS transistor M5 is grounded, and the drain of NMOS transistor M5 is connected between the sources of NMOS transistor M3 and NMOS transistor M4.

[0156] In a possible design, the second-stage operational amplifier 212 includes: PMOS transistor M6, NMOS transistor M7, resistor Rc, capacitor Cc, resistor array RA1, and resistor array RA2;

[0157] The source of PMOS transistor M6 receives the first voltage VDD;

[0158] The drain of PMOS transistor M6 is connected to the drain of NMOS transistor M7 through series-connected resistor arrays RA1 and RA2. The source of NMOS transistor M7 is grounded, and the gate of NMOS transistor M7 receives the second voltage Vb.

[0159] The gate of PMOS transistor M6 is respectively connected to the first-stage operational amplifier 211 and is connected to the drain of PMOS transistor M6 through series-connected resistor Rc and capacitor Cc.

[0160] Resistor array RA1 outputs vthp in the adjustable voltage threshold, and resistor array RA2 outputs vthn in the adjustable voltage threshold.

[0161] The gate of NMOS transistor M3 is connected between resistor array RA1 and resistor array RA2. A feedback voltage value vcm_out is output between resistor array RA1 and resistor array RA2.

[0162] The gate of PMOS transistor M6 is respectively connected to the first-stage operational amplifier 211, including: the gate of PMOS transistor M6 is connected between the drain of NMOS transistor M4 and the drain of PMOS transistor M2.

[0163] In a possible design, resistor arrays RA1 and RA2 have the same structure.

[0164] Resistor array RA1 includes N series-connected resistors and switches connected to each resistor.

[0165] For example, when N is equal to 8, resistor array RA1 includes 8 resistors R, a switch TP7 connected to the first resistor R, a switch TP6 connected to the second resistor R, a switch TP5 connected to the third resistor R, a switch TP4 connected to the fourth resistor R, a switch TP3 connected to the fifth resistor R, a switch TP2 connected to the sixth resistor R, a switch TP1 connected to the seventh resistor R, and a switch TP0 connected to the eighth resistor R. Among them, GP<7> controls the conduction or cutoff of switch TP7, GP<6> controls the conduction or cutoff of switch TP6, GP<5> controls the conduction or cutoff of switch TP5, GP<4> controls the conduction or cutoff of switch TP4, GP<3> controls the conduction or cutoff of switch TP3, GP<2> controls the conduction or cutoff of switch TP2, GP<1> controls the conduction or cutoff of switch TP1, and GP<0> controls the conduction or cutoff of switch TP0.

[0166] For example, when N is equal to 8, the resistor array RA2 includes eight resistors R, a switch TN7 connected to the first resistor R, a switch TN6 connected to the second resistor R, a switch TN5 connected to the third resistor R, a switch TP4 connected to the fourth resistor R, a switch TN3 connected to the fifth resistor R, a switch TN2 connected to the sixth resistor R, a switch TN1 connected to the seventh resistor R, and a switch TN0 connected to the eighth resistor R. Among them, GP<7> controls the conduction or cut-off of the switch TN7, GP<6> controls the conduction or cut-off of the switch TN6, GP<5> controls the conduction or cut-off of the switch TN5, GP<4> controls the conduction or cut-off of the switch TN4, GP<3> controls the conduction or cut-off of the switch TN3, GP<2> controls the conduction or cut-off of the switch TN2, GP<1> controls the conduction or cut-off of the switch TN1, and GP<0> controls the conduction or cut-off of the switch TN0.

[0167] For example, when GP<7:0> is 0111 1111, GP<7> controls the switches TP7 and TN7 to conduct, GP<6> controls the switches TP6 and TN6 to cut off, GP<5> controls the switches TP5 and TN5 to cut off, GP<4> controls the switches TP4 and TN4 to cut off, GP<3> controls the switches TP3 and TN3 to cut off, GP<2> controls the switches TP2 and TN2 to cut off, GP<1> controls the switches TP1 and TN1 to cut off, and GP<0> controls the switches TP0 and TN0 to cut off. It should be noted that Figure 5 it is described by taking M = 2 and N = 7 as examples.

[0168] The following combines Figure 5 , taking TH<2:0> as 111 and GP<7:0> as 0111 1111 as examples, to describe the working process of the voltage threshold generation unit 21.

[0169] GP<7> controls the conduction of switches TP7 and TN7, GP<6> controls the cutoff of switches TP6 and TN6, GP<5> controls the cutoff of switches TP5 and TN5, GP<4> controls the cutoff of switches TP4 and TN4, GP<3> controls the cutoff of switches TP3 and TN3, GP<2> controls the cutoff of switches TP2 and TN2, GP<1> controls the cutoff of switches TP1 and TN1, and GP<0> controls the cutoff of switches TP0 and TN0. The output vthp is the same as the voltage at node vp7, the output vthn is the same as the voltage at node vn7, and the output vcm_out is equal to (vthp + vthn) / 2; when the input of the first-stage operational amplifier 211, vcm_out, is the same as vcm, the currents flowing through NMOS transistors M3 and M4 are the same; when the input vcm_out is greater than vcm, the current flowing through NMOS transistor M3 will increase. Since there is no other path for the current to flow from PMOS transistor M1 through NMOS transistor M3, the current flowing through PMOS transistor M1 is the same as the current flowing through NMOS transistor M3, and the current flowing through PMOS transistor M1 also increases, resulting in a decrease in the drain voltage of PMOS transistor M1, the drain voltage of NMOS transistor M3, and the gate voltage of PMOS transistor M2; the decrease in the gate voltage of PMOS transistor M2 further causes an increase in the current flowing through PMOS transistor M2, which in turn causes an increase in the drain voltage of PMOS transistor M2 and the gate voltage of PMOS transistor M6; the increase in the gate voltage of PMOS transistor M6 further causes a decrease in the current flowing through PMOS transistor M6, resulting in a decrease in the drain voltage of PMOS transistor M6, further causing a decrease in vcm_out, and finally reducing vcm_out to be consistent with the input reference voltage value vcm, and the above working process stops.

[0170] When the input vcm_out is less than vcm, the current flowing through NMOS transistor M3 will decrease. Since there is no other path for the current to flow from PMOS transistor M1 through NMOS transistor M3, the current flowing through PMOS transistor M1 is the same as the current flowing through NMOS transistor M3, and the current flowing through PMOS transistor M1 also decreases, resulting in an increase in the drain voltage of PMOS transistor M1, the drain voltage of NMOS transistor M3, and the gate voltage of PMOS transistor M2; the increase in the gate voltage of PMOS transistor M2 further causes a decrease in the current flowing through PMOS transistor M2, which in turn causes a decrease in the drain voltage of PMOS transistor M2 and the gate voltage of PMOS transistor M6; the decrease in the gate voltage of PMOS transistor M6 further causes an increase in the current flowing through PMOS transistor M6, resulting in an increase in the drain voltage of PMOS transistor M6, further causing an increase in vcm_out, and finally increasing vcm_out to be consistent with the input reference voltage value vcm, and the above working process stops.

[0171] In Figure 5 the provided voltage threshold generation unit 21, the decoder 210 processes the adjustable symbol sequence TH <m:0>Perform decoding processing to obtain the switch control sequence GP <n:0>, and then control the sequence GP through the switch <n:0>The second-stage operational amplifier 212 outputs an adjustable voltage threshold, which can reduce the number of input control words, thereby reducing the number of pins of the test circuit. In the present application, if there is no decoder 210, then in order for the second-stage operational amplifier 212 to output an adjustable voltage threshold, when N is equal to 7, 8 pins are required to provide 8 control words to the second-stage operational amplifier 212 to enable the second-stage operational amplifier 212 to output an adjustable voltage threshold. However, in the present application, due to the adoption of the decoder 210, an adjustable symbol sequence TH can be input to the decoder 210 through 3 pins <m:0>, so that the second-stage operational amplifier 212 outputs an adjustable voltage threshold.

[0172] In Figure 5 the embodiment, since the adjustable symbol sequence TH <m:0>It can be adjusted, so the adjustable symbol sequence can be flexibly configured, enabling the test circuit provided in this application to adapt to SerDes in different working scenarios. For example, it can include working scenarios applying PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), or working scenarios applying USB (Universal Serial Bus).

[0173] In addition, in Figure 5 the provided voltage threshold generation unit 21, for example, an 8-level adjustable voltage threshold (including vthp and vthn) can be generated. Through the negative feedback structure of the second-stage operational amplifier 212, the feedback voltage value vcm_out is made equal to the reference voltage value vcm. Then, through the series voltage division of the resistor R in the resistor array RA1 and the resistor array RA2, it is ensured that (vpj + vnj) / 2 = vcm always holds (where j is an integer between 0 and 7). The beneficial effect brought by this is that the common-mode voltages of the inputs inn and inp are the same as the common-mode voltages of the voltage thresholds vthp and vthn, which is convenient for subsequent comparison. Compared with a simple resistor voltage division structure, that is, VDD is connected to a series of resistor arrays to the ground terminal, the resistance values need to be precisely selected to ensure that the common-mode level of the output threshold level is the same as vcm. At the same time, the fluctuation of VDD will directly affect the common-mode level, increasing the error. The voltage threshold generation unit 21 adopts an amplifier negative feedback structure (the two-stage amplifier has one output terminal and two input terminals: the output terminal is the center of the two resistor arrays; the input terminals include an inverting input terminal and a non-inverting input terminal. The inverting input terminal is the gate of M3, and the non-inverting input terminal is the gate of M4. The output of the two-stage amplifier is connected to the inverting input terminal, forming negative feedback, that is, the output result will be fed back to the input. When the output vcm_out and vcm are not the same, it will affect the input of the M3 gate, and then further affect the output vcm_out until vcm_out and vcm are the same), making the output threshold level and the common-mode point more stable, and the resistance value selection of the resistors in the resistor array more flexible.

[0174] In a possible design, the detection circuit can also include an amplitude determination unit. The amplitude determination unit is connected to the voltage threshold generation unit 21, and the amplitude determination unit is used to determine the difference between vthp and vthn as the amplitude of the differential signal.

[0175] In this application, the detection circuit can determine whether the differential signal is a valid signal and determine the amplitude of the differential signal, enabling the detection circuit to meet the detection requirements for differential signals in the PCIe4.0 protocol, and further providing an amplitude reference for the equalization circuit in the receiving end, improving the working efficiency of SerDes.

[0176] Based on the above embodiments, the pre-comparison unit 22 provided by the present application will be described below in conjunction with Figure 6 The pre-comparison unit 22 provided by the present application will be described.

[0177] Figure 6 FIG. is a schematic structural diagram of the pre-comparison unit 22 provided by the present application. As Figure 6 shown, the pre-comparison unit 22 includes: a first amplifier 221 and a second amplifier 222.

[0178] The first amplifier 221 and the second amplifier 222 are respectively connected to the voltage threshold generation unit 21.

[0179] The first amplifier 221 is configured to output a first voltage difference outn1 and a first common-mode voltage vcmn1 according to the first signal inp, the second signal inp, and vthp and vthn in the adjustable voltage threshold.

[0180] The second amplifier 222 is configured to output a second voltage difference outn2 and a second common-mode voltage vcmn2 according to the first signal inp, the second signal inp, and vthp and vthn in the adjustable voltage threshold.

[0181] The first comparison result includes: the first voltage difference outn1, the first common-mode voltage vcmn1, the second voltage difference outn2, and the second common-mode voltage vcmn2.

[0182] In a possible design, the structures of the first amplifier 221 and the second amplifier 222 are the same;

[0183] The first amplifier 221 includes: a resistor R2, a resistor R3, a resistor R4, a resistor R5, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, an NMOS transistor M12, and an NMOS transistor M13; wherein,

[0184] The series-connected resistor R2 and resistor R4 are in parallel with the series-connected resistor R3 and resistor R5; the resistor R2 and resistor R3 receive the first voltage VDD, and the first common-mode voltage vcmn1 is output between the resistor R4 and resistor R5;

[0185] The source of the NMOS transistor M8 is connected to the source of the NMOS transistor M9, and the source of the NMOS transistor M11 is connected to the source of the NMOS transistor M12;

[0186] The gate of NMOS transistor M10 receives the second voltage Vb, the source of NMOS transistor M10 is grounded, the drain of NMOS transistor M10 is connected between the source of NMOS transistor M8 and the source of NMOS transistor M9, the gate of NMOS transistor M8 receives the minimum adjustable voltage threshold, the drain of NMOS transistor M8 is connected to the drain of NMOS transistor M11, as well as resistor R2 and resistor R4, the gate of NMOS transistor M9 receives the second signal, the drain of NMOS transistor M9 is connected to the drain of NMOS transistor M12, as well as resistor R3 and resistor R5, and the drain of NMOS transistor M9 outputs the first voltage difference outn1;

[0187] The gate of NMOS transistor M13 is connected to the second voltage Vb, the source of NMOS transistor M13 is grounded, the drain of NMOS transistor M13 is connected between the source of NMOS transistor M11 and the source of NMOS transistor M12, the gate of NMOS transistor M11 receives the first signal, and the drain of NMOS transistor M12 is connected to the drain of NMOS transistor M9, as well as resistor R3 and resistor R5.

[0188] Taking the first amplifier 221 (AMP1) as an example below, the working principle of AMP1 will be described.

[0189] For AMP1, the gate of NMOS transistor M9 receives inp, the gate of NMOS transistor M11 receives inn, and the working principle of AMP1 is divided into the following two cases (Case 11 and Case 12).

[0190] In Case 11, if the maximum voltage value and the minimum voltage value of the differential signal (including inp and inn) are between vthp and the maximum adjustable voltage threshold vthn, then the voltage value of inp input to the first stage is always greater than vthn, and the voltage value of inn is always less than vthp. Therefore, the current flowing through NMOS transistor M8 and NMOS transistor M11 is always less than the current flowing through NMOS transistor M9 and NMOS transistor M12. Therefore, the first difference voltage outp1 is always greater than the first difference voltage outn1, and the first common-mode voltage vcmn1 is equal to (outp + outn) / 2.

[0191] For Case 11, the first difference voltage outn1 is always less than the first common-mode voltage vcmn1. Specifically, please refer to Figure 7 the embodiment.

[0192] Case 12, the maximum voltage value and the minimum voltage value of the differential signals (including inp and inn) exceed vthp and vthn. When the voltage value of inp is less than vthn and the voltage value of the second signal inn is greater than vthp, the current flowing through NMOS transistor M8 and NMOS transistor M11 is always less than the current flowing through NMOS transistor M9 and NMOS transistor M12, and the first differential voltage outp1 is greater than the first differential voltage outn1;

[0193] When the voltage value of inp is greater than vthn and the voltage value of the second signal inn is less than vthp, the current flowing through NMOS transistor M8 and NMOS transistor M11 is always greater than the current flowing through NMOS transistor M9 and NMOS transistor M12, the first differential voltage outp1 is less than the first differential voltage outn1, and the first common-mode voltage vcmn1 is equal to (outp + outn) / 2. Specifically, please refer to Figure 8 the embodiment.

[0194] It should be noted that since the structures of AMP2 and AMP1 are the same, the operating principles of AMP2 and AMP1 are similar. The difference between AMP2 and AMP1 is that the phases of the differential voltage and the common-mode voltage output by AMP2 are opposite to those of the differential voltage and the common-mode voltage output by AMP1. In this embodiment, the input voltage and output voltage of AMP2 will not be described.

[0195] Next, taking the first amplifier 221 (AMP1) as an example, the working process of AMP1 will be described.

[0196] The current flowing through NMOS transistor M8 is I8, the current flowing through NMOS transistor M9 is I9, the current flowing through NMOS transistor M11 is I11, and the current flowing through NMOS transistor M12 is I12. outp1 = VDD - R2*(I8 + I11), the output outn1 = VDD - R3*(I9 + I12), and the resistance values of resistor R2 and resistor R3 are the same.

[0197] Case 11: When the maximum voltage value and the minimum voltage value of the differential signals (including inp and inn) are between vthp and the maximum adjustable voltage threshold vthn, that is, the gate voltage of NMOS transistor M8 is less than the gate voltage of NMOS transistor M9, that is, the gate voltage of NMOS transistor M11 is less than the gate voltage of NMOS transistor M12, then I8 is less than I9, I11 is less than I12, then (I8 + I11) is less than (I9 + I12). According to the above outp1 and outn1 calculation formulas, it can be obtained that the first differential voltage outp1 is always greater than the first differential voltage outn1.

[0198] Case 12: The maximum and minimum voltage values of the differential signals (including inp and inn) exceed vthp and vthn. When the voltage value of inp is less than vthn and the voltage value of inn is greater than vthp, that is, the gate voltage of NMOS transistor M8 is greater than the gate voltage of NMOS transistor M9, that is, the gate voltage of NMOS transistor M11 is greater than the gate voltage of NMOS transistor M12, then I8 is greater than I9, I11 is greater than I12, so (I8 + I11) is greater than (I9 + I12). According to the above outp1 and outn1 calculation formulas, the first differential voltage outp1 is less than the first differential voltage outn1;

[0199] When the voltage value of inp is greater than vthn and the voltage value of the second signal inn is less than vthp, that is, the gate voltage of NMOS transistor M8 is less than the gate voltage of NMOS transistor M9, that is, the gate voltage of NMOS transistor M11 is less than the gate voltage of NMOS transistor M12, then I8 is less than I9, I11 is less than I12, so (I8 + I11) is less than (I9 + I12). According to the above outp1 and outn1 calculation formulas, the first differential voltage outp1 is greater than the first differential voltage outn1.

[0200] Figure 7 Schematic diagram of the relationship between inp, inn, vthp, and vthn in AMP1 provided by this application Figure 1 As Figure 7 shown, the maximum and minimum voltage values of the differential signals (including inp and inn) are between vthp and vthn, and the first common-mode voltage vcmn1 is equal to half of the sum of the first differential voltage outp1 and the first differential voltage outn1.

[0201] Figure 8 Schematic diagram of the relationship between inp, inn, vthp, and vthn in AMP1 provided by this application Figure 2 As Figure 8 shown, the maximum and minimum voltage values of the differential signals (including inp and inn) exceed vthp and vthn, and the first common-mode voltage vcmn1 is equal to half of the sum of the first differential voltage outp1 and the first differential voltage outn1.

[0202] Figure 9 Schematic diagram of the relationship between outn1, outn2, vcmn1, and vcmn2 in the pre-comparison unit 22 provided by this application Figure 1 As Figure 9 As shown, the first common-mode voltage vcmn1 is equal to the second common-mode voltage vcmn2. The maximum voltage value and the minimum voltage value of the differential signal (including inp and inn) are between vthp and vthn. The first difference voltage outn1 and the second difference voltage outn2 are always less than the first common-mode voltage vcmn1.

[0203] Figure 10 Schematic diagram of the relationship among outn1, outn2, vcmn1, and vcmn2 in the pre-comparison unit 22 provided by this application Figure 2 As Figure 10 shown, the first common-mode voltage vcmn1 is equal to the second common-mode voltage vcmn2. When the maximum voltage value and the minimum voltage value of the differential signal (including inp and inn) exceed vthp and vthn, either the first difference voltage outn1 or the second difference voltage outn2 is always greater than the first common-mode voltage vcmn1.

[0204] Figure 11 Schematic diagram of the structure of the detection circuit for the differential signal provided by this application Figure 2 As Figure 11 shown, the rectification comparison unit 23 includes: a rectification module 231 and a comparator module 232.

[0205] Among them, the rectification module 231 is respectively connected to the pre-comparison unit 22 and the comparator module 232, and the comparator module 232 is also connected to the detection processing unit 24.

[0206] The rectification module 231 is used to rectify the first comparison result and provide the first rectification signal rec_p and the second rectification signal rec_n to the comparator module 232;

[0207] The comparator module 232 is used to compare the first voltage value of the first rectification signal rec_p and the second voltage value of the second rectification signal rec_n, and provide the signal to be detected to the detection processing unit 24.

[0208] Figure 12 Schematic diagram of the structure of the rectification module 231 provided by this application. As Figure 12 shown, the rectification module 231 includes: a first rectifier 2311 and a second rectifier 2312;

[0209] The first rectifier 2311 is used to output the second rectification signal rec_n according to the first common-mode voltage vcmn1 and the second common-mode voltage vcmn2 in the first comparison result;

[0210] The second rectifier 2312 is used to output the first rectification signal rec_p according to the first voltage difference outn1 and the second voltage difference outn2 in the first comparison result.

[0211] The second rectified signal rec_n and the first rectified signal rec_p are used to determine whether the differential signal is a valid signal.

[0212] In a possible design, the first rectifier 2311 includes: a resistor R6, a resistor R7, an NMOS transistor M14, an NMOS transistor M15, and an NMOS transistor M16; among them,

[0213] The resistor R6 and the resistor R7 are connected, and the resistor R6 and the resistor R7 receive the first voltage VDD;

[0214] The source of the NMOS transistor M14 is connected to the source of the NMOS transistor M15;

[0215] The drain of the NMOS transistor M14 is connected to the resistor R6, and the gate of the NMOS transistor M14 receives the first common-mode voltage vcmn1;

[0216] The drain of the NMOS transistor M15 is connected to the resistor R7, and the gate of the NMOS transistor M17 receives the second common-mode voltage vcmn2;

[0217] The gate of the NMOS transistor M16 receives the second voltage Vb, the source of the NMOS transistor M16 is grounded, the drain of the NMOS transistor M16 is connected between the source of the NMOS transistor M14 and the source of the NMOS transistor M15, and the second rectified signal is output between the source of the NMOS transistor M14 and the source of the NMOS transistor M15.

[0218] In a possible design, the structures of the first rectifier 2311 and the second rectifier 2312 are the same.

[0219] Different from the first rectifier 2311, in the second rectifier 2312, the gate of the NMOS transistor M14 receives the first differential voltage outn1, and the gate of the NMOS transistor M15 receives the second differential voltage outn2.

[0220] Figure 12 The working principle of the shown rectification module 231 is divided into the following two cases (Case 21 and Case 22).

[0221] Case 21, when the maximum voltage value and the minimum voltage value of the differential signal are between vthp and vthn, since the first differential voltage outn1 and the first differential voltage outn2 are always less than the first common-mode voltage vcmn1, the sum of the resistance values of the NMOS transistor M14, the resistor R6, the NMOS transistor M15, and the resistor R7 in the first rectifier 2311 is less than the sum of the resistance values of the NMOS transistor M14, the resistor R6, the NMOS transistor M15, and the resistor R7 in the second rectifier 2312. Therefore, the voltage value of the second rectified signal rec_n is greater than the voltage value of the first rectified signal rec_p.

[0222] Case 22, when the maximum and minimum values of the differential signal exceed vthp and vthn, since the first differential voltage outn1 and the second differential voltage outn2 alternately exceed the first common-mode voltage vcmn1, the sum of the resistance values of M14, resistor R6, NMOS transistor M15, and resistor R7 in the first rectifier 2311 is greater than the sum of the resistance values of M14, resistor R6, NMOS transistor M15, and resistor R7 in the second rectifier 2312. Therefore, the voltage value of the second rectified signal rec_n is less than the voltage value of the first rectified signal rec_p.

[0223] Taking the first rectifier 2311 as an example below, the working process of the first rectifier 2311 will be described.

[0224] Assume that the current flowing through NMOS transistor M16 is I16, the equivalent resistance of NMOS transistor M14 is RM14, the equivalent resistance of NMOS transistor M15 is RM15, and the output voltage rec_n = VDD - I16 * ((R6 + RM14) / / (R7 + RM15)). When the gate voltages of NMOS transistors M14 and M15 are high, RM14 and RM15 are small, resulting in a higher rec_n; when the gate voltages of M14 and M15 are low, RM14 and RM15 are large, resulting in a lower rec_n.

[0225] Figure 13 The structural schematic diagram of the comparator module 232 provided by the present application is shown as Figure 13 shown. The comparator module 232 includes: a first comparator 2321 and a second comparator 2322.

[0226] The first comparator 2321 is respectively connected to the second comparator 2322 and the rectification module 231.

[0227] The first comparator 2321 is configured to compare and process the first voltage value and the second voltage value, and provide a second comparison result to the second comparator 2322;

[0228] The second comparator 2322 is configured to convert and process the second comparison result, and provide a signal to be detected to the detection processing unit 24.

[0229] The first comparator 2321 is configured to compare and process the first voltage value and the second voltage value to obtain a second comparison result. When the first voltage value is greater than the second voltage value, the second comparison result indicates that the second-stage comparator outputs a high level; when the first voltage value is less than the second voltage value, the second comparison result indicates that the second-stage comparator outputs a low level.

[0230] In a possible design, the first comparator 2321 includes: an NMOS transistor M17, an NMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20, a PMOS transistor M21, a PMOS transistor M22, and a PMOS transistor M23;

[0231] The source of the NMOS transistor M17 is connected to the source of the NMOS transistor M18, the sources of the PMOS transistor M20, the PMOS transistor M21, the PMOS transistor M22, and the PMOS transistor M23 are connected, the drain of the PMOS transistor M20 is connected to the drain of the PMOS transistor M21, and the drain of the PMOS transistor M22 is connected to the drain of the PMOS transistor M23;

[0232] The gate of the PMOS transistor M20 receives a third voltage Vb1, and the gate of the PMOS transistor M21 is connected between the drains of the PMOS transistor M22 and the PMOS transistor M23;

[0233] The gate of the PMOS transistor M23 receives a third voltage Vb1, and the gate of the PMOS transistor M22 is connected between the drains of the PMOS transistor M20 and the PMOS transistor M21;

[0234] The gate of the NMOS transistor M17 receives a second rectified signal, and the drain of the NMOS transistor M17 is connected between the drains of the PMOS transistor M20 and the PMOS transistor M21;

[0235] The gate of the NMOS transistor M18 receives a first rectified signal, and the drain of the NMOS transistor M18 is connected between the drains of the PMOS transistor M22 and the PMOS transistor M23;

[0236] The gate of the NMOS transistor M19 receives a fourth voltage Vb2, the source of the NMOS transistor M19 is grounded, and the drain of the NMOS transistor M19 is connected between the sources of the NMOS transistor M17 and the NMOS transistor M18.

[0237] In a possible design, the second comparator 2322 includes: a PMOS transistor M24, a PMOS transistor M25, an NMOS transistor M26, an NMOS transistor M27, an NMOS transistor M28, and an NMOS transistor M29;

[0238] The source of the PMOS transistor M24 is connected to the source of the PMOS transistor M25, and the sources of the PMOS transistor M24 and the PMOS transistor M25 receive a first voltage VDD;

[0239] The sources of the NMOS transistor M26, the NMOS transistor M27, the NMOS transistor M28, and the NMOS transistor M29 are grounded;

[0240] The gate of PMOS transistor M24 is connected between the drains of PMOS transistors M20 and M21. The drain of PMOS transistor M24 is connected to the drains of NMOS transistors M27 and M26. The gate of NMOS transistor M27 is connected to the drain of NMOS transistor M28 and the drains and gates of NMOS transistors M29;

[0241] The gate of PMOS transistor M25 is connected between the drains of PMOS transistors M23 and M22. The drain of PMOS transistor M25 is connected to the drain of NMOS transistor M28 and the gates and drains of NMOS transistors M29. The gate of NMOS transistor M28 is connected to NMOS transistor M27 and the drains and gates of NMOS transistors M26;

[0242] The signal to be detected, Voutp, is output between the drain of PMOS transistor M25 and the drain of NMOS transistor M28.

[0243] The working process of the first comparator 2321 will be described below.

[0244] When the input voltage rec_n is greater than rec_p, the gate voltage of NMOS transistor M17 is greater than the gate voltage of NMOS transistor M18. The current flowing through NMOS transistor M17 is greater than the current flowing through NMOS transistor M18. The voltage of node OP drops faster than that of node ON, that is, the gate voltage of PMOS transistor M21 is greater than the gate voltage of PMOS transistor M22, causing PMOS transistor M21 to approach the cut-off region and PMOS transistor M22 to conduct more deeply, further pulling down the voltage of node OP and raising the voltage of node ON at the same time, making the voltage of ON output by the first comparator 2321 greater than the voltage of OP. When the input voltage rec_n is less than rec_p, the gate voltage of NMOS transistor M17 is less than the gate voltage of NMOS transistor M18. The current flowing through NMOS transistor M17 is less than the current flowing through NMOS transistor M18. The voltage of node OP drops more slowly than that of node ON, that is, the gate voltage of PMOS transistor M22 is less than the gate voltage of PMOS transistor M21, causing PMOS transistor M22 to approach the cut-off region and PMOS transistor M21 to conduct more deeply, further raising the voltage of node OP and pulling down the voltage of node ON at the same time, making the voltage of ON output by the first comparator 2321 less than the voltage of OP. Finally, the working process of the second comparator 2322 will be described.

[0245] Similar to the principle of the first comparator, when the voltage of OP is greater than the voltage of ON, that is, the gate voltage of PMOS transistor M24 is greater than that of PMOS transistor M25, the current flowing through PMOS transistor M24 is smaller than the current flowing through PMOS transistor M25. The voltage of node Voutp rises faster than that of node Voutn, that is, the gate voltage of NMOS transistor M27 is greater than that of NMOS transistor M28, causing NMOS transistor M28 to approach the cut-off region and the conduction degree of NMOS transistor M27 to deepen, further pulling the voltage of node Voutn to a low level and raising the voltage of node Voutp to a high level at the same time. When the voltage of OP is less than the voltage of ON, that is, the gate voltage of PMOS transistor M24 is less than that of PMOS transistor M25, the current flowing through PMOS transistor M24 is greater than the current flowing through PMOS transistor M25. The voltage of node Voutn rises faster than that of node Voutp, that is, the gate voltage of NMOS transistor M28 is greater than that of NMOS transistor M27, causing NMOS transistor M27 to approach the cut-off region and the conduction degree of NMOS transistor M28 to deepen, further pulling the voltage of node Voutp to a low level and raising the voltage of node Voutn to a high level at the same time.

[0246] In this application, the reference voltage value is the voltage output by the first preset power supply. The reference voltage value is used to generate an adjustable voltage threshold in combination with the adjustable symbol sequence.

[0247] The first voltage VDD is the voltage output by the second preset power supply. The first voltage VDD is used to drive the operation of related devices. For example, in Figure 5 it is used to drive PMOS transistors M1, M2, and M6 to operate.

[0248] The second voltage Vb is the voltage output by the third preset power supply. The second voltage Vb is used to provide a bias voltage to related devices to ensure the normal operation of the circuit where the related devices are located. For example, in Figure 6 the second voltage Vb is provided to NMOS transistor M10 to ensure the normal operation of AMP1 and AMP2.

[0249] The third voltage Vb1 is the voltage output by the fourth preset power supply, and the fourth voltage Vb2 is the voltage output by the fifth preset power supply. The third voltage Vb1 and the fourth voltage Vb2 are used to provide a bias voltage to related devices to ensure the normal operation of the circuit where the related devices are located. For example, in Figure 13 the third voltage Vb1 provides a bias voltage to PMOS transistors M20 and M23, and the fourth voltage Vb2 provides a bias voltage to NMOS transistor M19 to ensure the normal operation of the first comparator 2321.

[0250] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0251] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A detection circuit for differential signals, characterized in that, Comprising: a voltage threshold generation unit, a pre-comparison unit, a rectification comparison unit, and a detection processing unit; The voltage threshold generation unit includes: a decoder, a first-stage operational amplifier, and a second-stage operational amplifier; wherein, The decoder is configured to perform decoding processing on the input adjustable symbol sequence to obtain a switch control sequence; The first-stage operational amplifier is configured to amplify the feedback voltage provided by the second-stage operational amplifier and the input reference voltage value to obtain an amplified reference voltage value; The second-stage operational amplifier is configured to output an adjustable voltage threshold according to the amplified reference voltage value and the switch control sequence, and provide a feedback voltage to the first-stage operational amplifier; the pre-comparison unit is configured to compare the voltage value of the input differential signal with the adjustable voltage threshold, and provide a first comparison result to the rectification comparison unit; The rectification comparison unit is configured to perform rectification and comparison processing on the first comparison result, and provide a signal to be detected to the detection processing unit; The detection processing unit is configured to determine that the differential signal is a valid signal when the signal to be detected is detected as a high level; when the signal to be detected is detected as a low level, subtract a preset value from the adjustable symbol sequence, and provide the adjustable symbol sequence after subtracting the preset value to the voltage threshold generation unit to obtain a new signal to be detected.

2. The circuit according to claim 1, wherein The first-stage operational amplifier includes: PMOS transistor M1, PMOS transistor M2, NMOS transistor M3, NMOS transistor M4, and NMOS transistor M5; The source of PMOS transistor M1 is connected to the source of PMOS transistor M2, the gate of PMOS transistor M1 is connected to the gate of PMOS transistor M2, and the source of NMOS transistor M3 is connected to the source of NMOS transistor M4; The sources of PMOS transistor M1 and PMOS transistor M2 receive a first voltage; The drain of NMOS transistor M3 is respectively connected to the drain and gate of PMOS transistor M1, and the gate of NMOS transistor M3 is connected to the first output terminal of the second-stage operational amplifier; The drain of NMOS transistor M4 is respectively connected to the drain of PMOS transistor M2 and the input terminal of the second-stage operational amplifier, and the gate of NMOS transistor M4 receives the reference voltage value; The gate of NMOS transistor M5 receives a second voltage, the source of NMOS transistor M5 is grounded, and the drain of NMOS transistor M5 is connected between the sources of NMOS transistor M3 and NMOS transistor M4.

3. The circuit according to claim 2, wherein The second-stage operational amplifier includes: PMOS transistor M6, NMOS transistor M7, resistor Rc, capacitor Cc, resistor array RA1, and resistor array RA2; The source of PMOS transistor M6 receives a first voltage; The drain of PMOS transistor M6 is connected to the drain of NMOS transistor M7 through the series-connected resistor array RA1 and resistor array RA2, the source of NMOS transistor M7 is grounded, and the gate of NMOS transistor M7 receives a second voltage; The gate of the PMOS transistor M6 is connected to the first-stage operational amplifier and is also connected to the drain of the PMOS transistor M6 through the series-connected resistor Rc and capacitor Cc; The resistor array RA1 outputs the maximum adjustable voltage threshold among the adjustable voltage thresholds, and the resistor array RA2 outputs the minimum adjustable voltage threshold among the adjustable voltage thresholds; The gate of the NMOS transistor M3 is connected between the resistor array RA1 and the resistor array RA2.

4. The circuit according to claim 3, characterized in that, The resistor arrays RA1 and RA2 have the same structure; The resistor array RA1 includes N resistors connected in series and switches connected to each resistor.

5. The circuit according to any one of claims 1-4, characterized in that, The differential signal includes: a first signal and a second signal; The adjustable voltage threshold includes: a maximum adjustable voltage threshold and a minimum adjustable voltage threshold; The first comparison result includes: a first voltage difference, a first common-mode voltage, a second voltage difference, and a second common-mode voltage; The pre-comparison unit includes: a first amplifier and a second amplifier; The first amplifier is configured to output the first voltage difference and the first common-mode voltage according to the first signal, the second signal, and the maximum adjustable voltage threshold and the minimum adjustable voltage threshold among the adjustable voltage thresholds; The second amplifier is configured to output the second voltage difference and the second common-mode voltage according to the first signal, the second signal, and the maximum adjustable voltage threshold and the minimum adjustable voltage threshold among the adjustable voltage thresholds.

6. The circuit according to claim 5, characterized in that, The first amplifier and the second amplifier have the same structure; The first amplifier includes: resistor R2, resistor R3, resistor R4, resistor R5, NMOS transistors M8, M9, M10, M11, M12, and M13; where The series-connected resistor R2 and resistor R4 are connected in parallel with the series-connected resistor R3 and resistor R5; the resistor R2 and resistor R3 receive a first voltage, and the first common-mode voltage is output between the resistor R4 and resistor R5; The source of the NMOS transistor M8 is connected to the source of the NMOS transistor M9, and the source of the NMOS transistor M11 is connected to the source of the NMOS transistor M12; The gate of the NMOS transistor M10 receives a second voltage, the source of the NMOS transistor M10 is grounded, the drain of the NMOS transistor M10 is connected between the source of the NMOS transistor M8 and the source of the NMOS transistor M9, the gate of the NMOS transistor M8 receives the minimum adjustable voltage threshold, the drain of the NMOS transistor M8 is respectively connected to the drain of the NMOS transistor M11 and the resistor R2 and resistor R4, the gate of the NMOS transistor M9 receives the second signal, and the drain of the NMOS transistor M9 outputs the first voltage difference; The gate of the NMOS transistor M13 is connected to the second voltage, the source of the NMOS transistor M13 is grounded, the drain of the NMOS transistor M13 is connected between the source of the NMOS transistor M11 and the source of the NMOS transistor M12, the gate of the NMOS transistor M11 receives the first signal, and the drain of the NMOS transistor M12 is respectively connected to the drain of the NMOS transistor M9, as well as the resistor R3 and the resistor R5.

7. The circuit according to any one of claims 1-4, characterized in that, The rectification and comparison unit includes: a rectification module and a comparator module; The rectification module is configured to rectify the first comparison result and provide a first rectified signal and a second rectified signal to the comparator module; The comparator module is configured to compare the first voltage value of the first rectified signal and the second voltage value of the second rectified signal and provide a signal to be detected to the detection processing unit.

8. The circuit according to claim 7, wherein The rectification module includes: a first rectifier and a second rectifier; The first rectifier is configured to output the second rectified signal according to the first common-mode voltage and the second common-mode voltage in the first comparison result; The second rectifier is configured to output the first rectified signal according to the first voltage difference and the second voltage difference in the first comparison result.

9. The circuit according to claim 8, wherein The first rectifier and the second rectifier have the same structure; The first rectifier includes: a resistor R6, a resistor R7, an NMOS transistor M14, an NMOS transistor M15, and an NMOS transistor M16; wherein, The resistor R6 and the resistor R7 are connected, and the resistor R6 and the resistor R7 receive a first voltage; The source of the NMOS transistor M14 and the source of the NMOS transistor M15 are connected; The drain of the NMOS transistor M14 is connected to the resistor R6, and the gate of the NMOS transistor M14 receives the first common-mode voltage; The drain of the NMOS transistor M15 is connected to the resistor R7, and the gate of the NMOS transistor M17 receives the second common-mode voltage; The gate of the NMOS transistor M16 receives a second voltage, the source of the NMOS transistor M16 is grounded, and the drain of the NMOS transistor M16 is connected between the source of the NMOS transistor M14 and the source of the NMOS transistor M15, and the second rectified signal is output between the source of the NMOS transistor M14 and the source of the NMOS transistor M15.

10. The circuit according to claim 7, characterized in that, The comparator module includes: a first comparator and a second comparator; The first comparator is configured to compare the first voltage value and the second voltage value and provide a second comparison result to the second comparator; The second comparator is configured to convert the second comparison result and provide the signal to be detected to the detection processing unit.

11. The circuit according to claim 10, characterized in that, The first comparator includes: an NMOS transistor M17, an NMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20, a PMOS transistor M21, a PMOS transistor M22, and a PMOS transistor M23; The source of the NMOS transistor M17 is connected to the source of the NMOS transistor M18, the sources of the PMOS transistors M20, M21, M22, and M23 are connected, the drain of the PMOS transistor M20 is connected to the drain of the PMOS transistor M21, and the drain of the PMOS transistor M22 is connected to the drain of the PMOS transistor M23; The gate of the PMOS transistor M20 receives the third voltage, and the gate of the PMOS transistor M21 is connected between the drains of the PMOS transistors M22 and M23; The gate of the PMOS transistor M23 receives the third voltage, and the gate of the PMOS transistor M22 is connected between the drains of the PMOS transistors M20 and M21; The gate of the NMOS transistor M17 receives the second rectified signal, and the drain of the NMOS transistor M17 is connected between the drains of the PMOS transistors M20 and M21; The gate of the NMOS transistor M18 receives the first rectified signal, and the drain of the NMOS transistor M18 is connected between the drains of the PMOS transistors M22 and M23; The gate of the NMOS transistor M19 receives the fourth voltage, the source of the NMOS transistor M19 is grounded, and the drain of the NMOS transistor M19 is connected between the sources of the NMOS transistors M17 and M18.

12. The circuit according to claim 11, wherein The second comparator includes: PMOS transistors M24, M25, NMOS transistors M26, M27, M28, and M29; The source of the PMOS transistor M24 is connected to the source of the PMOS transistor M25, and the sources of the PMOS transistors M24 and M25 receive the first voltage; The sources of the NMOS transistors M26, M27, M28, and M29 are grounded; The gate of the PMOS transistor M24 is connected between the drains of the PMOS transistors M20 and M21, the drain of the PMOS transistor M24 is connected to the drain of the NMOS transistor M27, and the gate of the NMOS transistor M27 is connected to the drains and gates of the NMOS transistors M28 and M29 respectively; The gate of the PMOS transistor M25 is connected between the drains of the PMOS transistors M23 and M22, the drain of the PMOS transistor M25 is connected between the drains of the NMOS transistors M28 and M29, and the gate of the NMOS transistor M28 is connected to the drain and gate of the NMOS transistor M26 and the drain of the NMOS transistor M27; The signal to be detected is output between the drain of the PMOS transistor M25 and the drain of the NMOS transistor M28.

13. A method for detecting differential signals, characterized in that, A detection circuit for the differential signal according to any one of claims 1 to 12; the method includes: Receiving a reference voltage value and an adjustable symbol sequence, Outputting an adjustable voltage threshold according to the reference voltage value and the adjustable symbol sequence; Receiving a differential signal; Outputting a first comparison result according to the differential signal and the adjustable voltage threshold; Rectifying and comparing the first comparison result to obtain a signal to be detected; If the signal to be detected is at a high level, determining that the differential signal is a valid signal; If the signal to be detected is at a low level, subtracting a preset value from the adjustable symbol sequence, and obtaining a new signal to be detected according to the adjustable symbol sequence after subtracting the preset value.

14. An electronic device, characterized in that, Including: The detection circuit for the differential signal according to any one of claims 1 to 12.

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