Testing Device, Testing System, and Testing Method for Keyboard Encoder

Abstract

An embodiment of the present invention discloses a test device, a test system, and a test method for a keyboard encoder. The test device for the keyboard encoder includes: a decoding unit that decodes a received test signal to generate a first signal; and a selection unit that selects corresponding sub-switches based on the first signal to generate a row selection signal and a column selection signal, so as to select the row input port and the column input port of the keyboard encoder to implement a function test. Through the combination of the decoding unit and the selection unit, it is possible to directly convert the test signal into a row selection signal and a column selection signal for the keyboard encoder by using a chip, thereby realizing the key selection of the keyboard encoder and implementing a function test. The test device occupies a small space and has a long service life, and has broad application prospects.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology. More specifically, it relates to a test device, a test system, and a test method for a keyboard encoder. Background Art

[0002] An encoder chip is a chip that can represent information with specific meanings as binary codes. A keyboard encoder can use the combination of the row input port and the column input port of the chip to simulate the key positions of the keyboard by receiving specific signals and outputting binary signals. Due to the particularity of this function, the test of the keyboard encoder also needs to consider the position combination function of the two ports, and the test device is different from that of a conventional encoder.

[0003] See Figure 1 As shown, the traditional keyboard encoder test device mainly consists of an FPGA (Field Programmable Gate Array) and relays. Usually, relays arranged in an array are used to simulate the key positions in the keyboard. Each relay has a row position and a column position, which are equivalent to the row coordinates and column coordinates of the keyboard key positions, and also correspond to the row input port and the column input port of the keyboard encoder. During the test, the FPGA is used to control the opening and closing of each relay in the relay array, and the key position signals represented by each relay are correspondingly input into the row input port and the column input port of the keyboard encoder. Traversing all relays completes the functional test of the keyboard encoder.

[0004] In the traditional solution, the relays are usually electromagnetic relays, and the suction is completed by the magnetic attraction force generated between the electromagnet core and the armature when energized. Obviously, if it works in the opening and closing state frequently for a long time, it is very likely to cause damage to the relay, thereby reducing production efficiency and increasing test costs and expenses. Especially for mass-produced keyboard encoders, they need to be tested before leaving the factory and in use, which will increase the damage rate of the relays and significantly increase the test cost; in addition, due to the large space occupied by the relay array, the requirements for the space environment conditions of the test device are also relatively high, thus increasing the complexity of the test work.

[0005] Therefore, it is necessary to provide a test device for a keyboard encoder that has low requirements for the environment and space conditions and low costs. Summary of the Invention

[0006] To solve the above problems, the present invention adopts the following technical solutions:

[0007] In a first aspect of the present invention, there is provided a test device for a keyboard encoder, including:

[0008] A decoding unit that decodes the received test signal to generate a first signal;

[0009] A selection unit, based on the control of the first signal, selects corresponding sub-switches to generate a row selection signal and a column selection signal, so as to select the row input port and the column input port of the keyboard encoder to implement function testing.

[0010] In some alternative embodiments, the decoding unit includes at least one decoder chip; the test signal is an N-bit binary signal, and the decoding unit decodes the test signal to generate a N 2-bit first signal, where one bit in the first signal is a valid bit, and N is a positive integer.

[0011] In some alternative embodiments, the selection unit includes: 2 N sub-switches connected in parallel.

[0012] Among the sub-switches of the selection unit, the sub-switch corresponding to the valid bit in the first signal is turned on to generate a pair of row selection signals and column selection signals, which are output to one of the N row input ports and one of the N column input ports of the keyboard encoder, so as to select a key coordinate to implement function testing.

[0013] In some alternative embodiments, the selection unit includes: at least one bilateral switch chip.

[0014] Wherein, each bilateral switch chip includes a plurality of sub-switches, and each sub-switch includes a control terminal, a first output terminal and a second output terminal. The control terminal is connected to a valid bit in the first signal, the first output terminal outputs a row selection signal, and the second output terminal outputs a column selection signal.

[0015] In some alternative embodiments, the decoding unit is a 4-line - 16-line decoder.

[0016] In some alternative embodiments, the selection unit includes 4 bilateral switch chips, and each bilateral switch chip includes 4 sub-switches.

[0017] In some alternative embodiments, the decoding unit is selected from one or more of the CC4514 type chip, CC4028 type chip, 74LS154 type chip, 74HC154 type chip and 74LS138 type chip; the bilateral switch chip is a CC4066 type chip.

[0018] In some alternative embodiments, it further includes:

[0019] A first communication interface, used to communicate with the test machine to receive the test signal from the test machine; and

[0020] A second communication interface, used to communicate with the keyboard encoder to output the row selection signal and the column selection signal to the keyboard encoder.

[0021] The second aspect of the present invention provides a test system, including: a test machine platform and a test device for a keyboard encoder according to the first aspect described above.

[0022] The test machine platform outputs test signals to the test device of the keyboard encoder in a predetermined timing sequence, so that the test device of the keyboard encoder generates a row selection signal and a column selection signal to select the row input port and the column input port of the keyboard encoder, thereby realizing functional testing.

[0023] The third aspect of the present invention provides a test method based on the test device of the keyboard encoder described above, including:

[0024] Outputting test signals to the test device of the keyboard encoder in a predetermined timing sequence, so that the test device of the keyboard encoder decodes the test signals and generates a row selection signal and a column selection signal to select the row input port and the column input port of the keyboard encoder to realize functional testing.

[0025] The beneficial effects of the present invention are as follows:

[0026] In view of the existing problems, the present invention provides a test device, a test system, and a test method for a keyboard encoder. The test device for the keyboard encoder includes a decoding unit and a selection unit. The decoding unit decodes the test signals, and based on the first signal generated by the decoding, the corresponding sub-switches are gated through the selection unit to generate a row selection signal and a column selection signal corresponding to the row input port and the column input port of the keyboard encoder to complete functional testing. The combination of the decoding unit and the selection unit has a high integration degree and occupies a small space, reducing the requirements for the test environment and space; in addition, the working life of the chip is much higher than that of the relay, thereby saving maintenance time and cost and improving the reliability and working efficiency of the device. Therefore, the test device and the test system have broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following further describes in detail the specific embodiments of the present invention with reference to the drawings.

[0028] Figure 1 Showing a schematic block diagram of a test device for a keyboard encoder in the prior art;

[0029] Figure 2 Showing a schematic block diagram of a test device for a keyboard encoder according to an embodiment of the present application;

[0030] Figure 3 Showing a schematic block diagram of a test system according to an embodiment of the present application;

[0031] Figure 4 Showing a schematic circuit diagram of a test device for a keyboard encoder according to an embodiment of the present application;

[0032] Figure 5a and 5b shows Figure 4 an enlarged view of the decoding unit in and its device truth table;

[0033] Figure 6 shows Figure 4 a schematic structural diagram of the selection unit in;

[0034] Figure 7 shows the device truth table of the keyboard encoder according to an embodiment of the present invention. Detailed implementation manners

[0035] To more clearly illustrate the present invention, the present invention will be further described below in conjunction with embodiments and drawings. Similar components in the drawings are denoted by the same or similar reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present invention.

[0036] Terms such as "having", "containing", "including", "comprising", etc. are open-ended, and they indicate the existence of the described structures, components or features, but do not exclude additional components or features.

[0037] It should be understood that the ordinal numbers first, second, etc. described in the specification are only for the sake of clear description, rather than for limiting the order of components, parts or assemblies, that is, the described first components, parts and assemblies and the second components, parts or assemblies can also be expressed as the second components, parts and assemblies and the first components, parts or assemblies.

[0038] As Figure 2 shown, an embodiment of the present invention provides a test device 10 for a keyboard encoder, including:

[0039] a decoding unit 101, which decodes the received test signal to generate a first signal;

[0040] a selection unit 103, which based on the first signal, gates the corresponding sub-switches to generate a row selection signal and a column selection signal, so as to select the row input port and the column input port of the keyboard encoder to implement a function test.

[0041] In this embodiment, the test device of the keyboard encoder includes a decoding unit and a selection unit. The decoding unit decodes the test signal, and based on the first signal generated by the decoding, the selection unit gates the corresponding sub-switches to generate a row selection signal and a column selection signal corresponding to the row input port and the column input port of the keyboard encoder to complete the function test. The combination of the decoding unit and the selection unit has a high integration degree, occupies a small space, and reduces the environmental requirements for testing; in addition, the working life of the chip is much higher than that of a relay, saving maintenance time and cost, and improving the reliability and working efficiency of the device.

[0042] To facilitate the understanding of the functions and structure of the test device, the application scenario of the test device for the keyboard encoder will be described below in conjunction with Figure 3 the overall block diagram of the shown test system.

[0043] Referring to Figure 3 as shown, the test system includes a test device 10 for the keyboard encoder and a test machine platform 20. Among them, the test machine platform 20 can be a local computer or a server. A plug-in for testing is loaded in the test machine platform 20, and when the plug-in is executed, it can cause the test machine platform 20 to send test signals to the test device 10 for the keyboard encoder in a predetermined time sequence. The number of the test signals usually depends on the number of bits at the input end of the decoding unit 101 of the test device 10 for the keyboard encoder. Of course, in design, the number of bits at the input end of the decoding unit 101 actually depends on the number of key positions represented by the row input port and the column input port of the keyboard encoder 30, so the number of test signals substantially depends on the number of key positions that the keyboard encoder 30 can represent.

[0044] The test device 10 for the keyboard encoder can be a test board integrated with a decoding unit 101 and a selection unit 103, such as integrating the decoding unit 101 and the selection unit 103 on a printed circuit board. In addition, in addition to the decoding unit 101 and the selection unit 103, the test device 10 can also include a first communication interface 105 and a second communication interface 107. The first communication interface 105 can be a socket, which communicates by connecting with the pins of the test machine platform 20 during testing. The second communication interface 107 can be an IC locking socket. During testing, the keyboard encoder 30 can be directly plugged into the IC locking socket and locked as the chip to be tested, so as to enable communication between the test device 10 for the keyboard encoder and the keyboard encoder 30, and transmit the row selection signal and the column selection signal generated by the test device 10 for the keyboard encoder to the corresponding row input port and column input port of the keyboard encoder 30. Those skilled in the art should understand that the present application does not aim to limit the specific forms of the first communication interface 105 and the second communication interface 107, as well as the specific communication methods between the first communication interface 105 and the test machine platform 20 and between the second communication interface 107 and the keyboard encoder 30, as long as they can transmit test signals, as well as row selection signals and column selection signals, and will not be elaborated here.

[0045] The structure and functions of the test device for the keyboard encoder according to the embodiments of the present application will be further explained below with specific examples.

[0046] Referring to Figure 4As shown, in this example, the decoding unit 101 is a 4-line - 16-line decoder, and the selection unit 103 includes 4 bilateral switch chips. More specifically, in this example, the 4-line - 16-line decoder is a CC4514 type chip, and the bilateral switch chip is a CC4066 type chip.

[0047] It should be noted that the specific types of decoders and chip models used in this example are intended to illustrate the working principle of the embodiments of the present application, and are not intended to limit the present application. In actual applications, those skilled in the art can select appropriate decoder types and specific chip models according to the number of row input ports and column input ports of the keyboard encoder, in accordance with the working principle and implementation method of this example. The present application will not elaborate further.

[0048] Combined with Figure 5a As shown, in this example, the decoding unit 101 includes 4 data input terminals DATA1, DATA2, DATA3, and DATA4; 16, that is, 2 4 output terminals S0, S1, ……, S14, and S15, and also includes an inhibit terminal INHIBIT and a power supply terminal V DD . Referring to Figure 5b the device truth table shown, when the inhibit terminal INHIBIT is at a low level of 0, the decoding unit 101 is effective. The data input terminals DATA4, DATA3, DATA2, and DATA1 form a 4-bit binary number "DCBA". Based on the specific values of this 4-bit binary signal, the corresponding output terminal (one of S0, S1, ……, S14, and S15) outputs a high level. For example, as Figure 5b shown, when the data input terminals DATA4, DATA3, DATA2, and DATA1 all input a low level of 0, the output terminal S0 outputs a high level of 1; when the data input terminals DATA4, DATA3, DATA2, and DATA1 input low levels of 0, 0, 0, and a high level of 1 respectively, the output terminal S1 outputs a high level of 1, and so on. The decoding unit 101 realizes the decoding function.

[0049] Continuing to refer to Figure 4 , the decoding unit 101 receives a 4-bit binary test signal and decodes it to generate a first signal, and this first signal includes 16 bits. According to the function of the decoding unit 101 described above, during testing, the data input terminals DATA4, DATA3, DATA2, and DATA1 receive test signals from the test machine. After the decoding unit 101 decodes the test signals, it outputs the first signal. Among them, only the output terminal corresponding to the specific value of the test signal outputs a high level.

[0050] Referring to Figure 4 and Figure 6As shown, in this example, the selection unit 103 includes four bidirectional switch chips 103-1, 103-2, 103-3, and 103-4. Each bidirectional switch chip includes four sub-switches SWA, SWB, SWC, and SWD. Each sub-switch includes a control terminal, a first output terminal, and a second output terminal. The control terminal receives a valid bit in the first signal. The first output terminal outputs a row selection signal, and the second output terminal outputs a column selection signal. That is, each bidirectional switch chip includes four control terminals CONTROLA, CONTROLB, CONTROLC, and CONTROLD; and eight output terminals I / O. Those skilled in the art can understand that I / O means that this pin can be used as either an input terminal or an output terminal. In this application, it is only used as an output terminal, so it is called the output terminal I / O herein.

[0051] Combined with Figure 6 As shown, taking the sub-switch SWB as an example, pin 5 of the bidirectional switch chip is the control terminal CONTROL B of the sub-switch SWB, and pins 3 and 4 are the first output terminal and the second output terminal respectively.

[0052] Similarly, pin 13 of the bidirectional switch chip corresponds to the control terminal CONTROL A of the sub-switch SWA, pin 6 of the bidirectional switch chip corresponds to the control terminal CONTROL C of the sub-switch SWC, and pin 12 of the bidirectional switch chip corresponds to the control terminal CONTROL D of the sub-switch SWD. Referring to Figure 4 It can be seen that taking the bidirectional switch chip 103-1 as an example, the output terminals S0, S1, S2, and S3 of the decoder unit 101 are respectively connected to the control terminals CONTROLA, CONTROLB, CONTROLC, and CONTROLD of the bidirectional switch chip 103-1. And so on, the 16 output terminals S0 to S15 of the decoding unit 101 are respectively input to all the control terminals of the bidirectional switch chips 103-1 to 103-4.

[0053] Continuing to refer to Figure 4 As shown, when the keyboard encoder 30 is inserted into the IC locking socket of the second communication interface 107, the keyboard encoder 30 communicates with the selection unit 103 according to the Figure 4 schematic diagram shown. Specifically, the first output terminal and the second output terminal of each sub-switch in each bidirectional switch chip are respectively connected to a pair of row input ports and column input ports of the keyboard encoder 30 in combination. Still taking the bidirectional switch chip 103-1 as an example, referring to Figure 4As shown, the first output terminal I / O and the second output terminal I / O of the sub-switch SWA of the bidirectional switch chip 103-1 are respectively connected to the row input port Y1 and the column input port X1 of the keyboard encoder 30. The first output terminal I / O and the second output terminal I / O of the sub-switch SWB of the bidirectional switch chip 103-1 are respectively connected to the row input port Y1 and the column input port X2 of the keyboard encoder 30. The first output terminal I / O and the second output terminal I / O of the sub-switch SWC of the bidirectional switch chip 103-1 are respectively connected to the row input port Y1 and the column input port X3 of the keyboard encoder 30. The first output terminal I / O and the second output terminal I / O of the sub-switch SWD of the bidirectional switch chip 103-1 are respectively connected to the row input port Y1 and the column input port X4 of the keyboard encoder 30.

[0054] For each sub-switch, when a high level is applied to the control terminal, the sub-switch conducts, and both output terminals of the sub-switch output a high level. Therefore, when the control terminal of the sub-switch is at a high level, a pair of row input port and column input port combinations corresponding to the sub-switch are selected. Thus, through the bidirectional switch chip 103-1, the selection operation of the input combinations of 4 representative key positions (i.e., Y1X1, Y1X2, Y1X3, Y1X4) of the keyboard encoder 30 can be achieved. Similarly, referring to Figure 4 As shown, each of the bidirectional switch chips 103-2, 103-3, and 103-4 corresponds to a combination of one row input port and 4 different column input ports. Therefore, all input combinations of the keyboard encoder with 4 row input ports and 4 column input ports can be selected through 4 bidirectional switch chips CC4066.

[0055] It should be noted that for a bidirectional switch, when the switch conducts, both ends other than the control terminal in the switch are usually at a high level, and only when both conduct can the selection of a pair of row input port and column input port be achieved. Therefore, the functions of the I / O terminals of each sub-switch in this application are equivalent. Thus, although Figure 4 pin 3 is used as the first output terminal and pin 4 is used as the second output terminal in [reference], in actual application, pin 4 can also be used as the first output terminal and pin 3 as the second output terminal. Therefore, the circuit schematic diagram of each bidirectional switch chip does not have to be limited to the connection method in Figure 4 [reference], as long as the 4 sub-switches can correspond to 4 pairs of row input port and column input port combinations, which will not be elaborated here.

[0056] It should be noted that based on the above functional description of the CC4066 type bilateral switch chip, the conduction control of each sub-switch is independent. It is equivalent to using 4 bilateral switch chips to independently select 16 combinations of row input ports and column input ports, which is equivalent to 16 sub-switches connected in parallel. Therefore, in principle, as long as a functional unit that can realize the function of bilateral switch parallel connection based on control terminal gating can be used as the selection unit in this application.

[0057] That is to say, optionally, this example can also be implemented in the following way: The selection unit includes 2 sub-switches connected in parallel. The sub-switch corresponding to the valid bit (high level) in the first signal in the selection unit is turned on to generate a pair of row selection signals and column selection signals and output them to one of the 4 row input ports and one of the 4 column input ports of the keyboard encoder to select a key coordinate to complete the function test. 4 During the test process, continue to refer to the illustration. Assume that the test signal input by the test machine to the decoding unit 101 is "0001". The signal path of the test signal input is emphasized by thick lines in the figure. As can be seen, when the test signal received by the decoding unit 101 is "0001", the decoding unit 101 decodes the test signal. Only the bit corresponding to S1 in the obtained first signal is high level 1, and other bits are low level 0. At this time, the control terminal of the sub-switch SWB of the bilateral switch chip 103-1 in the selection unit 103 receives the high level signal corresponding to the output terminal S1 of the keyboard encoder 101, that is, the sub-switch SWB is gated, and its first output terminal and second output terminal respectively output row selection signals and column selection signals to the row input port Y1 and column input port X2 of the keyboard encoder 30. Referring to the device truth table of the 16-key keyboard encoder shown, when the row input port Y1 and column input port X2 are selected, the normal output "DCBA" of the device should be "0001", which is consistent with the test signal. At this time, as long as the 4-bit binary number output by the output terminals D, C, B, A of the keyboard encoder is consistent with the test signal, the device completes one round of testing. The test machine outputs all test signals in a predetermined sequence. If each output signal of the keyboard encoder is consistent with the test signal, the function of the keyboard encoder 30 is normal, otherwise it is abnormal.

[0058] During the test, continue to refer to Figure 4 As shown, assume that the test signal input by the test machine to the decoding unit 101 is "0001". The signal path of the test signal input is emphasized by thick lines in the figure. As can be seen, when the test signal received by the decoding unit 101 is "0001", the decoding unit 101 decodes the test signal. Only the bit corresponding to S1 in the obtained first signal is high level 1, and other bits are low level 0. At this time, the control terminal of the sub-switch SWB of the bilateral switch chip 103-1 in the selection unit 103 receives the high level signal corresponding to the output terminal S1 of the keyboard encoder 101, that is, the sub-switch SWB is gated, and its first output terminal and second output terminal respectively output row selection signals and column selection signals to the row input port Y1 and column input port X2 of the keyboard encoder 30. Referring to the device truth table of the 16-key keyboard encoder shown, when the row input port Y1 and column input port X2 are selected, the normal output "DCBA" of the device should be "0001", which is consistent with the test signal. At this time, as long as the 4-bit binary number output by the output terminals D, C, B, A of the keyboard encoder is consistent with the test signal, the device completes one round of testing. The test machine outputs all test signals in a predetermined sequence. If each output signal of the keyboard encoder is consistent with the test signal, the function of the keyboard encoder 30 is normal, otherwise it is abnormal. Figure 4 As can be seen, when the test signal received by the decoding unit 101 is "0001", the decoding unit 101 decodes the test signal. Only the bit corresponding to S1 in the obtained first signal is high level 1, and other bits are low level 0. At this time, the control terminal of the sub-switch SWB of the bilateral switch chip 103-1 in the selection unit 103 receives the high level signal corresponding to the output terminal S1 of the keyboard encoder 101, that is, the sub-switch SWB is gated, and its first output terminal and second output terminal respectively output row selection signals and column selection signals to the row input port Y1 and column input port X2 of the keyboard encoder 30. Referring to the device truth table of the 16-key keyboard encoder shown, when the row input port Y1 and column input port X2 are selected, the normal output "DCBA" of the device should be "0001", which is consistent with the test signal. At this time, as long as the 4-bit binary number output by the output terminals D, C, B, A of the keyboard encoder is consistent with the test signal, the device completes one round of testing. The test machine outputs all test signals in a predetermined sequence. If each output signal of the keyboard encoder is consistent with the test signal, the function of the keyboard encoder 30 is normal, otherwise it is abnormal. Figure 7 As can be seen from the device truth table of the 16-key keyboard encoder shown, when the row input port Y1 and column input port X2 are selected, the normal output "DCBA" of the device should be "0001", which is consistent with the test signal. At this time, as long as the 4-bit binary number output by the output terminals D, C, B, A of the keyboard encoder is consistent with the test signal, the device completes one round of testing. The test machine outputs all test signals in a predetermined sequence. If each output signal of the keyboard encoder is consistent with the test signal, the function of the keyboard encoder 30 is normal, otherwise it is abnormal.

[0059] Those skilled in the art can also understand that in order to facilitate the tester to determine the output results of the output terminals D, C, B, A of the keyboard encoder, an indicator can also be set on or outside the test device 10 to display the indication numbers corresponding to the output values of DCBA, or the number of indicator lights corresponding to the output values of DCBA. This will not be elaborated here.

[0060] It should also be noted that only a 4-line - 16-line decoder is taken as an example above to give the specific schematic diagram and implementation method. In the example, the decoding unit is a CC4514 type chip and the selection unit is a CC4066 type chip. Those skilled in the art should understand that the present application is not intended to be limited thereto. When the decoding unit is a 4-line - 16-line decoder, the decoding unit can be implemented by a CC4514 type chip of the present application, or can be extended to a 4-line - 16-line decoder by one or more CC4028 type chips, 74LS154 type chips, 74HC154 type chips, and 74LS138 type chips, etc. In addition, the decoding unit is not limited to a 4-line - 16-line decoder, and its specific type depends on the number of keyboard keys represented by the combination of the row input port and the column input port of the keyboard encoder. Those skilled in the art can make a reasonable combination to be able to implement the functions of the above decoding unit, which will not be elaborated here.

[0061] In the above embodiments, by adopting a decoding unit and a selection unit, specifically, after the decoding unit decodes the test signal, it can output an output signal corresponding to the maximum number of bits of the combination of the row input port and the column input port of the keyboard encoder to be tested. That is, if the keyboard encoder is a device including 2 N devices for combining the row input port and the column input port, the decoding unit is at least an N-line - 2 N line decoder, and the selection unit includes at least 2 N sub-switches, and each sub-switch is independently turned on under the control of the control end to output a pair of row selection signals and column selection signals to select the combination of the row input port and the column input port whose output value of the keyboard encoder corresponds to the value of the test signal, so as to complete the translation of the test signal only through the combination of the decoding unit and the selection unit, and thus there is no need to set up a relay array to simulate the selection of the key positions represented by the row input port and the column input port. The combination of the decoding unit and the selection unit has a high integration degree, occupies a small space, and reduces the requirements for space and environment; in addition, the working life of the chip is much higher than that of the relay, saving maintenance time and cost, improving the reliability and working efficiency of the device, and having a wide application prospect.

[0062] Based on the same inventive concept, as Figure 3 shown, an embodiment of the present invention further provides a test system, including: a test machine platform 20 and a test device 10 for the keyboard encoder described above,

[0063] The test machine platform 20 outputs a test signal to the test device 10 of the keyboard encoder in a predetermined time sequence, so that the test device 10 of the keyboard encoder generates row selection signals and column selection signals to select the row input port and the column input port of the keyboard encoder to complete the function test.

[0064] With the above settings, by providing a test device with a keyboard encoder and a test system with a test machine platform, the automatic test of the keyboard encoder can be completed with low cost loss and environmental requirements, and has broad application prospects.

[0065] Based on the same inventive concept, an embodiment of the present invention further provides a test method for a test device of a keyboard encoder based on the test device of the keyboard encoder described in the above embodiment, including:

[0066] Output test signals to the test device of the keyboard encoder according to a predetermined time sequence, so that the test device of the keyboard encoder decodes the test signals and generates a row selection signal and a column selection signal to select the row input port and the column input port of the keyboard encoder to complete the function test.

[0067] Among them, the present application does not aim to limit the specific time interval of the predetermined time sequence, and it is sufficient to use a time interval that can be recognized by a digital integrated chip.

[0068] With the above settings, a test plug-in is set in the test machine platform. When the test plug-in is executed, the test machine platform can output test signals to the keyboard encoder test device according to a predetermined time sequence. The test signals correspond to the binary signal values represented by the combinations of different row input ports and column input ports of the keyboard encoder. In this way, the automatic test of the keyboard encoder can be realized by using the test device. Of course, the above test plug-in can also be replaced by other forms, and its ultimate goal is to enable the test machine platform to send test signals according to a predetermined time sequence.

[0069] In view of the existing problems, the present invention provides a test device, a test system, and a test method for a keyboard encoder. The test device of the keyboard encoder includes a decoding unit and a selection unit. The decoding unit decodes the test signals, and based on the first signal generated by the decoding, the selection unit selects the corresponding sub-switch to generate a row selection signal and a column selection signal corresponding to the row input port and the column input port of the keyboard encoder to complete the function test. The combination of the decoding unit and the selection unit has a high integration degree and occupies a small space, reducing the requirements for the test space and environment; in addition, the working life of the chip is much higher than that of the relay, saving maintenance time and cost, improving the reliability and working efficiency of the device, and having broad application prospects.

[0070] Obviously, the above embodiments of the present invention are only examples for clearly explaining the present invention, and are not limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation manners here. Any obvious changes or modifications derived from the technical solutions of the present invention still fall within the protection scope of the present invention.

Claims

1. A test device for a keyboard encoder, characterized in that, comprising: a decoding unit that decodes a received test signal to generate a first signal; a selection unit that, based on the first signal, gates corresponding sub-switches to generate a row selection signal and a column selection signal, so as to select the row input port and the column input port of the keyboard encoder to implement a function test, the selection unit includes at least one bilateral switch chip, each bilateral switch chip includes a plurality of the sub-switches, each sub-switch includes a control end, a first output end and a second output end, the control end accesses a valid bit in the first signal, the first output end outputs the row selection signal, and the second output end outputs the column selection signal.

2. The test device for a keyboard encoder according to claim 1, characterized in that, the decoding unit includes at least one decoder chip; The test signal is an N-bit binary signal, and the decoding unit decodes the test signal to generate a first signal of 2 N bits, and one of the bits in the first signal is a valid bit, where N is a positive integer.

3. The test device for a keyboard encoder according to claim 2, characterized in that, The selection unit includes: 2 N sub-switches connected in parallel; among the sub-switches of the selection unit, the sub-switch corresponding to the valid bit in the first signal is turned on to generate a pair of the row selection signal and the column selection signal, and output to one of the N row input ports and one of the N column input ports of the keyboard encoder, so as to select a key position to implement a function test.

4. The test device for a keyboard encoder according to claim 2 or 3, characterized in that, the decoding unit is a 4-line - 16-line decoder.

5. The test device for a keyboard encoder according to claim 4, characterized in that, the selection unit includes 4 bilateral switch chips, and each bilateral switch chip includes 4 of the sub-switches.

6. The test device for a keyboard encoder according to claim 5, characterized in that, the decoding unit is selected from one or more of a CC4514 type chip, a CC4028 type chip, a 74LS154 type chip, a 74HC154 type chip and a 74LS138 type chip; the bilateral switch chip is a CC4066 type chip.

7. The test device for a keyboard encoder according to any one of claims 1 - 3, characterized in that, further comprising: a first communication interface for communicating with a test machine platform to receive the test signal from the test machine platform; and a second communication interface for communicating with the keyboard encoder to output the row selection signal and the column selection signal to the keyboard encoder.

8. A test system, characterized in that, comprising: a test machine platform and the test device for a keyboard encoder according to any one of claims 1 - 7; the test machine platform outputs a test signal to the test device for a keyboard encoder in a predetermined time sequence, so that the test device for a keyboard encoder generates a row selection signal and a column selection signal to select the row input port and the column input port of the keyboard encoder to implement a function test.

9. A test method based on the test device for a keyboard encoder according to any one of claims 1 - 7, characterized in that, comprising: Output a test signal to the test device of the keyboard encoder according to a predetermined time sequence, so that the test device of the keyboard encoder decodes the test signal and generates a row selection signal and a column selection signal to select the row input port and the column input port of the keyboard encoder to implement a function test.

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