Managing read level voltage offset for low threshold voltage offset interval placement

Abstract

Embodiments of this application relate to managing read level voltage offsets for placement in low threshold voltage offset ranges. A block family is created associated with a memory device. This block family is associated with a threshold voltage offset range. A set of read level voltage offsets is determined such that applying this set of read level voltage offsets to the base read level threshold voltage associated with the block family produces a suboptimal error rate not exceeding the maximum permissible error rate. The determined set of read level offsets is associated with the threshold voltage offset range by updating the block family metadata.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to managing read level voltage offsets for placement in low threshold voltage offset ranges. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to embodiments of this disclosure, a method is provided. The method includes: creating a block family associated with a memory device; associating the block family with a threshold voltage offset interval; determining a read level voltage offset set such that when applied to a base read level threshold voltage associated with the block family, a suboptimal error rate not exceeding a maximum permissible error rate is generated; and associating the read level voltage offset set with the threshold voltage offset interval.

[0004] According to embodiments of this disclosure, a system is provided. The system includes: a memory device; and a processing means operatively coupled to the memory device to perform the following operations: identifying a block associated with the memory device; performing a series of read operations on the block using a plurality of read level voltage offset sets; and identifying a read level voltage offset set among the plurality of read level voltage offset sets, wherein the read level voltage offset set produces a suboptimal error rate not exceeding a maximum permissible error rate when applied to a base read level voltage associated with the block.

[0005] According to embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing means, cause the processing means to perform the following operations: create a family of blocks associated with a memory means; associate the family of blocks with a threshold voltage offset interval; determine a set of read level voltage offsets such that when applied to a base read level threshold voltage associated with the family of blocks, a suboptimal error rate not exceeding a maximum permissible error rate is generated; and associate the set of read level voltage offsets with the threshold voltage offset interval. Attached Figure Description

[0006] This disclosure will be more fully understood from the accompanying drawings, which are given below and describe various embodiments of the present disclosure. However, the drawings should not be construed as limiting the disclosure to the specific embodiments, but are merely for illustration and understanding.

[0007] Figure 1An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 The illustration schematically depicts time-voltage shifts caused by the slow charge loss exhibited by a three-level memory cell, according to some embodiments of the present disclosure.

[0009] Figure 3 Example graphs depicting the correlation between threshold voltage offset and programming time (i.e., the time elapsed since the block was programmed) according to embodiments of the present disclosure.

[0010] Figure 4 A set of predefined threshold voltage offset intervals according to embodiments of the present disclosure is illustrated schematically.

[0011] Figure 5 The block family management operation is schematically illustrated by the block family manager component of a memory subsystem controller operating according to an embodiment of the present disclosure.

[0012] Figure 6 The illustration schematically shows the selection of a block family for calibration according to an embodiment of the present disclosure.

[0013] Figure 7 The illustration schematically shows instance metadata maintained by the memory subsystem controller according to embodiments of the present disclosure for associating blocks and / or partitions with block families.

[0014] Figure 8 An example graph depicting the development of the error rate over time after programming, according to embodiments of the present disclosure.

[0015] Figure 9 This is a flowchart of an example method for determining a set of read level voltage offsets for a threshold voltage offset range according to some embodiments of the present disclosure.

[0016] Figure 10 This is a flowchart of an example method for determining a set of read level voltage offsets for a read operation according to some embodiments of the present disclosure.

[0017] Figure 11 This is an example of a set of read level voltage offsets determined according to some embodiments of this disclosure.

[0018] Figure 12 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0019] This disclosure relates to managing read level voltage offsets for placement in low threshold voltage offset ranges. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0020] The memory subsystem may utilize one or more memory devices to store data provided by the host system, said one or more memory devices comprising different types of non-volatile memory devices and / or any combination of volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following is combined with... Figure 1 Other examples of non-volatile memory devices are described. Each of these memory devices may contain one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. The logical states may be represented by binary values, such as “0” and “1” or combinations of such values.

[0021] Various data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and to read data from a memory device on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location that the host system associates with the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., expiration date used to distinguish the written data), validity bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0022] A memory device comprises multiple memory cells capable of storing one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written into the memory cell) by applying a voltage to it, which causes the charge to change from a voltage known as the "threshold voltage" and denoted as V. TThe memory cells are retained.

[0023] High-quality memory devices can have a narrow distribution of control voltages compared to the operating range of the device's cells. Therefore, multiple distributions (where the "valleys" between distributions) can be fitted into the operating voltage window, allowing for the storage and reliable detection of multiple bits per cell, for example, 2 bits for a three-level cell (TLC). 3 =8 distribution (7 valleys), for multilevel cell (MLC) it is 2 2 =4 distributions (3 valleys), etc. Voltage intervals (valley margins) are interspersed between the distributions, in which the memory cells of the device have no (or very few) their threshold voltages. Therefore, such valley margins can be used to separate various charge states, and the logic state of the cell can be determined by detecting during a read operation by applying a read voltage corresponding to each valley. This effectively allows a single memory cell to store multiple bits of information: with 2... N A distributed (also known as hierarchical) memory cell can store N bits of information. During a read operation, a 2 N -1 read voltage to distinguish 2 N There are several distributions. Specifically, this can be achieved by comparing the measured threshold voltage V as shown by the memory cell. T A read operation is performed with one or more reference read voltage levels (read levels) corresponding to a known valley value (e.g., the center of the valley value) of the memory device.

[0024] This is attributed to a phenomenon known as slow charge loss (SCL), where the threshold voltage V of a memory cell decreases as the cell's charge diminishes. T This process, which varies over time, is sometimes referred to as "time-voltage shift" (TVS). TVS can contain various components, such as inherent charge loss, system charge loss, and fast charge loss. TVS typically increases with the number of program-erase cycles (PEC), higher temperatures, and higher programming voltages. TVS can exhibit significant die-to-die variations.

[0025] Because a typical cell stores negatively charged particles (electrons), the loss of electrons causes the threshold voltage to shift along the voltage axis towards a lower threshold voltage V. T Shifting. The threshold voltage can be changed rapidly initially (immediately after the memory cell is programmed), while the time elapsed since the cell programming event, referred to in this paper as the post-programming time (TAP), changes in a roughly logarithmic linear or power-law manner (ΔV). T (t) = - C*t bThe TAP slows down over a longer period. It can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., based on the controller clock). Cells, blocks, pages, block families (groups of blocks), etc., are new (or relatively new) when they have (relatively) small TAPs and old (or relatively old) when they have (relatively) large TAPs. A time slice is the duration between two TAP points during which measurements can be performed (e.g., performing a reference calibration 8 to 12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes). In some embodiments of this disclosure, this can be achieved by keeping track of the time elapsed since the programming event and the environmental conditions, such as temperature, of a particular memory partition (block, plane, etc.), and by offsetting the voltage by ΔV for each valley value to be used during a read operation. T Correlation to mitigate TVS, where the standard "baseline read level" threshold voltage V T (Immediately displayed by the cell after programming) The change is a voltage offset: V T → V T +ΔV T , where ΔV T It is negative due to charge loss. Although TVS is a continuous process and is related to ΔV T The compensation for (t) can change over time, but in some embodiments, a discrete number of threshold voltage offset "intervals" can be used to achieve sufficient accuracy of the offset. A block "family" (or any other memory partition) programmed within a specified time window and / or under similar environmental (e.g., temperature) conditions can be associated with one of the threshold voltage offset intervals. Given that wear leveling is maintained under similar program-erase cycles (PECs), the elapsed time since programming and temperature conditions are major factors affecting the amount of TVS, it can be assumed that different partitions within a single block family exhibit a similar distribution of threshold voltages for their memory cells, and therefore the same voltage offset will need to be applied to the base read level for read operations.

[0026] Block families can be created asynchronously relative to block programming events. A “block” in this document refers to a collection of contiguous or non-contiguous memory pages. An instance of a “block” is an “erasable block,” which is the smallest erasable unit of memory, while a “page” is the smallest writable unit of memory. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information. A “block family” in this document refers to a potentially non-contiguous collection of memory cells (which may reside in one or more complete and / or partial blocks, the latter referred to herein as “partitions”) that has been programmed within a specified time window and a specified temperature window, and is therefore expected to exhibit similar or related changes in its corresponding data state metrics in terms of time-voltage shift. Block families can be made at any granularity, thus having only all codewords, all pages, all superpages, or all superblocks, or any combination thereof.

[0027] The process of creating a block family as an open block family, maintaining the open block family for a period of time, and then closing the block family. Opening a block family begins with an open block family period, which is a period during which the driver can write data to or read data from the block family. Closing a block family begins with a closing block family period, which is a period during which the driver can read data from the block family but not write data to it. Invalidating a block family begins with an invalidating block family period, which is a period during which the block family typically passes garbage collection and does not have any data that has not yet become invalid. The open block family period and the closing block family period together constitute the block family period.

[0028] In the illustrative example, whenever a specified time period has elapsed since the creation of the previous block family, it is used. A new block family can be created (opened) when (for example, after a predetermined number of minutes) or whenever the reference temperature of a memory cell has changed by more than a specified threshold ΔΘ (for example, 10°C, 20°C, or any other value). Similarly, a new block family can be created (opened) whenever a period of time has elapsed since the family was created. Subsequently, or when the reference temperature (in either direction) has changed by more than ΔΘ, the family can be "shut down" (and a new family can be created). The memory subsystem controller can maintain identifiers for active block families, which are associated with one or more blocks when they are programmed.

[0029] The memory subsystem controller may periodically perform a calibration process to associate partitions of each family with one of the threshold voltage offset intervals. Each threshold voltage offset interval may in turn be associated with a set of voltage offsets to be applied for read operations. The association between partitions and families, and between families and threshold voltage offset intervals, is referred to herein as Auxiliary Read Metadata (ARM), which represents a portion of the broader state metrics of the memory device. State metrics may also include the number of discarded physical memory blocks (or other partitions), the number of times various physical blocks have been erased, the configuration type of cells in various memory partitions (e.g., single-level cells vs. multi-level cells), or any other type of information indicating the state of the memory device. ARM may be stored in a metadata table maintained by the memory subsystem controller.

[0030] According to embodiments of this disclosure, TVS can be selectively tracked for programmed partitions grouped into families. Based on partition-to-family grouping, an appropriate interval-specific read (voltage) offset is applied to the base read (voltage) level during a read operation. The base read level can also be stored in the metadata of the memory device. Upon receiving a read command, the memory subsystem controller can (1) identify the family associated with the memory partition identified by the logical address specified in the read command, (2) identify the current threshold voltage offset interval associated with the identified family, (3) determine the set of read offsets for the identified threshold voltage offset interval, (4) calculate a new read voltage by superimposing the read offsets associated with the identified threshold voltage offset interval onto the base read level, and (5) perform a read operation using the new read voltage, as described in more detail below.

[0031] The calibration process can evaluate a data state metric (e.g., voltage shift or bit error rate) for each die of each block family by measuring the value of the data state metric stored on the die for each die of each block family. The calibration process can then update the interval pointers associated with the die and block family to point to the threshold voltage offset interval corresponding to the measured value of the data state metric. Each threshold voltage offset interval is, in turn, associated with a voltage offset to be applied for a read operation; for a TLC with 8 distributions (hierarchies), there are 7 valleys, and for a given threshold voltage offset interval containing 7 offsets, each valley represents one offset. For example, if the data state metric is within the range associated with an existing interval pointer, the interval pointer can remain the same, or if the data state metric is within the range associated with an earlier interval, the interval pointer can be changed to point to the earlier interval. Although a block family can be associated with multiple different intervals (via interval pointers), the block family is referred to herein as being associated with a specific interval (“in which”). More precisely, a block family is associated with (or within) an earlier interval of the bare piece that is associated with the block family.

[0032] Generally speaking, time-voltage shifts for newer block families (i.e., the most recently created block families) are more important than time-voltage shifts for older block families (i.e., the earlier created block families). The memory subsystem controller can periodically perform a calibration process for each block family based on the age of the block family, which corresponds to a threshold voltage offset interval associated with the block family. For example, in an 8-threshold voltage offset interval architecture, newly created block families may be associated with threshold voltage offset interval 0, while the oldest (i.e., the earliest created) block families are associated with threshold voltage offset interval 7. Compared to block families in threshold voltage offset interval 7, the memory subsystem controller performs calibration processes more frequently for block families in threshold voltage offset interval 0 based on the age of the block families associated with threshold voltage offset interval 0 (e.g., based on the log-linear property of SCL).

[0033] In some implementations, the voltage offset associated with each threshold voltage offset interval minimizes the error rate when applied to the base read level; that is, there is no other set of threshold voltage offsets that would produce a lower error rate for a particular interval. An example of a reliable error rate metric is the Raw Bit Error Rate (RBER). RBER corresponds to the number of bit errors experienced by each data unit stored at a block. When the error rate exceeds a threshold (e.g., exceeding the maximum permissible error rate based on ECC correction capability with hard information), the memory subsystem performs an error recovery operation that increases system latency. To achieve a low error rate, calibration scans of recently created blocks will need to be performed more frequently than calibration scans of earlier created blocks, because, as described above, the time voltage shift for recently created blocks is more important. As an example, a time voltage shift experienced by a cell between 1 and 10 minutes after programming will be similar to a time voltage shift experienced between 10 and 100 minutes after programming, and similar to a time voltage shift experienced between 100 and 1000 minutes after programming. For efficiency, the calibration process should be more frequent than the amount of time a block family spends associated with a specific threshold voltage offset interval. As an example, suppose that on average, a block family is associated with interval 0 for 10 minutes. In this case, the calibration process for interval 0 needs to be more frequent than 10 minutes, for example, every 5 minutes, to determine whether to associate the block family with interval 1. The calibration process can utilize significant memory subsystem resources. Furthermore, while the calibration process is in progress, requests received from the host cannot be executed, potentially causing increased latency to the host system that impacts QoS (Quality of Service). Therefore, frequently performing calibration processes for recently created block families in lower threshold voltage offset intervals (e.g., interval 0) increases overall system latency.

[0034] The aspects of this disclosure address the aforementioned and other shortcomings by implementing a memory subsystem that reduces the frequency of calibration processes for recently created block families by extending the time it takes for block families to be assigned to a lower threshold voltage offset interval (e.g., interval 0). The memory subsystem controller can set the read level voltage offset of the lower threshold voltage offset interval to a value that produces a suboptimal error rate, not exceeding the maximum permissible error rate, when applied to the base read level (i.e., the system can use different sets of voltage offsets that produce lower error rates). This allows block families to remain in the lower voltage threshold offset interval for a longer period, which reduces the frequency of calibration processes that assign block families to the voltage threshold offset interval. Continuing with the example provided above, this option can increase the average time associated with the block family and interval 0, for example, from 10 minutes to 30 minutes. Therefore, the calibration process can run every 15 minutes instead of every 5 minutes. This reduces the system performance impact of the calibration process. The suboptimal error rate can be an error rate within a predetermined interval that is lower than the maximum permissible error rate. The maximum permissible error rate can, for example, be higher than the error rate required for the memory subsystem controller 115 to perform additional error recovery operations in order to return valid data (i.e., the error rate that the hard-input ECC decoder can correct).

[0035] As a block family undergoes a time-voltage shift, the voltage distribution shifts along the voltage axis toward a lower voltage level. As the voltage distribution shifts, the memory subsystem controller performs a calibration process to determine the appropriate voltage offset to be added to the base read level to compensate for the time-voltage shift within a predetermined offset set. This is equivalent to assigning each die of the block family to a threshold voltage offset interval with a corresponding offset for each valley value. Given that the distribution has shifted to a lower voltage value (i.e., charge loss), the added interval voltage offset can be negative (i.e., less than zero). In an embodiment, the memory subsystem controller may add a voltage offset to the base read level of the block family to effectively simulate the shift of the voltage distribution along the voltage axis toward a lower voltage level compared to the level at programming time. If the memory subsystem controller determines that the read level voltage offset for interval 0 will last longer than optimal (e.g., optimal for 30 minutes) relative to time 0, then the time interval during which the block family will be associated with interval 0 during the scalable period. This can result in a suboptimal RBER at time 0, i.e., higher than possible. However, the impact on the memory subsystem is minimal as long as the RBER at time 0 is less than the error rate that the hard-input ECC decoder can correct. This method can also be applied to other threshold voltage offset intervals. Simply put, it measures the average time that the memory subsystem extension block remains in interval 0, at the cost of suboptimal performance at time 0 (i.e., higher RBER).

[0036] In an embodiment, if the data state metric is within a range associated with the next threshold voltage offset interval, the memory subsystem controller may determine, based on the calibration process, to change the interval pointer to point to the next threshold voltage offset interval. By adjusting the read level voltage offset of the block family according to embodiments of this disclosure, the data state metric can reach the range associated with the next threshold voltage offset interval at a later time point. For example, while the adjusted voltage level of a block family without voltage offset at programming time may reach the error rate required to move to the next threshold voltage offset interval after 1 hour, the adjusted voltage level of a block family with voltage offset at programming time according to embodiments of this disclosure may not reach the error rate required to move to the next voltage until 3 hours after programming. Furthermore, since the frequency of the calibration process is based on the time period associated with the block family and the threshold voltage offset interval, by extending the time period associated with the block family and a particular threshold voltage offset interval, the memory subsystem controller can reduce the frequency of calibration processes for blocks within the threshold voltage offset interval.

[0037] The advantages of this disclosure include, but are not limited to, reducing system latency and improving overall quality of service by extending the time period associated with block families and lower threshold voltage offset intervals, thereby reducing the frequency of operations associated with interval calibration. Each calibration operation of the memory device consumes valuable resources. By calibrating block families at programming time with a higher error rate, aspects of this disclosure extend the time period associated with block families and lower creation threshold voltage offset intervals (e.g., interval 0). Since the frequency of the calibration process is based on the amount of time a block family is associated with a threshold voltage offset interval, by extending the time associated with block families and lower threshold voltage offset intervals (e.g., interval 0), aspects of this disclosure reduce the frequency of block family calibration in interval 0. Less frequent calibration frees up resources available for other operations, thus reducing latency and improving system performance.

[0038] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0039] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0040] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0041] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes connections such as electrical connections, optical connections, magnetic connections, etc.

[0042] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0043] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0044] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0045] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0046] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0047] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0048] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0049] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing operations controlling the memory subsystem 110, including various processes, operations, logical flows, and routines for handling communication between the memory subsystem 110 and the host system 120.

[0050] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0051] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0052] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0053] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0054] Memory subsystem 110 includes block family manager component 113, which sets the read offset voltage level of a block family within a threshold voltage offset range (e.g., within threshold voltage offset range 0) to maximize the time period associated with a given block family with a specific threshold voltage offset range. In some embodiments, memory subsystem controller 115 includes at least a portion of block family manager component 113. In some embodiments, block family manager component 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of block family manager component 113 and is configured to perform the functions described herein.

[0055] Block family manager component 113 can determine the read level offset to be associated with a threshold voltage offset interval in order to maximize the time period associated with a given block family with a specific threshold voltage offset interval (e.g., threshold voltage offset interval 0). Block family manager component 113 can create block families and associate block families with threshold voltage offset intervals. In an embodiment, block families can be created by grouping the blocks when they are programmed. Grouping can be based on the time range and / or temperature range in which the blocks are programmed. Block family manager component 113 can associate block families with threshold voltage offset intervals by updating block family metadata.

[0056] Block family manager component 113 determines the set of read level voltage offsets to be applied to threshold voltage offset intervals in order to maximize the time period associated with a given block family and a specific threshold voltage offset interval. This process may be referred to as an "interval offset calibration process." The interval offset calibration process may include generating and / or determining the set of read level voltage offsets to be applied to each threshold voltage offset interval. For example, if there are 8 threshold voltage offset intervals associated with a TLC, then the interval offset calibration process may generate a set of read level voltage offsets for each of the 8 threshold voltage offset intervals, and each set may contain 7 read level voltage offsets, with one read level voltage offset for each valley value. About Figure 11 An instance of reading the voltage offset set is described.

[0057] In an embodiment, to determine the set of read level voltage offsets to be applied, the block family manager component 113 may identify the set of read level voltage offsets. The set of read level voltage offsets may be stored in the non-volatile memory device 130. Alternatively, the block family manager component 113 may generate a set of read level voltage offsets within a certain range. For example, if the threshold voltage of a block typically shifts towards a specific threshold voltage during a time period associated with a specific threshold voltage offset interval (e.g., interval 0), then the block family manager component 113 may generate a set of read level voltage offsets that will be within 0 and that the specific threshold voltage shift is typically experienced by blocks associated with the threshold voltage offset interval (e.g., interval 0). The block family manager component 113 may determine the average voltage shift when determining the range for the set of read level voltage offsets, or it may determine the maximum voltage shift when determining the set of read level voltage offsets. In an embodiment, the block family manager component 113 may use a minimum threshold voltage offset, an average threshold voltage offset, or some other measurement when generating the set of read level voltage offsets. An interval offset calibration process can be performed during the manufacturing phase of the memory subsystem before customer use to determine the set of read level voltage offsets associated with each threshold voltage offset interval. This extends the time a block family is associated with a specific interval (e.g., interval 0) without exceeding an allowable / predetermined error rate. Therefore, once the customer uses the memory subsystem, the read level voltage offsets are available, and the calibration process assigns the block family to the threshold voltage offset interval using the predetermined read level voltage offsets. Alternatively, the interval offset calibration process can be performed periodically at a predetermined pace throughout the lifetime of the memory subsystem.

[0058] Block family manager component 113 may perform a series of read operations on a block family using multiple voltage offset sets. Each read operation in the series of read operations uses one of the voltage offset sets. Each voltage offset set contains the voltage offset of each valley value of the memory cell being read. In an embodiment, a series of read operations may be performed on randomly selected blocks or pages within the block family. Block family manager component 113 may then select from the series of read operations a read operation that produces a second-best error rate not exceeding the maximum allowable error rate, i.e., an error rate lower than the maximum allowable error rate within a predetermined interval. The predetermined interval may be, for example, a predetermined share of the maximum allowable error rate (e.g., ½ or ¾). Therefore, for each read operation in the series of read operations, block family manager component 113 may determine the error rate associated with the voltage offset set associated with the read operation. Block family manager component 113 may then select a voltage offset associated with the read operation that produces a second-best error rate not exceeding the maximum allowable error rate. Within the interval offset voltage set, the selected voltage offset produces the lowest error rate, however, this lowest error rate is second-best in the sense that different interval offset voltage sets produce lower error rates. In an embodiment, the block family manager component 113 may set the maximum permissible error rate as a percentage of the hardware decoding error rate, such as 90% of the hardware decoding rate, to allow for error tolerance. A range offset calibration process, which determines the read level offset voltage to extend the time a block family remains within a specific range (e.g., range 0) without exceeding a predetermined maximum permissible error rate, can be performed during the manufacturing stage of the memory subsystem prior to customer use. Therefore, once the customer uses the memory subsystem, the read level voltage offset for each range is available, and the calibration process assigns the block family to the range using the predetermined read level voltage offset.

[0059] By setting the read level voltage offset of the threshold voltage offset range to a level that produces a suboptimal error rate not exceeding the maximum permissible error rate during programming, the block family can remain associated with the threshold voltage offset range for a longer period of time. The block family manager component 113 can therefore reduce the frequency of calibration processes performed when the block family is associated with the threshold voltage offset range.

[0060] In one embodiment, the block family manager component 113 applies a read level voltage offset set for background operations, including read operations to determine the normal state of the memory device. To determine the accurate normal state of the memory device, the block family manager component 113 may perform background read operations using a threshold voltage offset that minimizes the error rate, rather than a threshold voltage offset that extends the time period associated with a specific threshold voltage offset interval for the block family. Therefore, in response to determining that a read operation is a background operation, the block family manager component 113 may apply a read level voltage offset set that produces an error rate below a threshold. That is, the block family manager component 113 may determine a read level voltage offset set that produces either the lowest error rate or an error rate below a threshold. The block family manager component 113 may then apply the read level voltage offset set to minimize the error rate of the background read operation. In other embodiments, for background read operations, the block family manager component 113 may use a special read mode that delivers the lowest possible error rate. These special read modes determine an optimized read threshold voltage level to deliver a real-time read level offset with the lowest possible error rate.

[0061] The following describes further details regarding the operation of the block family manager component 113.

[0062] Figure 2 The illustration schematically depicts time-voltage shifts caused by the slow charge loss exhibited by a three-level memory cell, according to some embodiments of this disclosure. Although Figure 2 The illustrative example utilizes a three-level cell, but the same observations can be made, and therefore the same remedy applies to single-level and multi-level cells, as well as any other fractional or integer units per cell (e.g., 3.5 units per cell, etc.), to compensate for slow charge loss.

[0063] A memory cell can be programmed (written to) by applying a voltage (e.g., a programming voltage) to it, which generates a charge stored in the memory cell. Precise control over the amount of charge stored in a memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information. (With 2...) n A memory cell that operates at different threshold voltage levels can store n bits of information.

[0064] Each of Figures 210 and 230 illustrates a programming voltage distribution 220A to 220N (also referred to herein as a “programming distribution”, “voltage distribution”, “distribution”, or “level”) for a memory cell programmed to encode a corresponding logic level (“000” to “111” in the case of TLC) by a corresponding write level (which may be assumed to be located at the midpoint of the programming distribution). Programming distributions 220A to 220N may illustrate a range of threshold voltages (e.g., a normal distribution of threshold voltages) for a memory cell programmed at a corresponding write level (e.g., a programming voltage). To distinguish adjacent programming distributions (corresponding to two different logic levels), a read threshold voltage level is defined (shown by a vertical dashed line) such that any measured voltage below the read threshold level is associated with one of a pair of adjacent programming distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other of a pair of adjacent distributions.

[0065] In Figure 210, eight states of the memory cell are shown below the corresponding programming distribution (the distribution of states is not shown except for the state marked ER, which is the erased state). Each state corresponds to a logic level. The read threshold voltage levels are marked Va-Vh. As shown, any measured voltage below Va is associated with the ER state. The states marked P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 220A to 220N, respectively.

[0066] Post-programming time (TAP) in this document refers to the time since a cell was written and is the primary driver of time-varying voltage shift (TVS) as a function of temperature. TVS captures SCL and other charge loss mechanisms. TAP can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., based on the controller clock). Cells, blocks, pages, block families, etc., are new (or relatively new) with (relatively) small TAPs and old (or relatively old) with (relatively) large TAPs. A time slice is the duration between two TAP points during which measurements can be performed (e.g., performing a reference calibration X to Y minutes or hours after programming). A time slice can be referenced by its center point.

[0067] As can be seen from example graphs 210 and 230, which compare the time after programming (TAP) which is 0 (immediately after programming) and the TAP after T hours (where T is the number of hours), the programming distribution changes over time primarily due to slow charge loss. To reduce the read error rate, the corresponding read threshold voltage needs to be adjusted to compensate for the shift in the programming distribution, as shown by the vertical dashed line. In various embodiments of this disclosure, the time voltage shift is selectively tracked for the die group based on measurements taken at one or more representative dies of the die group. Based on measurements of the time voltage shift and operating temperature of the die group's dies, which are characterized on representative dies of the die group, the read threshold voltage offset for reading the memory cells of the die group's dies is updated and applied to the base read threshold level to perform a read operation.

[0068] Figure 3 Example graph 300 depicts the correlation between threshold voltage offset 310 and programming time 320 (i.e., the time elapsed since the block was programmed) according to an embodiment of the present disclosure. (As shown by...) Figure 3 The diagram schematically illustrates that a memory device is divided into blocks of families 330A to 330N, such that each family contains one or more blocks programmed within a specified time window and a specified temperature window. As noted above, since the elapsed time and temperature after programming are the main factors affecting the time voltage shift, it is presumed that all blocks and / or partitions within families 330A to 330N will exhibit similar threshold voltage distributions in the memory cells, and therefore the same voltage offset will need to be applied to the base read level for read operations.

[0069] Block families can be created asynchronously relative to page programming events. In an illustrative example, a block family is created whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the previous block family, or whenever the reference temperature of a memory cell updated at specified time intervals since the creation of the current block family has changed by more than a specified threshold. Figure 1 The memory subsystem controller 115 can create new block families.

[0070] The newly created block family can be associated with interval 0. Then, the memory subsystem controller can periodically perform a foreground or background calibration process to ensure that each die in each block family is offset from a predefined threshold voltage interval (within...). Figure 3 In the illustrative example, this is associated with one of the intervals (0-7), and the predefined threshold voltage interval is associated with the voltage offset to be applied for the read operation. The association between blocks and block families, as well as between block families and dies, and the threshold voltage offset interval can be stored in the corresponding metadata table maintained by the memory subsystem controller.

[0071] Figure 4The set of threshold voltage offset intervals (intervals 0 to 9) placed according to embodiments of the present disclosure is illustrated schematically. Figure 4 As illustrated schematically, the threshold voltage offset curve can be subdivided into multiple threshold voltage offset intervals, such that each interval corresponds to a range of threshold voltage offsets. Although Figure 4 The illustrative example specifies ten intervals, but in other implementations, various other numbers of intervals may be used (e.g., 64 intervals).

[0072] The memory subsystem controller can associate each die of each block family with a threshold voltage offset range based on a periodically performed calibration process. The calibration process selects a set of threshold voltage offsets to be applied to a base voltage read level for performing read operations. The calibration process involves performing read operations with different threshold voltage offset sets relative to a specified number of randomly selected pages or blocks within the calibrated block family, and selecting a set of threshold voltage offsets that produces a defined error rate (e.g., bit error rate) for the read operations. The defined error rate can be a minimum error rate, or it can be an error rate within a certain range. In an embodiment, the memory subsystem controller can select a set of threshold voltage offsets that, when applied to a base read level, produces a suboptimal error rate not exceeding the maximum permissible error rate, i.e., an error rate lower than the maximum permissible error rate within a predetermined interval. The predetermined interval can be, for example, a predetermined share (e.g., ½ or ¾) of the maximum permissible error rate. Figure 9 Provide further details about the calibration process.

[0073] Figure 5 The illustration schematically depicts block family management operations performed by a block family manager component of a memory subsystem controller operating according to embodiments of the present disclosure. For example... Figure 5 As illustrated schematically, the block family manager 510 may maintain an identifier 520 for an active block family in a memory variable, the identifier being associated with one or more blocks of the cursor 530A to 530K when the cursor is programmed. "Cursor" will be used broadly herein to refer to the location on the memory device to which data is written.

[0074] The memory subsystem controller can use a power-on minute (POM) clock to track the creation time of block families. In some implementations, in addition to the POM clock, a less accurate clock that continues to operate while the controller is in various low-power states can be used, so that the POM clock is updated immediately based on the less accurate clock after the controller wakes up from a low-power state.

[0075] Therefore, after initializing each block family, the current time 540 is stored in a memory variable as the block family start time 550. When programming a page or block, the current time 540 is compared with the block family start time 550. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), the memory variable storing the block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), and the memory variable storing the block family start time 550 is updated to store the current time 540.

[0076] The block family manager 510 also maintains two memory variables to store the high and low reference temperatures of selected dies for each memory device. After initializing each block family, the high temperature 560 and low temperature 570 variables store the current temperature values ​​of the selected dies of the memory device. In operation, although the active block family identifier 520 remains the same, temperature measurements are periodically obtained and compared with the correspondingly updated stored high temperature 560 and low temperature 570 values: if a temperature measurement is found to be greater than or equal to the value stored by the high temperature variable 560, the value stored by the high temperature variable is updated to store the temperature measurement; conversely, if a temperature measurement is found to have dropped below the value stored by the low temperature variable 570, the value stored by the low temperature variable is updated to store the temperature measurement.

[0077] The block family manager 510 can further periodically calculate the difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is greater than or equal to a specified temperature threshold, the block family manager 510 can close an existing block family and create a new active block family: update the memory variable storing the active block family identifier 520 to store the next block family number (e.g., the next sequential integer number), update the memory variable storing the block family start time 550 to store the current time 540, and update the high temperature 560 and low temperature 570 variables to store the current temperature value of the selected die of the memory device.

[0078] When programming a block, the memory subsystem controller associates the block with the currently active block family. The association between each block and its corresponding block family is reflected in the block family metadata 580, as referenced below. Figure 7 To describe in more detail.

[0079] As described above, based on a periodically performed calibration process, the memory subsystem controller associates each die in each block family with a threshold voltage offset interval, which defines the set of threshold voltage offsets to be applied to the base voltage read level to perform a read operation. The calibration process involves performing read operations with different threshold voltage offsets relative to a specified number of selected blocks within the calibrated block family, selecting the interval that produces an error rate for read operations within a defined range. Blocks within the block family can be selected randomly or based on conforming to specific criteria (e.g., being the oldest in the block family).

[0080] In some embodiments, the frequency at which the memory subsystem controller performs a calibration process for each threshold voltage offset interval may be based on the time period associated with the block family and a particular threshold voltage offset interval. The memory subsystem controller may determine the threshold voltage offset to be associated with the threshold voltage offset interval in order to maximize the time period associated with the block family and a particular threshold voltage offset interval, thereby reducing the frequency at which the memory subsystem controller performs the calibration process.

[0081] Figure 6 This illustration schematically shows the selection of a block family for calibration according to an embodiment of this disclosure. For example... Figure 6 As illustrated, the memory subsystem controller can limit the calibration operation to the oldest block family in each interval (e.g., block family 610 in interval 0 and block family 620 in interval 1) because it will shift to the oldest block family in the next interval before any other block family in the current interval due to slow charge loss.

[0082] Figure 7 The illustration schematically depicts instance metadata maintained by the memory subsystem controller according to embodiments of the present disclosure for associating blocks and / or partitions with block families. Figure 7 As schematically shown, the memory subsystem controller can maintain a superblock table 710, a family table 720, and an offset table 730.

[0083] Each record in the superblock table 710 specifies a block family associated with a specified superblock and partition combination. In some implementations, the superblock table record may further include time and temperature values ​​associated with the specified superblock and partition combination.

[0084] Family table 720 is indexed by block family number, such that each record in family table 720 specifies a set of threshold voltage offset intervals associated with the corresponding die of the block family referenced by the record's index. In other words, each record in family table 720 contains a vector, each element of which specifies a threshold voltage offset interval associated with the die referenced by the index of the vector element. The threshold voltage offset intervals associated with the block family die can be determined through a calibration process, as described in more detail above.

[0085] Finally, offset table 730 is indexed by interval numbering. Each record in offset table 730 (e.g., for TLC, MLC, and / or SLC) specifies a set of threshold voltage offsets associated with a threshold voltage offset interval. The memory subsystem controller can determine the threshold voltage offsets, as referenced below. Figure 9 and 10 To describe in more detail.

[0086] Metadata tables 710 to 730 can be stored Figure 1 On one or more memory devices 130. In some embodiments, at least a portion of the metadata table may be cached. Figure 1 The memory subsystem controller 115 is located in the local memory 119.

[0087] In operation, upon receiving a read command, the memory subsystem controller determines the physical address corresponding to the logical block address (LBA) specified in the read command. For example, the physical address components of the physical block number and the die identifier are used to perform a metadata table traversal: first, the superblock table 710 identifies the block family identifier corresponding to the physical block number; then, the block family identifier is used as an index in the family table 720 to determine the threshold voltage offset interval associated with the block family and the die; finally, the identified threshold voltage offset interval is used as an index in the offset table 730 to determine the threshold voltage offset corresponding to the interval. The memory subsystem controller can then apply the identified threshold voltage offset superimposed to the base voltage read level to perform the requested read operation.

[0088] exist Figure 7 In an illustrative example, superblock table 710 maps partition 0 of superblock 0 to block family 4, which is used as an index to family table 720 to determine that die 0 is mapped to interval 2. The latter value is used as an index to an offset table to determine the threshold voltage offset value for interval 2.

[0089] Figure 8An example graph depicting the evolution of the error rate over time according to embodiments of the present disclosure is provided. The x-axis represents the time after programming. The y-axis represents the error rate associated with a read operation performed using an adjusted threshold voltage (i.e., a threshold offset voltage referenced by a threshold voltage offset range added to the base voltage read level). In embodiments, the error rate metric is the raw bit error rate (RBER). Line 810 represents the maximum permissible error rate. In embodiments, line 810 may be determined based on a trigger metric. A trigger metric refers to a measurement indicating the degree to which the memory device must enter error recovery or is related to said degree. In one embodiment, the trigger metric may be a trigger rate, which represents the share of codewords with an uncorrectable high error rate when read outside of the error handling process. Line 810 may be determined based on hard ECC correction capability, provided a predefined trigger rate requirement is met.

[0090] Line 816 represents the evolution of the error rate associated with a read operation performed using an adjusted threshold voltage as determined by embodiments of this disclosure. Figure 8 As shown, embodiments of this disclosure enable a memory subsystem controller to assign a threshold voltage offset set to a low threshold voltage offset interval (e.g., interval 0), such that a read operation performed at time 0 can have a suboptimal error rate not exceeding the maximum permissible error rate (i.e., line 810). As determined according to embodiments of this disclosure, the threshold voltage offset set associated with a low threshold voltage offset interval (e.g., interval 0) can simulate a large threshold voltage shift that a cell would experience at a higher TAP. During programming, the error rate of a read operation performed using a threshold voltage offset set determined according to embodiments of this disclosure can be high, for example, as shown below. Figure 8 The error rate is 820%. When the threshold voltage shifts along the voltage axis towards a lower threshold voltage in the post-programming time, the error rate associated with read operations performed using a threshold voltage offset set as determined according to embodiments of this disclosure can be reduced, such as... Figure 8 As shown in the illustration. In an embodiment, the threshold voltage may be shifted along the voltage axis to a threshold voltage such that when combined with a threshold voltage offset set as determined according to embodiments of the present disclosure, a lower error rate is produced, for example, as shown in the illustration. Figure 8 The error rate is shown in 822. That is, the set threshold voltage offset associated with a low threshold voltage offset interval (e.g., interval 0) cancels out the threshold voltage shift experienced by the block. As the threshold voltage continues to shift along the voltage axis, the error rate associated with read operations performed using a set of threshold voltage offsets determined according to embodiments of this disclosure may begin to increase, such as... Figure 8 As shown in the image.

[0091] As time passes and the charge in the programmed unit decreases, the threshold voltage associated with the low threshold voltage offset range can reduce the error rate before it increases again, such as Figure 8 As shown in the diagram. Therefore, the time required for the block family to reach the trigger rate required to move the block family to the next threshold voltage offset interval is extended. For example, an error rate of 824 may represent the trigger rate associated with moving the block family to the next threshold voltage offset interval. Once the error rate associated with a read operation performed using a set of threshold voltage offsets determined according to embodiments of this disclosure reaches error rate 824, the block family manager may associate the block family with another threshold voltage offset interval that will deliver an error rate lower than 824. By associating a low threshold voltage offset interval (e.g., interval 0) with a threshold voltage offset according to embodiments of this disclosure, the block family manager can extend the amount of time required to reach the error rate. For example, the block family may reach the trigger rate 6 hours after programming, instead of 1 hour after programming. Therefore, for example, if the memory subsystem performs 3 calibrations while the block family is in interval 0, then a conventional memory subsystem would perform a calibration every 20 minutes while the block family is in interval 0. Using the adjusted voltage read level of interval 0 according to embodiments of this disclosure, the memory subsystem controller may perform a calibration every 2 hours while the block family is in interval 0. Reducing the frequency of the calibration process frees up memory subsystem resources, thus reducing latency and improving system performance.

[0092] Figure 9 This is a flowchart of an example method 900 for determining a set of read level voltage offsets for a threshold voltage offset range according to some embodiments of the present disclosure. Method 900 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 900 is performed by… Figure 1 The block family manager component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0093] At operation 910, the processing logic creates a block family associated with the memory device. During block family creation, the processing logic may initialize the block family associated with the memory device and store the block family's identifier. The processing logic may initialize the timeout associated with the block family. In response to programming a block residing on the memory device, the processing logic may associate the block with the block family. In response to detecting a timeout expiration, the processing logic may close the block family.

[0094] In an embodiment, the processing logic may also initialize low and high temperatures associated with the block family to store the current temperature of a selected die of the memory device (e.g., a randomly selected die). In response to determining that the difference between the high and low temperature values ​​is greater than or equal to a specific temperature threshold, the processing logic may shut down the block family.

[0095] At operation 920, the processing logic associates a block family with a threshold voltage offset interval. In an embodiment, the processing logic associates a block family with a low threshold voltage offset interval (e.g., interval 0) during programming. The processing logic associates a block family with a threshold voltage offset interval by updating the block family metadata associated with the memory device. The block family metadata may contain a data structure, such as a table storing records. Each record in the table associates a block with a block family. About Figure 7 An instance that describes the metadata of a block family.

[0096] At operation 930, the processing logic determines and / or selects a set of read level voltage offsets from a plurality of sets such that a suboptimal error rate not exceeding the maximum permissible error rate is produced when the base read level threshold voltage associated with the block family is applied. In an embodiment, the error rate may be the raw bit error rate (RBER). The set of read level voltage offsets may be generated during the manufacture of the memory subsystem or during use of the memory subsystem.

[0097] The processing logic can perform a series of read operations against a block family using multiple voltage offset sets. Within this series of read operations, the processing logic can identify read operations that produce a bit error rate below the maximum permissible error rate within a predetermined interval. For example, the predetermined interval can be a predetermined share of the maximum permissible error rate (e.g., ½ or ¾). The processing logic can then determine and / or select the voltage offset set for performing the identified read operations, i.e., the read operations that produce the bit error rate within the predetermined interval.

[0098] In an embodiment, a maximum permissible bit error rate can be determined for a specific trigger metric and the hard-input ECC decoder correction capability. The trigger metric can refer to a measure indicating the degree to which the memory device must enter error recovery or is related to said degree. In an embodiment, the memory subsystem controller can set the maximum permissible bit error rate to a value below the hard-input ECC decoder correction capability while satisfying the trigger metric. For example, the maximum permissible bit error rate can be 5% lower than the hard-input ECC decoder correction capability to allow for an error margin.

[0099] At operation 940, the processing logic associates the read level voltage offset set with the threshold voltage offset interval. At operation 950, the processing logic updates the block family metadata associated with the memory device. The block family metadata may contain an offset table that associates the read level voltage offset with the corresponding threshold voltage offset interval. Figure 7 The image shows an example of an offset table.

[0100] At operation 960, the processing logic performs a series of calibrations over a threshold voltage offset interval. The calibration updates the interval pointer associated with the block family to point to the threshold voltage offset interval corresponding to a measurement of the data state metric (e.g., bit error rate). The time interval between two calibrations in the series is determined based on the time intervals that the block family has been associated with the threshold voltage offset intervals.

[0101] In an embodiment, the processing logic may receive a command specifying an identifier for a logical block. The processing logic may translate the logical block identifier into a physical address of a physical block stored on the memory device. The physical address may contain an identifier for the memory device die. In an illustrative example, the translation is performed by looking up the logical block identifier (also referred to as the logical block address or LBA) in a logic-to-physical (L2P) table associated with the memory device. The L2P table contains multiple mapping records, such that each mapping record maps an LBA to a corresponding physical address. For flash memory devices, the physical address may contain a channel identifier, die identifier, page identifier, plane identifier, and / or frame identifier.

[0102] The processing device identifies block families associated with physical addresses based on block family metadata associated with the memory device. In an illustrative example, the processing device utilizes... Figure 7 The superblock table 710 is used to identify block families associated with physical addresses.

[0103] The processing device determines the threshold voltage offset associated with the block family and memory device die. In an illustrative example, the processing device utilizes... Figure 7 The block family table 720 determines the interval identifier corresponding to the combination of the block family identifier and the die identifier. The processing device then utilizes... Figure 7 The offset table 730 determines the threshold voltage offset for the identified threshold voltage offset range. The processing device calculates the modified threshold voltage by applying the identified threshold voltage offset to the base read level voltage associated with the memory device. As mentioned above, the base read level voltage may be stored in the metadata area of ​​the memory device. The processing device uses the calculated modified threshold voltage to perform the requested read operation.

[0104] Figure 10This is a flowchart of an example method 1000 for determining a set of read level offsets for a read operation according to some embodiments of the present disclosure. Method 1000 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 1000 is performed by… Figure 1 The block family manager component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0105] At operation 1010, the processing logic identifies a block associated with the memory device. In one embodiment, the processing logic may identify a block specified in a read request received from the host. Alternatively, the processing logic may identify a block to which memory management operations are to be performed.

[0106] At operation 1020, the processing logic performs a series of read operations on the block using multiple voltage offset sets. Each read operation in the series uses one of the voltage offset sets. Each voltage offset set contains the voltage offset for each valley value of the memory cell being read. Multiple voltage offset sets may be stored within the memory subsystem or may be constructed by the memory subsystem controller.

[0107] At operation 1030, the processing logic identifies a first read level voltage offset set among multiple read level voltage sets. This first read level voltage offset set, when applied to the base read level voltage associated with the block, produces a suboptimal error rate not exceeding the maximum permissible error rate.

[0108] The processing logic can identify, from a series of read operations, read operations that produce a bit error rate below the maximum permissible error rate within a predetermined interval. For example, the predetermined interval may be a predetermined share of the maximum permissible error rate (e.g., ½ or ¾). The processing logic can then determine a set of voltage offsets for performing the identified read operations, i.e., read operations that produce the bit error rate within the predetermined interval.

[0109] In an embodiment, the maximum permissible error rate may be a hard-decoding error level used for a predefined trigger metric. The trigger metric may refer to a measure indicating the degree to which the memory device must enter error recovery or related to said degree. In an embodiment, the memory subsystem controller may set the maximum permissible bit error rate to a value below the hard-input ECC decoder correction capability in terms of error level. For example, the maximum permissible bit error rate may be 5% lower than the hard-input ECC decoder correction capability to allow for error tolerance.

[0110] At operation 1040, the processing logic determines that the read operation is a background operation. For example, the read operation may be part of a memory management operation of the memory subsystem controller, such as a normal state read. In response to determining that the read operation is a background operation, the processing logic identifies a second read level voltage offset set. This second read level voltage offset set produces an error rate below a threshold when applied to the base read level voltage associated with the block. The threshold may be set to minimize the error rate associated with a read operation performed as a background operation (e.g., a normal state read).

[0111] In an embodiment, the processing logic may assign a special read mode to certain background operations, such as normal state reads. When a special read mode is executed, the processing logic may determine the read offset level that produces the lowest error rate when applied to the base read level voltage associated with the block being read.

[0112] At operation 1050, the processing logic calculates the modified threshold voltage by applying either a first read level voltage offset set or a second read level voltage offset set to the base read level voltage associated with the block. The processing logic may apply the second read level voltage offset set in response to determining that the read operation is a background operation; otherwise, the processing logic may apply the first read level voltage offset set. At operation 1060, the processing logic reads data from the block using the modified threshold voltage.

[0113] In an embodiment, the processing logic may determine a threshold voltage offset range associated with the identified block and may associate a first read level voltage offset set with the threshold voltage offset range. The processing logic may associate the first read level voltage offset set with the threshold voltage offset range by updating block family metadata associated with the memory device. The block family metadata may include an offset table that associates read level voltage offsets with corresponding threshold voltage offset ranges. Figure 7 The image shows an example of an offset table.

[0114] In an embodiment, the processing logic may identify the physical address of the identified block stored on the memory device. The physical address may contain an identifier of the memory device die. The processing logic may identify the block family associated with the physical address based on block family metadata associated with the memory device. The processing logic may identify a threshold voltage offset range associated with the block family based on the block family metadata associated with the memory device. The block family metadata may contain multiple records, and each record may associate a block with a block family.

[0115] Figure 11 This is for an instance read level voltage offset set determined according to some embodiments of this disclosure. The interval offset calibration process determines a read level voltage offset set that produces a suboptimal error rate not exceeding the maximum permissible error rate, thus extending the time period associated with a given block family with a specific threshold voltage offset interval. Figure 11 The example set N 1101 for reading level voltage offsets is shown. This example set of reading level voltage offsets is for three-level cell (TLC) and therefore has 7 valleys 1105. It should be noted that the set for single-level cell (SLC) will have 1 valley, the set for multi-level cell (MLC) will have 3 valleys, the set for four-level cell (QLC) will have 15 valleys, and so on. Furthermore, in Figure 11 In the example shown, the set has 8 intervals 1103. The letters a through z represent the read level voltage offset. It should be noted that letters a through z are examples; some valleys and read level voltage offsets within intervals may be the same, or they may all be different. Figure 11 Compared to what is shown, there may be more or fewer different read level voltage offsets (that is, the read level voltage offset is not limited to). Figure 11 (The 26 a to z values ​​shown).

[0116] In this example, the memory subsystem controller has determined that: when read level voltage offset a is applied to valley 1 of the TLC associated with interval 0, a suboptimal error rate not exceeding the maximum permissible error rate is produced; when read level voltage offset b is applied to valley 2 of the TLC associated with interval 0, a suboptimal error rate not exceeding the maximum permissible error rate is produced; when read level voltage offset d is applied to valley 3 of the TLC associated with interval 0, a suboptimal error rate not exceeding the maximum permissible error rate is produced; and so on. Therefore, associating the block family with set N 1101 extends the time period during which the block family will be in interval 0, thus reducing the frequency of the calibration process and improving overall system performance.

[0117] Figure 12An example machine is shown as a computer system 1200, within which an executable instruction set is provided to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1200 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., run an operating system to perform corresponding...). Figure 1 (Operation of the block family manager component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0118] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute (one or more) sets of instructions to perform any one or more of the methods discussed herein.

[0119] Example computer system 1200 includes processing devices 1202 that communicate with each other via bus 1230, main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 1218.

[0120] Processing device 1202 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein. Computer system 1200 may further include a network interface device 1208 for communication via network 1220.

[0121] Data storage system 1218 may include machine-readable storage medium 1224 (also referred to as computer-readable medium) on which one or more instructions 1226 or software embodying any one or more of the methods or functions described herein are stored. Instructions 1226 may also reside wholly or at least partially within main memory 1204 and / or processing device 1202 during execution by computer system 1200, the main memory 1204 and processing device 1202 also constituting the machine-readable storage medium. Machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 may correspond to... Figure 1 The memory subsystem 110.

[0122] In one embodiment, instruction 1226 includes instructions for implementing a component corresponding to a block family manager (e.g., Figure 1 The block family manager component 113) provides functional instructions. Although the machine-readable storage medium 1224 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions that can be executed by a machine and causing a machine to perform any one or more of the methods disclosed herein. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0123] Some parts of the previously described algorithms and symbolic representations of operations on data bits in computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for common use, it has proven convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0124] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage systems of a computer system.

[0125] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, compact disc read-only memory (CD-ROM) and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0126] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to execute the methods. Structures for various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0127] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0128] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for a memory sub-system, comprising: creating a block family associated with a memory device; associating the block family with a threshold voltage offset interval; determining a set of read level voltage offsets that produce a sub-optimal error rate that does not exceed a maximum allowable error rate when applied to a base read level threshold voltage associated with the block family, wherein the sub-optimal error rate exceeds a minimum error rate for the block family; and associating the set of read level voltage offsets with the threshold voltage offset interval.

2. The method of claim 1, wherein associating the set of read level voltage offsets with the threshold voltage offset interval comprises: updating block family metadata associated with the memory device, wherein the block family metadata comprises an offset table comprising a plurality of records, wherein a record of the plurality of records associates a set of read level voltage offsets with a corresponding threshold voltage offset interval.

3. The method of claim 1, wherein creating the block family associated with the memory device comprises: initializing the block family associated with the memory device; initializing a timeout associated with the block family; in response to programming a block resident on the memory device, associating the block with the block family; and in response to detecting that the timeout expires, closing the block family.

4. The method of claim 1, wherein associating the block family with the threshold voltage offset interval comprises: updating block family metadata associated with the memory device, wherein the block family metadata comprises a table comprising a plurality of records, and wherein a record of the plurality of records associates a block family with a threshold voltage offset interval.

5. The method of claim 1, wherein determining the set of read level voltage offsets that produce the sub-optimal error rate that does not exceed the maximum allowable error rate when applied to the base read level threshold voltage associated with the block family comprises: performing a series of read operations for the block family using a plurality of sets of voltage offsets; identifying, among the series of read operations, a read operation that produces a bit error rate within a predetermined interval that is lower than the maximum allowable error rate; and determining a set of voltage offsets of the plurality of sets of voltage offsets used to perform the identified read operation.

6. The method of claim 1, further comprising: performing a series of calibrations for the threshold voltage offset interval, wherein a time period between two calibrations of the series of calibrations is determined based on a time period for which the block family has been associated with the threshold voltage offset interval.

7. The method of claim 2, further comprising: receiving a read command specifying an identifier of a logical block; translating the identifier of the logical block to a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; based on block family metadata associated with the memory device, identifying the block family associated with the physical address; determining a threshold voltage offset associated with the block family and the memory device die; computing a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and reading data from the physical block using the modified threshold voltage.

8. A system for a memory sub-system, comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: identifying a block associated with the memory device; performing a series of read operations for the block using a plurality of read level voltage offset sets; and identifying a read level voltage offset set of the plurality of read level voltage offset sets, wherein the read level voltage offset set, when applied to a base read level voltage associated with the block, results in a sub-optimal error rate that does not exceed a maximum allowable error rate, wherein the sub-optimal error rate exceeds a minimum error rate for the block.

9. The system of claim 8, further comprising: determining a read operation is a background operation; in response to determining the read operation is the background operation, identifying a second read level voltage offset set of the plurality of read level voltage offset sets, wherein the second read level voltage offset set, when applied to the base read level voltage associated with the block, results in a lowest error rate; computing a modified threshold voltage by applying the second read level voltage offset set to the base read level voltage associated with the block; and reading data from the block using the modified threshold voltage.

10. The system of claim 8, further comprising: determining a threshold voltage offset interval associated with the block; associating the read level voltage offset set with the threshold voltage offset interval by updating block family metadata associated with the memory device, wherein the block family metadata comprises an offset table comprising a plurality of records, wherein a record of the plurality of records associates a read level voltage offset set with a corresponding threshold voltage offset interval.

11. The system of claim 10, determining the threshold voltage offset interval associated with the block comprises: identifying a physical address of the block stored on the memory device, wherein the physical address comprises an identifier of the memory device die; based on block family metadata associated with the memory device, identifying a block family associated with the physical address; and based on the block family metadata associated with the memory device, identifying a threshold voltage offset interval associated with the block family, wherein the block family metadata comprises a table comprising a plurality of records, and wherein a record of the plurality of records associates the block with the block family.

12. The system of claim 11, further comprising: computing a modified threshold voltage by applying the read level voltage offset set to the base read level voltage associated with the memory device die; and reading data from the block using the modified threshold voltage.

13. The system of claim 11, further comprising: performing a series of calibrations for the threshold voltage shift interval, wherein a time period between two calibrations of the series of calibrations is determined based on a time period for which the block family has been associated with the threshold voltage shift interval.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: creating a block family associated with a memory device; associating the block family with a threshold voltage shift interval; determining a set of read level voltage shifts such that when applied to a base read level threshold voltage associated with the block family, produces a sub-optimal error rate that does not exceed a maximum allowable error rate, wherein the sub-optimal error rate exceeds a minimum error rate for the block family; and associating the set of read level voltage shifts with the threshold voltage shift interval.

15. The non-transitory computer-readable storage medium of claim 14, wherein associating the set of read level voltage shifts with the threshold voltage shift interval comprises: updating block family metadata associated with the memory device, wherein the block family metadata comprises a shift table comprising a plurality of records, wherein a record of the plurality of records associates a set of read level voltage shifts with a corresponding threshold voltage shift interval.

16. The non-transitory computer-readable storage medium of claim 14, wherein creating the block family associated with the memory device comprises: initializing the block family associated with the memory device; initializing a timeout associated with the block family; in response to programming a block resident on the memory device, associating the block with the block family; and in response to detecting expiration of the timeout, closing the block family.

17. The non-transitory computer-readable storage medium of claim 14, wherein associating the block family with the threshold voltage shift interval comprises: updating block family metadata associated with the memory device, wherein the block family metadata comprises a table comprising a plurality of records, and wherein a record of the plurality of records associates a block family with a threshold voltage shift interval.

18. The non-transitory computer-readable storage medium of claim 14, wherein determining the set of read level voltage shifts such that when applied to the base read level threshold voltage associated with the block family, produces the sub-optimal error rate that does not exceed the maximum allowable error rate comprises: performing a series of read operations for the block family using a plurality of sets of voltage shifts; identifying, among the series of read operations, a read operation that produces a bit error rate between a threshold and the maximum allowable error rate; and determining a set of voltage shifts of the plurality of sets of voltage shifts used to perform the identified read operation.

19. The non-transitory computer-readable storage medium of claim 14, further comprising: performing a series of calibrations for the threshold voltage shift interval, wherein a time period between two calibrations of the series of calibrations is determined based on a time period for which the block family has been associated with the threshold voltage shift interval.

20. The non-transitory computer readable storage medium of claim 15, further comprising: receiving a read command that specifies an identifier of a logical block; translating the identifier of the logical block to a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identifying, based on block family metadata associated with the memory device, the block family associated with the physical address; determining a threshold voltage offset associated with the block family and the memory device die; computing a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and reading data from the physical block using the modified threshold voltage. ​

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