Etching Method of Channel, Semiconductor Device, Preparation Method Thereof and Electronic Device

Abstract

The present invention provides an etching method for a channel. A to-be-etched object is provided. After the to-be-etched object is etched once, surface treatment-secondary etching is alternately performed until the sacrificial layers of all fin structures are etched away. Among them, the first etching is used to etch away all the sacrificial layers of the fin structure with the smallest current width among the several fin structures and part of the sacrificial layers of other fin structures with wider widths. The surface treatment is used to form a protective layer on the exposed surface of the channel layer and the remaining sacrificial layers of the to-be-etched object. The secondary etching is used to etch away all the sacrificial layers of the fin structure with the second smallest current width and the protective layer. The present invention adds an oxidation step to the traditional etching process, which not only realizes the protection of the channel layer but also reduces the loss of the channel layer during etching with different channel widths.

Description

Technical Field

[0001] The present invention relates to an etching field, and particularly to an etching method for a channel, a semiconductor device, a preparation method thereof, and an electronic device. Background Art

[0002] With the continuous advancement of Moore's Law, after the semiconductor process develops to the 3nm node, the GAAFET gate-all-around transistor is considered an effective alternative to the FinFET fin-type transistor.

[0003] High-performance logic devices tend to adopt nanosheet gate-all-around transistors. The nanosheet gate-all-around transistor obtains a horizontally stacked nanosheet channel by selectively etching away the channel sacrificial layer, which requires the selective etching process to have a very high etching selectivity between the channel material and the channel sacrificial layer material to reduce the loss of the channel material during the process of etching away the channel sacrificial layer. The loss of the channel material will bring a series of subsequent negative impacts on the performance of the gate-all-around transistor.

[0004] Currently, the most recognized technical solution in the industry is to use a dry etching process for one-step etching. It is impossible to ensure that the loss of the channel sacrificial layer material is very small while realizing the etching of nanosheets with different widths along the channel direction. Moreover, after the etching process is completed, the channel layer material of the transistor with a smaller channel width will have serious losses.

[0005] To achieve current matching between N-type GAAFET and P-type GAAFET, stress engineering needs to be introduced in the P-type GAAFET, that is, SiGe with stress is epitaxially grown in the Source and Drain regions of the P-type GAAFET. The epitaxial SiGe, as a stress source, will apply compressive stress to the channel, thereby improving the hole mobility in the channel and achieving current matching between N-type GAAFET and P-type GAAFET.

[0006] According to different applications, the channel length and width of the GAAFET will be adjusted accordingly. In some applications, the channel length of the GAAFET needs to be much larger than the GAAFET channel length under normal size scaling rules, such as the input / output transistor (I / O transistor). When manufacturing these GAA-structured transistors using the back-gate process, after the channel release step in the P-type GAAFET, the channel layer will deform and the phenomenon of channel collapse will occur.

[0007] Therefore, when etching fin structures with different widths and lengths existing simultaneously, the problems of channel layer loss and deformation and collapse have become technical problems that the industry urgently needs to solve. Summary of the Invention

[0008] The present invention provides an etching method for a channel, a semiconductor device, a manufacturing method thereof, and an electronic device, so as to solve the problems of deformation and collapse of the channel layer caused by too fast stress release, and to realize the etching of fin structures with different channel widths on the premise of ensuring very little Si loss.

[0009] According to a first aspect of the present invention, there is provided an etching method for a channel of a gate-all-around transistor, which is used for etching a sacrificial layer of a fin structure of the gate-all-around transistor to release the channel layer; the method includes:

[0010] Adopting a multi-step etching method to remove the sacrificial layer.

[0011] According to a second aspect of the present invention, there is provided an etching method for a channel, including:

[0012] S1: Providing an object to be etched, where the object to be etched includes a plurality of fin structures formed on a substrate, each fin structure includes an overlapping sacrificial layer and a channel layer, and the widths of the plurality of fin structures in the channel direction are different;

[0013] S2: After performing a first etching on the object to be etched, alternately performing surface treatment - second etching until all the sacrificial layers of the fin structures are etched away; both the first etching and the second etching respectively include the multi-step etching;

[0014] Wherein, the first etching is used to etch away all the sacrificial layers of the fin structure with the smallest current width among the plurality of fin structures and part of the sacrificial layers of other fin structures with wider widths;

[0015] The surface treatment is used to form a protective layer on the exposed surfaces of the channel layer and the remaining sacrificial layer of the object to be etched;

[0016] The second etching is used to etch away all the sacrificial layers of the fin structure with the second smallest current width, part of the sacrificial layers of other fin structures with larger current widths, and the protective layer.

[0017] Optionally, the surface treatment is an oxidation treatment, and the protective layer is an oxide layer.

[0018] Optionally, the number of the fin structures is two, specifically a first fin structure formed in a first region on the substrate and a second fin structure formed in a second region on the substrate; the first fin structure includes an overlapping first sacrificial layer and a first channel layer, and the second fin structure includes an overlapping second sacrificial layer and a second channel layer; the width of the first sacrificial layer and the first channel layer in the channel direction is smaller than the width of the second sacrificial layer and the second channel layer in the channel direction;

[0019] Perform a first etching on the object to be etched to etch away all of the first sacrificial layer and part of the second sacrificial layer;

[0020] Form an oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched;

[0021] Perform a second etching on the object to be etched to etch away all of the sacrificial layer on the second region and the oxide layer.

[0022] Optionally, the etching time of the first etching matches the etching time required to completely remove the first sacrificial layer.

[0023] Optionally, the etching time of the second etching matches the etching time required to completely remove the remaining part of the second sacrificial layer.

[0024] Optionally, forming the oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched includes:

[0025] Form the oxide layer by plasma oxidation or thermal oxidation.

[0026] Optionally, the material of the channel layer is Si, and the material of the sacrificial layer is SiGe.

[0027] Optionally, when performing the second etching on the object to be etched, it further includes: etching away the surface layer part of the channel layer covered by the remaining sacrificial layer after the first etching.

[0028] Optionally, performing a first etching on the object to be etched to etch away all of the first sacrificial layer and part of the second sacrificial layer; includes:

[0029] Perform a first etching on the object to be etched by a first etching method.

[0030] Optionally, performing a second etching on the object to be etched includes:

[0031] Perform a second etching on the object to be etched by a first etching method.

[0032] Optionally, performing a second etching on the object to be etched includes:

[0033] Perform a second etching on the object to be etched by a second etching method; wherein, the etching selectivity of the second etching method is less than the etching selectivity of the first etching method.

[0034] According to the third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including:

[0035] Any one of the above-mentioned channel etching methods.

[0036] According to the fourth aspect of the present invention, the present invention further provides a semiconductor device, including: prepared by using the preparation method of the above semiconductor device.

[0037] According to the fifth aspect of the present invention, the present invention further provides an electronic device, including a semiconductor device according to the fourth aspect above.

[0038] An etching method for a channel of a gate-all-around transistor provided by the present invention adopts a multi-step etching method to remove the sacrificial layer in the fin structure of the gate-all-around transistor, so that for the fin structure of the gate-all-around transistor, the channel layer in the fin structure is stepped, and the compressive stress is released step by step, thereby achieving the purpose of slowly releasing the compressive stress, and solving the problems of deformation and collapse of the channel layer caused by too fast release of the compressive stress.

[0039] In an etching method for a channel, a semiconductor device, a preparation method thereof, and an electronic device provided by the present invention, when etching a channel, first perform the first etching on the object to be etched to etch away all the sacrificial layers of the fin structure with the smallest current width among the plurality of fin structures and part of the sacrificial layers of other fin structures with wider widths; then form a protective layer on the exposed surfaces of the channel layer and the remaining sacrificial layer of the object to be etched; perform a second etching on the object to be etched to etch away all the sacrificial layers of the fin structure with the second smallest current width, part of the sacrificial layers of other fin structures with larger current widths, and the protective layer; that is: after the first etching, alternately perform surface treatment - second etching until all the sacrificial layers of the fin structures are etched away; it can be seen that for fin structures with multiple widths, a surface treatment process step is added before each second etching, so that the protective layer formed on the surface of the channel layer realizes the protection of the channel layer, and effectively etches fin structures with different nanosheet channel widths on the premise of ensuring very little material loss of the channel layer, and solves the problem of etching fin structures with different channel widths on the premise of ensuring very little Si loss; at the same time, both the first etching and the second etching include multi-step etching, so that for each fin structure with a width along the channel direction, the stress of the epitaxial layers on both sides of the fin structure is released step by step, thereby achieving the purpose of slowly releasing the stress, and solving the problems of deformation and collapse of the channel layer caused by too fast release of the stress. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for describing the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0041] Figure 1 It is a schematic diagram of the etching steps of an etching method for a channel of the present invention;

[0042] Figure 2 It is a schematic diagram of the etching steps of an etching method for a channel in an embodiment of the present invention;

[0043] Figures 3(a)-(b) are schematic diagrams of different stages in the channel region in an embodiment of the present invention Figure 1 ;

[0044] Figures 4(a)-(b) are schematic diagrams of different stages in the channel region in an embodiment of the present invention Figure 2 ;

[0045] Figures 5(a)-(b) are the third schematic diagrams of different stages in the channel region in an embodiment of the present invention;

[0046] Figures 6(a)-(b) are the fourth schematic diagrams of different stages in the channel region in an embodiment of the present invention;

[0047] Figure 7 It is a schematic diagram of the channel direction in an embodiment of the present invention.

[0048] Explanation of reference numerals:

[0049] 1011 - First channel layer;

[0050] 1012 - First sacrificial layer;

[0051] 1021 - Second channel layer;

[0052] 1022 - Second sacrificial layer;

[0053] 1013 - Substrate;

[0054] 1023 - Substrate;

[0055] 1122 - Part of the second sacrificial layer;

[0056] 1211 - Oxide layer. Detailed implementation manners

[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0058] In the specification, claims and the above-mentioned drawings of the present invention, the terms "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0059] With the continuous advancement of Moore's Law, after the semiconductor process develops to the 3nm node, the GAAFET gate-all-around transistor is considered an effective alternative to the FinFET fin field-effect transistor. According to the different channels of the GAAFET gate-all-around transistor, it is further divided into nanowire type and nanosheet type. Since the nanosheet has a larger channel width than the nanowire, high-performance logic devices tend to use the nanosheet gate-all-around transistor. The nanosheet gate-all-around transistor obtains a horizontally stacked nanosheet channel by selectively etching away the channel sacrificial layer, which requires a high etching selectivity between the channel material and the channel sacrificial layer material in the selective etching process to reduce the loss of the channel material during the process of removing the channel sacrificial layer by the etching process. The loss of the channel material will bring a series of subsequent negative impacts on the performance of the gate-all-around transistor.

[0060] When the transistor structure changes from FinFET to GAAFET, the hole mobility in the channel is much lower than the electron mobility, that is to say, the current of the NMOS with the same size is much higher than that of the PMOS. To achieve the current balance between the NMOS and the PMOS, there is currently a technical solution to set different widths of nanosheets for the NMOS and the PMOS respectively to achieve different effective channel widths, where the channel width of the PMOS is greater than that of the NMOS. The Si / SiGe stacked wafer structure means that there are transistors with different channel widths in the same area, which brings a problem that different widths of Si / SiGe stacks need to be etched simultaneously. Low-power type devices require a relatively narrow nanosheet width to reduce leakage current; high-performance computing type devices require a relatively wide nanosheet width to increase the drive current. This also requires simultaneous etching of Si / SiGe stacks with different widths.

[0061] However, when Si / SiGe stacks with different widths coexist, the condition for traditional etching technology to achieve a high selectivity in etching the Si / SiGe stack is that the Si / SiGe stack exists simultaneously during the etching process. When the SiGe material is completely removed, the etching rate of Si by traditional etching technology will increase sharply, resulting in the loss of the channel layer in the narrow channel.

[0062] Therefore, when Si / SiGe stacks with different widths coexist, the prior art does not provide a method to solve the problem of channel layer loss.

[0063] In addition, to achieve current matching between the N-type gate-all-around field-effect transistor (GAAFET) and the P-type GAAFET, stress engineering needs to be introduced in the P-type GAAFET, that is, SiGe with stress is epitaxially grown in the source and drain regions of the P-type device. The epitaxial SiGe, as a stress source, will apply compressive stress to the channel, thereby enhancing the hole mobility in the channel and achieving current matching between the N-type GAAFET and the P-type GAAFET.

[0064] According to different applications, the channel length and width of the GAAFET will be adjusted accordingly. In some applications, the channel length of the GAAFET needs to be much larger than that of the GAAFET under normal size scaling rules. The channel length is Figure 7 the length in the X direction in, such as the input / output transistor (I / O transistor). When manufacturing these GAA-structured transistors using the back-gate process, after the channel release step in the P-type gate-all-around transistor GAAFET, the channel layer will deform, and even channel collapse may occur, that is, adjacent nanosheets are squeezed together. The compressive stress from the source and drain regions to the channel is the cause of the channel collapse in the P-type GAA channel. The characteristic of the back-gate process is that the SiGe epitaxial step in the source and drain regions is before the channel release process step, that is, the channel has been subjected to the compressive stress from the source and drain regions before the channel release process. Only because the sacrificial layer supports the channel before the channel release process, the channel will not deform due to the compressive stress from the source and drain regions. However, when the sacrificial layer in the channel region is removed during the release process, the channel loses the support of the sacrificial layer, and the compressive stress applied by the source and drain regions to the channel leads to the deformation of the channel layer and the occurrence of channel collapse.

[0065] And the prior art does not propose a means to solve the problem of channel deformation and collapse caused by stress release.

[0066] The technical solutions of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0067] To solve the above problems, the present technical solution is proposed as follows: According to an embodiment of the present invention, there is provided an etching method for a channel of a gate-all-around transistor, which is used to etch a sacrificial layer of a fin structure of the gate-all-around transistor to release a channel layer; including:

[0068] Adopt a multi-step etching method to remove the sacrificial layer.

[0069] Among them, the gate-all-around transistor is manufactured by a back-gate process, and the channel layer in the fin structure is subjected to a large stress from the source-drain region. If a traditional single-step process for releasing the channel layer is used, the channel layer will be released too quickly, resulting in deformation and collapse of the channel layer;

[0070] The present technical solution divides the traditional single-step process for releasing the channel layer into multiple steps. In this way, the compressive stress applied by the source-drain region to the channel layer will be slowly applied to the channel layer, which can avoid deformation and collapse of the channel layer. Please refer to Figure 1 , an embodiment of the present invention provides an etching method for a channel, including:

[0071] Step S1: Provide an object to be etched, the object to be etched includes a plurality of fin structures formed on a substrate, each fin structure includes an overlapping sacrificial layer and a channel layer, and the widths of the plurality of fin structures in the channel direction are different;

[0072] Step S2: After alternately performing a first etching on the object to be etched, alternately perform surface treatment - second etching until all the sacrificial layers of the fin structures are etched away; both the first etching and the second etching respectively include the multi-step etching;

[0073] Among them, the first etching is used to etch away all the sacrificial layers of the fin structure with the smallest current width among the plurality of fin structures and part of the sacrificial layers of other fin structures with wider widths;

[0074] The surface treatment is used to form a protective layer on the exposed surfaces of the channel layer and the remaining sacrificial layer of the object to be etched;

[0075] The second etching is used to etch away all the sacrificial layers of the fin structure with the second smallest current width, part of the sacrificial layers of other fin structures with larger current widths, and the protective layer.

[0076] The fin structure with the second smallest current width refers to: the fin structure width is only larger than the fin structure with the smallest current width; arrange the current widths of the fin structures in ascending order, and the fin structure whose order is second to the fin structure with the smallest current width.

[0077] Among them, for fin structures of multiple widths, step S2 specifically includes: after one etching, cyclically performing the steps of - surface treatment - secondary etching until the sacrificial layer in all fin structures is etched away; the one etching etches away all the sacrificial layer of the fin structure with the smallest current width, and part of the sacrificial layer of other fin structures with a larger current width. During the secondary etching, all the sacrificial layer of the fin structure with the second smallest current width and part of the sacrificial layer of other fin structures with a larger current width are etched away, and then surface treatment is performed. In the next cycle, all the sacrificial layer of the fin structure with the second smallest current width and part of the sacrificial layer of other fin structures with a larger current width are included in the part of the sacrificial layer of other fin structures with a larger current width in the previous cycle.

[0078] The number of fin structures with the smallest current width, and the number of other fin structures with a wider width for each width, can both be greater than or equal to 1;

[0079] In one implementation, there is only one fin structure for each width;

[0080] In other implementations, the number of fin structures of any width can be multiple;

[0081] The one etching and each secondary etching finish etching the sacrificial layer of a fin structure with one width;

[0082] In this technical solution, a surface treatment step is added after the one etching and after each secondary etching, so that after the channel layer of each width of fin structure is completely released, before etching the sacrificial layer of other widths in the next etching, there is a protective layer to protect the released channel layer, realizing high-selectivity etching of the channel layer and the sacrificial layer;

[0083] The multi-step etching means that for each fin structure with a specific width, during one etching process, the sacrificial layer of the fin structure with the smallest current width is etched in several steps until completion, and the stress of the epitaxial layers on both sides of the fin structure is released step by step, so as to achieve the purpose of slowly releasing stress and avoid deformation and collapse of the channel layer caused by too rapid stress release; for the fin structure with the second smallest current width and a part of the sacrificial layer of other fin structures with a wider current width, of course, multi-step etching is also performed; after surface treatment, during the second etching, all the sacrificial layer in the fin structure with the second smallest current width is etched in steps. Of course, a part of the sacrificial layer in other fin structures with a larger current width is also etched in multiple steps during this process; during the next surface treatment and the cycle of the second etching, the same effect is achieved. Thus, the channel layers in all fin structures with different widths in the entire device are all etched in multiple steps, and the stress of the epitaxial layers on both sides of the fin structure is released step by step, so that the entire device achieves the purpose of slowly releasing stress and avoids deformation and collapse of all channel layers in the entire device caused by too rapid stress release.

[0084] In one embodiment, the surface treatment is oxidation treatment, and the protective layer is an oxide layer.

[0085] In one implementation manner, the surface treatment method is oxidation treatment, and the protective layer is an oxide layer;

[0086] In another implementation manner, the surface treatment method can also be nitridation treatment, and the protective layer is a nitride layer; the surface treatment method can also be other similar treatment methods, as long as it can achieve the functions of the protective layer described in the present invention, it is within the protection scope of the present invention.

[0087] The present invention provides an embodiment. Taking oxidation treatment as the surface treatment method to form an oxide layer as an example, two fin structures with different widths are provided, which are divided into the first region and the second region. For the etching methods of fin structures with more width types, refer to this embodiment. The specific etching steps are as follows:

[0088] Please refer to Figure 2 and FIGS. 3(a)-(b), S10: Provide an object to be etched; the number of fin structures is two, specifically, a first fin structure formed in the first region (please refer to FIG. 3(a)) on the substrate 1013, and a second fin structure formed in the second region (please refer to FIG. 3(b)) on the substrate 1023; the first fin structure includes an overlapping first sacrificial layer 1012 and a first channel layer 1011, and the second fin structure includes an overlapping second sacrificial layer 1022 and a second channel layer 1021 formed on the substrate 1023; the width L1 of the first sacrificial layer and the first channel layer along the channel direction is smaller than the width L2 of the second sacrificial layer and the second channel layer along the channel direction;

[0089] S11: Perform a first etching on the object to be etched to etch away all of the first sacrificial layer and part of the second sacrificial layer;

[0090] S12: Form an oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched;

[0091] The channel layer in step S12 includes the first channel layer and the second channel layer;

[0092] S13: Perform a second etching on the object to be etched to etch away all of the sacrificial layer on the second region and the oxide layer.

[0093] Please refer to Figure 7 , the fin structure is located between the source 201 and the drain 202. Please refer to FIGS. 3(b) and Figure 7 , the width in the channel direction refers to the width in the direction indicated by the arrow in FIG. 3(b), that is, Figure 7 the Y direction in

[0094] Wherein, the substrate 1013 and the substrate 1023 may be the same substrate. For the convenience of description in this specification, the substrate in the first region is labeled as 1013, and the substrate in the second region is labeled as 1023.

[0095] The channel direction is as shown by the arrow direction in the figure.

[0096] The first sacrificial layer is disposed on the part to be etched in the first region;

[0097] The first channel layer is disposed on the part to be retained in the first region;

[0098] The second sacrificial layer is disposed on the part to be etched in the second region;

[0099] The second channel layer is disposed on the part to be retained in the second region;

[0100] In one embodiment, the first sacrificial layer and the first channel layer, and the second sacrificial layer and the second channel layer may form a nanosheet structure. Since nanosheets are more conducive to improving the performance of the object to be etched than nanowires, nanosheets are more preferably used.

[0101] In one embodiment, the first region refers to the region where the NMOS nanosheets are located, and the second region refers to the region where the PMOS nanosheets are located. The width L1 of the channel layer of the NMOS nanosheets in the channel direction is less than the width L2 of the channel layer of the PMOS nanosheets in the channel direction, that is: L2 is greater than L1. The width of the sacrificial layer of the NMOS nanosheets in the channel direction is less than the width of the sacrificial layer of the PMOS nanosheets in the channel direction.

[0102] In the above embodiments, the full English name of NMOS is N-Metal-Oxide-Semiconductor, which means N-type metal-oxide-semiconductor and is a component of a transistor; the full English name of PMOS is positive channel MetalOxide Semiconductor, which is an n-type substrate and a p-channel, and transports current by the flow of holes and is used to form a transistor.

[0103] In the above embodiments, since the current of NMOS nanosheets of the same size is much higher than that of PMOS nanosheets, in order to achieve the current balance between NMOS nanosheets and PMOS nanosheets, therefore, the width of the channel layer of the PMOS nanosheet along the channel direction and the width of the sacrificial layer along the channel direction are set to be greater than the width of the sacrificial layer and the channel layer of the NMOS nanosheet along the channel direction. Therefore, it is necessary to etch the channel layer and the sacrificial layer with different widths along the channel direction at the same time.

[0104] In this embodiment, after the first channel layer is released, an oxidation step is added so that after the first channel layer is released and before the second sacrificial layer is etched, there is a protective layer to protect the first channel layer, realizing high-selectivity etching of the channel layer and the sacrificial layer; of course, the second channel layer is also protected by the oxide layer;

[0105] The etching method adopted in this solution forms an oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched. The etching rate of the oxide layer on the surface of the channel layer is much lower than that of the channel layer itself, and the etching rate of the oxide layer on the surface of the channel layer is much lower than that of the oxide layer on the surface of the sacrificial layer. Experiments show that the natural oxide layer on the surface of the channel layer can protect the channel layer. Therefore, after the oxide layer on the surface of the sacrificial layer is etched, there is still the oxide layer on the surface of the channel layer to protect the channel layer when etching the channel layer. Therefore, the loss of the channel layer will be reduced. Thus, conditions are provided for improving the performance of the object to be etched.

[0106] The first etching completely releases the first channel layer; the second etching completely releases the second channel layer;

[0107] In this embodiment, the first etching and the second etching of course include the multi-step etching; the problems of channel layer deformation and collapse are solved.

[0108] In this embodiment, the fin structures with two widths are taken as an example for illustration, but the etching method of the present invention is not limited to the fin structures with two widths in this embodiment;

[0109] When a fin structure with three widths is included, it is also within the protection scope of the present invention. For the fin structure with three widths, specifically, it is not shown in the figure. For example, when the object to be etched contains three regions to be etched. For the sake of description, the three regions to be etched are respectively: A, B, C, and the widths along the channel direction are respectively: L1, L2, L3, and L3 > L2 > L1. Using the etching method of the solution of the present application, first perform a first etching to etch off the sacrificial layer of all region A, and part of the sacrificial layer of region B and part of the sacrificial layer of region C; then form an oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched; then perform a second etching to etch off the sacrificial layer of region B and part of the sacrificial layer of region C; then perform the second oxidation again; then perform the second etching again to etch off the remaining part of the sacrificial layer of all region C. When the object to be etched includes other numbers of regions to be etched, the above similar method is adopted.

[0110] Among several regions to be etched with different widths along the channel direction, the sacrificial layers of the regions to be etched with different widths along the channel direction are etched off in sequence in ascending order of the widths along the channel direction.

[0111] It can be seen from this that the etching method of the channel provided by the present application is not only applicable to the object to be etched with two different widths, but also applicable to the object to be etched with other numbers of fin structures with different current widths, (not only applicable to the fin structures with different current widths from each other, but also applicable to the fin structures with the same current width and the fin structures with different current widths included at the same time.) As long as the adopted etching method does not deviate from the concept of the present invention, it is within the protection scope of the present invention.

[0112] For each fin structure with a certain width, the first etching and the second etching of course also include the multi-step etching.

[0113] In one embodiment, the etching time of the first etching matches the etching time required for complete removal of the first sacrificial layer.

[0114] The matching here can be understood as being the same or similar. Please refer to FIGS. 4(a)-(b). In one embodiment, the time of the first etching matches the time for complete removal of the first sacrificial layer (please refer to FIG. 4(a)). That is: the part etched by the first etching includes all the first sacrificial layer and part of the second sacrificial layer 1122 (please refer to FIG. 4(b)), where only a small amount of the channel layer is lost.

[0115] In one embodiment, the etching time of the second etching matches the etching time required for complete removal of the remaining part of the second sacrificial layer.

[0116] The matching here can be understood as being the same or similar.

[0117] Please refer to FIGS. 6(a)-(b). For the structures of the first region and the second region after the second etching, please refer to FIGS. 6(a) and 6(b) respectively.

[0118] Please refer to FIGS. 5(a) and 5(b). In one embodiment, an oxide layer 1211 is formed on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched.

[0119] The formation of the oxide layer includes: forming the oxide layer by plasma oxidation, thermal oxidation or natural oxidation.

[0120] The oxide layer refers to the oxide layer formed after the oxidation process. In practice, the etched oxide layer also includes the natural oxide layer. The natural oxide layer is the oxide layer generated in the natural state.

[0121] In one embodiment, specifically, the oxidation method can adopt plasma oxidation or thermal oxidation.

[0122] In another embodiment, other suitable methods for generating the oxide layer can be adopted.

[0123] The thermal oxidation method therein is dry thermal oxidation or wet thermal oxidation.

[0124] In one embodiment, the thickness of the oxide layer is less than a specified threshold. The specified threshold refers to the thickness value of the oxide layer less than 1 nm. In practice, this thickness value is not limited to 1 nm and can be an allowable numerical range around this value. The thickness of the oxide layer is flexibly adjusted according to process requirements. It cannot be too thin or too thick. The thickness of the oxide layer is controlled to be able to protect the channel material in the subsequent etching process and can be just etched completely in the subsequent etching process.

[0125] Since the width of the second sacrificial layer along the channel direction is greater than the width of the first sacrificial layer along the channel direction, after the first sacrificial layer is completely etched, there is still a remaining part of the second sacrificial layer that needs to be etched. When etching the remaining part of the second sacrificial layer, since there is no first sacrificial layer in the first region, the first channel layer will also be etched, resulting in too much loss of the first channel layer, which will affect the performance of the object to be etched. In one embodiment of the present invention, an oxide layer is formed on the surface of the channel layer after the first etching. During the etching of the remaining part of the second sacrificial layer, the channel layer is protected, and the etching rate of the channel layer is reduced, thereby reducing the loss of the channel layer and providing conditions for the object to be etched to have good performance.

[0126] In one embodiment, the material of the channel layer is Si, and the material of the sacrificial layer is SiGe.

[0127] In one embodiment, when performing secondary etching on the object to be etched, it further includes: etching away the surface portion of the channel layer covered by the remaining sacrificial layer after the first etching.

[0128] Since an oxidation step is added before each secondary etching, the released channel layer is oxidized, so the thickness of the channel layer becomes narrower, while the channel layer covered by the remaining sacrificial layer is not oxidized and thus its thickness remains unchanged. For the second channel layer, there is a difference in thickness between the channel layer covered by the remaining sacrificial layer and the released channel layer. Therefore, the secondary etching needs to etch away the surface portion of the channel layer covered by the remaining sacrificial layer, that is, to eliminate the thickness difference, so that after removing the excess surface portion of the channel layer, the thickness of the second channel layer is consistent. When there are fin structures of more widths, similar steps are taken to make the thickness of each channel layer consistent, thereby improving the device performance.

[0129] Among them, by controlling the thickness of the oxide layer, it can be ensured that before the above-mentioned partial channel layer etching is completed, that is, before the vertical thickness of the channel layer with an oxide layer generated on the surface is the same as the vertical thickness of the channel layer without an oxide layer generated on the surface, the surface of the channel layer with an oxide layer generated on the surface is always protected by the oxide layer, so as to achieve the same vertical thickness. The vertical thickness refers to the thickness perpendicular to the channel direction.

[0130] In one embodiment, when performing primary etching on the object to be etched to etch away all of the first sacrificial layer and part of the second sacrificial layer, it includes:

[0131] Performing primary etching on the object to be etched by a first etching method.

[0132] Among them, the first etching method refers to an etching method with better selectivity for etching the sacrificial layer and the channel layer. Specifically, dry etching or wet etching can be used.

[0133] In one embodiment, when performing secondary etching on the object to be etched, it includes:

[0134] Performing secondary etching on the object to be etched by a first etching method.

[0135] In order to achieve the purpose of etching away the surface portion of the channel layer covered by the remaining sacrificial layer after the first etching, the same effect can be achieved by controlling the etching time. For example, the time of the secondary etching can be extended so that the corresponding channel layer portion is over-etched during the second etching.

[0136] In one implementation manner, dry etching is used to etch the object to be etched.

[0137] In another implementation manner, other methods, such as wet etching, can be used to etch the object to be etched.

[0138] Dry etching is a technique for etching using plasma.

[0139] In one implementation, preferably, dry etching is: etching the object to be etched based on F-based gases (such as NF3, CF4, etc.) and an RPS etching system. Among them, the dry etching technique based on F-based gases (such as NF3, CF4, etc.) and an RPS etching system is: (taking NF3 gas as an example) a dry etching technique with NF3 as the etching gas and RPS as the plasma source; the dry etching technique based on F-based gases (such as NF3, CF4, etc.) and an RPS etching system can achieve a very high Si / SiGe etching selectivity; among them, the prerequisite for this etching technique to achieve a very high Si / SiGe etching selectivity is that Si and SiGe materials should exist simultaneously during the etching process. That is to say, when Si and SiGe materials exist simultaneously, this etching technique preferentially etches the SiGe material, the etching rate of Si is very low, and finally, after the SiGe material is completely removed, the Si material is retained with only very little loss. This etching technique requires good control of the etching time to reduce the loss of the channel layer material Si.

[0140] Specifically, because the loss of the channel layer will bring a series of subsequent negative impacts on the performance of the gate-all-around transistor. Removing the sacrificial layer by selective etching to obtain a horizontally stacked channel layer requires that the selective etching process has a very high etching selectivity between the channel layer material and the sacrificial layer material to reduce the loss of the channel layer during the etching process of removing the sacrificial layer.

[0141] More specifically, since this application uses Si as the channel layer material and SiGe (the Ge concentration in SiGe is variable) as the sacrificial layer material. Among the publicly available technical solutions for Si / SiGe selective etching, the dry etching technique based on F-based gases (such as NF3, CF4, etc.) and an RPS etching system can achieve a very high selectivity. Therefore, this dry etching technique is used as the preferred etching technique.

[0142] Specifically, this etching technique can achieve a very high Si / SiGe etching selectivity, but there are also technical defects. Among them, the prerequisite for this etching technique to achieve a very high Si / SiGe etching selectivity is that both Si and SiGe materials should exist simultaneously during the etching process. That is to say, when both Si and SiGe materials exist, this etching technique preferentially etches the SiGe material, and the etching rate of Si is very low. Finally, after the SiGe material is completely removed, the Si material is retained with only very little loss; however, the current of NMOS nanosheets of the same size is much higher than that of PMOS nanosheets. To achieve the current balance between NMOS nanosheets and PMOS nanosheets, there is currently a technical solution to set different widths of nanosheets for NMOS nanosheets and PMOS nanosheets respectively, so as to achieve different widths along the channel direction, where the width of the PMOS nanosheet along the channel direction is greater than that of the NMOS nanosheet. When the SiGe material is completely etched away and only Si material remains, the etching rate of Si by this etching technique will increase sharply. It is necessary to etch Si / SiGe stacks with different widths simultaneously. If the traditional technical solution based on NF3 gas and RPS etching system is used, when the SiGe material in the channel region is completely etched and only Si material remains, the etching rate of the channel layer Si by the traditional etching technique will increase sharply. This results in that when the SiGe of the sacrificial layer of the transistor with a smaller width along the channel direction is completely etched, there is still some SiGe left in the sacrificial layer of the transistor with a larger width along the channel direction. Therefore, it is necessary to extend the etching time. At this time, the Si layer of the transistor with a smaller width along the channel direction is completely exposed to the etching environment (losing the protection of SiGe), and during this extended etching time, the loss of Si in this part increases sharply. Therefore, after the entire etching process is completed, there will be serious loss of Si in the channel layer with a smaller width along the channel direction. Therefore, this etching technique needs to well control the etching time to reduce the loss of the channel material Si. The etching scheme we adopted has an etching rate for the natural oxide layer on the Si surface that is much lower than that of Si itself. Similarly, the etching rate of the natural oxide layer on the SiGe surface by the etching scheme we adopted is also much lower than that of SiGe itself. At the same time, the etching rate of the natural oxide layer on the Si surface by the etching scheme we adopted is also much lower than that of the natural oxide layer on the SiGe surface. Based on this experimental phenomenon, an etching method for nanosheets with different widths along the channel direction is proposed in this application. It has successfully achieved the etching of nanosheets with different widths along the channel direction while ensuring very little loss of Si.

[0143] In other embodiments, other etching gases and plasma sources can be used.

[0144] As a preferred embodiment, performing a secondary etching on the object to be etched includes: performing a secondary etching on the object to be etched by a second etching method, where the etching selectivity of the second etching method is less than the etching selectivity of the first etching method.

[0145] Specifically, the second etching method can adopt an etching manner with a poor etching selectivity between the sacrificial layer and the channel layer, so that the etching rate of the channel layer is higher.

[0146] The secondary etching needs to etch away the surface layer part of the channel layer covered by the remaining sacrificial layer, that is, to eliminate the thickness difference; in one implementation manner, the above object is achieved by changing the etching method; the etching selectivity of the second etching method is less than the etching selectivity of the first etching method.

[0147] The present invention also provides a method for manufacturing a semiconductor device, including:

[0148] Any of the channel etching methods described above.

[0149] The present invention also provides a semiconductor device, characterized in that it is manufactured by using the method for manufacturing a semiconductor device described above.

[0150] The present invention also provides an electronic device, including the above semiconductor device.

[0151] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: various media such as ROM, RAM, magnetic disk, or optical disc that can store program codes.

[0152] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An etching method for a channel, characterized in that Including: S1: Provide an object to be etched, where the object to be etched includes a plurality of fin structures formed on a substrate, each fin structure includes an overlapping sacrificial layer and a channel layer, and the widths of the plurality of fin structures in the channel direction are different; S2: After performing a first etching on the object to be etched, alternately perform surface treatment - second etching until all the sacrificial layers of the fin structures are etched away; both the first etching and the second etching respectively include multiple steps of etching; Wherein, the first etching is used to etch away all the sacrificial layer of the fin structure with the smallest current width among the plurality of fin structures and part of the sacrificial layers of other fin structures with wider widths; The surface treatment is used to form a protective layer on the exposed surfaces of the channel layer and the remaining sacrificial layer of the object to be etched; The second etching is used to etch away all the sacrificial layer of the fin structure with the second smallest current width, part of the sacrificial layers of other fin structures with larger current widths, and the protective layer.

2. The etching method of the channel according to claim 1, wherein The surface treatment is an oxidation treatment, and the protective layer is an oxide layer.

3. The etching method of the channel according to claim 2, wherein The number of the fin structures is two, specifically a first fin structure formed in a first region on the substrate and a second fin structure formed in a second region on the substrate; the first fin structure includes an overlapping first sacrificial layer and a first channel layer, and the second fin structure includes an overlapping second sacrificial layer and a second channel layer; the width of the first sacrificial layer and the first channel layer in the channel direction is smaller than the width of the second sacrificial layer and the second channel layer in the channel direction; Perform a first etching on the object to be etched to etch away all the first sacrificial layer and part of the second sacrificial layer; Form an oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched; Perform a second etching on the object to be etched to etch away all the sacrificial layer on the second region and the oxide layer.

4. The etching method of the channel according to claim 3, wherein, The etching time of the first etching matches the etching time required for completely removing the first sacrificial layer.

5. The etching method of the channel according to claim 3 or 4, characterized in that The etching time of the second etching matches the etching time required for completely removing the remaining part of the second sacrificial layer.

6. The etching method of the channel according to claim 3, wherein Forming the oxide layer on the exposed surfaces of the remaining sacrificial layer and the channel layer of the object to be etched includes: Forming the oxide layer by means of plasma oxidation or thermal oxidation.

7. The etching method of the channel according to claim 3, wherein The material of the channel layer is Si, and the material of the sacrificial layer is SiGe.

8. The etching method of the channel according to claim 3, characterized in that, Performing a second etching on the object to be etched further includes: etching away the surface layer part of the channel layer covered by the remaining sacrificial layer after the first etching.

9. The etching method of the channel according to claim 8, wherein Performing a first etching on the object to be etched to etch away all the first sacrificial layer and part of the second sacrificial layer; includes: Performing a first etching on the object to be etched by a first etching method.

10. The etching method of the channel according to claim 9, wherein Performing a second etching on the object to be etched includes: The object to be etched is subjected to secondary etching by a first etching method.

11. The etching method of the channel according to claim 9, characterized in that The secondary etching of the object to be etched includes: The object to be etched is subjected to secondary etching by a second etching method; wherein, the etching selectivity of the second etching method is less than that of the first etching method.

12. A method for manufacturing a semiconductor device, characterized in that, including: The etching method of the channel according to any one of claims 1 to 11.

13. A semiconductor device, characterized in that, Prepared by using the manufacturing method of the semiconductor device according to claim 12.

14. An electronic device, comprising the semiconductor device according to claim 13.

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