Field effect transistor structure and method of manufacturing the same

Abstract

A field effect transistor structure (1) includes a substrate (10), a source / drain portion (20), a dielectric layer (DL), a gate structure (30), and a semiconductor layer (40). The source / drain portion (20) is formed on the substrate (10), and includes a source and a drain (210 / 220). The dielectric layer (DL) is formed on the same layer as the source / drain portion (20) and electrically isolates the source and the drain (210 / 220). The gate structure (30) is formed on a different layer from the source / drain portion (20), and includes a gate conductive layer (310) and a gate insulating layer (320). The gate conductive layer (310) is formed on the dielectric layer, and the gate insulating layer (320) is formed on the gate conductive layer (310) and covers the gate conductive layer (310). The semiconductor layer (40) is formed on the gate insulating layer (320) and covers the gate insulating layer (320). The gate structure (30) is between the dielectric layer (DL) and the semiconductor layer (40). The source / drain portion (20) is coupled to the semiconductor layer (40), and a channel is formed in the semiconductor layer (40) by applying a voltage to the gate conductive layer (310).

Description

TECHNICAL FIELD

[0001] The present application relates to a transistor structure, in particular, a field effect transistor structure and a method for manufacturing the same. BACKGROUND

[0002] Semiconductor microprocessors and high integration circuits are manufactured by integrating elements such as field effect transistors (FETs) on a semiconductor substrate. Generally, complementary metal oxide semiconductor (CMOS) is used as a field effect transistor as an active element (switching element) of an integrated circuit. The material of the semiconductor substrate mainly uses silicon as a group IV semiconductor. By miniaturizing the transistor constituting the CMOS, the integration and performance of the semiconductor microprocessor and the high integration circuit can be improved. One of the problems in miniaturizing the CMOS is the increase in power consumption. As one of the reasons for the increase in power consumption, the short channel effect derived from the miniaturization of the transistor causes the problem of the increase in drain current. The increase in drain current leads to the increase in supply voltage, and therefore, the development of the CMOS must consider suppressing the drain current and reducing the driving voltage.

[0003] The semiconductor industry has advanced to nanotechnology, and further pursues higher device density, better performance, and lower cost process nodes. Under this progress, challenges from manufacturing and design promote the development of three-dimensional field effect transistor structures, and fin field effect transistor structures are one of them. However, the fin field effect transistor structure still has quite a few defects. For example, as the gate line width is reduced to tens of nanometers to a few nanometers, even the fin field effect transistor structure has the problem of short channel effect. SUMMARY

[0004] In view of the above problems, the present application discloses a field effect transistor structure which can reduce the short channel effect while meeting the demand for small line width gate.

[0005] The field effect transistor structure disclosed in the present application comprises a substrate, a source / drain portion, a dielectric layer, a gate structure, and a semiconductor layer. The source / drain portion is formed on the substrate and comprises a source and a drain. The dielectric layer is formed on the same layer as the source / drain portion and electrically isolates the source and the drain. The gate structure is formed on a different layer from the source / drain portion. The gate structure comprises a gate conductive layer formed on the dielectric layer and a gate insulating layer formed on the gate conductive layer and covering the gate conductive layer. The semiconductor layer is formed on the gate insulating layer and covers the gate insulating layer. The gate structure is between the dielectric layer and the semiconductor layer. The source / drain portion is coupled to the semiconductor layer, and a channel is formed in the semiconductor layer by applying a voltage to the gate.

[0006] The method for manufacturing the field effect transistor structure disclosed in the present application comprises the following steps: providing a substrate; forming a source / drain portion on the substrate; forming a gate structure on a different layer from the source / drain portion; and forming a semiconductor layer on the gate structure. The gate structure is between the substrate and the semiconductor layer. The source / drain portion is coupled to the semiconductor layer, and a channel is formed in the semiconductor layer by applying a voltage to the gate.

[0007] According to the field effect transistor structure disclosed in the present application, unlike the channel formed in the substrate in the conventional field effect transistor structure, the semiconductor layer is provided above the gate structure to form the channel, so that the length of the channel can be greater than the line width of the gate, thereby increasing the length of the channel without increasing the line width of the gate. Thus, in the case of continuously increasing transistor density to continue Moore's Law, the semiconductor layer helps the field effect transistor structure to meet the requirements of small gate line width and sufficient channel length at the same time, effectively reducing the short channel effect.

[0008] The above description of the content of the present application and the following description of the embodiments are used to demonstrate and explain the spirit and principles of the present application, and provide further explanation of the scope of protection of the claims of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A cross-sectional view of a field effect transistor structure according to an embodiment of the present application.

[0010] Figure 2 A cross-sectional view of a field effect transistor structure according to an embodiment of the present application. Figure 1 A partial enlarged view of a field effect transistor structure according to an embodiment of the present application.

[0011] Figure 3 A cross-sectional view of a field effect transistor structure according to an embodiment of the present application. Figure 4 Figure 1 A cross-sectional view of a field effect transistor structure according to an embodiment of the present application.

[0012] Figures 5 to 7 A cross-sectional view of a field effect transistor structure according to an embodiment of the present application. Figure 1 A cross-sectional view of a field effect transistor structure according to an embodiment of the present application.​

[0013] Figure 8 and Figure 9 for forming Figure 1 a cross-sectional view of a semiconductor layer of a field effect transistor structure.

[0014] Figure 10 for forming Figure 9 a heavily doped region in a source and a drain.

[0015] Figure 11 for forming Figure 1 a spacer layer of a field effect transistor structure.

[0016] Figure 12 for forming Figure 11 a passivation layer and a wire on a field effect transistor structure.

[0017] wherein the reference signs:

[0018] field effect transistor structure 1

[0019] substrate 10

[0020] N-type well region 110

[0021] P-type well region 120

[0022] source / drain portion 20

[0023] source / drain 210, 220

[0024] gate structure 30

[0025] gate conductive layer 310

[0026] bottom side 311

[0027] top side 312

[0028] peripheral side 313

[0029] gate insulating layer 320

[0030] semiconductor layer 40

[0031] channel 410

[0032] spacer layer 50

[0033] silicon oxide film 510

[0034] silicon nitride film 520

[0035] direction D

[0036] dielectric layer DL

[0037] Heavy doped region DR

[0038] Dielectric layer process region DLR

[0039] Epitaxial layer EPL

[0040] Dielectric layer ILD

[0041] Pitch L1

[0042] Extension length L2

[0043] Metal layer ML

[0044] Oxide layer OX

[0045] Poly-silicon layer POLY

[0046] Sacrificial layer SL

[0047] Conductive pillar VIA DETAILED DESCRIPTION

[0048] The forgoing detailed description of the application, such as specific features and / or advantages, is sufficient to fully and completely understand the technical content of the application and to implement the same by any skilled in the art, and any skilled in the art can easily understand the related purposes and advantages of the application according to the content disclosed in the specification, the scope of claims and the drawings. The following examples further illustrate the ideas of the application, but do not limit the scope of the application in any way.

[0049] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or structure's or portion's relation to another element or structure's or portion's or spatial orientation and provided that the spatially relative terms are intelligible by a person of ordinary skill in the art. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] Please refer to Figure 1 and Figure 2 , which are cross-sectional views of a field effect transistor structure according to an embodiment of the application, Figure 2 is Figure 1 a partial enlarged view of the field effect transistor structure. In this embodiment, the field effect transistor structure 1 comprises a substrate 10, a source / drain portion 20, a gate structure 30, a semiconductor layer 40 and a spacer layer 50.

[0051] The substrate 10 includes, for example, silicon or other semiconductor elements such as germanium or group III-V elements, but is not limited thereto. In the present embodiment, the substrate 10 is a silicon substrate including a deep N-well region (DNW) 110 and a P-well region 120.

[0052] The source / drain portion 20 is formed on the substrate 10. In detail, the source / drain portion 20 includes a source / drain 210 and a source / drain 220. The source / drain 210 and the source / drain 220 can be formed in the substrate 10 or on the top surface of the substrate 10. In the present embodiment, the source / drain 210 and the source / drain 220 are epitaxial layers formed on the top surface of the substrate 10. Figure 1 In the present embodiment, the source / drain 210 and the source / drain 220 are P-type silicon epitaxial layers or N-type silicon epitaxial layers. In other embodiments, the source / drain portion can be formed in the substrate, and the source / drain portion and the P-well region can be in the same layer.

[0053] The gate structure 30 is formed in a different layer from the source / drain portion 20. In detail, the source / drain 210 and the source / drain 220 are formed in a dielectric layer DL on the substrate 10, and the gate structure 30 is formed on the top surface of the dielectric layer DL. The gate structure 30 includes a gate conductive layer 310 and a gate insulating layer 320. The gate conductive layer 310 is formed on the top surface of the dielectric layer DL, and the gate conductive layer 310 is between the substrate 10 and the gate insulating layer 320. The gate insulating layer 320 is conformally formed on the gate conductive layer 310, and the gate insulating layer 320 covers the top side and the peripheral side of the gate conductive layer 310. The material of the gate conductive layer 310 includes tungsten (W), titanium (Ti), platinum (Pt), or copper (Cu). The material of the gate insulating layer 320 includes silicon oxide or silicon nitride.

[0054] A semiconductor layer 40 is formed on a gate configuration 30, and the gate configuration 30 is situated between the substrate 10 and the semiconductor layer 40. Specifically, the gate configuration 30 has a bottom side 311 and a top side 312 opposite to each other, with the bottom side 311 closer to the source / drain 210 and source / drain 220 than the top side 312. The gate configuration 30 further has a peripheral side 313 situated between the bottom side 311 and the top side 312. The bottom side 311 of the gate configuration 30 contacts the dielectric layer DL, and the semiconductor layer 40 is conformally formed on the top side 312 and the peripheral side 313 of the gate configuration 30, completely covering the gate conductive layer 310 and the gate insulating layer 320. In a direction D from the source / drain 210 to the source / drain 220, the spacing L1 between the source / drain 210 and the source / drain 220 is less than the extension length L2 of the semiconductor layer 40. Semiconductor layer 40 contacts and is coupled to source / drain 210 and source / drain 220. A channel 410 is formed in semiconductor layer 40 by applying a voltage to gate conductive layer 310. After channel 410 is formed, field-effect transistor structure 1 allows current to pass through, and the magnitude of the current flowing through channel 410 can be controlled according to the voltage applied to gate conductive layer 310.

[0055] The semiconductor layer 40, which provides the channel 410, conformally covers the gate configuration 30 and the gate insulating layer 320. Therefore, the length of the channel 410 is approximately twice the horizontal spacing of the source / drain 210 plus the vertical height of the gate insulating layer 320. In this way, as transistor density continues to increase to maintain Moore's Law, the semiconductor layer 40 helps the field-effect transistor structure 1 to simultaneously have sufficient channel length and effectively reduce the short-channel effect of the field-effect transistor under process miniaturization.

[0056] Spacer layer 50, for example, comprising silicon oxide or silicon nitride, is formed on semiconductor layer 40. Semiconductor layer 40 is situated between spacer layer 50 and gate insulating layer 320. Spacer layer 50 can be a single-layer or multi-layer structure. Figure 1 In the middle, the spacer layer 50 includes a multilayer film structure composed of a silicon monoxide film 510 and a silicon nitride film 520.

[0057] The following explanation Figure 1 The manufacturing method of field-effect transistor structure 1 is described below. First, the formation of the lower electrode of the field-effect transistor will be explained. Please refer to... Figure 3 and Figure 4 , in order to form Figure 1 Cross-sectional views of the source and drain of a field-effect transistor structure. First, as... Figure 3 As shown, a substrate 10 is provided, and deep N-type well regions 110 and P-type well regions 120 are formed in the substrate 10 with ion distribution values.

[0058] like Figure 4As shown, an epitaxial layer EPL is formed on the top surface of the substrate 10, and portions of the epitaxial layer are removed to form the source / drain portions 20. Specifically, the epitaxial layer EPL can be formed on the top surface of the substrate 10 by epitaxial growth techniques. Then, the epitaxial layer EPL is patterned by lithography and etching processes. Portions of the patterned epitaxial layer EPL are removed, and the epitaxial layer EPL remaining on the top surface of the substrate 10 serves as the source / drain 210 and the source / drain 220 of the source / drain portions 20.

[0059] Figures 5 to 7 To form the gate of the field effect transistor structure, as shown, a dielectric layer DL is formed to cover the source / drain 210 and the source / drain 220. Specifically, the dielectric layer DL (e.g., silicon oxide) can be deposited to cover the substrate 10, the source / drain 210 and the source / drain 220. Then, the excess dielectric layer DL can be removed by, for example, chemical mechanical polishing (CMP) processes to expose the top surfaces of the source / drain 210 and the source / drain 220 from the dielectric layer DL, thereby achieving a planarization effect. Figure 1 Figure 5 Figure 5 As shown, a metal layer ML is formed on the dielectric layer DL, and portions of the metal layer ML are removed to form the gate conductive layer 310. Specifically, the metal layer ML (e.g., tungsten) can be deposited on the top surface of the dielectric layer DL. Then, the metal layer ML is patterned by lithography and etching processes. After patterning, portions of the metal layer ML formed on the source / drain 210 and the source / drain 220 are removed, and the metal layer ML remaining on the source / drain 210 and the source / drain 220 serves as the gate conductive layer 310 of the gate structure 30. Further, the gate conductive layer 310 can be formed on a dielectric layer process region DLR between the source / drain 210 and the source / drain 220, and the bottom side of the gate conductive layer 310 contacts the dielectric layer process region DLR.

[0060] As shown, a metal layer ML is formed on the dielectric layer DL, and portions of the metal layer ML are removed to form the gate conductive layer 310. Specifically, the metal layer ML (e.g., tungsten) can be deposited on the top surface of the dielectric layer DL. Then, the metal layer ML is patterned by lithography and etching processes. After patterning, portions of the metal layer ML formed on the source / drain 210 and the source / drain 220 are removed, and the metal layer ML remaining on the source / drain 210 and the source / drain 220 serves as the gate conductive layer 310 of the gate structure 30. Further, the gate conductive layer 310 can be formed on a dielectric layer process region DLR between the source / drain 210 and the source / drain 220, and the bottom side of the gate conductive layer 310 contacts the dielectric layer process region DLR. Figure 6

[0061] As shown, a metal layer ML is formed on the dielectric layer DL, and portions of the metal layer ML are removed to form the gate conductive layer 310. Specifically, the metal layer ML (e.g., tungsten) can be deposited on the top surface of the dielectric layer DL. Then, the metal layer ML is patterned by lithography and etching processes. After patterning, portions of the metal layer ML formed on the source / drain 210 and the source / drain 220 are removed, and the metal layer ML remaining on the source / drain 210 and the source / drain 220 serves as the gate conductive layer 310 of the gate structure 30. Further, the gate conductive layer 310 can be formed on a dielectric layer process region DLR between the source / drain 210 and the source / drain 220, and the bottom side of the gate conductive layer 310 contacts the dielectric layer process region DLR. Figure 7 ​​​As shown, an oxide layer OX is formed on the dielectric layer DL and the gate conductive layer 310, and a portion of the oxide layer OX is removed to form a gate insulating layer 320. Specifically, an oxide layer OX (e.g., silicon oxide) can be deposited on the top surfaces of the dielectric layer DL, source / drain 210 and source / drain 220, the top side of the gate conductive layer 310, and the peripheral side surfaces. Next, the oxide layer OX can be patterned using lithography and etching processes. After patterning, the oxide layer OX remaining on the source / drain 210, source / drain 220, and covering the gate conductive layer 310 is conformally formed on the gate conductive layer 310 as the gate insulating layer 320.

[0062] Figure 8 and Figure 9 To form Figure 1 A cross-sectional view of the semiconductor layer in a field-effect transistor structure. (See diagram below.) Figure 8 As shown, a polysilicon layer (POLY) is formed to cover the gate insulating layer 320 and to cover the source / drain electrodes 210 and 220. Next, as... Figure 9 As shown, a polycrystalline silicon layer (POLY) is used as a seed crystal for epitaxial growth to form a semiconductor layer 40. The semiconductor layer 40 extends from the source / drain 210 through the gate insulating layer 320 to the source / drain 220. Before epitaxial growth, the polycrystalline silicon layer (POLY) can be annealed to eliminate defects.

[0063] Figure 10 In order to be in Figure 9 A cross-sectional view showing the formation of heavily doped regions in the source and drain electrodes. First, a sacrificial layer SL (e.g., silicon oxide) is formed to cover the semiconductor layer 40 and the dielectric layer DL. Next, heavily doped regions DR are formed by ion implantation. Specifically, heavily doped regions DR are formed at the contact interfaces between the semiconductor layer 40 and the source / drain electrodes 210 and 220. A "heavily doped region" refers to a region with a higher doping concentration than the surrounding area, and the region surrounding the heavily doped region can be called a lightly doped region. The heavily doped region DR helps improve the efficiency of current injection from the source / drain electrode 210 through the semiconductor layer 40 to the source / drain electrode 220. Next, the heavily doped region DR is annealed to eliminate defects within it. After the implantation of the heavily doped region DR is completed, the sacrificial layer SL can be removed by lithography and etching processes.

[0064] Figure 11 To form Figure 1 A cross-sectional view of the spacer layer in a field-effect transistor structure. A spacer layer 50 is formed on the semiconductor layer 40. Specifically, at least one insulating layer (e.g., silicon oxide or silicon nitride) may be deposited on the semiconductor layer 40, and the insulating layer may be patterned using photolithography and etching processes to form the spacer layer 50. Figure 11In this case, a silicon oxide film 510 and a silicon nitride film 520 are deposited and patterned to form the spacer layer 50 having a double-layer structure.

[0065] Figure 12 To form a passivation layer and a conductive pillar on the field effect transistor structure. Figure 11 A cross-sectional view of a field effect transistor structure with a passivation layer and a conductive pillar formed thereon. One or more dielectric layers ILD can be additionally formed as the passivation layer to seal the field effect transistor structure 1. In addition, a conductive pillar VIA can also be formed in the dielectric layer ILD to enable the field effect transistor structure 1 to be coupled to external conductive lines.

[0066] In summary, according to the field effect transistor structure disclosed in the present application, the channel is formed above the semiconductor layer instead of in the substrate as in conventional field effect transistor structures. Therefore, the channel length can be greater than the gate line width, and the channel length can be increased without increasing the gate line width. Thus, the semiconductor layer helps the field effect transistor structure to meet the requirements of a small gate line width and a sufficient channel length at the same time, effectively reducing the short channel effect, when the transistor density continues to increase to continue Moore's Law.

Claims

1. A field-effect transistor structure, characterized in that, This field-effect transistor structure includes: One substrate; A source-drain portion is formed on the substrate, and the source-drain portion includes a source and a drain; A dielectric layer is formed on the same layer as the source and drain portions and electrically isolates the source and drain portions; A gate configuration is located on a different layer from the source and drain portions. The gate configuration includes a gate conductive layer and a gate insulating layer. The gate conductive layer is formed on the dielectric layer, and the gate insulating layer is formed on the gate conductive layer and covers the gate conductive layer. as well as A semiconductor layer is formed on and covers the gate insulating layer, wherein the semiconductor layer is made of polycrystalline silicon. The gate is located between the dielectric layer and the semiconductor layer, the source and drain are coupled to the semiconductor layer, and a channel is formed in the semiconductor layer by applying a voltage to the gate conductive layer. In one direction from the source to the drain, the distance between the source and the drain is less than the extension length of the semiconductor layer.

2. The field-effect transistor structure as described in claim 1, characterized in that, The gate has a bottom side and a top side facing each other, and a peripheral side of the gate is located between the bottom side and the top side. The bottom side contacts the dielectric layer, and the semiconductor layer is formed on the top side and the peripheral side.

3. The field-effect transistor structure as described in claim 1, characterized in that, It further includes a spacer layer, wherein the semiconductor layer is located between the spacer layer and the gate insulating layer.

4. A method for manufacturing a field-effect transistor structure, characterized in that, The method for manufacturing this field-effect transistor structure includes: Provide a substrate; A source and drain portion is formed on the substrate; A gate is formed, which is located on a different layer from the source and drain sections; as well as A semiconductor layer is formed on the gate configuration, the material of the semiconductor layer is polysilicon, the gate configuration is located between the substrate and the semiconductor layer, the source and drain portions are coupled to the semiconductor layer, and a channel is formed in the semiconductor layer by applying a voltage to the gate configuration. In one direction from the source to the drain, the distance between the source and the drain is less than the extension length of the semiconductor layer.

5. The method for manufacturing the field-effect transistor structure as described in claim 4, characterized in that, The source and drain sections comprise: An epitaxial layer is formed on the substrate; and A portion of the epitaxial layer is removed to form the source and drain portions.

6. The method for manufacturing the field-effect transistor structure as described in claim 5, characterized in that, Also includes: A dielectric layer is formed to cover the source and drain portions; Remove part of the dielectric layer so that the top surface of the source and drain portions is on the same plane as the top surface of the dielectric layer. Horizontal height; A metal layer is formed on the dielectric layer; Remove part of the metal layer to form a gate conductive layer constituting the gate; An oxide layer is formed on the dielectric layer to cover the gate conductive layer; as well as Remove part of the oxide layer to form a gate insulating layer constituting the gate.

7. The method for manufacturing the field-effect transistor structure as described in claim 6, characterized in that, The semiconductor layer comprises: A polysilicon layer is formed to cover the gate insulating layer, and the polysilicon layer contacts the source and drain portions; and The polycrystalline silicon layer is used as a seed crystal for epitaxial growth to form the semiconductor layer.

8. The method for manufacturing the field-effect transistor structure as described in claim 7, characterized in that, It also includes: A sacrificial layer is formed on the semiconductor layer; At least one doped region is formed by ion implantation, and the at least one doped region is located at the contact interface between the semiconductor layer and the source and drain portions; Annealing should involve at least one doped region; as well as Remove the sacrifice layer.

9. The method for manufacturing the field-effect transistor structure as described in claim 8, characterized in that, It further includes: forming a spacer layer on the semiconductor layer.

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