analog-to-digital converter

Abstract

An analog-to-digital converter (ADC) circuit includes a signal input terminal (101), a sample-and-hold circuit (110), and a successive approximation register (SAR) ADC (112). The sample-and-hold circuit (110) includes an input terminal (110A) coupled to the signal input terminal (101). The SAR ADC (112) includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

Description

BACKGROUND

[0001] Various analog-to-digital data converters and conversion techniques can be used to convert an electrical signal from an analog domain to a digital domain. Generally, the process of analog-to-digital conversion involves sampling an analog signal and comparing the sampled analog signal to a threshold value. A binary result is recorded depending on the comparison result. The process of comparing a sample to a threshold value can be repeated a number of times, with each successive comparison using a different threshold value and a residue of the sample. The number of iterations is generally determined by the noise level in a particular iteration and the resolution of the final digital signal.

[0002] A successive approximation register (SAR) converter is one example of an analog-to-digital converter (ADC). A SAR ADC performs a binary search for a digital value that best corresponds to a voltage of an analog signal. In a SAR ADC, a voltage input is compared to one-half of a reference voltage. If the voltage input is greater than one-half of the reference voltage, a logical '1' is stored in a register. Alternatively, if the voltage input is less than one-half of the reference voltage, a logical '0' is stored in the register. Next, if the previous comparison indicated that the voltage input was greater than one-half of the reference voltage, the voltage input is compared to three-quarters of the reference voltage. Again, if the comparison indicates a greater than condition, a logical '1' is stored in the register. Conversely, if the comparison indicates a less than condition, a logical '0' is stored in the register. Alternatively, the previous comparison indicated that the voltage input was less than one-half of the reference voltage, the voltage input is compared to one-quarter of the reference voltage. Again, if the comparison indicates a greater than condition, a logical '1' is stored in the register. Conversely, if the comparison indicates a less than condition, a logical '0' is stored in the register. This process continues for lower order multiples of the reference voltage. As will be appreciated, the above-described process is capable of providing an ADC result with high resolution in a relatively short amount of time. In particular, only a single iteration can be used to produce each bit of resolution. For example, for a 10-bit resolution, 10 iterations are theoretically required, and for a 20-bit resolution, 20 iterations are theoretically required. SUMMARY

[0003] A two-step successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed herein that improves coarse SAR ADC resolution through dynamic error correction. In one example, an analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample and hold circuit, and a successive approximation register (SAR) ADC. The sample and hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample and hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

[0004] In another example, an analog-to-digital converter (ADC) circuit includes a sample and hold circuit and a SAR ADC. The sample and hold circuit is configured to sample an input signal to be digitized. The SAR ADC is coupled to the sample and hold circuit and is configured to digitize the input signal. The SAR ADC includes a comparator, a first CDAC, and a second CDAC. The first CDAC is coupled to a first input terminal of the comparator and is configured to sample the input signal to be digitized and to sample an output of the sample and hold circuit. The second CDAC is coupled to a second input terminal of the comparator and is configured to sample the input signal to be digitized.

[0005] In another example, an analog-to-digital converter (ADC) circuit includes a sample and hold circuit and a SAR ADC. The sample and hold circuit is configured to sample an input signal to be digitized. The SAR ADC is coupled to the sample and hold circuit and is configured to digitize the input signal. The SAR ADC includes a comparator, a first CDAC, and a second CDAC. The first CDAC is coupled to a first input terminal of the comparator and is configured to sample the input signal to be digitized and to sample an output of the sample and hold circuit. The second CDAC is coupled to a second input terminal of the comparator and is configured to sample the input signal to be digitized. BRIEF DESCRIPTION OF DRAWINGS

[0006] With specific descriptions for various examples, reference is now made to the drawings in which:

[0007] Figure 1 A block diagram showing a two-step successive approximation register (SAR) analog-to-digital converter (ADC) according to the present description;

[0008] Figure 2 A schematic diagram showing a sample-and-hold circuit and buffer according to the present description;

[0009] Figure 3 A block diagram showing a first stage of a two-step SAR ADC with dynamic error correction according to the present description;

[0010] Figure 4 A schematic diagram showing a coarse SAR ADC according to the present description;

[0011] Figure 5 A timing diagram showing digitization in a coarse SAR ADC according to the present description;

[0012] Figure 6 A block diagram showing a differential input two-step SAR ADC according to the present description; and

[0013] Figure 7 A schematic diagram showing a differential input coarse SAR ADC according to the present description. DETAILED DESCRIPTION

[0014] In this description, the term "couple / couples" means either a direct or indirect wired or wireless connection. Thus, if a first device couples to a second device, that connection can be through a direct connection or through an indirect connection via other devices and connections. Also in this description, the statement "based on" means "based, at least in part, on." Therefore, if X is based on Y, X can be based on Y and any number of other factors.

[0015] In two-step successive approximation register (SAR) analog-to-digital converters (ADCs), the resolution of the coarse stage SAR ADC is limited by sampling bandwidth mismatch, clock skew, and other factors. Some two-step SAR ADCs attempt to improve resolution by using a sample-and-hold amplifier or merging the capacitive analog-to-digital converter (CDAC) of the coarse ADC with the main CDAC. However, sample-and-hold amplifiers consume excessive power, and merging the coarse ADC CDAC with the main CDAC limits conversion speed.

[0016] The two-step SAR ADC disclosed herein improves coarse ADC resolution without adding a sample-and-hold amplifier or merging a coarse ADC CDAC with a main CDAC by reducing errors associated with sampling bandwidth mismatch. The two-step SAR ADC of the present disclosure modifies the search destination of a coarse SAR ADC during conversion to compensate for signal-dependent residual errors in different sampling paths. Embodiments use a scaled-down copy of the main CDAC to generate a sampling input voltage for the main CDAC and apply the sampling input voltage in the coarse ADC CDAC to adjust the search destination of the coarse SAR ADC. The adjusted search destination compensates for errors in different sampling paths.

[0017] Figure 1 A block diagram of a two-step successive approximation register (SAR) analog-to-digital converter (ADC) 100 according to the present description is shown. The two-step SAR ADC 100 includes a first stage 102, a second stage 104, and output circuitry 106. The two-step SAR ADC 100 generates an M-bit digital output representing an analog signal received at a signal input terminal 101. The first stage 102 generates a predetermined number of most significant bits of the M bits, and the second stage 104 generates the remainder of the M bits. For example, in an embodiment of the two-step SAR ADC 100 that generates a 16-bit output, the first stage 102 generates 6 most significant bits (with 1 or more additional redundant bits), and the second stage 104 generates 10 least significant bits. The output circuitry 106 receives the digital values generated by the first stage 102 and the second stage 104 and combines (e.g., concatenates and overlaps) the digital values to generate a digital output value. The two-step architecture allows for a reduction in the size of the capacitors used in the first stage 102 and the second stage 104.

[0018] The first stage 102 includes a sample-and-hold circuit 108, a sample-and-hold circuit 110, a SAR ADC 112, a digital-to-analog converter (DAC) 114 (main DAC), subtraction circuitry 116, and a residue amplifier 118. The sample-and-hold circuit 108, the sample-and-hold circuit 110, and the SAR ADC 112 are coupled to the signal input terminal 101. The sample-and-hold circuit 108 includes an input terminal 108A coupled to the signal input terminal 101, the sample-and-hold circuit 110 includes an input terminal 110A coupled to the signal input terminal 101, and the SAR ADC 112 includes an input terminal 112A coupled to the signal input terminal 101. Each of the sample-and-hold circuit 108, the sample-and-hold circuit 110, and the SAR ADC 112 takes a sample of the input signal 103 provided at the signal input terminal 101 to be digitized. An output terminal 112B of the SAR ADC 112 is coupled to the output circuitry 106 and an input terminal 114A of the DAC 114. The SAR ADC 112 digitizes the taken sample and provides a digital value 120 to the output circuitry 106 and the DAC 114. The DAC 114 converts the digital value 120 to an analog voltage 122. The subtraction circuitry 116 is coupled to the sample-and-hold circuit 108, the DAC 114, and the residue amplifier 118. The subtraction circuitry 116 subtracts the analog voltage 122 from a sample 124 provided by the sample-and-hold circuit 108 to produce a residue signal 126 representing the total unadjusted error of the SAR ADC 112. The residue amplifier 118 is coupled to the subtraction circuitry 116 and amplifies the residue signal 126 to produce an amplified residue signal 128.

[0019] The second stage 104 includes a SAR ADC 130. The SAR ADC 130 is coupled to the residue amplifier 118 and digitizes the amplified residue signal 128 to produce a digital value 132. The SAR ADC 130 provides the digital value 132 to the output circuitry 106 to be combined with the digital value 120.

[0020] The sample-and-hold circuit 110 is a scaled-down version of the sample-and-hold circuit 108. The sample-and-hold circuit 110 includes an input terminal 110A coupled to the signal input terminal 101 and an output terminal 110B coupled to an input terminal 112C of the SAR ADC 112. For any given sample 124 taken by the sample-and-hold circuit 108, the sample-and-hold circuit 110 takes a sample 134 having the same voltage as the sample 124. Figure 2 A schematic diagram showing an embodiment of the sample-and-hold circuit 110 according to the present description is shown. The sample-and-hold circuit 108 and the SAR ADC 112 are also shown in Figure 2 for reference. In Figure 2In particular embodiments, sample-and-hold circuit 108 includes a higher capacitance and a lower resistance than sample-and-hold circuit 110. The ratio of the capacitance and resistance of sample-and-hold circuit 110 to the capacitance and resistance of sample-and-hold circuit 108 varies among different implementations of two-step SAR ADC 100.

[0021] Sample-and-hold circuit 110 includes sample capacitor 202, resistor 204 (representing a switched resistance), resistor 206 (representing a switched resistance), switch 208, switch 210, amplifier 212, switch 214, switch 216, and switch 218. Switches 208 and 210 are closed when sampling input signal 103, and are open when sampling is complete and sample-and-hold circuit 110 is in a hold state. Amplifier 212 buffers the voltage across sample capacitor 202 for providing to SAR ADC 112. During sampling (e.g., within a sampling interval), switches 214 and 216 are open, and switch 218 is closed, thereby disconnecting amplifier 212 from sample capacitor 202. Similarly, when sample-and-hold circuit 110 is in a hold state (e.g., within a hold interval), switches 214 and 216 are closed, and switch 218 is open, thereby connecting amplifier 212 to sample capacitor 202.

[0022] Amplifier 212 includes an input terminal 212A coupled to sample capacitor 202 via switch 214, and an output terminal 212B coupled to input terminal 112C of SAR ADC 112. Switch 214 includes a terminal 214A coupled to terminal 202B of sample capacitor 202, and a terminal 214B coupled to input terminal 212A of amplifier 212. Switch 216 includes a terminal 216A coupled to terminal 202A of sample capacitor 202, and a terminal 216B coupled to output terminal 212B of amplifier 212. Switch 218 includes a terminal 218A coupled to output terminal 212B of amplifier 212, and a terminal 218B coupled to input terminal 212A of amplifier 212.

[0023] Figure 3 A block diagram of coarse SAR ADC 300 is shown. Coarse SAR ADC 300 is an embodiment of SAR ADC 112. Coarse SAR ADC 300 includes a sampling network 302 for sampling input signal 103. A sampled signal 308 (V n2 ) is provided at an output terminal of sampling network 302. However, due to differences in sampling bandwidth, sampled signal 308 is different from sample 134 (V n1). As explained previously, the sample 134 is the same as the sample 124 from which the residual signal 126 is derived. The coarse SAR ADC 300 compensates for the difference between the sample signal 308 and the sample 124 by taking the difference between the sample 134 and the sample signal 308, and subtracting the difference from the sample signal 308 to produce the voltage 304 that is the same as the voltage of the sample 134 to use as a reference in digitization.

[0024] Figure 4 A schematic diagram of a coarse SAR ADC 400 according to the present description is shown. The SAR ADC 400 is an embodiment of the SAR ADC 112 and the SAR ADC 300. The SAR ADC 400 includes a CDAC 402, a CDAC 404, a comparator 406, a SAR control circuit 408, a switch 410, and a switch 412. The CDAC 402 includes a binary-weighted capacitor 414 and a switch 416. The switch 416 is controllable to connect a bottom plate of the binary-weighted capacitor 414 to the input terminal 112A or the input terminal 112C, and thereby charge the binary-weighted capacitor 414 to the input signal 103 or the sample 134. The CDAC 402 includes an output terminal 402A coupled to an input terminal 406A of the comparator 406, an input terminal 402B coupled to the input terminal 112C of the SAR ADC 112, and an input terminal 402C coupled to the input terminal 112A of the SAR ADC 112. A top plate of the binary-weighted capacitor 414 is coupled to the output terminal 402A.

[0025] Similarly, the CDAC 404 includes a binary-weighted capacitor 418 and a switch 420. The switch 420 is controllable to connect a bottom plate of the binary-weighted capacitor 418 to the input terminal 112A, a reference voltage source, or a common voltage source (e.g., ground). The switches 410 and 412 are controllable to connect top plates of the binary-weighted capacitor 414 and the binary-weighted capacitor 418 to ground, respectively. The CDAC 404 includes an output terminal 404A coupled to an input terminal 406B of the comparator 406 and an input terminal 404C coupled to the input terminal 112A of the SAR ADC 112. A top plate of the binary-weighted capacitor 418 is coupled to the output terminal 404A.

[0026] The comparator 406 compares the voltage on the top plate of the binary-weighted capacitor 418 to the voltage on the top plate of the binary-weighted capacitor 414 and provides the comparison to the SAR control circuit 408. The SAR control circuit 408 is coupled to the comparator 406, the CDAC 402, and the CDAC 404 and sets the bits of the digital value 120 based on the comparison. The SAR control circuit 408 generates a switch control signal 422 that controls the switches 410, 412, 416, and 420. The SAR control circuit 408 determines how to set the switch 420 based on the output of the comparator 406 and activates the switch control signal 422 accordingly.

[0027] At the start of each sample digitization (acquisition phase), the SAR control circuit 408 sets the switches 416 and 420 to connect the bottom plates of the binary-weighted capacitor 414 and the binary-weighted capacitor 418 to the input terminal 112A of the SAR ADC 112 so that the binary-weighted capacitor 414 and the binary-weighted capacitor 418 are charged to the input signal 103. After the SAR control circuit 408 selects the value of one or more bits of the digital value 120 (the number of bits based on the redundancy needed to correct for dynamic errors), the SAR control circuit 408 sets the switch 416 of the CDAC 402 to connect the bottom plate of the binary-weighted capacitor 414 to the input terminal 112C of the SAR ADC 112, thereby applying the sample 134 to the bottom plate of the binary-weighted capacitor 414. Thus, the voltage on the top plate of the binary-weighted capacitor 414 is set to the voltage of the sample 134 minus the voltage previously sampled from the input terminal 112A (i.e., V n1 -V n2 ). Thus, the reference voltage applied to the comparator 406 is shifted from zero to V n1 -V n2 , and digitization continues. By shifting the reference from zero to V n1 -V n2 , the voltage digitized by the SAR ADC 400 is effectively the voltage of the sample 134, not the voltage sampled from the input terminal 112A by the binary-weighted capacitor 418.

[0028] Figure 5A timing diagram for digitization using SAR ADC 400 as a coarse SAR ADC in two-step SAR ADC 100 is shown. In interval 502, sample-and-hold circuit 108, sample-and-hold circuit 110, CDAC 402, and CDAC 404 sample input signal 103. At the end of interval 502, switches 214 and 216 are closed, and the output of amplifier 212 settles over interval 504. At the end of interval 502, switch 416 is set to disconnect signal input terminal 101 from binary-weighted capacitor 414. During interval 514, the bottom plate of capacitor 416 floats. At the end of interval 504, before the DEC bit interval, switch 416 is set to connect output terminal 110B of sample-and-hold circuit 110 to binary-weighted capacitor 414, so the top plate of binary-weighted capacitor 414 becomes V n1 -V n2 In interval 506, the error in the bit selected in interval 504 (error related to using zero as a reference over interval 504) is determined. In some embodiments, the error is digitally corrected after digitization is complete by two-step SAR ADC 100. In interval 508, V n1 -V n2 The remaining bit decisions are made in SAR ADC 400 as reference voltages applied at 406A of comparator 406, rather than the usual zero.

[0029] Figure 6 A block diagram of a differential-input two-step SAR ADC 600 according to the present description is shown. Differential-input two-step SAR ADC 600 includes a first stage 602, a second stage 604, and output circuitry 606. First stage 602 includes sample-and-hold circuit 608, sample-and-hold circuit 609, sample-and-hold circuit 610, sample-and-hold circuit 611, SAR ADC 612, digital-to-analog converter (DAC) 614 (main DAC), subtraction circuitry 616, and residual amplifier 618. Sample-and-hold circuit 608, sample-and-hold circuit 610, and SAR ADC 612 are coupled to signal input terminal 601. Sample-and-hold circuit 609, sample-and-hold circuit 611, and SAR ADC 612 are coupled to signal input terminal 603. Sample-and-hold circuit 608 includes input terminal 608A coupled to signal input terminal 601, sample-and-hold circuit 610 includes input terminal 610A coupled to signal input terminal 601, and SAR ADC 612 includes input terminal 612A coupled to signal input terminal 601. Each of sample-and-hold circuit 608, sample-and-hold circuit 610, and SAR ADC 612 takes an input signal 605 (V IN+) samples.

[0030] Sample and hold circuit 609 includes an input terminal 609A coupled to signal input terminal 603, sample and hold circuit 611 includes an input terminal 611A coupled to signal input terminal 603, and SAR ADC 612 includes an input terminal 612E coupled to signal input terminal 603. Each of sample and hold circuit 609, sample and hold circuit 611, and SAR ADC 612 acquires the input signal 607(V) to be digitized provided at signal input terminal 603. IN -) samples.

[0031] Sample and hold circuits 608 and 609 are implementations of sample and hold circuit 108. Sample and hold circuits 610 and 611 are implementations of sample and hold circuit 110. Sample and hold circuit 610 is a scaled-down version of sample and hold circuit 608, and sample and hold circuit 611 is a scaled-down version of sample and hold circuit 609. Sample and hold circuit 610 includes an input terminal 610A coupled to signal input terminal 601 and an output terminal 610B coupled to input terminal 612C of SAR ADC 612. For any given sample 624 acquired by sample and hold circuit 608, sample and hold circuit 610 acquires a sample 634 having the same voltage as sample 624. Sample and hold circuit 611 includes an input terminal 611A coupled to signal input terminal 603 and an output terminal 611B coupled to input terminal 612D of SAR ADC 612. For any given sample 644 acquired by the sample and hold circuit 609, the sample and hold circuit 611 acquires a sample 635 having the same voltage as the sample 644.

[0032] Figure 7A schematic diagram of a differential input coarse SAR ADC 700 according to the present description is shown. The differential input coarse SAR ADC 700 is an embodiment of the SAR ADC 612. The differential input coarse SAR ADC 700 includes a CDAC 702, a CDAC 704, a CDAC 714, a CDAC 716, a comparator 706, a SAR control circuit 708, a switch 710, a switch 712, a switch 718, and a switch 720. The SAR control circuit 708 is coupled to the comparator 706, the CDAC 702, the CDAC 704, the CDAC 714, and the CDAC 716. The CDAC 702, the CDAC 704, the CDAC 714, and the CDAC 716 include binary weighted capacitors and switches. In the CDAC 702, the switches are controllable to connect the bottom plate of the capacitor to the input terminal 612E or the input terminal 612D, and thereby charge the capacitor to the voltage of the input signal 607 or the sample 635. The CDAC 702 includes an output terminal 702A coupled to an input 706D of the comparator 706, an input terminal 702B coupled to the input terminal 612D, and an input terminal 702C coupled to the input terminal 612E. The top plate of the capacitor of the CDAC 702 is coupled to the output terminal 702A. In the CDAC 702, the switches are controllable to connect the bottom plate of the capacitor of the CDAC 702 to the input terminal 612E or the input terminal 612D, and thereby charge the capacitor to the voltage of the input signal 607 or the sample 635.

[0033] The CDAC 716 includes an output terminal 716A coupled to an input terminal 706C of the comparator 706, an input terminal 716B coupled to the input terminal 612C, and an input terminal 716C coupled to the input terminal 612A of the SAR ADC 612. The top plate of the capacitor of the CDAC 716 is coupled to the output terminal 716A. In the CDAC 716, the switches are controllable to connect the bottom plate of the capacitor of the CDAC 716 to the input terminal 612A or the input terminal 612C, and thereby charge the capacitor to the voltage of the input signal 605 or the sample 634.

[0034] The CDAC 704 includes an output terminal 704A coupled to an input 706B of the comparator 706 and an input terminal 704B coupled to the input terminal 612E. The top plate of the capacitor of the CDAC 704 is coupled to the output terminal 704A. The switches of the CDAC 704 are controllable to connect the bottom plate of the capacitor to the input terminal 612E, a reference voltage source, or a common voltage source (e.g., ground).

[0035] The CDAC 714 includes an output terminal 714A coupled to an input terminal 706A of the comparator 706 and an input terminal 714B coupled to the input terminal 612A. The top plate of the capacitor of the CDAC 714 is coupled to the output terminal 714A. The switches of the CDAC 714 are controllable to connect the bottom plate of the capacitor to the input terminal 612A, a reference voltage source, or a common voltage source (e.g., ground).

[0036] At the start of each sample digitization, the SAR control circuit 708 sets the switches of the CDAC 702 and the CDAC 704 to connect the bottom plates of the capacitors of the CDAC 702 and the CDAC 704 to the signal input terminal 603 and to charge the capacitors of the CDAC 702 and the CDAC 704 to the voltage of the input signal 607. After the SAR control circuit 708 selects the value of one or more bits of the digital value 620, the SAR control circuit 708 sets the switches of the CDAC 702 via the switch control signals 722 to disconnect the bottom plate of the capacitor of the CDAC 702 from the signal input terminal 603 and to connect the bottom plate of the capacitor of the CDAC 702 to the output 611B of the sample-and-hold circuit 611 to charge the capacitor to the voltage of the sample 635. Thus, the voltage on the top plate of the capacitor of the CDAC 702 is set to the voltage of the sample 635 minus the previously sampled voltage of the input signal 607.

[0037] Similarly, at the start of each sample digitization, the SAR control circuit 708 sets the switches of the CDAC 714 and the CDAC 716 to connect the bottom plates of the capacitors of the CDAC 714 and the CDAC 716 to the signal input terminal 601 and to charge the capacitors of the CDAC 714 and the CDAC 716 to the voltage of the input signal 605. After the SAR control circuit 708 selects the value of one or more bits of the digital value 620, the SAR control circuit 708 sets the switches of the CDAC 716 to disconnect the bottom plate of the capacitor of the CDAC 716 from the signal input terminal 601 and to connect the bottom plate of the capacitor of the CDAC 716 to the output 610B of the sample-and-hold circuit 610 to charge the capacitor to the voltage of the sample 634. Thus, the voltage on the top plate of the capacitor of the CDAC 716 is set to the voltage of the sample 634 minus the previously sampled voltage of the input signal 605.

[0038] In the described embodiments, modifications are possible and other embodiments are possible within the scope of the claims.

Claims

1. An analog-to-digital converter (ADC) circuit, comprising: a signal input terminal; a sample-and-hold circuit comprising an input terminal coupled to the signal input terminal; a successive approximation register (SAR) ADC comprising: a comparator; a first capacitive digital-to-analog converter (CDAC) comprising: a first input terminal coupled to the signal input terminal; a second input terminal coupled to an output terminal of the sample-and-hold circuit; and an output terminal coupled to a first input terminal of the comparator; and a second CDAC comprising: a first input terminal coupled to a reference voltage; and an output terminal coupled to a second input terminal of the comparator; wherein the sample-and-hold circuit comprises: a sampling capacitor; and an amplifier comprising: an input terminal coupled to the sampling capacitor; and an output terminal coupled to the second input terminal of the first CDAC; a first switch comprising: a first terminal coupled to a first terminal of the sampling capacitor; a second terminal coupled to the input terminal of the amplifier; a second switch comprising: a first terminal coupled to a second terminal of the sampling capacitor; and a second terminal coupled to the output terminal of the amplifier; and a third switch comprising: a first terminal coupled to the output terminal of the amplifier; and a second terminal coupled to the input terminal of the amplifier.

2. The ADC circuit of claim 1, wherein: the sample-and-hold circuit is a first sample-and-hold circuit; and the ADC circuit comprises a second sample-and-hold circuit comprising an input terminal coupled to the signal input terminal.

3. The ADC circuit of claim 2, further comprising: a main digital-to-analog converter (DAC) comprising an input coupled to an output of the SAR ADC; and subtraction circuitry coupled to the main DAC and the second sample-and-hold circuit.

4. The ADC circuit of claim 3, wherein: the SAR ADC is a first SAR ADC; and the ADC circuit further comprises: a residual amplifier coupled to the subtraction circuitry; and a second SAR ADC coupled to the residual amplifier.

5. The ADC circuit of claim 1, wherein the SAR ADC further comprises a SAR control circuit coupled to the comparator and the first CDAC, and configured to, in a given bit decision cycle: disconnect a bottom plate of a capacitor of the first CDAC from the signal input terminal; and connect the bottom plate to the sample-and-hold circuit.

6. An ADC circuit, comprising: a first signal input terminal; a second signal input terminal; a first sample-and-hold circuit comprising an input terminal coupled to the first signal input terminal; a second sample-and-hold circuit comprising an input terminal coupled to the second signal input terminal; a successive approximation register (SAR) ADC comprising: a comparator; ​ a first capacitive digital-to-analog converter (CDAC) comprising: a first input terminal coupled to the first signal input terminal; a second input terminal coupled to an output terminal of the first sample-and-hold circuit; and an output terminal coupled to a first input terminal of the comparator; and a second CDAC comprising: a first input terminal coupled to the second signal input terminal; a second input terminal coupled to an output terminal of the second sample-and-hold circuit; and an output terminal coupled to a second input terminal of the comparator; wherein the SAR ADC comprises: a third CDAC comprising: a first input terminal coupled to the first signal input terminal; and an output terminal coupled to a third input terminal of the comparator; and a fourth CDAC comprising: a first input terminal coupled to the second signal input terminal; and an output terminal coupled to a fourth input terminal of the comparator.

7. An ADC circuit comprising: a first signal input terminal; a second signal input terminal; a first sample-and-hold circuit comprising an input terminal coupled to the first signal input terminal; a second sample-and-hold circuit comprising an input terminal coupled to the second signal input terminal; a successive approximation register (SAR) ADC comprising: a comparator; a first capacitive digital-to-analog converter (CDAC) comprising: a first input terminal coupled to the first signal input terminal; a second input terminal coupled to an output terminal of the first sample-and-hold circuit; and an output terminal coupled to a first input terminal of the comparator; and a second CDAC comprising: a first input terminal coupled to the second signal input terminal; a second input terminal coupled to an output terminal of the second sample-and-hold circuit; and an output terminal coupled to a second input terminal of the comparator; wherein the first sample-and-hold circuit comprises: a first sampling capacitor; a first amplifier comprising an output terminal coupled to the second input terminal of the first CDAC; a first switch comprising: a first terminal coupled to a first terminal of the first sampling capacitor; and a second terminal coupled to an input terminal of the first amplifier; a second switch comprising: a first terminal coupled to a second terminal of the first sampling capacitor; and a second terminal coupled to the output terminal of the first amplifier; and a third switch comprising: a first terminal coupled to the output terminal of the first amplifier; and a second terminal coupled to the input terminal of the first amplifier.

8. The ADC circuit of claim 7, wherein the second sample-and-hold circuit comprises: a second sampling capacitor; a second amplifier comprising an output terminal coupled to the second input terminal of the second CDAC; a third switch comprising: a first terminal coupled to a first terminal of the second sampling capacitor; and a second terminal coupled to an input terminal of the second amplifier; a fourth switch comprising: a first terminal coupled to a second terminal of the second sampling capacitor; and a second terminal coupled to the output terminal of the second amplifier. a first terminal coupled to a second terminal of the second sampling capacitor; and a second terminal coupled to the output terminal of the second amplifier; and a fifth switch comprising: a first terminal coupled to the output terminal of the second amplifier; and a second terminal coupled to the input terminal of the second amplifier.

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