Clock tree processing method, device, equipment and storage medium

Abstract

The present application provides a clock tree processing method, apparatus, device, and storage medium. The method includes: obtaining a clock tree design to be processed, where the clock tree includes at least two levels of clock branches, and the first level is led out by the second level, and the number of clock branches in the first level is greater than the number of clock branches in the second level; counting buffer units in the first level with a wire delay less than a preset threshold to obtain a first target number of redundant buffer units in the first level; inserting the first target number of the redundant buffer units into the clock branches in the second level, and respectively deleting the first target number of the redundant buffer units from each of the clock branches in the first level to obtain a simplified clock tree. The present application realizes the purpose of reducing the number of clock buffer units as much as possible on the premise of ensuring that the delay from the clock source to the register clock terminal is controllable, so as to reduce the number of units and the area on the clock tree and reduce the power consumption on the clock.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a clock tree processing method, device, equipment, and storage medium. Background Art

[0002] A clock tree is a network structure built by balancing many buffer cells. It has a source point, which is generally a clock input port, or it may also be a cell output pin of a certain unit inside the design, and then it is built by buffer cells level by level.

[0003] In an ideal synchronous circuit, the clock edges of all registers in the same clock domain are considered to arrive simultaneously. However, in an actual circuit, this is impossible to achieve. Therefore, it is necessary to manage the clock signals in the clock domain. Using a clock tree to manage clock signals is a common practice. The clock tree can ensure that the clock edge skew of the registers in the clock domain is minimized, thereby ensuring good timing characteristics.

[0004] For advanced process chip design, high frequency often brings high power consumption. The power consumption on the clock tree usually accounts for about 40% of the chip's power consumption. In the stage close to signoff, various means are usually taken to optimize power consumption. However, it is very difficult to optimize power consumption after the clock structure is determined. Therefore, it is particularly important to find a solution to optimize the power consumption on the clock tree. Summary of the Invention

[0005] The purpose of the embodiments of this application is to provide a clock tree processing method, device, equipment, and storage medium, which can reduce the number of clock buffer cells as much as possible on the premise of ensuring that the delay from the clock source to the register clock terminal is controllable, so as to reduce the number of units and the area on the clock tree and reduce the power consumption on the clock.

[0006] The first aspect of the embodiments of this application provides a clock tree processing method, including: obtaining a clock tree design to be processed, where the clock tree includes at least two levels of clock branches, and the first level is led out from the second level, and the number of clock branches in the first level is greater than the number of clock branches in the second level; counting the buffer cells in the first level whose wire delay is less than a preset threshold to obtain a first target number of redundant buffer cells in the first level; inserting the first target number of redundant buffer cells into the clock branches of the second level, and deleting the first target number of redundant buffer cells from each clock branch of the first level respectively to obtain a simplified clock tree.

[0007] In one embodiment, the step of counting the buffer units in the first stage with line delay less than a preset threshold to obtain the first target number of redundant buffer units in the first stage includes: according to the delay parameters of the clock tree, counting the number of the redundant buffer units fanned out by each clock branch in the first stage, where the redundant buffer units are those with line delay less than the preset threshold, to obtain a set of numbers of the redundant buffer units in the first stage; and selecting the minimum number from the set of numbers corresponding to the first stage as the first target number of the redundant buffer units in the first stage.

[0008] In one embodiment, the step of inserting the first target number of the redundant buffer units into the clock branches in the second stage includes: inserting the first target number of the redundant buffer units into each of the clock branches in the second stage.

[0009] In one embodiment, each clock branch in the second stage leads out a plurality of first-stage clock branches through a common point; the step of counting the buffer units in the first stage with line delay less than a preset threshold to obtain the first target number of redundant buffer units in the first stage includes: according to the delay parameters of the clock tree, for the same common point, counting the number of the redundant buffer units fanned out by each of the first-stage clock branches led out by the common point, where the redundant buffer units are those with line delay less than the preset threshold, to obtain a set of numbers of the redundant buffer units in the first-stage clock branches corresponding to the common point; and selecting the minimum number from the set of numbers corresponding to the common point as the first target number corresponding to the common point.

[0010] In one embodiment, the step of inserting the first target number of the redundant buffer units into the clock branches in the second stage and deleting the first target number of the redundant buffer units from each of the clock branches in the first stage to obtain a simplified clock tree includes: inserting the first target number of the redundant buffer units into the clock branch in the second stage where the common point is located, and deleting the first target number of the redundant buffer units from each of the plurality of first-stage clock branches led out by the common point to obtain a simplified clock tree.

[0011] In one embodiment, the clock tree further includes: a third-level clock branch leading out from the second level, where the number of clock branches at the third level is less than the number of clock branches at the second level; after inserting the first target number of the redundant buffer units into the clock branches at the second level, the method further includes: counting the buffer units in the second level whose wire delay is less than the preset threshold after inserting the first target number of the redundant buffer units, to obtain a second target number of the redundant buffer units in the second level; inserting the second target number of the redundant buffer units into the third-level clock branches, and deleting the second target number of the redundant buffer units from each of the clock branches at the second level respectively, to obtain a simplified clock tree.

[0012] In one embodiment, the clock tree further includes: a third-level clock branch leading out from the second level, where the number of clock branches at the third level is less than the number of clock branches at the second level; the method further includes: counting the buffer units in the second level whose wire delay is less than the preset threshold, to obtain a third target number of the redundant buffer units in the second level; inserting the third target number of the redundant buffer units into the third-level clock branches, and deleting the third target number of the redundant buffer units from each of the clock branches at the second level respectively, to obtain a simplified clock tree.

[0013] In one embodiment, the preset threshold is 2 ps.

[0014] A second aspect of the embodiments of the present application provides a clock tree processing device, including: an acquisition module, configured to acquire a clock tree design to be processed, where the clock tree includes at least two levels of clock branches, and among them, the first level is led out from the second level, and the number of clock branches at the first level is greater than the number of clock branches at the second level; a first statistics module, configured to count the buffer units in the first level whose wire delay is less than the preset threshold, to obtain a first target number of the redundant buffer units in the first level; a first addition and deletion module, configured to insert the first target number of the redundant buffer units into the clock branches at the second level, and configured to delete the first target number of the redundant buffer units from each of the clock branches at the first level respectively, to obtain a simplified clock tree.

[0015] In one embodiment, the first statistics module is configured to: according to the delay parameters of the clock tree, count the number of the redundant buffer units fan-out by each clock branch in the first level, where the redundant buffer units are the number of redundant buffer units whose wire delay is less than the preset threshold, to obtain a set of numbers of the redundant buffer units in the first level; select the minimum number from the set of numbers corresponding to the first level as the first target number of the redundant buffer units in the first level.

[0016] In one embodiment, the first addition and deletion module is configured to: insert the first target number of the redundant buffer units into each of the clock branches at the second level.

[0017] In one embodiment, each clock branch at the second level leads out a plurality of first-level clock branches through a common point; the first statistics module is configured to: according to the delay parameter of the clock tree, for the same common point, count the number of the redundant buffer units fanned out by each of the first-level clock branches led out by the common point, where the redundant buffer unit is a buffer unit with a wire delay less than the preset threshold, to obtain a set of the number of the redundant buffer units in the first-level clock branches corresponding to the common point; and select the minimum number from the set of the number corresponding to the common point as the first target number corresponding to the common point.

[0018] In one embodiment, the first addition and deletion module is configured to: insert the first target number of the redundant buffer units into the clock branch at the second level where the common point is located, and delete the first target number of the redundant buffer units from each of the plurality of first-level clock branches led out by the common point, so as to obtain a simplified clock tree.

[0019] In one embodiment, the clock tree further includes: third-level clock branches leading out from the second level, and the number of the clock branches at the third level is less than the number of the clock branches at the second level; the apparatus further includes: a second statistics module, configured to, after inserting the first target number of the redundant buffer units into the clock branches at the second level, count the buffer units with a wire delay less than the preset threshold in the second level after inserting the first target number of the redundant buffer units, to obtain a second target number of the redundant buffer units in the second level; and a second addition and deletion module, configured to insert the second target number of the redundant buffer units into the third-level clock branches, and delete the second target number of the redundant buffer units from each of the clock branches at the second level, so as to obtain a simplified clock tree.

[0020] In one embodiment, the clock tree further includes: third-level clock branches leading out from the second level, and the number of the clock branches at the third level is less than the number of the clock branches at the second level; the apparatus further includes: a third statistics module, configured to count the buffer units with a wire delay less than the preset threshold in the second level, to obtain a third target number of the redundant buffer units in the second level; and a third addition and deletion module, configured to insert the third target number of the redundant buffer units into the third-level clock branches, and delete the third target number of the redundant buffer units from each of the clock branches at the second level, so as to obtain a simplified clock tree.

[0021] In one embodiment, the preset threshold is 2 ps.

[0022] A third aspect of the embodiments of the present application provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the method according to the first aspect and any of its embodiments of the present application.

[0023] A fourth aspect of the embodiments of the present application provides a non-transitory computer-readable storage medium for an electronic device, including: a program which, when run by the electronic device, causes the electronic device to execute the method according to the first aspect and any of its embodiments of the present application.

[0024] The clock tree processing method, device, equipment and storage medium provided by the present application perform statistics on the clock tree design to be processed, count the target number of redundant buffer units to be deleted at each level, then insert the target number of redundant buffer units in the previous level, and at the same time delete the target number of redundant buffer units in each branch of the current level. Since there are many branches in the current level, the number of deleted buffer units is greater than the number of inserted buffer units. Therefore, on the premise of ensuring that the delay from the clock source to the register clock terminal is controllable, the clock buffer units can be reduced as much as possible, achieving the purpose of reducing the number and area of units on the clock tree and reducing the power consumption on the clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present application;

[0027] Figure 2 Schematic diagram of a clock tree structure in an application scenario according to an embodiment of the present application;

[0028] Figure 3 Schematic flowchart of a clock tree processing method according to an embodiment of the present application;

[0029] Figure 4A Schematic diagram of a clock tree structure to be processed according to an embodiment of the present application;

[0030] Figure 4B Schematic diagram of a simplified clock tree structure according to an embodiment of the present application;

[0031] Figure 5ASchematic flowchart of a clock tree processing method according to an embodiment of the present application;

[0032] Figure 5B Schematic diagram of a clock tree structure to be processed according to an embodiment of the present application;

[0033] Figure 6 Schematic diagram of a clock tree processing apparatus according to an embodiment of the present application. Detailed implementation manners

[0034] The following will describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. In the description of the present application, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0035] In order to clearly describe the solution of this embodiment, the nouns involved are defined as follows:

[0036] Common path: The common clock point. When the clock signal starts to branch and grow a tree from a certain starting point, this starting point is called the common clock point of the clock tree.

[0037] multi-fanout: Multiple fanouts. When a point on the clock tree outputs one-to-many, this point is called a multi-fanout.

[0038] Such as Figure 1 As shown, this embodiment provides an electronic device 1, including: at least one processor 11 and a memory 12, Figure 1 Taking one processor as an example. The processor 11 and the memory 12 are connected through a bus 10. The memory 12 stores instructions executable by the processor 11. When the instructions are executed by the processor 11, the electronic device 1 can execute all or part of the processes of the methods in the following embodiments to reduce the clock buffer units as much as possible, achieve the purpose of reducing the number and area of units on the clock tree, and reducing the power consumption on the clock.

[0039] In one embodiment, the electronic device 1 can be a mobile phone, a tablet computer, a laptop computer, a desktop computer, or a large computing system composed of multiple computers.

[0040] Such as Figure 2 As shown, it is a schematic diagram of the clock tree of a chip in an actual scenario according to an embodiment of the present application. The clock tree starts from a clock source PLL and leads out N levels of clock branches, namely the Nth level Level N, the (N - 1)th level Level N - 1... the 2nd level Level 2, the 1st level Level 1, where N is a positive integer. Each level of the clock tree can include multiple clock branches, for example Figure 2Level 2 in total includes 4 Level-2 clock branches, and each Level-2 clock branch leads out 2 Level-1 clock branches. Therefore, Level 1 in total includes 8 clock branches. Based on the delay required by the actual load on each clock branch, it may include multiple buffer units (such as Figure 2 in represents a buffer unit), and each Level-1 clock branch is finally connected to the clock pin CP of the corresponding register to provide clock signal management for the circuit.

[0041] In the clock tree of the above chip, the more buffer units on the clock tree, the larger the proportion of the clock tree power consumption in the chip power consumption, which usually reaches about 40%. Therefore, in the clock tree design stage, optimizing the power consumption on the clock tree is very important for reducing the chip power consumption. The embodiment of the present application provides a clock tree processing method, which can minimize the clock buffer units as much as possible on the premise of ensuring that the delay from the clock source to the register clock terminal remains unchanged, so as to reduce the number and area of units on the clock tree and reduce the power consumption on the clock.

[0042] The following further describes in detail the clock tree processing method of the embodiment of the present application in conjunction with the illustrations.

[0043] Please refer to Figure 3 , which is the clock tree processing method of an embodiment of the present application. This method can be executed by the electronic device 1 shown in Figure 1 and can be applied to the clock tree optimization scenario shown in the above Figure 2 to minimize the clock buffer units as much as possible on the premise of ensuring that the delay from the clock source to the register clock terminal remains unchanged, so as to reduce the number and area of units on the clock tree and reduce the power consumption on the clock. The method includes the following steps:

[0044] Step 301: Obtain the clock tree design to be processed.

[0045] In this step, in the chip physical design stage, for the clock tree corresponding to the specific chip circuit design, after the clock tree design is completed, in order to reduce the power consumption of the clock tree, its structure can be optimized. The clock tree here can include multiple levels of clock branches, and the number of current-level clock branches is greater than that of the previous-level clock branches. As Figure 4A shown, it is a delay equivalence schematic diagram of a clock tree. Taking a clock tree with two levels of clock branches as an example, starting from the clock source clook root, the second level Level 2 leads out the first level Level 1. The number of clock branches of the first level Level 1 is 2, which is greater than the number of clock branches of the second level Level 2, which is 1. The two clock branches of the first level Level 1 are respectively connected to the clock pins CP of the registers to form the sinks sink1 and sink2 of two clock paths respectively.

[0046] Step 302: Count the buffer units in the first level with a wire delay less than a preset threshold to obtain the first target number of redundant buffer units in the first level.

[0047] In this step, the redundant buffer units are the buffer units with a wire delay less than the preset threshold, and the preset threshold can be 2 ps. In the actual scenario, to ensure the normal performance of the clock tree, it is necessary to keep the clock tree before and after optimization having the same clock function, that is, it is necessary to ensure that the delay from the clock source to the register clock pin CP remains unchanged. Therefore, only the buffer units with a wire delay of zero or close to zero are redundant buffer units. To eliminate the redundant buffer units, the buffer units in the first level with a wire delay less than the preset threshold can be counted to obtain the first target number of redundant buffer units. Here, the buffer units with a wire delay in the range of 0 ps to 2 ps can be selected as the redundant buffer units.

[0048] In one embodiment, step 302 may specifically include: According to the delay parameters of the clock tree, count the number of redundant buffer units fan out by each clock branch in the first level, where the redundant buffer units are the buffer units with a wire delay less than the preset threshold, to obtain the number set of redundant buffer units in the first level. Select the minimum number from the number set corresponding to the first level as the first target number of redundant buffer units in the first level.

[0049] In this step, the delay parameter here may be the RC parameter (circuit time parameter). In the backend physical process of chip design, for the module that has completed the clock tree design and metal layer wiring, by extracting the RC parameter, the delay information file of all units and wires on the clock tree can be obtained. Search for the wires on the clock tree with a delay of zero or close to zero (such as within 0 ps to 2 ps) from the file list, and the units before such wires are used as buffer units. Usually, the same type of buffer units are selected in the clock tree design, and the delay at the same temperature and voltage is a fixed value. Count the number of redundant buffer units fan out by each clock branch in the first level. That is to say, there are multiple clock branches in the first level, and each clock branch corresponds to a number of redundant buffer units. They are used as elements in the number set of redundant buffer units in the first level, and then select the minimum value from the number set of redundant buffer units in the first level as the first target number. In this way, the impact of adding and deleting redundant buffer units on the clock tree performance can be reduced.

[0050] As Figure 4A shown, one symbol represents one buffer unit, "●" represents the wire on the clock tree with a delay of zero or close to zero, and one The symbol represents a redundant buffer unit with a fan-out delay of zero or close to zero. It is statistically obtained that the number of units with a fan-out delay of zero in the previous stage of sink 1 (assumed to be level 1) is 3, and the number of units with a fan-out delay of zero in the previous stage of sink 2 (also level 1) is 2. Then, the minimum value of 2 among them can be taken as the first target tree quantity of the redundant buffer units in level 1, that is, the first target quantity is 2.

[0051] Step 303: Insert the first target quantity of redundant buffer units into the clock branches of the second level, and delete the first target quantity of redundant buffer units from each clock branch of the first level to obtain a simplified clock tree.

[0052] In this step, after statistically obtaining the first target quantity of the redundant buffer units in the first level, the original clock tree can be pruned based on this first target quantity to achieve the purpose of minimizing the clock buffer units as much as possible while ensuring that the delay from the clock source to the register clock terminal remains unchanged. Since these redundant buffer units have little or no impact on the clock delay in the first level, the first target quantity of redundant buffer units can be deleted from the clock branches of the first level, and at the same time, the first target quantity of redundant buffer units can be inserted into the clock branches of the second level to obtain a simplified clock tree.

[0053] Take Figure 4A the shown clock tree design to be processed as an example. The first target quantity of the redundant buffer units in level 1 is 2. Then, 2 redundant buffer units can be deleted from the two clock branches of level 1 respectively, that is, delete Figure 4A the 2 in the branch of level 1, and then find the clock bifurcation unit in the previous level, level 2, and insert the 2 buffer units with a fan-out delay of zero close to this bifurcation unit to obtain the optimized clock tree as shown in Figure 4B . This operation is to hang the buffer units inserted before multiple sink points to the previous level path. In this way, compared with the clock tree shown in Figure 4A , the number of buffer units that can be reduced in the clock tree in Figure 4B is the number of redundant buffer units deleted in the first level minus the number of buffer units added in the previous level, that is, the number of deleted in level 1 minus the number of inserted in level 2.

[0054] It can be calculated using the following formula:

[0055] ▲=(A - 1)α

[0056] Among them, A is the number of clock branches in the first - level level 1, that is, the number of sinks. α is the first target number, that is Figure 4A and Figure 4B the minimum number of buffer units with zero fan - out of sink1 and sink2 in Figure 4B The number of buffer units that can be reduced in the clock tree in

[0057] The delay from the clock root to sink 1 remains unchanged before and after this process, and the delay from the clock root to sink2 also remains unchanged. During the timing repair process, the clock latency of sink1 and sinks2 remains unchanged, which does not affect the clock skew of the timing path between sinks and does not introduce new timing violations, that is, the setup time and hold time still remain satisfied. On the premise of ensuring that the delay from the clock source to the register clock terminal remains unchanged, the clock buffer units are reduced as much as possible to achieve the purpose of reducing the number and area of units on the clock tree and reducing the power consumption on the clock.

[0058] For the above - mentioned clock tree processing method, by statistically analyzing the clock tree design to be processed, the target number of redundant buffer units to be deleted at each level is counted, and then the target number of redundant buffer units is inserted in the previous level. At the same time, the redundant buffer units with the target number of each branch in the current level are deleted. Since there are more branches in the current level, the number of deleted buffer units is greater than the number of inserted buffer units. Therefore, on the premise of ensuring that the delay from the clock source to the register clock terminal is controllable, the clock buffer units can be reduced as much as possible to achieve the purpose of reducing the number and area of units on the clock tree and reducing the power consumption on the clock.

[0059] Please refer to Figure 5A which is the clock tree processing method of an embodiment of the present application. This method can be executed by the Figure 1 shown electronic device 1 and can be applied to the clock tree optimization scenario shown in the above Figure 2 to reduce the clock buffer units as much as possible on the premise of ensuring that the delay from the clock source to the register clock terminal remains unchanged, so as to achieve the purpose of reducing the number and area of units on the clock tree and reducing the power consumption on the clock. The method includes the following steps:

[0060] Step 501: Obtain the clock tree design to be processed. For details, refer to the description of step 301 in the above - mentioned embodiment.

[0061] Step 502: According to the delay parameters of the clock tree, for the same common point, count the number of redundant buffer units with the fan - out of each first - level clock branch led out from the common point, and obtain the set of the number of redundant buffer units in multiple first - level clock branches corresponding to the common point.

[0062] In this step, the second level may include multiple clock branches, and each clock branch of the second level leads out multiple first-level clock branches through a common point. When counting redundant buffer units with a statistical wire delay less than a preset threshold, the clock branches led out by each common point are counted separately, and a set of the number of redundant buffer units in the first-level clock branches corresponding to each common point is obtained. That is, calculate the number of clock buffer units with zero wire delay for each branch fanning out from the same common point, and take the minimum value of all branches.

[0063] As Figure 5B shown, it is a clock tree to be processed in an embodiment of the present application. This clock tree starts from the clock source PLL and leads out 5 levels of clock branches, namely the fifth level Level 5, the fourth level Level 4, the third level Level 3, the second level Level 2, and the first level Level 1. One symbol represents a buffer unit, and one symbol represents a redundant buffer unit with a fanning-out wire delay of zero or close to zero. Each level of the clock tree may include multiple clock branches. For example Figure 5B in, from Level 1 to Level 5, the number of clock branches at each level is 16, 8, 4, 2 in sequence. The 16 clock branches in Level 1 are led out by each clock branch in Level 2 at a common point. When counting redundant buffer units with a wire delay less than the preset threshold in Level 1, for each clock branch in Level 2 at the common point, the statistics of each clock branch in Level 1 are separately performed, and a set of the number of redundant buffer units in one clock branch in Level 1 corresponding to each common point can be obtained. There are 8 common points for leading out the 16 clock branches in Level 1, so 8 sets of the number of redundant buffer units in the clock branches in Level 1 will be obtained and correspond to the corresponding common points one by one. In this way, it is possible to avoid missing a certain clock branch and perform regular statistics, which is beneficial to simplifying the calculation process.

[0064] Step 503: Select the minimum number from the set of numbers corresponding to the common point as the first target number corresponding to the common point.

[0065] In this step, taking the example shown above Figure 5B in, the number of clock branches in Level 1 is 16, corresponding to 8 common points, that is, 8 sets of the number of redundant buffer units. Then, the minimum value in each set of numbers is separately selected as the first target number of the common point. For example Figure 5BIn Level 1, 2 clock branches are drawn from the uppermost common point S. The number of redundant buffer units in these 2 first-level clock branches is 5 and 6 respectively. Then the set of numbers corresponding to the common point S is {5, 6}, and the minimum value is 5. So the first target number in Level 1 corresponding to the common point S is 5. Similarly, the first target numbers corresponding to the other 7 common points can be obtained.

[0066] Step 504: Insert the first target number of redundant buffer units into the second-level clock branches where the common points are located, and delete the first target number of redundant buffer units from each of the multiple first-level clock branches drawn from the common points, to obtain a simplified clock tree.

[0067] In this step, during the process of adding and deleting buffer units, the addition and deletion processing can be performed on the front and rear two-level clock branches corresponding to each common point. Specifically, taking the common point S in step 503 as an example, 5 redundant buffer units are deleted from each clock branch of Level 1, and 5 redundant buffer units are inserted into the branch corresponding to the common point S in the second level Level 2.

[0068] Similarly, corresponding processing is also done for other common points, that is, inserting the first target number of redundant buffer units into each clock branch of the second level, and a simplified clock tree can be obtained. Since during the addition and deletion process, the number of deleted redundant buffer units is greater than the number of inserted redundant buffer units, the number of buffer units in the clock tree can be greatly reduced, reducing power consumption.

[0069] In one embodiment, the method may further include: counting the buffer units in the second level whose wire delay is less than a preset threshold after inserting the first target number of redundant buffer units, to obtain the second target number of redundant buffer units in the second level. Insert the second target number of redundant buffer units into the third-level clock branches, and delete the second target number of redundant buffer units from each clock branch of the second level, to obtain a simplified clock tree.

[0070] In this step, if the clock tree to be processed includes clock branches of more than two levels, for example, the clock tree further includes: third-level clock branches leading out from the second level, and the number of clock branches in the third level is less than the number of clock branches in the second level. As Figure 5B shown, this clock tree includes 5 levels of clock branches, namely the fifth level Level 5, the fourth level Level 4, the third level Level 3, the second level Level 2, and the first level Level 1. It can be counted starting from the first level in a manner similar to that in steps 502 to 504, counting the number of redundant buffer units level by level, and adding and deleting redundant buffer units level by level. For the current level, when counting the number of redundant buffer units, the buffer units inserted from the subsequent level participate in the counting of this level.

[0071] Taking the above as an example Figure 5B After step 504, count the number of redundant buffer units in the second level. At this time, the redundant buffer units inserted into the second level in step 504 will be included in the statistics of this level. Therefore, count the buffer units in the second level whose wire delay is less than the preset threshold after inserting the first target number of redundant buffer units, and obtain the second target number of redundant buffer units in the second level. Then, in a manner similar to step 504, insert the second target number of redundant buffer units into the clock branches of the third level, and delete the second target number of redundant buffer units from each clock branch of the second level respectively, to obtain the simplified clock tree of this level. Perform the same processing on the subsequent third level (Level 3), fourth level (Level 4), fifth level (Level 5), and so on in sequence, and finally obtain the simplified clock tree.

[0072] In one embodiment, the method may further include: counting the buffer units in the second level whose wire delay is less than the preset threshold, and obtaining the third target number of redundant buffer units in the second level. The clock tree further includes: leading out the clock branches of the third level from the second level, and the number of clock branches in the third level is less than the number of clock branches in the second level. Insert the third target number of redundant buffer units into the clock branches of the third level, and delete the third target number of redundant buffer units from each clock branch of the second level respectively, to obtain the simplified clock tree.

[0073] In this step, if the clock tree to be processed includes more than two levels of clock branches, the processes of counting, deleting, and inserting redundant buffer units can also be performed independently and in parallel for each level, and the buffer units inserted from the subsequent level do not participate in the statistics of this level. The specific process is as follows:

[0074] First step: Start counting from the first level, and count the number of redundant buffer units with zero wire delay in each level in parallel.

[0075] Second step: Calculate the number of clock buffer units with zero fan-out wire delay for each branch at the same common point, and take the minimum value x of all branches as the corresponding target number.

[0076] Third step: Add x redundant buffer units in front of the corresponding common point, specifically insert them closely in front of the branching unit of the previous level.

[0077] Fourth step: Without affecting the timing, that is, both the setup clock and the hold time need to meet the requirements, it is necessary to ensure that the Clock latency of the sink is equivalent to the original. Since x redundant buffer units have been inserted in front of the branching unit of the previous level, then x redundant buffer units of each branch in the current level need to be deleted, that is, delete x redundant buffer units from the corresponding branches in the current level.

[0078] The above corresponding operations are performed at the second level, and the third level can be executed in parallel until the last-level common point is reached, obtaining a simplified clock tree.

[0079] For example, starting from the first level, the number of branches at each level is A, B, C... Z in sequence, and the minimum number of redundant buffer units corresponding to the clock branches at each level is α, β, γ... ω in sequence.

[0080] Then, the number of units reduced at the first level is: ▲=(A - 1)α

[0081] The number of units reduced at the second level is: ▲=(B - 1)β

[0082] The number of units reduced at the third level is: ▲=(C - 1)γ ......

[0084] The number of units reduced at the Nth level is: ▲=(Z - 1)ω

[0085] The total number of units that can be reduced is: Σ▲=(A - 1)α+(B - 1)β+(C - 1)γ+......(Z - 1)ω.

[0086] As Figure 5B shown, where N = 5. Starting from the first level, the number of clock branches at each level is 16, 8, 4, 2, 1 in sequence. The minimum number of redundant buffer units corresponding to the clock branches at each level is 4, 5, 3, 3, 0 in sequence. According to the above formula, we can obtain:

[0087] Σ▲=(A - 1)α+(B - 1)β+(C - 1)γ+......(Z - 1)ω

[0088] =(16 - 1)*4+(8 - 1)*5+(4 - 1)*3+(2 - 1)*3+(1 - 1)*0

[0089] =60 + 35 + 9 + 3 = 107

[0090] Therefore, after the simplification process, as Figure 5B shown, the number of redundant buffer units that can be reduced in the clock tree structure is 107.

[0091] In one embodiment, the above clock tree processing method can be used in all stages after the clock tree is designed at the back end of the chip. Optionally, this method can be used to optimize the clock tree to be processed before approaching tape-out, which can not only efficiently achieve the purpose of optimizing the clock structure, but also minimize the delay units on the clock to the greatest extent, achieving the purpose of reducing the area of clock units, reducing the design density, and reducing power consumption.

[0092] Please refer to Figure 6, which is the clock tree processing device 600 according to an embodiment of the present application. This device can be applied to Figure 1 the electronic device 1 shown in Figure 2 and can be applied to the clock tree optimization scenario shown above. On the premise of ensuring that the delay from the clock source to the register clock terminal remains unchanged, as many clock buffer units as possible are reduced to achieve the purpose of reducing the number and area of units on the clock tree and reducing the power consumption on the clock. The device includes: an acquisition module 601, a first statistics module 602, and a first addition and deletion module 603. The principle relationships of each module are as follows:

[0093] The acquisition module 601 is used to acquire the clock tree design to be processed. The clock tree includes at least two levels of clock branches, where the first level is led out from the second level, and the number of clock branches in the first level is greater than the number of clock branches in the second level. The first statistics module 602 is used to count the buffer units in the first level whose wire delay is less than a preset threshold to obtain the first target number of redundant buffer units in the first level. The first addition and deletion module 603 is used to insert the first target number of redundant buffer units into the clock branches in the second level and is used to delete the first target number of redundant buffer units from each clock branch in the first level respectively to obtain a simplified clock tree.

[0094] In one embodiment, the first statistics module 602 is used to: according to the delay parameters of the clock tree, count the number of redundant buffer units fan-out by each clock branch in the first level, where the redundant buffer units are the number of redundant buffer units whose wire delay is less than the preset threshold, to obtain the set of the number of redundant buffer units in the first level. Select the minimum number from the set of numbers corresponding to the first level as the first target number of redundant buffer units in the first level.

[0095] In one embodiment, the first addition and deletion module 603 is used to: insert the first target number of redundant buffer units into each clock branch in the second level.

[0096] In one embodiment, each clock branch in the second level leads out multiple first-level clock branches through a common point. The first statistics module 602 is used to: according to the delay parameters of the clock tree, for the same common point, count the number of redundant buffer units fan-out by each first-level clock branch led out by the common point, where the redundant buffer units are the buffer units whose wire delay is less than the preset threshold, to obtain the set of the number of redundant buffer units in the first-level clock branches corresponding to the common point. Select the minimum number from the set of numbers corresponding to the common point as the first target number corresponding to the common point.

[0097] In one embodiment, the first addition and deletion module 603 is used to: insert the first target number of redundant buffer units into the clock branch in the second level where the common point is located and delete the first target number of redundant buffer units from each of the multiple first-level clock branches led out by the common point respectively to obtain a simplified clock tree.

[0098] In one embodiment, the clock tree further includes: a third-level clock branch leading out from the second level, and the number of third-level clock branches is less than the number of second-level clock branches. The apparatus further includes: a second statistics module 604, configured to, after inserting a first target number of redundant buffer units into the second-level clock branches, count the buffer units in the second level whose wire delay is less than a preset threshold after inserting the first target number of redundant buffer units, so as to obtain a second target number of redundant buffer units in the second level. A second addition and deletion module 605, configured to insert a second target number of redundant buffer units into the third-level clock branches, and respectively delete the second target number of redundant buffer units from each clock branch in the second level, so as to obtain a simplified clock tree.

[0099] In one embodiment, the clock tree further includes: a third-level clock branch leading out from the second level, and the number of third-level clock branches is less than the number of second-level clock branches. The apparatus further includes: a third statistics module 606, configured to count the buffer units in the second level whose wire delay is less than a preset threshold, so as to obtain a third target number of redundant buffer units in the second level. A third addition and deletion module 607, configured to insert a third target number of redundant buffer units into the third-level clock branches, and respectively delete the third target number of redundant buffer units from each clock branch in the second level, so as to obtain a simplified clock tree.

[0100] In one embodiment, the preset threshold is 2 ps.

[0101] For a detailed description of the above clock tree processing apparatus 600, please refer to the description of the relevant method steps in the above embodiments.

[0102] The embodiment of the present invention further provides a non-transitory computer-readable storage medium, including: a program, which, when running on an electronic device, enables the electronic device to execute all or part of the processes of the methods in the above embodiments. Wherein, the storage medium may be a disk, an optical disc, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc. The storage medium may also include a combination of the above types of memories.

[0103] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A clock tree processing method, characterized in that, it includes: Obtain a clock tree design to be processed, where the clock tree includes at least two levels of clock branches. Among them, the first level is led out from the second level, and the number of clock branches in the first level is greater than the number of clock branches in the second level; Count the buffer units in the first level with wire delay less than a preset threshold to obtain a first target number of redundant buffer units in the first level; Insert the first target number of the redundant buffer units into the clock branches of the second level, and delete the first target number of the redundant buffer units from each of the clock branches in the first level respectively to obtain a simplified clock tree; The step of counting the buffer units in the first level with wire delay less than a preset threshold to obtain a first target number of redundant buffer units in the first level includes: According to the delay parameters of the clock tree, count the number of the redundant buffer units fan - out from each clock branch in the first level, where the redundant buffer unit is a buffer unit with wire delay less than the preset threshold, to obtain a set of numbers of redundant buffer units in the first level; Select the minimum number from the set of numbers corresponding to the first level as the first target number of the redundant buffer units in the first level; Or, Each clock branch of the second level leads out multiple first - level clock branches through a common point; The step of counting the buffer units in the first level with wire delay less than a preset threshold to obtain a first target number of redundant buffer units in the first level includes: According to the delay parameters of the clock tree, for the same common point, count the number of the redundant buffer units fan - out from each of the first - level clock branches led out by the common point, where the redundant buffer unit is a buffer unit with wire delay less than the preset threshold, to obtain a set of numbers of redundant buffer units in the first - level clock branches corresponding to the common point; Select the minimum number from the set of numbers corresponding to the common point as the first target number corresponding to the common point.

2. The method according to claim 1, characterized in that, The step of inserting the first target number of the redundant buffer units into the clock branches of the second level includes: Insert the first target number of the redundant buffer units into each of the clock branches of the second level.

3. The method according to claim 1, characterized in that, The step of inserting the first target number of the redundant buffer units into the clock branches of the second level and deleting the first target number of the redundant buffer units from each of the clock branches in the first level respectively to obtain a simplified clock tree includes: Insert the first target number of the redundant buffer units into the clock branches of the second level where the common point is located, and delete the first target number of the redundant buffer units from each of the multiple first - level clock branches led out by the common point respectively to obtain a simplified clock tree.

4. The method according to claim 1, characterized in that, The clock tree further includes: a third-level clock branch leading out from the second level, where the number of clock branches at the third level is less than the number of clock branches at the second level; after inserting the first target number of the redundant buffer units into the clock branches at the second level, the method further includes: Counting the buffer units in the second level whose wire delay is less than the preset threshold after inserting the first target number of the redundant buffer units, to obtain a second target number of the redundant buffer units in the second level; Inserting the second target number of the redundant buffer units into the third-level clock branches, and respectively deleting the second target number of the redundant buffer units from each of the clock branches at the second level, to obtain a simplified clock tree.

5. The method according to claim 1, wherein, The clock tree further includes: a third-level clock branch leading out from the second level, where the number of clock branches at the third level is less than the number of clock branches at the second level; the method further includes: Counting the buffer units in the second level whose wire delay is less than the preset threshold, to obtain a third target number of the redundant buffer units in the second level; Inserting the third target number of the redundant buffer units into the third-level clock branches, and respectively deleting the third target number of the redundant buffer units from each of the clock branches at the second level, to obtain a simplified clock tree.

6. The method according to claim 1, wherein, The preset threshold is 2 ps.

7. A clock tree processing device, wherein, It includes: An acquisition module, configured to acquire a clock tree design to be processed, where the clock tree includes at least two levels of clock branches, wherein the first level leads out from the second level, and the number of clock branches at the first level is greater than the number of clock branches at the second level; A first statistics module, configured to count the buffer units in the first level whose wire delay is less than a preset threshold, to obtain a first target number of redundant buffer units in the first level; A first addition and deletion module, configured to insert the first target number of the redundant buffer units into the clock branches at the second level, and configured to respectively delete the first target number of the redundant buffer units from each of the clock branches at the first level, to obtain a simplified clock tree; The first statistics module is specifically configured to: According to the delay parameters of the clock tree, count the number of the redundant buffer units fan-out by each clock branch in the first level, where the redundant buffer units are buffer units with wire delay less than the preset threshold, to obtain a set of the number of redundant buffer units in the first level; select the minimum number from the set of numbers corresponding to the first level as the first target number of the redundant buffer units in the first level; Or, Each clock branch of the second stage leads out a plurality of first-stage clock branches through a common point; according to the delay parameter of the clock tree, for the same common point, count the number of redundant buffer units fan-out by each of the first-stage clock branches led out by the common point, where the redundant buffer unit is a buffer unit with a wire delay less than the preset threshold, to obtain a set of the number of redundant buffer units in the first-stage clock branches corresponding to the common point; select the minimum number from the set of numbers corresponding to the common point as the first target number corresponding to the common point.

8. An electronic device, characterized in that, comprising: a memory for storing a computer program; a processor for executing the computer program to implement the method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium for an electronic device, characterized in that, comprising: a program which, when run by an electronic device, causes the electronic device to execute the method according to any one of claims 1 to 6.

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