Circuit, computing chip and method for executing hash algorithm

Abstract

The present disclosure relates to a circuit, a computing chip and a method for executing a hash algorithm. A circuit includes: a plurality of operation stages arranged in a pipeline structure, each including the 0th to 15th extended registers; and a plurality of extended data operation logic modules, each arranged between adjacent operation stages, and including a first submodule for calculating the extended data of the 0th extended register for the next operation stage based on the extended data of the 2nd extended register of the current operation stage, a second submodule for calculating the extended data of the 14th extended register for the next operation stage based on the extended data of the 0th and 14th extended registers of the current operation stage, a third submodule for calculating the extended data of the 1st extended register for the next operation stage based on the extended data of the 3rd extended register of the current operation stage, and a fourth submodule for calculating the extended data of the 15th extended register for the next operation stage based on the extended data of the 1st and 15th extended registers of the current operation stage.

Description

Technical Field

[0001] The present disclosure generally relates to circuits, computing chips, and related methods for performing hash algorithms. Background Art

[0002] A hash algorithm is an algorithm that takes variable-length data as input and generates a fixed-length hash value as output. Its essence is the refinement of information. Since 1993, the U.S. National Institute of Standards and Technology has designed and released several versions of the secure hash algorithm SHA (Secure Hash Algorithm), and SHA-256 is one of the secure hash algorithms with a hash length of 256 bits. Summary of the invention

[0003] According to a first aspect of the present disclosure, a circuit for executing a hash algorithm is provided, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register, each extension register being configured to store extended data of a current operation stage; and a plurality of extended data operation logic modules, each extended data operation logic module being arranged between corresponding two adjacent operation stages of the plurality of operation stages, the adjacent two operation stages comprising a first operation stage and a second operation stage after the first operation stage, each extended data operation logic module comprising: a first submodule configured to calculate a hash value for storage in a second operation stage based on the extended data stored in the second extension register of the first operation stage; a second submodule configured to calculate, based on the extended data stored in the 0th extended register of the first operation level and the 14th extended register of the first operation level, the extended data for storage in the 14th extended register of the second operation level; a third submodule configured to calculate, based on the extended data stored in the 3rd extended register of the first operation level, the extended data for storage in the 1st extended register of the second operation level; and a fourth submodule configured to calculate, based on the extended data stored in the 1st extended register and the 15th extended register of the first operation level, the extended data for storage in the 15th extended register of the second operation level; wherein the extended data for storage in the (i-2)th extended register of the second operation level is the extended data stored in the i-th extended register of the first operation level, wherein 4≤i≤15 and i is an integer.

[0004] According to a second aspect of the present disclosure, a circuit for executing a hash algorithm is provided, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a first additional register and a second additional register, each extension register being configured to store extended data of a current operation stage, each additional register being configured to store intermediate data for calculating the extended data; and a plurality of extended data operation logic modules, each extended data operation logic module being arranged between corresponding two adjacent operation stages of the plurality of operation stages, the adjacent two operation stages comprising a first operation stage and a second operation stage after the first operation stage, each extended data operation logic module comprising: a first submodule configured to calculate a hash value based on the extended data stored in the extension register of the first operation stage a second submodule configured to calculate the extended data for storage in the 14th extended register of the second operation level based on the intermediate data stored in the first additional register of the first operation level and the extended data stored in the 14th extended register of the first operation level; a third submodule configured to calculate the intermediate data for storage in the second additional register of the second operation level based on the extended data stored in the extended register of the first operation level; and a fourth submodule configured to calculate the extended data for storage in the 15th extended register of the second operation level based on the intermediate data stored in the second additional register of the first operation level and the extended data stored in the 15th extended register of the first operation level; wherein the extended data for storage in the (i-2)th extended register of the second operation level is the extended data stored in the i-th extended register of the first operation level, wherein 2≤i≤15 and i is an integer.

[0005] According to a third aspect of the present disclosure, a circuit for executing a hash algorithm is provided, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a second additional register, each extension register being configured to store extended data of a current operation stage, and the second additional register being configured to store intermediate data for calculating the extended data; and a plurality of extended data operation logic modules, each extended data operation logic module being arranged between corresponding two adjacent operation stages of the plurality of operation stages, the adjacent two operation stages comprising a first operation stage and a second operation stage after the first operation stage, each extended data operation logic module comprising: a first submodule configured to calculate a hash value based on the extended data stored in the second extension register of the first operation stage The invention relates to a method for calculating the extended data for storing in the 0th extended register of the second operation level based on the extended data stored in the 0th extended register of the second operation level; a second submodule is configured to calculate the extended data for storing in the 14th extended register of the second operation level based on the extended data stored in the 0th extended register and the 14th extended register of the first operation level; a third submodule is configured to calculate the intermediate data for storing in the second additional register of the second operation level based on the extended data stored in the extended register of the first operation level; and a fourth submodule is configured to calculate the extended data for storing in the 15th extended register of the second operation level based on the intermediate data stored in the second additional register of the first operation level and the extended data stored in the 15th extended register of the first operation level; wherein the extended data for storing in the (i-2)th extended register of the second operation level is the extended data stored in the ith extended register of the first operation level, wherein 3≤i≤15 and i is an integer.

[0006] According to a fourth aspect of the present disclosure, a circuit for executing a hash algorithm is provided, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a first additional register, each extension register being configured to store extended data of a current operation stage, the first additional register being configured to store intermediate data for calculating the extended data; and a plurality of extended data operation logic modules, each extended data operation logic module being arranged between corresponding two adjacent operation stages of the plurality of operation stages, the adjacent two operation stages comprising a first operation stage and a second operation stage after the first operation stage, each extended data operation logic module comprising: a first submodule configured to calculate an intermediate data for storage in the first additional register of a second operation stage based on the extended data stored in the extension register of the first operation stage a second submodule configured to calculate the extended data for storage in the 14th extended register of the second operation level based on the intermediate data stored in the first additional register of the first operation level and the extended data stored in the 14th extended register of the first operation level; a third submodule configured to calculate the extended data for storage in the 1st extended register of the second operation level based on the extended data stored in the 3rd extended register of the first operation level; and a fourth submodule configured to calculate the extended data for storage in the 15th extended register of the second operation level based on the extended data stored in the 1st extended register and the 15th extended register of the first operation level; wherein the extended data for storage in the (i-2)th extended register of the second operation level is the extended data stored in the i-th extended register of the first operation level, wherein 4≤i≤15 and i is an integer, and the extended data for storage in the 0th extended register of the second operation level is the extended data stored in the 2nd extended register of the first operation level.

[0007] According to a fifth aspect of the present disclosure, a computing chip is provided, which includes the circuit as described in the above aspects.

[0008] According to a sixth aspect of the present disclosure, there is provided a method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extended register to a 15th extended register, each extended register being configured to store extended data of a current operation stage, the method comprising: for two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: calculating, based on the extended data stored in the 2nd extended register of the first operation stage, a 0th extended register for storage in the second operation stage; ; calculating the extended data for storage in the 14th extended register of the second operation level based on the extended data stored in the 0th extended register and the 14th extended register of the first operation level; calculating the extended data for storage in the 1st extended register of the second operation level based on the extended data stored in the 3rd extended register of the first operation level; calculating the extended data for storage in the 15th extended register of the second operation level based on the extended data stored in the 1st extended register and the 15th extended register of the first operation level; and using the extended data stored in the ith extended register of the first operation level as the extended data for storage in the (i-2)th extended register of the second operation level, where 4≤i≤15 and i is an integer.

[0009] According to a seventh aspect of the present disclosure, a method for calculating extended data in a circuit for executing a hash algorithm is provided, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a first additional register and a second additional register, each extension register being configured to store extended data of a current operation stage, each additional register being configured to store intermediate data for calculating extended data, the method comprising: for two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: calculating, based on the extended data stored in the extension register of the first operation stage, intermediate data for storing in the second operation stage ; calculating the extended data for storage in the 14th extended register of the second operation level based on the intermediate data stored in the first additional register of the first operation level and the extended data stored in the 14th extended register of the first operation level; calculating the intermediate data for storage in the second additional register of the second operation level based on the extended data stored in the extended register of the first operation level; calculating the extended data for storage in the 15th extended register of the second operation level based on the intermediate data stored in the second additional register of the first operation level and the extended data stored in the 15th extended register of the first operation level; and using the extended data stored in the i-th extended register of the first operation level as the extended data for storage in the (i-2)-th extended register of the second operation level, where 2≤i≤15 and i is an integer.

[0010] According to an eighth aspect of the present disclosure, there is provided a method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a second additional register, each extension register being configured to store extended data of a current operation stage, the second additional register being configured to store intermediate data for calculating the extended data, the method comprising: for two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: calculating, based on the extended data stored in the second extension register of the first operation stage, an intermediate data for storing in the second extension register of the first operation stage; The invention relates to a method for calculating the extended data in the 0th extended register of the second operation level; calculating the extended data for storage in the 14th extended register of the second operation level based on the extended data stored in the 0th extended register and the 14th extended register of the first operation level; calculating the intermediate data for storage in the second additional register of the second operation level based on the extended data stored in the extended register of the first operation level; calculating the extended data for storage in the 15th extended register of the second operation level based on the intermediate data stored in the second additional register of the first operation level and the extended data stored in the 15th extended register of the first operation level; and using the extended data stored in the i-th extended register of the first operation level as the extended data for storage in the (i-2)th extended register of the second operation level, wherein 3≤i≤15 and i is an integer.

[0011] According to a ninth aspect of the present disclosure, there is provided a method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a first additional register, each extension register being configured to store extended data of a current operation stage, the first additional register being configured to store intermediate data for calculating extended data, the method comprising: for two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: calculating intermediate data for storage in the first additional register of the second operation stage based on the extended data stored in the extension register of the first operation stage; calculating extended data for storage in the 14th extension register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extension register of the first operation stage; calculating extended data for storage in the 1st extension register of the second operation stage based on the extended data stored in the 3rd extension register of the first operation stage; The extended data for storage in the 15th extended register of the second operation level is calculated based on the extended data stored in the 1st extended register and the 15th extended register of the first operation level; and the extended data stored in the ith extended register of the first operation level is used as the extended data for storage in the (i-2)th extended register of the second operation level, where 4≤i≤15 and i is an integer, and the extended data stored in the 2nd extended register of the first operation level is used as the extended data for storage in the 0th extended register of the second operation level.

[0012] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0014] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram showing an exemplary pipeline structure having 64 operation stages for executing the SHA-256 algorithm is shown;

[0016] Figure 2 Schematically shows Figure 1 Conventional operation logic between extended data in extended registers of two adjacent operation stages in the pipeline structure;

[0017] Figure 3 The schematic diagram shows Figure 1 The pipeline structure in the embodiment is transformed into an operation logic between extended data in extended registers of two adjacent operation stages in the case of 32 operation stages;

[0018] Figure 4 A schematic block diagram of a circuit for executing a hash algorithm according to some embodiments of the present disclosure is shown;

[0019] Figures 5 to 7 The embodiment according to the present disclosure is schematically shown as follows Figure 4 An exemplary configuration of a portion of the circuit shown that includes an extended data operation logic module;

[0020] Figure 8 A schematic block diagram of a circuit for executing a hash algorithm according to some embodiments of the present disclosure is shown;

[0021] Figures 9 to 12 The embodiment according to the present disclosure is schematically shown as follows Figure 8 An exemplary configuration of a portion of the circuit shown that includes an extended data operation logic module;

[0022] Fig.13 A schematic block diagram of a circuit for executing a hash algorithm according to some embodiments of the present disclosure is shown;

[0023] Fig.14 and Fig.15 The embodiment according to the present disclosure is schematically shown as follows Fig.13 An exemplary configuration of a portion of the circuit shown that includes an extended data operation logic module;

[0024] Fig.16 A schematic block diagram of a circuit for executing a hash algorithm according to some embodiments of the present disclosure is shown;

[0025] Fig.17 The embodiment according to the present disclosure is schematically shown as follows Fig.16 An exemplary configuration of a portion of the circuit shown including an extended data arithmetic logic module; and

[0026] Figures 18 to 21 An exemplary flow chart of a method for calculating extended data according to an embodiment of the present disclosure is shown.

[0027] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0028] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0029] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0030] The following description of at least one exemplary embodiment is merely illustrative in nature and is not intended to limit the present disclosure and its application or use. It will be appreciated by those skilled in the art that they are merely illustrative of exemplary ways that may be used to implement the present invention, rather than an exhaustive approach.

[0031] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0032] In order to present the inventive concept of the present disclosure more clearly and intuitively, the SHA-256 algorithm will be briefly introduced below and used as a representative example of the hash algorithm to describe the circuit and related method for executing the hash algorithm according to the embodiment of the present disclosure. Those skilled in the art will understand that the circuit and related method for executing the hash algorithm according to the embodiment of the present disclosure are applicable to any hash algorithm, and can even be further applied to any other suitable circuit and method, and is not limited to implementing the SHA-256 algorithm.

[0033] Figure 1 A schematic diagram of an exemplary pipeline structure for executing the SHA-256 algorithm is shown. The input of SHA-256 is a maximum length less than 2 64The output is a 256-bit data summary, i.e., a hash value. The input data is processed in 512-bit blocks. In order to implement the SHA-256 algorithm, 64 rounds of repeated operations are required for each 512-bit data block. Therefore, a pipeline structure including 64 operation stages can be used to parallelize 64 sets of data. Figure 1 As shown, the pipeline structure includes the 0th operation stage to the 63rd operation stage, each operation stage includes 8 32-bit compression registers A to H for storing intermediate values ​​and 16 32-bit extension registers R for storing extended data. 0 To R 15 The 0th operation stage can receive the input data block and divide it into 8 32-bit data and store them in compression registers A to H respectively, and then process them and provide them to the 1st operation stage. After that, each operation stage operates on the operation result received by the previous operation stage and provides its own operation result to the next operation stage. Finally, after 64 operation stages, the operation core can output the hash operation result of the SHA-256 algorithm executed once on the input data.

[0034] The following is a detailed discussion of the internal logic of a round of operations performed by SHA-256 at each operation level. The tth round of operations performed at the tth operation level is defined by the following operation formula (t is an integer and satisfies 0≤t≤63):

[0035] T1 = H + Σ 1 (E) + Ch(E, F, G) + K t + W t ;

[0036] T2 = Σ 0 (A) + Maj(A, B, C);

[0037] H = G;

[0038] G = F;

[0039] F = E;

[0040] E = D + T1;

[0041] D = C;

[0042] C = B;

[0043] B = A;

[0044] A = T1 + T2; (Calculation 1)

[0045] in:

[0046] Ch(x, y, z)=(x AND y) ⊕ ((NOT x) AND z)

[0047] Maj(x, y, z)= (x AND y) ⊕ (x AND z) ⊕ (y AND z)

[0048] Σ 0 (x) = ROTR 2 (x) ⊕ ROTR 13 (x) ⊕ ROTR 22 (x)

[0049] Σ 1 (x) = ROTR 6 (x) ⊕ ROTR 11 (x) ⊕ ROTR 25 (x)

[0050] Among them, ROTR n (x) means cyclically shifting the 32-bit variable x right by n bits; W t is a 32-bit word derived from the current 256-bit input data block; K t A 32-bit additional constant; + is modulo 2 32 Addition; AND is a 32-bit bitwise AND operation; NOT is a negation operation; ⊕ is an exclusive OR operation.

[0051] Next, we describe the 32-bit word W. t How is it derived from a 512-bit block of data? t It can be obtained according to the following calculation formula:

[0052] For 0 ≤ t ≤ 15: W t Data blocks taken directly from the input;

[0053] For 16 ≤ t ≤ 63:

[0054] W t =σ 1 (W t-2 ) + W t-7 + σ 0 (W t-15 ) + W t-16 (Equation 2)

[0055] in:

[0056] σ 0 (x) = ROTR 7 (x) ⊕ ROTR 18 (x) ⊕ SHR 3 (x)

[0057] σ 1 (x) = ROTR 17 (x) ⊕ ROTR 19 (x) ⊕ SHR 10 (x)

[0058] Among them, ROTR n (x) means circularly shifting the 32-bit variable x right by n bits; SHR n (x) means shifting the 32-bit variable x right by n bits and filling the left side with 0; ⊕ is the XOR operation; + is modulo 2 32 In this article, the above W t It is called the W parameter.

[0059] Note that the above Σ 0 (x), Σ 1 (x),σ 0 (x),σ 1 The formula of the (x) function is a specific form for processing 32-bit data given by taking SHA-256 as an example. Those skilled in the art know that these functions can be adaptively adopted in other corresponding forms for processing data of other sizes (such as 64-bit data, etc.) in other SHA algorithms (such as SHA-512, etc.) or even other hash algorithms.

[0060] Specifically, Figure 2 Shows Figure 1 The conventional operation logic between the extended data in the extended registers of two adjacent operation stages in the pipeline structure. It is necessary to use the extended register R of each operation stage. 0 , R 1 , R 9 and R 14 The extended data in the calculation is used to calculate the extended register R to be stored in the next operation stage. 15 In the extended data, the extended register R 1 to R 15 The extended data in can be directly shifted to the corresponding extended register R of the next operation stage 0 to R 14 Specifically, the extended register R of the t+1th operation level 15 The extended data in w 15 ' is to use three adders ADD1, ADD2, ADD3 to add the extended register R of the tth operation level 0 The extended data in w 0 , 0 The operator performs σ 0 The extended register R of the tth operation level after the operation 1 The extended data σ in 0 (w1 ), the extended register R of the tth operation level 9 The extended data in w 9 , 1 The operator performs σ 1 The extended register R of the tth operation level after the operation 14 The extended data σ in 1 (w 14 ) are added in sequence, that is, w 15 '= w 0 +σ 0 (w 1 )+w 9 +σ 1 (w 14 ).

[0061] According to the above internal logic, SHA-256 needs to calculate a W parameter for each round of operations at each operation level, which is then used to calculate the intermediate value for storage in the compressed memory in the operation at the t+16th operation level. However, in some scenarios, two W parameters may be needed to calculate the intermediate value, so each round of operations needs to be able to calculate two W parameters.

[0062] A non-limiting example of such a scenario may be, for example, a pipeline structure with 32 operation stages for executing the SHA-256 algorithm. Figure 3 The operation logic between the extended data in the extended registers of the yth operation stage and the y+1th operation stage for calculating two W parameters is shown, where 0≤y≤31 and y is an integer. Figure 3 In FIG. 1 , a solid arrow indicates a data movement direction for calculating a first W parameter, a dashed arrow indicates a data movement direction for calculating a second W parameter, and a dotted arrow indicates a data movement direction for direct shifting without undergoing an operation. Figure 3 As shown, the extended register R of the y+1th operation level 14 The extended data in w 14 ' is to use three adders ADD11, ADD21, ADD31 to add the extended register R of the yth operation level 0 The extended data in w 0 , 0 1 operator performs σ 0 The extended register R of the yth operation level after the operation 1 The extended data in w 1 , the extended register R of the yth operation level 9 The extended data in w 9 , 1 1 operator performs σ 1 The extended register R of the yth operation level after the operation 14The extended data in w 14 The sum of the two is w 14 '= w 0 +σ 0 (w 1 )+w 9 +σ 1 (w 14 ). Figure 3 As shown, the extended register R of the y+1th operation level 15 The extended data in w 15 ' is to use three adders ADD12, ADD22, ADD32 to add the extended register R of the yth operation level 1 The extended data in w 1 , 0 2 operators perform σ 0 The extended register R of the yth operation level after the operation 2 The extended data in w 2 , the extended register R of the yth operation level 10 The extended data in w 10 , 1 2 operators perform σ 1 The extended register R of the yth operation level after the operation 15 The extended data in w 15 The sum of the two is w 15 '= w 1 +σ 0 (w 2 )+w 10 +σ 1 (w 15 ). Thus, after one round of calculation, two W parameters (w 14 ' and w 15 '). In addition, the extended data stored in each of the 2nd to 15th extended registers of the yth operation stage is directly shifted to the corresponding extended register of the 0th to 13th extended registers of the y+1th operation stage.

[0063] pass Figure 3 The operation logic design shown in the figure can calculate two W parameters in each round of operation, and the calculation process of these two W parameters can be executed in parallel, that is, two W parameters can be obtained by using the time required to calculate one W parameter originally, thereby improving the operation throughput of the pipeline structure, further accelerating the operation speed and achieving a lower power consumption and computing power ratio.

[0064] However, from the extended register R of the yth operation stage 0 , R 1 , R 9 and R 14The extended data calculation in is to be stored in the extended register R of the y+1th operation level. 14 The extended data in the yth operation level needs to go through 4 levels of operation logic. 1 , R 2 , R 10 and R 15 The extended data calculation in is to be stored in the extended register R of the y+1th operation level. 15 The extended data in needs to go through 4 levels of operation logic. Therefore, even if the calculation process of the two W parameters is processed in parallel, the number of operation logic levels required is as high as 4, which brings significant calculation delay, limits the calculation speed of the pipeline structure, and makes it difficult to further achieve a lower power consumption and computing power ratio.

[0065] In this regard, the inventor of the present application has noticed that the extended register R 0 The extended register R of the yth operation level 2 There is a direct connection between the two, namely, the extended register R of the yth operation level 2 The extended data stored in is directly shifted to the extended register R of the y+1th operation level. 0 Therefore, the inventor of the present application thinks that the extended register R 0 With R 2 This direct connection will be used to calculate the extended register R of the y+2th operation level. 14 The process of storing the extended data in involves the extended register R of the y+1th operation level. 0 The extended data in (i.e., the extended register R of the yth operation level) 2 The extended data in the y+1th operation level is advanced to the extended register R 14 The process of storing the extended data in the y+1th operation level is carried out simultaneously and stored in the extended register R 0 In this way, the extended register R used to calculate the y+2th operation level can be 14 After the process of storing the extended data in the y+1th operation level is disassembled, the disassembled part is combined with the extended register R 14 By parallel processing, the number of operation logic levels required for calculating the extended data in each round of operation can be reduced.

[0066] Similarly, the inventor of the present application also noticed that the extended register R 1 The extended register R of the yth operation level 3 There is a direct connection between the two, namely, the extended register R of the yth operation level 3The extended data stored in is directly shifted to the extended register R of the y+1th operation level. 1 Therefore, the inventor of the present application thinks that the extended register R 1 With R 3 This direct connection will be used to calculate the extended register R of the y+2th operation level. 15 The process of storing the extended data in involves the extended register R of the y+1th operation level. 1 The extended data in (i.e., the extended register R of the yth operation level) 3 The extended data in the y+1th operation level is advanced to the extended register R 15 The process of storing the extended data in the y+1th operation level is carried out simultaneously and stored in the extended register R 1 In this way, the extended register R used to calculate the y+2th operation level can be 15 After the process of storing the extended data in the y+1th operation level is disassembled, the disassembled part is combined with the extended register R 15 By parallel processing, the number of operation logic levels required for calculating the extended data in each round of operation can be reduced.

[0067] Therefore, the present disclosure provides a circuit for executing a hash algorithm with an improved extended data operation logic module and an improved method for calculating extended data in a circuit for executing a hash algorithm, which can reduce the number of operation logic levels required to calculate the extended data of the next operation level based on the extended data of the previous operation level between adjacent operation levels, significantly improve the operation speed of the circuit and the computing chip including the circuit, thereby facilitating the realization of a lower power consumption and computing power ratio.

[0068] Figure 4 A schematic block diagram of a circuit 100 for performing a hash algorithm according to some embodiments of the present disclosure is shown, wherein arrows indicate data transfer directions. The circuit 100 may include an input module 110 and an operation module 120. The input module 110 may be configured to receive data. The operation module 120 may be configured to calculate a hash value based on the received data. The operation module 120 may include a plurality of operation stages 120-0, ..., 120-31 arranged in a pipeline structure, each operation stage may include a 0th extension register R 0 To the 15th extended register R 15 , each extension register can be configured to store the extension data of the current operation level.

[0069] It should be understood that although the operation module 120 is depicted in the accompanying drawings as including 32 operation stages, as mentioned above, this article only takes the circuit with a pipeline structure including 32 operation stages for executing the SHA-256 algorithm as a non-limiting example, and the present disclosure can actually be applied to any suitable scenario where two W parameters need to be provided for each round of operation. The circuit according to the present disclosure can also be applied to execute any hash algorithm now known or later developed (not limited to the SHA series of algorithms), and can include any suitable number of operation stages.

[0070] It should also be understood that the actual circuit may also have additional other components (such as compression registers, etc.), but in order to avoid obscuring the main points of the present disclosure, these other components are not shown in the drawings and are not discussed in this article.

[0071] Typically, the 0th extension register R of the first operation stage 120-0 of the operation module 120 0 To the 15th extended register R 15 The extended data stored in the register 120 may be directly obtained from the data received by the input module 110, and the 0th extended register R of each operation stage starting from the operation stage 120-1 is 0 To the 15th extended register R 15 The extended data to be stored in the previous operation stage can be based on the 0th extended register R 0 To the 15th extended register R 15 The present disclosure mainly discusses how to determine the extended data stored in the 0th extended register R of the previous operation level. 0 To the 15th extended register R 15 The extended data stored in the next operation level determines the 0th extended register R 0 To the 15th extended register R 15 The extended data to be stored in the .

[0072] The operation module 120 may further include a plurality of extended data operation logic modules 130, each of which is disposed between two corresponding adjacent operation stages of the plurality of operation stages 120-0, ..., 120-31 of the operation module 120. In this document, the preceding operation stage of the two adjacent operation stages may be referred to as the first operation stage and the succeeding operation stage of the two adjacent operation stages may be referred to as the second operation stage. Note that "first" and "second" are only used for distinction and are not restrictive. For example, Figure 4 As shown, an extended data operation logic module 130 is disposed between two adjacent operation stages 120 - a and 120 - b. Each extended data operation logic module 130 may include a first submodule 131 , a second submodule 132 , a third submodule 133 and a fourth submodule 134 .

[0073] The extended data operation logic module 130 may be configured to calculate the extended data to be stored in the extended register of the second operation stage (e.g., 120-b) based on the extended data stored in the extended register of the first operation stage (e.g., 120-a). The first submodule 131 may be configured to calculate the extended data to be stored in the extended register of the second operation stage (e.g., 120-b) based on the extended data stored in the extended register of the first operation stage. 2 The extended data stored in is calculated for storage in the 0th extended register R of the second operation stage. 0 The second submodule 132 may be configured based on the 0th extension register R of the first operation stage. 0 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The third submodule 133 can be configured as a third extension register R based on the first operation stage. 3 The extended data stored in the calculation is used to store the first extended register R of the second operation stage. 1 The fourth submodule 134 can be configured to be based on the first extended register R of the first operation stage. 1 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 In addition, the extended data stored in the (i-2)th extended register of the second operation stage may be the extended data stored in the i-th extended register of the first operation stage, where 4≤i≤15 and i is an integer. The first submodule 131 and the second submodule 132 may be used to calculate the first W parameter. The third submodule 133 and the fourth submodule 134 may be used to calculate the second W parameter.

[0074] The first submodule 131 and the second submodule 132 may calculate the extended data in a variety of collaborative ways, thereby providing the first W parameter.

[0075] In some embodiments, the first submodule 131 may be configured as a second extended register R based on the first operation stage. 2 , the third extended register R 3 , 11th extended register R 11 The extended data stored in is calculated for storage in the 0th extended register R of the second operation stage. 0 The second submodule 132 can be configured as a 0th extension register R based on the first operation stage. 0 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0076] In some embodiments, the first submodule 131 may be configured as a second extended register R based on the first operation stage. 2 and the third extended register R 3 The extended data stored in is calculated for storage in the 0th extended register R of the second operation stage. 0 The second submodule 132 can be configured as a 0th extension register R based on the first operation stage. 0 , 9th extended register R 9 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0077] The third submodule 133 and the fourth submodule 134 may calculate the extended data in a variety of collaborative ways, thereby providing the second W parameter.

[0078] In some embodiments, the third submodule 133 may be configured as a third extended register R based on the first operation stage. 3 , the fourth extended register R 4 , 12th extended register R 12 The extended data stored in the calculation is used to store the first extended register R of the second operation stage. 1 The fourth submodule 134 can be configured as a first extended register R based on the first operation stage. 1 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0079] In some embodiments, the third submodule 133 may be configured as a third extended register R based on the first operation stage. 3 and the 4th extended register R 4 The extended data stored in the calculation is used to store the first extended register R of the second operation stage. 1 The fourth submodule 134 can be configured as a first extended register R based on the first operation stage. 1 , 10th extended register R 10 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0080] In some embodiments, the third submodule 133 is configured as a third extended register R based on the first operation stage.3 and the 12th extended register R 12 The extended data stored in the calculation is used to store the first extended register R of the second operation stage. 1 The fourth submodule 134 can be configured as a first extended register R based on the first operation stage. 1 , the second extended register R 2 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0081] According to the embodiment of the present disclosure, any cooperation mode of the first submodule 131 and the second submodule 132 and any cooperation mode of the third submodule 133 and the fourth submodule 134 can be freely combined to provide the first W parameter and the second W parameter.

[0082] Combine the following Figures 5 to 7 Describe the embodiment according to the present disclosure Figure 4 The circuit 100 shown includes several non-limiting example configurations of the part of the extended data operation logic module, which shows several non-limiting example combinations of the cooperation mode of the first submodule 131 and the second submodule 132 and the cooperation mode of the third submodule 133 and the fourth submodule 134. In these figures, two adjacent operation stages 120-a and 120-b are used as examples for explanation. It can be understood that any two adjacent operation stages in the operation module 120 can be the operation stages 120-a and 120-b discussed below. In addition, in these figures, for the sake of clarity, dotted arrows are used to indicate the movement direction of the extended data that is directly shifted without operation, solid arrows are used to indicate the movement direction of the extended data processed by the first submodule 131 and the second submodule 132, and dot-dashed arrows are used to indicate the movement direction of the extended data processed by the third submodule 133 and the fourth submodule 134. The schematic block diagram of the first to fourth submodules 131-134 is given separately below.

[0083] In such Figure 5 In the example shown, the 0th extension register R of the operation stage 120-b is 0 The extended data in w 0 ' is processed by the first submodule 131 to process the second extended register R of the operation stage 120-a 2 The extended data stored in 2 , the third extended register R 3 The extended data stored in 3 and the 11th extended register R 11 The extended data stored in 11Specifically, in this example, the first submodule 131 includes a module for executing σ 0 σ of operation 0 1 operator and full adder FAA1 and adder ADD1 for performing addition operation, wherein the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator, extended data w 2 and extended data w 11 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extension register R of the operation stage 120-b. 0 , so that w 0 '= w 2 +σ 0 (w 3 )+w 11 .

[0084] Further Figure 5 As shown, the 14th extended register R of the operation stage 120-b 14 The extended data in w 14 ' is processed by the second submodule 132 to process the 0th extension register R of the operation stage 120-a 0 The extended data stored in 0 and the 14th extended register R 14 The extended data stored in 14 Specifically, in this example, the second submodule 132 includes a 1 σ of operation 1 1 operator and an adder ADD2 for performing an addition operation, wherein the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator and extended data w 0 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 120-b. 14 , so that w 14 '= w 0 +σ 1 (w 14 ).

[0085] Further Figure 5 As shown, the first extended register R of the operation stage 120-b 1 The extended data in w 1 ' is processed by the third submodule 133 to process the third extended register R of the operation stage 120-a 3 The extended data stored in3 , the fourth extended register R 4 The extended data stored in 4 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 133 includes a 0 σ of operation 0 2 operators and full adder FAA2 and adder ADD3 for performing addition operations, wherein the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator, extended data w 3 and extended data w 12 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD3, and the output of the adder ADD3 is provided to the first extended register R of the operation stage 120-b. 1 , so that w 1 '= w 3 +σ 0 (w 4 )+w 12 .

[0086] Further Figure 5 As shown, the 15th extended register R of the operation stage 120-b 15 The extended data in w 15 ' is processed by the fourth submodule 134 to process the first extended register R of the operation stage 120-a 1 The extended data stored in 1 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 134 includes a module for executing σ 1 σ of operation 1 2 operators and an adder ADD4 for performing an addition operation, wherein the extended data w 15 is input into σ 1 2 operators, σ 1 2 Output of the operator and extended data w 1 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 120-b. 15 , so that w 15 '= w 1 +σ 1 (w 15 ).

[0087] Further Figure 5As shown, the extended data stored in the i-th extended register of the operation stage 120 - a is directly shifted to the (i-2)-th extended register of the operation stage 120 - b , where 4≤i≤15 and i is an integer.

[0088] exist Figure 5 In the example shown, the number of operation logic levels experienced by the first submodule 131 is 3, the number of operation logic levels experienced by the second submodule 132 is 2, the number of operation logic levels experienced by the third submodule 133 is 3, and the number of operation logic levels experienced by the fourth submodule 134 is 2. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 120-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0089] In such Figure 6 In the example shown, the 0th extension register R of the operation stage 120-b is 0 The extended data in w 0 ' is processed by the first submodule 131 to process the second extended register R of the operation stage 120-a 2 The extended data stored in 2 and the third extended register R 3 The extended data stored in 3 Specifically, in this example, the first submodule 131 includes σ 0 1 operator and adder ADD1, where the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator and extended data w 2 is input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extension register R of the operation stage 120-b. 0 , so that w 0 '= w 2 +σ 0 (w 3 ).

[0090] Further Figure 6 As shown, the 14th extended register R of the operation stage 120-b 14 The extended data in w 14 ' is processed by the second submodule 132 to process the 0th extension register R of the operation stage 120-a 0 The extended data stored in 0 , 9th extended register R 9 The extended data stored in 9 and the 14th extended register R 14 The extended data stored in14 Specifically, in this example, the second submodule 132 includes σ 1 1 operator, full adder FAA1 and adder ADD2, where the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator, extended data w 0 and extended data w 9 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 120-b. 14 , so that w 14 '= w 0 +w 9 +σ 1 (w 14 ).

[0091] Further Figure 6 As shown, the first extended register R of the operation stage 120-b 1 The extended data in w 1 ' is processed by the third submodule 133 to process the third extended register R of the operation stage 120-a 3 The extended data stored in 3 and the 4th extended register R 4 The extended data stored in 4 Specifically, in this example, the third submodule 133 includes σ 0 2 operators and adder ADD3, where the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator and extended data w 3 is input to the adder ADD3, and the output of the adder ADD3 is provided to the first extension register R of the operation stage 120-b. 1 , so that w 1 '= w 3 +σ 0 (w 4 ).

[0092] Further Figure 6 As shown, the 15th extended register R of the operation stage 120-b 15 The extended data in w 15 ' is processed by the fourth submodule 134 to process the first extended register R of the operation stage 120-a 1 The extended data stored in 1 , 10th extended register R 10 The extended data stored in10 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 134 includes σ 1 2 arithmetic units, full adder FAA2 and adder ADD4, where the extended data w 15 is input into σ 1 2 operators, σ 1 2 Output of the operator, extended data w 1 and extended data w 10 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 120-b. 15 , so that w 15 '= w 1 +w 10 +σ 1 (w 15 ).

[0093] Further Figure 6 As shown, the extended data stored in the i-th extended register of the operation stage 120 - a is directly shifted to the (i-2)-th extended register of the operation stage 120 - b , where 4≤i≤15 and i is an integer.

[0094] exist Figure 6 In the example shown, the number of operation logic levels experienced by the first submodule 131 is 2, the number of operation logic levels experienced by the second submodule 132 is 3, the number of operation logic levels experienced by the third submodule 133 is 2, and the number of operation logic levels experienced by the fourth submodule 134 is 3. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 120-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0095] In such Figure 7 In the example shown, the cooperation mode of the first submodule 131 and the second submodule 132 is the same as Figure 6 The example shown is the same, and the extended data stored in the i-th extended register of the operation stage 120 - a is directly shifted to the (i-2)-th extended register of the operation stage 120 - b , where 4≤i≤15 and i is an integer.

[0096] Further Figure 7 As shown, the first extended register R of the operation stage 120-b 1 The extended data in w 1 ' is processed by the third submodule 133 to process the third extended register R of the operation stage 120-a3 The extended data stored in 3 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 133 includes an adder ADD3, in which the extended data w 3 and w 12 is input to the adder ADD3, and the output of the adder ADD3 is provided to the first extension register R of the operation stage 120-b. 1 , so that w 1 '= w 3 +w 12 .

[0097] Further Figure 7 As shown, the 15th extended register R of the operation stage 120-b 15 The extended data in w 15 ' is processed by the fourth submodule 134 to process the first extended register R of the operation stage 120-a 1 The extended data stored in 1 , the second extended register R 2 The extended data stored in 2 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 134 includes σ 0 2 operators, σ 1 2 arithmetic units, full adder FAA2 and adder ADD4, where the extended data w 2 is input into σ 0 2 operators, extended data w 15 is input into σ 1 2 operators, σ 0 Operation and σ 1 The operations can be performed simultaneously. Then σ 0 2 The output of the operator, σ 1 2 Output of the operator and extended data w 1 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 120-b. 15 , so that w 15 '= w 1 +σ 0 (w 2 )+σ 1 (w 15 ).

[0098] exist Figure 7In the example shown, the number of operation logic levels experienced by the first submodule 131 is 2, the number of operation logic levels experienced by the second submodule 132 is 3, the number of operation logic levels experienced by the third submodule 133 is 1, and the number of operation logic levels experienced by the fourth submodule 134 is 3. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 120-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0099] Accordingly, the present disclosure also provides a method for calculating extended data in a circuit for executing a hash algorithm. Fig.18 An exemplary flow chart of a method 500 for calculating extended data in a circuit for executing a hash algorithm according to an embodiment of the present disclosure is shown. Such a circuit may include an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, wherein the operation module may include a plurality of operation stages arranged in a pipeline structure, each operation stage includes a 0th extension register to a 15th extension register, and each extension register may be configured to store extended data of the current operation stage. For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among multiple operation stages of the operation module, method 500 may include: at S501, based on the extended data stored in the second extended register of the first operation stage, calculating the extended data for storage in the 0th extended register of the second operation stage; at S502, based on the extended data stored in the 0th extended register and the 14th extended register of the first operation stage, calculating the extended data for storage in the 14th extended register of the second operation stage; at S503, based on the extended data stored in the 3rd extended register of the first operation stage, calculating the extended data for storage in the 1st extended register of the second operation stage; at S504, based on the extended data stored in the 1st extended register and the 15th extended register of the first operation stage, calculating the extended data for storage in the 15th extended register of the second operation stage; at S505, using the extended data stored in the i-th extended register of the first operation stage as the extended data for storage in the (i-2)th extended register of the second operation stage, where 4≤i≤15 and i is an integer. Note that S501 - S505 do not need to be performed in a sequential order, but may be performed in any order, or may be performed at least partially in parallel.

[0100] Method 500 can also calculate the extended data in a manner similar to various combinations of various cooperation modes between submodules according to the embodiments described above, which will not be described in detail here. Method 500 can reduce the calculation delay caused by calculating the extended data in the circuit for executing the hash algorithm, thereby greatly improving the operation speed of the circuit and the computing chip including the circuit, thereby achieving a lower power consumption and computing power ratio.

[0101] In addition, in the circuit and method according to the above-mentioned embodiment of the present disclosure, the extended register R is used. 0 , R 1 To store the advance calculations in the extended register R that was originally used to calculate the subsequent operation level 14 , R 15 The process of storing the extended data in the previous operation stage involves the extended register R 2 , R 3 In some alternative embodiments, additional registers may also be used to implement the extended register R 0 , R 1 In addition, when the additional register is used, it can not only be used to advance the extended register R originally used to calculate the subsequent operation level, but also to calculate the subsequent operation level. 14 , R 15 The process of storing the extended data in the previous operation stage involves the extended register R 0 , R 1 The extended data in the extended register R can be used to calculate the subsequent operation level in advance. 14 , R 15 Any suitable part of the process of storing the extended data in .

[0102] Figure 8 A schematic block diagram of a circuit 200 for executing a hash algorithm according to some other embodiments of the present disclosure is shown. The arrows indicate the direction of data transfer. The circuit 200 may include an input module 210 and an operation module 220. The input module 210 may be configured to receive data. The operation module 220 may be configured to calculate a hash value based on the received data. The operation module 220 may include a plurality of operation stages 220-0, ..., 220-31 arranged in a pipeline structure, each of which may include a 0th extension register R 0 To the 15th extended register R 15and a first additional register X1 and a second additional register X2. Each extended register may be configured to store extended data of the current operation stage, and each additional register may be configured to store intermediate data used to calculate the extended data. In some embodiments, in the first operation stage 220-0, the intermediate data in the first additional register X1 may be stored in the same manner as the intermediate data in the 0th extended register R 0 The intermediate data in the second additional register X2 can be the same as the extended data in the first extended register R 1 The extended data is the same as in .

[0103] The operation module 220 may further include a plurality of extended data operation logic modules 230, each of which is disposed between two corresponding adjacent operation stages of the plurality of operation stages 220-0, ..., 220-31 of the operation module 220. In this document, the preceding operation stage of the two adjacent operation stages may be referred to as the first operation stage and the succeeding operation stage of the two adjacent operation stages may be referred to as the second operation stage. Note that "first" and "second" are only used for distinction and are not restrictive. For example, Figure 8 As shown, an extended data operation logic module 230 is disposed between two adjacent operation stages 220 - a and 220 - b. Each extended data operation logic module 230 may include a first submodule 231 , a second submodule 232 , a third submodule 233 and a fourth submodule 234 .

[0104] The first submodule 231 may be configured to calculate intermediate data for storage in the first additional register X1 of the second operation stage based on the extended data stored in the extended register of the first operation stage. The second submodule 232 may be configured to calculate intermediate data for storage in the first additional register X1 of the second operation stage based on the intermediate data stored in the first additional register X1 of the first operation stage and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The third submodule 233 may be configured to calculate the intermediate data for storage in the second additional register X2 of the second operation stage based on the extended data stored in the extended register of the first operation stage. The fourth submodule 234 may be configured to calculate the intermediate data for storage in the second additional register X2 of the second operation stage based on the intermediate data stored in the second additional register X2 of the first operation stage and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15In addition, the extended data stored in the (i-2)th extended register of the second operation stage may be the extended data stored in the i-th extended register of the first operation stage, where 2≤i≤15 and i is an integer. The first submodule 231 and the second submodule 232 may be used to calculate the first W parameter. The third submodule 233 and the fourth submodule 234 may be used to calculate the second W parameter.

[0105] In some embodiments, the first submodule 231 may be configured as a second extended register R based on the first operation stage. 2 , the third extended register R 3 and the 11th extended register R 11 The extended data stored in two or three of them are used to calculate the intermediate data stored in the first additional register X1 of the second operation stage.

[0106] In some embodiments, the second submodule 232 may be configured to be based on the 0th extension register R of the first operation stage. 0 , the first extended register R 1 and the 9th extended register R 9 The extended data stored in one of the registers and the intermediate data stored in the first additional register X1 of the first operation stage and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0107] In some embodiments, the third submodule 233 may be configured as a third extended register R based on the first operation stage. 3 , the fourth extended register R 4 and the 12th extended register R 12 The extended data stored in two or three of them are used to calculate the intermediate data stored in the second additional register X2 of the second operation stage.

[0108] In some embodiments, the fourth submodule 234 may be configured as a first extended register R based on the first operation stage. 1 , the second extended register R 2 and the 10th extended register R 10 The extended data stored in one of the registers and the intermediate data stored in the second additional register X2 of the first operation stage and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The first submodule 231 and the second submodule 232 may calculate the extended data in a variety of collaborative ways, thereby providing the first W parameter.

[0109] In some embodiments, the first submodule 231 may be configured as a second extended register R based on the first operation stage. 2 , the third extended register R 3 , 11th extended register R 11 The second submodule 232 may be configured to calculate the intermediate data stored in the first additional register X1 of the second operation stage based on the intermediate data stored in the first additional register X1 of the first operation stage and the 14th extended register R of the first operation stage. 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0110] In some embodiments, the first submodule 231 may be configured as a second extended register R based on the first operation stage. 2 and the third extended register R 3 The second submodule 234 may be configured to calculate the intermediate data stored in the first additional register X1 of the second operation stage based on the intermediate data stored in the first additional register X1 of the first operation stage and the 9th extended register R of the first operation stage. 9 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0111] In some embodiments, the first submodule 231 may be configured as a second extended register R based on the first operation stage. 2 and the 11th extended register R 11 The second submodule 234 may be configured to calculate the intermediate data stored in the first additional register X1 of the second operation stage based on the intermediate data stored in the first additional register X1 of the first operation stage and the first extension register R 1 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0112] In some embodiments, the first submodule 231 may be configured as a third extended register R based on the first operation stage. 3 and the 11th extended register R 11 The second submodule 232 may be configured to calculate the intermediate data stored in the first additional register X1 of the second operation stage based on the intermediate data stored in the first additional register X1 of the first operation stage and the 0th extended register R of the first operation stage.0 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The extended data in .

[0113] The third submodule 233 and the fourth submodule 234 may calculate the extended data in a variety of collaborative ways to provide the second W parameter.

[0114] In some embodiments, the third submodule 233 may be configured as a third extended register R based on the first operation stage. 3 , the fourth extended register R 4 , 12th extended register R 12 The fourth submodule 234 may be configured to calculate the intermediate data stored in the second additional register X2 of the second operation stage based on the intermediate data stored in the second additional register X2 of the first operation stage and the 15th extended register R of the first operation stage. 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0115] In some embodiments, the third submodule 233 may be configured as a third extended register R based on the first operation stage. 3 and the 4th extended register R 4 The fourth submodule 234 may be configured to calculate the intermediate data stored in the second additional register X2 of the second operation stage based on the intermediate data stored in the second additional register X2 of the first operation stage and the 10th extended register R of the first operation stage. 10 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0116] In some embodiments, the third submodule 233 is configured as a third extended register R based on the first operation stage. 3 and the 12th extended register R 12 The fourth submodule 234 may be configured to calculate the intermediate data stored in the second additional register X2 of the second operation stage based on the intermediate data stored in the second additional register X2 of the first operation stage and the second extended register R 2 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0117] In some embodiments, the third submodule 233 may be configured as a fourth extended register R based on the first operation stage. 4 and the 12th extended register R 12 The fourth submodule 234 may be configured to calculate the intermediate data stored in the second additional register X2 of the second operation stage based on the intermediate data stored in the second additional register X2 of the first operation stage and the first extended register R of the first operation stage. 1 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 The extended data in .

[0118] According to the embodiment of the present disclosure, any cooperation mode of the first submodule 231 and the second submodule 232 and any cooperation mode of the third submodule 233 and the fourth submodule 234 can be freely combined to provide the first W parameter and the second W parameter.

[0119] Combine the following Figures 9 to 12 Describe the embodiment according to the present disclosure Figure 8 The circuit 200 shown includes several non-limiting example configurations of the part of the extended data operation logic module, which shows several non-limiting example combinations of the cooperation mode of the first submodule 231 and the second submodule 232 and the cooperation mode of the third submodule 233 and the fourth submodule 234. In these figures, two adjacent operation stages 220-a and 220-b are used as examples for explanation. It can be understood that any two adjacent operation stages in the operation module 220 can be the operation stages 220-a and 220-b discussed below. In addition, in these figures, for the sake of clarity, dotted arrows are used to indicate the movement direction of the extended data that is directly shifted without operation, solid arrows are used to indicate the movement direction of the extended data processed by the first submodule 231 and the second submodule 232, and dot-dash arrows are used to indicate the movement direction of the extended data processed by the third submodule 233 and the fourth submodule 234. The schematic block diagram of the first to fourth submodules 231-234 is given separately below.

[0120] In such Fig. 9 In the example shown, the intermediate data w in the first additional register X1 of the operation stage 220-b is x1 ' is the second extended register R of the operation stage 220-a processed by the first submodule 231 2 The extended data stored in 2 , the third extended register R 3 The extended data stored in 3 and the 11th extended register R 11The extended data stored in 11 Specifically, in this example, the first submodule 231 includes σ 0 1 operator, full adder FAA1 and adder ADD1, where the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator, extended data w 2 and extended data w 11 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD1, and the output of the adder ADD1 is provided to the first additional register X1 of the operation stage 220-b, so that w x1 '= w 2 +σ 0 (w 3 )+w 11 .

[0121] Further Fig. 9 As shown, the 14th extended register R of the operation stage 220-b 14 The extended data in w 14 ' is the intermediate data w stored in the first additional register X1 of the operation stage 220-a processed by the second submodule 232 x1 and the 14th extended register R of the operation stage 220-a 14 The extended data stored in 14 Specifically, in this example, the second submodule 232 includes σ 1 1 operator and adder ADD2, where the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator and intermediate data w x1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 220-b. 14 , so that w 14 '= w x1 +σ 1 (w 14 ).

[0122] Further Fig. 9 As shown, the intermediate data w in the second additional register X2 of the operation stage 220-b is x2 ' is processed by the third submodule 233 to process the third extended register R of the operation stage 220-a 3 The extended data stored in 3 , the fourth extended register R 4 The extended data stored in 4 and the 12th extended register R12 The extended data stored in 12 Specifically, in this example, the third submodule 233 includes σ 0 2 arithmetic units, full adder FAA2 and adder ADD3, where the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator, extended data w 3 and extended data w 12 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD3, and the output of the adder ADD3 is provided to the second additional register X2 of the operation stage 220-b, so that w x2 '= w 3 +σ 0 (w 4 )+w 12 .

[0123] Further Fig. 9 As shown, the 15th extended register R of the operation stage 220-b 15 The extended data in w 15 ' is the intermediate data w stored in the second additional register X2 of the operation stage 220-a processed by the fourth submodule 234 x2 and the 15th extended register R of the operation stage 220-a 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 234 includes σ 1 2 operators and adder ADD4, where the extended data w 15 is input into σ 1 2 operators, σ 1 2 Output of the operator and intermediate data w x2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 220-b. 15 , so that w 15 '= w x2 +σ 1 (w 15 ).

[0124] Further Fig. 9 As shown, the extended data stored in the i-th extended register of the operation stage 220-a is directly shifted to the (i-2)-th extended register of the operation stage 220-b, where 2≤i≤15 and i is an integer.

[0125] exist Fig. 9In the example shown, the number of operation logic levels experienced by the first submodule 231 is 3, the number of operation logic levels experienced by the second submodule 232 is 2, the number of operation logic levels experienced by the third submodule 233 is 3, and the number of operation logic levels experienced by the fourth submodule 234 is 2. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 220-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0126] In such Fig.10 In the example shown, the intermediate data w in the first additional register X1 of the operation stage 220-b is x1 ' is the second extended register R of the operation stage 220-a processed by the first submodule 231 2 The extended data stored in 2 and the third extended register R 3 The extended data stored in 3 Specifically, in this example, the first submodule 231 includes σ 0 1 operator and adder ADD1, where the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator and extended data w 2 is input to the adder ADD1, and the output of the adder ADD1 is provided to the first additional register X1 of the operation stage 220-b, so that w x1 '=w 2 +σ 0 (w 3 ).

[0127] Further Fig.10 As shown, the 14th extended register R of the operation stage 220-b 14 The extended data in w 14 ' is the intermediate data w stored in the first additional register X1 of the operation stage 220-a processed by the second submodule 232 x1 , 9th extended register R 9 The extended data stored in 9 and the 14th extended register R 14 The extended data stored in 14 Specifically, in this example, the second submodule 232 includes σ 1 1 operator, full adder FAA1 and adder ADD2, where the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator, intermediate data wx1 and extended data w 9 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 220-b. 14 , so that w 14 '= w x1 +w 9 +σ 1 (w 14 ).

[0128] Further Fig.10 As shown, the intermediate data w in the second additional register X2 of the operation stage 220-b is x2 ' is processed by the third submodule 233 to process the third extended register R of the operation stage 220-a 3 The extended data stored in 3 and the 4th extended register R 4 The extended data stored in 4 Specifically, in this example, the third submodule 233 includes σ 0 2 operators and adder ADD3, where the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator and extended data w 3 is input to the adder ADD3, and the output of the adder ADD3 is provided to the second additional register X2 of the operation stage 220-b, so that w x2 '= w 3 +σ 0 (w 4 ).

[0129] Further Fig.10 As shown, the 15th extended register R of the operation stage 220-b 15 The extended data in w 15 ' is the intermediate data w stored in the second additional register X2 of the operation stage 220-a processed by the fourth submodule 234 x2 , 10th extended register R 10 The extended data stored in 10 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 234 includes σ 1 2 arithmetic units, full adder FAA2 and adder ADD4, where the extended data w 15 is input into σ 1 2 operators, σ 12 Output of the operator, intermediate data w x2 and extended data w 10 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 220-b. 15 , so that w 15 '= w x2 +w 10 +σ 1 (w 15 ).

[0130] Further Fig.10 As shown, the extended data stored in the i-th extended register of the operation stage 220-a is directly shifted to the (i-2)-th extended register of the operation stage 220-b, where 2≤i≤15 and i is an integer.

[0131] exist Fig.10 In the example shown, the number of operation logic levels experienced by the first submodule 231 is 2, the number of operation logic levels experienced by the second submodule 232 is 3, the number of operation logic levels experienced by the third submodule 233 is 2, and the number of operation logic levels experienced by the fourth submodule 234 is 3. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 220-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0132] In such Fig.11 In the example shown, the intermediate data w in the first additional register X1 of the operation stage 220-b is x1 ' is the second extended register R of the operation stage 220-a processed by the first submodule 231 2 The extended data stored in 2 and the 11th extended register R 11 The extended data stored in 11 Specifically, in this example, the first submodule 231 includes an adder ADD1, in which the extended data w 2 and w 11 is input to the adder ADD1, and the output of the adder ADD1 is provided to the first additional register X1 of the operation stage 220-b, so that w x1 '= w 2 + w 11 .

[0133] Further Fig.11 As shown, the 14th extended register R of the operation stage 220-b 14 The extended data in w 14' is the intermediate data w stored in the first additional register X1 of the operation stage 220-a processed by the second submodule 232 x1 , the first extended register R 1 The extended data stored in 1 and the 14th extended register R 14 The extended data stored in 14 Specifically, in this example, the second submodule 232 includes σ 0 1 operator, σ 1 1 operator, full adder FAA1 and adder ADD2. Extended data w 1 is input into σ 0 1 operator, extended data w 14 is input into σ 1 1 operator, σ 0 Operation and σ 1 The operations can be performed simultaneously. Then, σ 0 1 output of the operator, σ 1 1 Output of the operator and intermediate data w x1 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 220-b. 14 , so that w 14 '= w x1 +σ 0 (w 1 )+σ 1 (w 14 ).

[0134] Further Fig.11 As shown, the intermediate data w in the second additional register X2 of the operation stage 220-b is x2 ' is processed by the third submodule 233 to process the third extended register R of the operation stage 220-a 3 The extended data stored in 3 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 233 includes an adder ADD3, in which the extended data w 3 and w 12 is input to the adder ADD3, and the output of the adder ADD3 is provided to the second additional register X2 of the operation stage 220-b, so that w x2 '= w 3 +w 12 .

[0135] Further Fig.11As shown, the 15th extended register R of the operation stage 220-b 15 The extended data in w 15 ' is the intermediate data w stored in the second additional register X2 of the operation stage 220-a processed by the fourth submodule 234 x2 , the second extended register R 2 The extended data stored in 2 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 234 includes σ 0 2 operators, σ 1 2 arithmetic units, full adder FAA2 and adder ADD4, where the extended data w 2 is input into σ 0 2 operators, extended data w 15 is input into σ 1 2 operators, σ 0 Operation and σ 1 The operations can be performed simultaneously. Then σ 0 2 The output of the operator, σ 1 2 Output of the operator and intermediate data w x2 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 220-b. 15 , so that w 15 '= w x2 +σ 0 (w 2 )+σ 1 (w 15 ).

[0136] Further Fig.11 As shown, the extended data stored in the i-th extended register of the operation stage 220-a is directly shifted to the (i-2)-th extended register of the operation stage 220-b, where 2≤i≤15 and i is an integer.

[0137] exist Fig.11 In the example shown, the number of operation logic levels experienced by the first submodule 231 is 1, the number of operation logic levels experienced by the second submodule 232 is 3, the number of operation logic levels experienced by the third submodule 233 is 1, and the number of operation logic levels experienced by the fourth submodule 234 is 3. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 220-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0138] In such Fig.12 In the example shown, the intermediate data w in the first additional register X1 of the operation stage 220-b is x1 ' is processed by the first submodule 231 to process the third extended register R of the operation stage 220-a 3 The extended data stored in 3 and the 11th extended register R 11 The extended data stored in 11 Specifically, in this example, the first submodule 231 includes σ 0 1 operator and adder ADD1, where the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator and extended data w 11 is input to the adder ADD1, and the output of the adder ADD1 is provided to the first additional register X1 of the operation stage 220-b, so that w x1 ' = σ 0 (w 3 )+w 11 .

[0139] Further Fig.12 As shown, the 14th extended register R of the operation stage 220-b 14 The extended data in w 14 ' is the intermediate data w stored in the first additional register X1 of the operation stage 220-a processed by the second submodule 232 x1 , 0th extension register R 0 The extended data stored in 0 and the 14th extended register R 14 The extended data stored in 14 Specifically, in this example, the second submodule 232 includes σ 1 1 operator, full adder FAA1 and adder ADD2, where the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator, extended data w 0 and the intermediate data w x1 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 220-b. 14 , so that w 14 '= w x1 + w 0 +σ 1 (w 14 ).

[0140] Further Fig.12 As shown, the intermediate data w in the second additional register X2 of the operation stage 220-b is x2 ' is processed by the third submodule 233 to process the fourth extended register R of the operation stage 220-a 4 The extended data stored in 4 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 233 includes σ 0 2 operators and adder ADD3, where the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator and extended data w 12 is input to the adder ADD3, and the output of the adder ADD3 is provided to the second additional register X2 of the operation stage 220-b, so that w x2 ' = σ 0 (w 4 )+w 12 .

[0141] Further Fig.12 As shown, the 15th extended register R of the operation stage 220-b 15 The extended data in w 15 ' is the intermediate data w stored in the second additional register X2 of the operation stage 220-a processed by the fourth submodule 234 x2 , the first extended register R 1 The extended data stored in 1 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 234 includes σ 1 2 arithmetic units, full adder FAA2 and adder ADD4, where the extended data w 15 is input into σ 1 2 operators, σ 1 2 Output of the operator, extended data w 1 and the intermediate data w x2 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 220-b. 15 , so that w 15 '= w x2 +w 1 +σ 1 (w 15 ).

[0142] Further Fig.12 As shown, the extended data stored in the i-th extended register of the operation stage 220-a is directly shifted to the (i-2)-th extended register of the operation stage 220-b, where 2≤i≤15 and i is an integer.

[0143] exist Fig.12 In the example shown, the number of operation logic levels experienced by the first submodule 231 is 2, the number of operation logic levels experienced by the second submodule 232 is 3, the number of operation logic levels experienced by the third submodule 233 is 2, and the number of operation logic levels experienced by the fourth submodule 234 is 3. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 220-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0144] Accordingly, the present disclosure also provides a method for calculating extended data in a circuit for executing a hash algorithm. Fig.19An exemplary flow chart of a method 600 for calculating extended data in a circuit for executing a hash algorithm according to an embodiment of the present disclosure is shown. Such a circuit may include an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, wherein the operation module may include a plurality of operation stages arranged in a pipeline structure, each operation stage including the 0th to 15th extended registers and a first additional register and a second additional register, each extended register being configured to store extended data of the current operation stage, and each additional register being configured to store intermediate data for calculating extended data. For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages of the operation module, the method 600 may include: at S601, calculating intermediate data for storage in a first additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; at S602, calculating extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extended register of the first operation stage; at S603, calculating the extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extended register of the first operation stage; The extended data stored in the extended register of the first operation stage is used to calculate the intermediate data stored in the second additional register of the second operation stage; at S604, the extended data stored in the 15th extended register of the second operation stage is calculated based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 15th extended register of the first operation stage; at S605, the extended data stored in the i-th extended register of the first operation stage is used as the extended data stored in the (i-2)-th extended register of the second operation stage, where 2≤i≤15 and i is an integer. Note that S601-S605 do not need to be performed in a sequential order, but can be performed in any order, or can be performed at least partially in parallel.

[0145] Method 600 can also calculate the extended data in a manner similar to various combinations of various cooperation modes between submodules according to the above-described embodiments, which will not be described in detail here. Method 600 can reduce the calculation delay caused by calculating the extended data in the circuit for executing the hash algorithm, thereby greatly improving the operation speed of the circuit and the computing chip including the circuit, thereby achieving a lower power consumption and computing power ratio.

[0146] Of course, it is not necessary to use the first additional register and the second additional register to replace the extended register R 0 , R 1 Instead of the role played in the above embodiment, the first additional register may be selected to implement the extended register R 0 In the above embodiment, the role played, or the second additional register is selected to replace the extended register R1 The role played in the above embodiments.

[0147] For example, Fig.13 A schematic block diagram of a circuit 300 for performing a hash algorithm according to some other embodiments of the present disclosure is shown. The arrow indicates the direction of data transfer. The circuit 300 may include an input module 310 and an operation module 320. The input module 310 may be configured to receive data. The operation module 320 may be configured to calculate a hash value based on the received data. The operation module 320 may also include a plurality of extended data operation logic modules 330, each of which is disposed between corresponding adjacent two operation stages (e.g., 320-a and 320-b) in the plurality of operation stages 320-0, ..., 320-31 of the operation module 320.

[0148] The circuit 300 is different from the circuits 100 and 200 in that each operation stage of the operation module 320 of the circuit 300 may include a 0th extension register R 0 To the 15th extended register R 15 and the second additional register X2 without including the first additional register X1, and accordingly, each extended data operation logic module 330 may include the first submodule 131, the second submodule 132, the third submodule 233 and the fourth submodule 234 as described above. In some embodiments, in the first operation stage 320-0, the intermediate data in the second additional register X2 may be compared with the first extended register R 1 The extended data is the same as in .

[0149] In the circuit 300: the first submodule 131 may be configured as a second extended register R based on the first operation stage (eg, 320-a). 2 The extended data stored in is calculated for storage in the 0th extended register R of the second operation stage (eg, 320-b). 0 The second submodule 132 can be configured as a 0th extension register R based on the first operation level 0 and the 14th extended register R 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The third submodule 233 can be configured as an extended register R based on the first operation level 3 The fourth submodule 234 can be configured to calculate the intermediate data stored in the second additional register X2 of the second operation stage based on the intermediate data stored in the second additional register X2 of the first operation stage and the 15th extended register R 15The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15 In addition, the extended data stored in the (i-2)th extended register of the second operation stage may be the extended data stored in the i-th extended register of the first operation stage, where 3≤i≤15 and i is an integer. In the circuit 300, the first submodule 131 and the second submodule 132 may be used to calculate the first W parameter, and the third submodule 233 and the fourth submodule 234 may be used to calculate the second W parameter.

[0150] As described above, the first submodule 131 and the second submodule 132 can use a variety of collaborative methods to calculate the extended data, thereby providing the first W parameter, and its embodiments are not repeated here. Similarly, as described above, the third submodule 233 and the fourth submodule 234 can use a variety of collaborative methods to calculate the extended data, thereby providing the second W parameter, and its embodiments are not repeated here. In various implementations of the circuit 300, any collaborative method of the first submodule 131 and the second submodule 132 according to the embodiment of the present disclosure can be freely combined with any collaborative method of the third submodule 233 and the fourth submodule 234, thereby providing the first W parameter and the second W parameter.

[0151] Combine the following Fig.14 and Fig.15 Describe the embodiment according to the present disclosure Fig.13 The circuit 300 shown includes several non-limiting example configurations of the part of the extended data operation logic module, which shows several non-limiting example combinations of the cooperation mode of the first submodule 131 and the second submodule 132 and the cooperation mode of the third submodule 233 and the fourth submodule 234. In these figures, two adjacent operation stages 320-a and 320-b are used as examples for explanation. It can be understood that any two adjacent operation stages in the operation module 320 can be the operation stages 320-a and 320-b discussed below. In addition, in these figures, for the sake of clarity, dotted arrows are used to indicate the movement direction of the extended data that is directly shifted without operation, solid arrows are used to indicate the movement direction of the extended data processed by the first submodule 131 and the second submodule 132, and dot-dash arrows are used to indicate the movement direction of the extended data processed by the third submodule 233 and the fourth submodule 234. The schematic block diagrams of the first submodule to the fourth submodule are given separately below.

[0152] In such Fig.14 In the example shown, the 0th extension register R of the operation stage 320-b is 0 The extended data in w 0 ' is the second extended register R of the operation stage 320-a processed by the first submodule 131 2 The extended data stored in2 , the third extended register R 3 The extended data stored in 3 and the 11th extended register R 11 The extended data stored in 11 Specifically, in this example, the first submodule 131 includes σ 0 1 operator, full adder FAA1 and adder ADD1, where the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator, extended data w 2 and extended data w 11 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extension register R of the operation stage 320-b. 0 , so that w 0 '= w 2 +σ 0 (w 3 )+w 11 .

[0153] Further Fig.14 As shown, the 14th extended register R of the operation stage 320-b 14 The extended data in w 14 ' is processed by the second submodule 132 to process the 0th extended register R of the operation stage 320-a 0 The extended data stored in 0 and the 14th extended register R 14 The extended data stored in 14 Specifically, in this example, the second submodule 132 includes σ 1 1 operator and adder ADD2, where the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator and extended data w 0 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 320-b. 14 , so that w 14 '=w 0 +σ 1 (w 14 ).

[0154] Further Fig.14 As shown, the intermediate data w in the second additional register X2 of the operation stage 320-b is x2' is the third extended register R of the processing operation stage 320-a by the third submodule 233 3 The extended data stored in 3 , the fourth extended register R 4 The extended data stored in 4 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 233 includes σ 0 2 arithmetic units, full adder FAA2 and adder ADD3, where the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator, extended data w 3 and extended data w 12 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD3, and the output of the adder ADD3 is provided to the second additional register X2 of the operation stage 320-b, so that w x2 '= w 3 +σ 0 (w 4 )+w 12 .

[0155] Further Fig.14 As shown, the 15th extended register R of the operation stage 320-b 15 The extended data in w 15 ' is the intermediate data w stored in the second additional register X2 of the processing operation stage 320-a by the fourth submodule 234 x2 and the 15th extended register R of the operation stage 220-a 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 234 includes σ 1 2 operators and adder ADD4, where the extended data w 15 is input into σ 1 2 operators, σ 1 2 Output of the operator and intermediate data w x2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 320-b. 15 , so that w 15 '= w x2 +σ 1 (w 15 ).

[0156] Further Fig.13As shown, the extended data stored in the i-th extended register of the operation stage 320-a is directly shifted to the (i-2)-th extended register of the operation stage 320-b, where 3≤i≤15 and i is an integer.

[0157] exist Fig.14 In the example shown, the number of operation logic levels experienced by the first submodule 131 is 3, the number of operation logic levels experienced by the second submodule 132 is 2, the number of operation logic levels experienced by the third submodule 233 is 3, and the number of operation logic levels experienced by the fourth submodule 234 is 2. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 320-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0158] In such Fig.15 In the example shown, the 0th extension register R of the operation stage 320-b is 0 The extended data in w 0 ' is the second extended register R of the operation stage 320-a processed by the first submodule 131 2 The extended data stored in 2 and the 11th extended register R 11 The extended data stored in 11 Specifically, in this example, the first submodule 131 includes an adder ADD1, in which the extended data w 2 and w 11 is input to the adder ADD1, and the output of the adder ADD1 is provided to the 0th extension register R of the operation stage 320-b. 0 , so that w 0 '= w 2 +w 11 .

[0159] Further Fig.15 As shown, the 14th extended register R of the operation stage 320-b 14 The extended data in w 14 ' is processed by the second submodule 132 to process the 0th extended register R of the operation stage 320-a 0 The extended data stored in 0 , the first extended register R 1 The extended data stored in 1 and the 14th extended register R 14 The extended data stored in 14 Specifically, in this example, the second submodule 132 includes σ 0 1 operator, σ 11 operator, full adder FAA1 and adder ADD2, where w 1 is input into σ 0 1 operator, extended data w 14 is input into σ 1 1 operator, σ 0 Operation and σ 1 The operations can be performed simultaneously. Then, σ 0 1 output of the operator, σ 1 1 Output of the operator and extended data w 0 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 320-b. 14 , so that w 14 '=w 0 +σ 0 (w 1 )+σ 1 (w 14 ).

[0160] Further Fig.15 As shown, the intermediate data w in the second additional register X2 of the operation stage 320-b is x2 ' is the third extended register R of the processing operation stage 320-a by the third submodule 233 3 The extended data stored in 3 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 233 includes an adder ADD3, in which the extended data w 3 and w 12 is input to the adder ADD3, and the output of the adder ADD3 is provided to the second additional register X2 of the operation stage 320-b, so that w x2 '= w 3 +w 12 .

[0161] Further Fig.15 As shown, the 15th extended register R of the operation stage 320-b 15 The extended data in w 15 ' is the intermediate data w stored in the second additional register X2 of the operation stage 220-a processed by the fourth submodule 234 x2 , the second extended register R 2 The extended data stored in 2 and the 15th extended register R 15 The extended data stored in 15Specifically, in this example, the fourth submodule 234 includes σ 0 2 operators, σ 1 2 arithmetic units, full adder FAA2 and adder ADD4, where the extended data w 2 is input into σ 0 2 operators, extended data w 15 is input into σ 1 2 operators, σ 0 Operation and σ 1 The operations can be performed simultaneously. Then σ 0 2 The output of the operator, σ 1 2 Output of the operator and intermediate data w x2 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 320-b. 15 , so that w 15 '= w x2 +σ 0 (w 2 )+σ 1 (w 15 ).

[0162] Further Fig.15 As shown, the extended data stored in the i-th extended register of the operation stage 320-a is directly shifted to the (i-2)-th extended register of the operation stage 320-b, where 3≤i≤15 and i is an integer.

[0163] exist Fig.15 In the example shown, the number of operation logic levels experienced by the first submodule 131 is 1, the number of operation logic levels experienced by the second submodule 132 is 3, the number of operation logic levels experienced by the third submodule 233 is 1, and the number of operation logic levels experienced by the fourth submodule 234 is 3. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 320-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0164] Accordingly, the present disclosure also provides a method for calculating extended data in a circuit for executing a hash algorithm. Fig. 20An exemplary flow chart of a method 700 for calculating extended data in a circuit for executing a hash algorithm according to an embodiment of the present disclosure is shown. Such a circuit may include an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, wherein the operation module may include a plurality of operation stages arranged in a pipeline structure, each operation stage includes a 0th to a 15th extended register and a second additional register, each extended register is configured to store extended data of a current operation stage, and the second additional register is configured to store intermediate data for calculating the extended data. For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among multiple operation stages of the operation module, method 700 may include: at S701, based on the extended data stored in the 2nd extended register of the first operation stage, calculating the extended data for storage in the 0th extended register of the second operation stage; at S702, based on the extended data stored in the 0th extended register and the 14th extended register of the first operation stage, calculating the extended data for storage in the 14th extended register of the second operation stage; at S703, based on the extended data stored in the extended register of the first operation stage, calculating the intermediate data for storage in the second additional register of the second operation stage; at S704, based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 15th extended register of the first operation stage, calculating the extended data for storage in the 15th extended register of the second operation stage; at S705, using the extended data stored in the i-th extended register of the first operation stage as the extended data for storage in the (i-2)th extended register of the second operation stage, where 3≤i≤15 and i is an integer. Note that S701 - S705 do not need to be performed in a sequential order, but may be performed in any order, or may be performed at least partially in parallel.

[0165] Method 700 can also calculate the extended data in a manner similar to various combinations of various cooperation modes between submodules according to the embodiments described above, which will not be described in detail here. Method 700 can reduce the calculation delay caused by calculating the extended data in the circuit for executing the hash algorithm, thereby greatly improving the operation speed of the circuit and the computing chip including the circuit, thereby achieving a lower power consumption and computing power ratio.

[0166] For example, Fig.16A schematic block diagram of a circuit 400 for performing a hash algorithm according to some other embodiments of the present disclosure is shown. The arrow indicates the direction of data transfer. The circuit 400 may include an input module 410 and an operation module 420. The input module 410 may be configured to receive data. The operation module 420 may be configured to calculate a hash value based on the received data. The operation module 420 may also include a plurality of extended data operation logic modules 430, each of which is disposed between corresponding adjacent two operation stages (e.g., 420-a and 420-b) in the plurality of operation stages 420-0, ..., 420-31 of the operation module 420.

[0167] The circuit 400 is different from the circuits 100 and 200 in that each operation stage of the operation module 420 of the circuit 400 may include a 0th extension register R 0 To the 15th extended register R 15 and the first additional register X1 without including the second additional register X2, and accordingly, each extended data operation logic module 430 may include the first submodule 231, the second submodule 232, the third submodule 133 and the fourth submodule 134 as described above. In some embodiments, in the first operation stage 220-0, the intermediate data in the first additional register X1 may be compared with the 0th extended register R 0 The extended data is the same as in .

[0168] In the circuit 400: the first submodule 231 can be configured as an extended register R based on the first operation stage (eg, 420-a). 2 The second submodule 232 may be configured to calculate the intermediate data stored in the first additional register X1 of the second operation stage (e.g., 420-b) based on the extended data stored in the first additional register X1 of the first operation stage and the 14th extended register R of the first operation stage. 14 The extended data stored in is calculated for storage in the 14th extended register R of the second operation stage. 14 The third submodule 133 can be configured as a third extended register R based on the first operation level 3 The extended data stored in the calculation is used to store the first extended register R of the second operation stage. 1 The fourth submodule 134 can be configured as a first expansion register R based on the first operation level 1 and the 15th extended register R 15 The extended data stored in is calculated for storage in the 15th extended register R of the second operation stage. 15In addition, the extended data for storage in the (i-2)th extended register of the second operation stage may be the extended data stored in the i-th extended register of the first operation stage, where 4≤i≤15 and i is an integer, and the extended data for storage in the 0th extended register of the second operation stage is the extended data stored in the 2nd extended register of the first operation stage. In the circuit 400, the first submodule 231 and the second submodule 232 may be used to calculate the first W parameter, and the third submodule 133 and the fourth submodule 134 may be used to calculate the second W parameter.

[0169] As described above, the first submodule 231 and the second submodule 232 can use a variety of collaborative methods to calculate the extended data, thereby providing the first W parameter, and its embodiments are not repeated here. Similarly, as described above, the third submodule 133 and the fourth submodule 134 can use a variety of collaborative methods to calculate the extended data, thereby providing the second W parameter, and its embodiments are not repeated here. In various implementations of the circuit 400, any collaborative method of the first submodule 231 and the second submodule 232 according to the embodiment of the present disclosure can be freely combined with any collaborative method of the third submodule 133 and the fourth submodule 134, thereby providing the first W parameter and the second W parameter.

[0170] Combine the following Fig.17 Describe the embodiment according to the present disclosure Fig.16 The circuit 400 shown includes several non-limiting example configurations of portions of the extended data operation logic module, which illustrate non-limiting example combinations of the cooperation of the first submodule 231 and the second submodule 232 and the cooperation of the third submodule 133 and the fourth submodule 134. Fig.17 In the figure, two adjacent operation stages 420-a and 420-b are used as an example for explanation. It can be understood that any two adjacent operation stages in the operation module 420 can be the operation stages 420-a and 420-b discussed below. In addition, in these figures, for the sake of clarity, dotted arrows are used to indicate the moving direction of the extended data that is directly shifted without being operated, solid arrows are used to indicate the moving direction of the extended data processed by the first submodule 231 and the second submodule 232, and dot-dash arrows are used to indicate the moving direction of the extended data processed by the third submodule 133 and the fourth submodule 134. The schematic block diagrams of the first to fourth submodules are separately given below.

[0171] In such Fig.17 In the example shown, the intermediate data w in the first additional register X1 of the operation stage 420-b is x1 ' is the second extended register R of the operation stage 420-a processed by the first submodule 231 2 The extended data stored in 2, the third extended register R 3 The extended data stored in 3 and the 11th extended register R 11 The extended data stored in 11 Specifically, in this example, the first submodule 231 includes σ 0 1 operator, full adder FAA1 and adder ADD1, where the extended data w 3 is input into σ 0 1 operator, σ 0 1 Output of the operator, extended data w 2 and extended data w 11 is input to the full adder FAA1, the output of the full adder FAA1 is input to the adder ADD1, and the output of the adder ADD1 is provided to the first additional register X1 of the operation stage 420-b, so that w x1 '= w 2 +σ 0 (w 3 )+w 11 .

[0172] Further Fig.17 As shown, the 14th extended register R of the operation stage 420-b 14 The extended data in w 14 ' is the intermediate data w stored in the first additional register X1 of the operation stage 220-a processed by the second submodule 232 x1 and the 14th extended register R of the operation stage 420-a 14 The extended data stored in 14 Specifically, in this example, the second submodule 232 includes σ 1 1 operator and adder ADD2, where the extended data w 14 is input into σ 1 1 operator, σ 1 1 Output of the operator and intermediate data w x1 is input to the adder ADD2, and the output of the adder ADD2 is provided to the 14th extended register R of the operation stage 420-b. 14 , so that w 14 '= w x1 +σ 1 (w 14 ).

[0173] Further Fig.17 As shown, the first extended register R of the operation stage 420-b 1 The extended data in w 1 ' is processed by the third submodule 133 to process the third extended register R of the operation stage 420-a 3The extended data stored in 3 , the fourth extended register R 4 The extended data stored in 4 and the 12th extended register R 12 The extended data stored in 12 Specifically, in this example, the third submodule 133 includes σ 0 2 arithmetic units, full adder FAA2 and adder ADD3, where the extended data w 4 is input into σ 0 2 operators, σ 0 2 Output of the operator, extended data w 3 and extended data w 12 is input to the full adder FAA2, the output of the full adder FAA2 is input to the adder ADD3, and the output of the adder ADD3 is provided to the first extended register R of the operation stage 420-b. 1 , so that w 1 '= w 3 +σ 0 (w 4 )+w 12 .

[0174] Further Fig.17 As shown, the 15th extended register R of the operation stage 420-b 15 The extended data in w 15 ' is the first extended register R of the operation stage 420-a processed by the fourth submodule 134 1 The extended data stored in 1 and the 15th extended register R 15 The extended data stored in 15 Specifically, in this example, the fourth submodule 134 includes σ 1 2 operators and adder ADD4, where the extended data w 15 is input into σ 1 2 operators, σ 1 2 Output of the operator and extended data w 1 is input to the adder ADD4, and the output of the adder ADD4 is provided to the 15th extended register R of the operation stage 420-b. 15 , so that w 15 '=w 1 +σ 1 (w 15 ).

[0175] Further Fig.17As shown, the extended data stored in the i-th extended register of the operation stage 420-a is directly shifted to the (i-2)-th extended register of the operation stage 420-b, where 4≤i≤15 and i is an integer, and the extended data stored in the 2nd extended register of the operation stage 420-a is directly shifted to the 0th extended register of the operation stage 420-b.

[0176] exist Fig.17 In the example shown, the number of operation logic levels experienced by the first submodule 231 is 3, the number of operation logic levels experienced by the second submodule 232 is 2, the number of operation logic levels experienced by the third submodule 133 is 3, and the number of operation logic levels experienced by the fourth submodule 134 is 2. The four submodules can operate independently and in parallel with each other, so that the number of operation logic levels required for the final calculation of the extended data for the operation level 420-b is reduced to 3, which greatly reduces the calculation delay and greatly improves the operation speed of the pipeline structure.

[0177] Accordingly, the present disclosure also provides a method for calculating extended data in a circuit for executing a hash algorithm. Fig.21An exemplary flow chart of a method 800 for calculating extended data in a circuit for executing a hash algorithm according to an embodiment of the present disclosure is shown. Such a circuit may include an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, wherein the operation module may include a plurality of operation stages arranged in a pipeline structure, each operation stage includes a 0th to a 15th extended register and a first additional register, each extended register is configured to store extended data of a current operation stage, and the first additional register is configured to store intermediate data for calculating the extended data. For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the multiple operation stages of the operation module, the method 800 may include: at S801, calculating intermediate data for storage in a first additional register of the second operation stage based on extended data stored in an extended register of the first operation stage; at S802, calculating extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in a 14th extended register of the first operation stage; at S803, calculating extended data for storage in a 14th extended register of the second operation stage based on the extended data stored in a 3rd extended register of the first operation stage. At S804, based on the extended data stored in the 1st and 15th extended registers of the first operation level, the extended data for storage in the 15th extended register of the second operation level is calculated; at S805, the extended data stored in the ith extended register of the first operation level is used as the extended data for storage in the (i-2)th extended register of the second operation level, where 4≤i≤15 and i is an integer, and the extended data stored in the 2nd extended register of the first operation level is used as the extended data for storage in the 0th extended register of the second operation level, where 4≤i≤15 and i is an integer. Note that S801-S805 do not need to be executed in a sequential order, but can be executed in any order, or can be executed at least partially in parallel.

[0178] Method 800 can also calculate the extended data in a manner similar to various combinations of various cooperation modes between submodules according to the embodiments described above, which will not be described in detail here. Method 800 can reduce the calculation delay caused by calculating the extended data in the circuit for executing the hash algorithm, thereby greatly improving the operation speed of the circuit and the computing chip including the circuit, thereby achieving a lower power consumption and computing power ratio.

[0179] The present disclosure may also provide a computing chip including the circuit described in any of the above embodiments.

[0180] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words used in this way are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0181] In the specification and claims, when an element is said to be "above", "attached" to, "connected" to, "coupled" to, or "in contact with" another element, the element may be directly above, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, or one or more intermediate elements may be present. In contrast, when an element is said to be "directly" "above", "directly attached" to, "directly connected" to, "directly coupled" to, or "in direct contact with" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is above or below an adjacent feature.

[0182] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described exemplarily herein is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any stated or implied theory given in the technical field, background, summary, or detailed description. As used herein, the word "substantially" is meant to include any minor variations caused by design or manufacturing defects, device or component tolerances, environmental effects, and / or other factors. The word "substantially" also allows for deviations from a perfect or ideal situation caused by parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0183] In addition, for reference purposes only, similar terms such as "first", "second" and the like may also be used herein, and are therefore not intended to be limited. For example, unless the context clearly indicates otherwise, the words "first", "second" and other such numerical terms relating to structures or elements do not imply order or sequence. It should also be understood that when the word "include / comprise" is used herein, it indicates the presence of the indicated features, integral bodies, steps, operations, units and / or components, but does not exclude the presence or increase of one or more other features, integral bodies, steps, operations, units and / or components and / or their combinations. In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" objects, etc.

[0184] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0185] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are equally possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0186] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A circuit for performing a hashing algorithm, include: an input module configured to receive data; as well as A computing module is configured to calculate a hash value based on the received data, the computing module comprising: A plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register, each extension register being configured to store extension data of a current operation stage; and A plurality of extended data operation logic modules, each of which is arranged between two corresponding adjacent operation stages in the plurality of operation stages, the two adjacent operation stages comprising a first operation stage and a second operation stage after the first operation stage, each of which comprises: A first submodule is configured to calculate the extended data for storage in the 0th extended register of the second operation stage based on the extended data stored in the 2nd extended register of the first operation stage; A second submodule is configured to calculate the extended data for storage in the 14th extended register of the second operation stage based on the extended data stored in the 0th extended register and the 14th extended register of the first operation stage; A third submodule is configured to calculate the extended data for storage in the first extended register of the second operation stage based on the extended data stored in the third extended register of the first operation stage; and a fourth submodule, configured to calculate, based on the extended data stored in the first extended register and the fifteenth extended register of the first operation stage, the extended data for storage in the fifteenth extended register of the second operation stage; The extended data stored in the (i-2)th extended register of the second operation stage is the extended data stored in the i-th extended register of the first operation stage, where 4≤i≤15 and i is an integer.

2. The circuit according to claim 1, in, The first submodule is configured to calculate the extended data for storage in the 0th extended register of the second operation stage based on the extended data stored in the 2nd extended register, the 3rd extended register and the 11th extended register of the first operation stage.

3. The circuit according to claim 1, in, The first submodule is configured to calculate the extended data for storage in the 0th extended register of the second operation level based on the extended data stored in the 2nd extended register and the 3rd extended register of the first operation level, and the second submodule is configured to calculate the extended data for storage in the 14th extended register of the second operation level based on the extended data stored in the 0th extended register, the 9th extended register and the 14th extended register of the first operation level.

4. The circuit according to claim 1, in, The third submodule is configured to calculate the extended data for storage in the first extended register of the second operation stage based on the extended data stored in the third extended register, the fourth extended register, and the twelfth extended register of the first operation stage.

5. The circuit according to claim 1, in, The third submodule is configured to calculate the extended data for storage in the 1st extended register of the second operation level based on the extended data stored in the 3rd extended register and the 4th extended register of the first operation level, and the fourth submodule is configured to calculate the extended data for storage in the 15th extended register of the second operation level based on the extended data stored in the 1st extended register, the 10th extended register and the 15th extended register of the first operation level.

6. The circuit according to claim 1, in, The third submodule is configured to calculate the extended data for storage in the 1st extended register of the second operation level based on the extended data stored in the 3rd extended register and the 12th extended register of the first operation level, and the fourth submodule is configured to calculate the extended data for storage in the 15th extended register of the second operation level based on the extended data stored in the 1st extended register, the 2nd extended register and the 15th extended register of the first operation level.

7. A circuit for performing a hash algorithm, include: an input module configured to receive data; as well as A computing module is configured to calculate a hash value based on the received data, the computing module comprising: a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th to a 15th extended register and a first additional register and a second additional register, each extended register being configured to store extended data of a current operation stage, and each additional register being configured to store intermediate data used to calculate the extended data; and A plurality of extended data operation logic modules, each of which is arranged between two corresponding adjacent operation stages in the plurality of operation stages, the two adjacent operation stages comprising a first operation stage and a second operation stage after the first operation stage, each of which comprises: A first submodule configured to calculate intermediate data for storage in a first additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; a second submodule configured to calculate extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extended register of the first operation stage; a third submodule configured to calculate intermediate data for storage in a second additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; and a fourth submodule configured to calculate, based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 15th extended register of the first operation stage, the extended data for storage in the 15th extended register of the second operation stage; The extended data stored in the (i-2)th extended register of the second operation stage is the extended data stored in the i-th extended register of the first operation stage, where 2≤i≤15 and i is an integer.

8. The circuit according to claim 7, in, The first submodule is configured to calculate intermediate data for storage in a first additional register of the second operation stage based on the extended data stored in the second extended register, the third extended register, and the eleventh extended register of the first operation stage.

9. The circuit according to claim 7, in, The first submodule is configured to calculate the intermediate data for storage in the first additional register of the second operation stage based on the extended data stored in the second extended register and the third extended register of the first operation stage, and the second submodule is configured to calculate the extended data for storage in the 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 9th extended register and the 14th extended register of the first operation stage.

10. The circuit according to claim 7, in, The first submodule is configured to calculate the intermediate data for storage in the first additional register of the second operation stage based on the extended data stored in the second extended register and the 11th extended register of the first operation stage, and the second submodule is configured to calculate the extended data for storage in the 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 1st extended register and the 14th extended register of the first operation stage.

11. The circuit according to claim 7, in, The first submodule is configured to calculate the intermediate data for storage in the first additional register of the second operation stage based on the extended data stored in the 3rd extended register and the 11th extended register of the first operation stage, and the second submodule is configured to calculate the extended data for storage in the 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 0th extended register and the 14th extended register of the first operation stage.

12. The circuit according to claim 7, in, The third submodule is configured to calculate intermediate data for storage in the second additional register of the second operation stage based on the extended data stored in the third extended register, the fourth extended register, and the twelfth extended register of the first operation stage.

13. The circuit according to claim 7, in, The third submodule is configured to calculate the intermediate data for storage in the second additional register of the second operation stage based on the extended data stored in the 3rd extended register and the 4th extended register of the first operation stage, and the fourth submodule is configured to calculate the extended data for storage in the 15th extended register of the second operation stage based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 10th extended register and the 15th extended register of the first operation stage.

14. The circuit according to claim 7, in, The third submodule is configured to calculate the intermediate data for storage in the second additional register of the second operation stage based on the extended data stored in the 3rd extended register and the 12th extended register of the first operation stage, and the fourth submodule is configured to calculate the extended data for storage in the 15th extended register of the second operation stage based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 2nd extended register and the 15th extended register of the first operation stage.

15. The circuit according to claim 7, in, The third submodule is configured to calculate the intermediate data for storage in the second additional register of the second operation level based on the extended data stored in the 4th extended register and the 12th extended register of the first operation level, and the fourth submodule is configured to calculate the extended data for storage in the 15th extended register of the second operation level based on the intermediate data stored in the second additional register of the first operation level and the extended data stored in the 1st extended register and the 15th extended register of the first operation level.

16. A circuit for performing a hash algorithm, include: an input module configured to receive data; as well as A computing module is configured to calculate a hash value based on the received data, the computing module comprising: A plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th to a 15th extension register and a second additional register, each extension register being configured to store extension data of a current operation stage, and the second additional register being configured to store intermediate data for calculating the extension data; and A plurality of extended data operation logic modules, each of which is arranged between two corresponding adjacent operation stages in the plurality of operation stages, the two adjacent operation stages comprising a first operation stage and a second operation stage after the first operation stage, each of which comprises: A first submodule is configured to calculate the extended data for storage in the 0th extended register of the second operation stage based on the extended data stored in the 2nd extended register of the first operation stage; A second submodule is configured to calculate the extended data for storage in the 14th extended register of the second operation stage based on the extended data stored in the 0th extended register and the 14th extended register of the first operation stage; a third submodule configured to calculate intermediate data for storage in a second additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; and a fourth submodule configured to calculate, based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 15th extended register of the first operation stage, the extended data for storage in the 15th extended register of the second operation stage; The extended data stored in the (i-2)th extended register of the second operation stage is the extended data stored in the i-th extended register of the first operation stage, where 3≤i≤15 and i is an integer.

17. A circuit for performing a hash algorithm, include: an input module configured to receive data; as well as A computing module is configured to calculate a hash value based on the received data, the computing module comprising: A plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th to a 15th extension register and a first additional register, each extension register being configured to store extension data of a current operation stage, and the first additional register being configured to store intermediate data for calculating the extension data; and A plurality of extended data operation logic modules, each of which is arranged between two corresponding adjacent operation stages in the plurality of operation stages, the two adjacent operation stages comprising a first operation stage and a second operation stage after the first operation stage, each of which comprises: A first submodule configured to calculate intermediate data for storage in a first additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; a second submodule configured to calculate extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extended register of the first operation stage; A third submodule is configured to calculate the extended data for storage in the first extended register of the second operation stage based on the extended data stored in the third extended register of the first operation stage; and a fourth submodule, configured to calculate, based on the extended data stored in the first extended register and the fifteenth extended register of the first operation stage, the extended data for storage in the fifteenth extended register of the second operation stage; Among them, the extended data used to be stored in the (i-2)th extended register of the second operation level is the extended data stored in the i-th extended register of the first operation level, where 4≤i≤15 and i is an integer, and the extended data used to be stored in the 0th extended register of the second operation level is the extended data stored in the 2nd extended register of the first operation level.

18. A computing chip comprising the circuit according to any one of claims 1-17.

19. A method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register, each extension register being configured to store extended data of a current operation stage, the method include: For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: Calculating the extended data to be stored in the 0th extended register of the second operation stage based on the extended data stored in the 2nd extended register of the first operation stage; Calculating the extended data to be stored in the 14th extended register of the second operation stage based on the extended data stored in the 0th extended register and the 14th extended register of the first operation stage; calculating, based on the extended data stored in the third extended register of the first operation stage, extended data for storage in the first extended register of the second operation stage; Calculating the extended data to be stored in the 15th extended register of the second operation stage based on the extended data stored in the 1st extended register and the 15th extended register of the first operation stage; as well as The extended data stored in the i-th extended register of the first operation stage is used as the extended data for storage in the (i-2)-th extended register of the second operation stage, where 4≤i≤15 and i is an integer.

20. A method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th to a 15th extended register and a first additional register and a second additional register, each extended register being configured to store extended data of a current operation stage, each additional register being configured to store intermediate data for calculating the extended data, the method include: For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: calculating intermediate data for storage in a first additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; calculating extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extended register of the first operation stage; calculating intermediate data for storage in a second additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; calculating extended data for storage in the 15th extended register of the second operation stage based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 15th extended register of the first operation stage; as well as The extended data stored in the i-th extended register of the first operation stage is used as the extended data for storage in the (i-2)-th extended register of the second operation stage, where 2≤i≤15 and i is an integer.

21. A method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a second additional register, each extension register being configured to store extended data of a current operation stage, the second additional register being configured to store intermediate data for calculating the extended data, the method include: For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: Calculating the extended data to be stored in the 0th extended register of the second operation stage based on the extended data stored in the 2nd extended register of the first operation stage; Calculating the extended data to be stored in the 14th extended register of the second operation stage based on the extended data stored in the 0th extended register and the 14th extended register of the first operation stage; calculating intermediate data for storage in a second additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; calculating extended data for storage in the 15th extended register of the second operation stage based on the intermediate data stored in the second additional register of the first operation stage and the extended data stored in the 15th extended register of the first operation stage; as well as The extended data stored in the i-th extended register of the first operation stage is used as the extended data for storage in the (i-2)-th extended register of the second operation stage, where 3≤i≤15 and i is an integer.

22. A method for calculating extended data in a circuit for executing a hash algorithm, the circuit comprising an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, the operation module comprising a plurality of operation stages arranged in a pipeline structure, each of the plurality of operation stages comprising a 0th extension register to a 15th extension register and a first additional register, each extension register being configured to store extended data of a current operation stage, the first additional register being configured to store intermediate data for calculating the extended data, the method include: For two adjacent operation stages including a first operation stage and a second operation stage after the first operation stage among the plurality of operation stages: calculating intermediate data for storage in a first additional register of the second operation stage based on the extended data stored in the extended register of the first operation stage; calculating extended data for storage in a 14th extended register of the second operation stage based on the intermediate data stored in the first additional register of the first operation stage and the extended data stored in the 14th extended register of the first operation stage; calculating, based on the extended data stored in the third extended register of the first operation stage, extended data for storage in the first extended register of the second operation stage; Calculating the extended data to be stored in the 15th extended register of the second operation stage based on the extended data stored in the 1st extended register and the 15th extended register of the first operation stage; as well as The extended data stored in the i-th extended register of the first operation level is used as the extended data for storage in the (i-2)-th extended register of the second operation level, where 4≤i≤15 and i is an integer, and the extended data stored in the 2nd extended register of the first operation level is used as the extended data for storage in the 0th extended register of the second operation level.

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