Optical detection device and optical detection system

Abstract

The present invention discloses an optical detection device and an optical detection system. In this device, in a planar view, at least a part of a first semiconductor region of a first conductivity type overlaps with at least a part of a third semiconductor region, at least a part of a second semiconductor region overlaps with at least a part of a fourth semiconductor region of a second conductivity type, the height of the potential of the third semiconductor region with respect to the charge of the first conductivity type is lower than the height of the potential of the fourth semiconductor region, and the difference between the height of the potential of the first semiconductor region and the height of the potential of the third semiconductor region is greater than the difference between the height of the potential of the second semiconductor region and the height of the potential of the fourth semiconductor region.

Description

[0001] This application is a divisional application of the invention patent application with the application date of October 13, 2017, the application number of 201710949673.5, and the invention title of "Optical Detection Device and Optical Detection System". Technical Field

[0002] Aspects of the embodiments relate to an optical detection device and an optical detection system that perform photoelectric conversion. Background Art

[0003] Conventionally, an optical detection device that can detect weak light at the single-photon level using avalanche (electron avalanche) multiplication has been known.

[0004] In the specification of U.S. Patent No. 9,209,336, a single-photon avalanche diode (SPAD) is discussed, in which photo carriers derived from a single photon cause avalanche amplification in the PN junction region of the semiconductor region constituting the photoelectric converter.

[0005] In the SPAD discussed in the specification of U.S. Patent No. 9,209,336, a P-type semiconductor region with a high impurity concentration is arranged on the surface of the semiconductor substrate, and an N-type semiconductor region is arranged below the P-type semiconductor region. The N-type semiconductor region is arranged to be included in the N-type epitaxial layer. The P-type semiconductor region and the N-type semiconductor region form a PN junction, and a high reverse bias voltage is applied to the PN junction.

[0006] In the SPAD discussed in the specification of U.S. Patent No. 9,209,336, the region where charges are detected is the PN junction region. A strong electric field is generated in the region where charges are detected, so there is a possibility of tunneling effect through the strong electric field in the PN junction. The charges generated by the tunneling effect may become noise by being detected as a pseudo signal in the region where charges are detected. The charges generated by the tunneling effect increase in proportion to the area of the region where charges are detected.

[0007] On the other hand, if the area of the region where charges are detected is reduced, the charges generated by the tunneling effect can be suppressed. However, if the area of the region where charges are detected is reduced, there is a possibility of reducing the optical detection efficiency. Summary of the Invention

[0008] According to one aspect of an embodiment, a device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, and a pixel unit disposed on the semiconductor substrate and having a plurality of pixels including avalanche diodes, wherein each avalanche diode includes: a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region disposed in contact with the first semiconductor region; a third semiconductor region disposed at a second depth deeper than the first depth relative to the first surface; a fourth semiconductor region of a second conductivity type disposed in contact with the third semiconductor region, the second conductivity type being opposite to the first conductivity type; and a fifth semiconductor region disposed at a third depth deeper than the second depth relative to the first surface, and wherein, in a plan view, at least a portion of the first semiconductor region overlaps with at least a portion of the third semiconductor region, at least a portion of the second semiconductor region overlaps with at least a portion of the fourth semiconductor region, and the third semiconductor region and the fourth semiconductor region overlap with the fifth semiconductor region, a height of a potential of a charge of the third semiconductor region with respect to the charge of the first conductivity type is lower than a height of a potential of a charge of the fourth semiconductor region with respect to the charge of the first conductivity type, and a difference between a height of a potential of a charge of the first semiconductor region with respect to the charge of the first conductivity type and a height of a potential of a charge of the third semiconductor region with respect to the charge of the first conductivity type is greater than a difference between a height of a potential of a charge of the second semiconductor region with respect to the charge of the first conductivity type and a height of a potential of a charge of the fourth semiconductor region with respect to the charge of the first conductivity type.

[0009] Additional features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic cross-sectional view of an avalanche diode.

[0011] Figure 2A and 2B is a schematic plan view of an avalanche diode.

[0012] Figure 3 is a potential diagram of an avalanche diode.

[0013] Figure 4 is a block diagram of a light detection device.

[0014] Figure 5 is a block diagram of a pixel including an equivalent circuit.

[0015] Figure 6 is a schematic cross-sectional view of an avalanche diode.

[0016] Figures 7A to 7C is a schematic plan view of an avalanche diode.

[0017] Figures 8A to 8DA method of manufacturing an avalanche diode is shown.

[0018] Figure 9A and 9B is an equivalent circuit diagram.

[0019] Figure 10 is a schematic cross-sectional view of an avalanche diode.

[0020] Figure 11 is a schematic cross-sectional view of an avalanche diode.

[0021] Figure 12 is a schematic cross-sectional view of an avalanche diode.

[0022] Figure 13A and 13B is a schematic plan view of an avalanche diode.

[0023] Figure 14 is a schematic cross-sectional view of an avalanche diode.

[0024] Figure 15A and 15B is a schematic plan view of an avalanche diode.

[0025] Figure 16 is a schematic cross-sectional view of an avalanche diode.

[0026] Figure 17 is a block diagram of a light detection system.

[0027] Figure 18 is a block diagram of a light detection system.

[0028] Figure 19A and 19B is a block diagram of a light detection system.

[0029] Figure 20 is a schematic cross-sectional view of an avalanche diode. Detailed implementation

[0030] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Reference will be made to Figures 1 to 3 A light detection device according to an exemplary embodiment will be described. The light detection device according to this exemplary embodiment has a pixel including an avalanche diode. The conductivity type of the charge used as a signal charge among a pair of charges generated in the avalanche diode is referred to as a first conductivity type. The opposite conductivity type of the first conductivity type is referred to as a second conductivity type.

[0032] Figure 1It is a schematic cross-sectional view of an avalanche diode according to this exemplary embodiment. The avalanche diode in this exemplary embodiment is disposed in a semiconductor substrate 15. The semiconductor substrate 15 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front surface of the semiconductor substrate 15, and the second surface is the back surface of the semiconductor substrate 15. In this exemplary embodiment, the depth direction is defined as the direction from the first surface toward the second surface. The gate electrode of the transistor and the multilayer interconnect structure are disposed on the front surface of the semiconductor substrate 15.

[0033] In Figure 1 it, a first semiconductor region 71 of a first conductivity type, a second semiconductor region 76, a third semiconductor region 74, a fourth semiconductor region 72 of a second conductivity type, and a fifth semiconductor region 75 are disposed in a region surrounded by an isolation portion 16.

[0034] The first semiconductor region 71 and the second semiconductor region 76 are disposed at a first depth X. The first semiconductor region 71 and the second semiconductor region 76 are in contact. The second semiconductor region 76 is disposed between the first semiconductor region 71 and the isolation portion 16. Here, the meaning that the first semiconductor region 71 and the second semiconductor region 76 are disposed at the first depth X is that, for example, the region with the highest implanted impurity concentration (peak) is disposed at the first depth X. However, this peak does not necessarily need to be disposed at the first depth X, and design errors or manufacturing errors are allowed.

[0035] The third semiconductor region 74 and the fourth semiconductor region 72 are disposed at a second depth Y deeper than the first depth X with respect to the first surface. The third semiconductor region 74 and the fourth semiconductor region 72 are in contact.

[0036] At least a part of the first semiconductor region 71 overlaps with at least a part of the third semiconductor region 74, and at least a part of the second semiconductor region 76 overlaps with at least a part of the fourth semiconductor region 72. The fourth semiconductor region 72 is disposed between the third semiconductor region 74 and the isolation portion 16.

[0037] The fifth semiconductor region 75 is disposed at a third depth Z deeper than the second depth Y with respect to the first surface. The third semiconductor region 74 and the fourth semiconductor region 72 overlap with the fifth semiconductor region 75.

[0038] Figure 2A and 2B are schematic plan views. Figure 2A shows a schematic plan view at the first depth X, Figure 2B shows a schematic plan view at the second depth Y.

[0039] As Figure 2AAs shown, the first semiconductor region 71 is included in the second semiconductor region 76 at the first depth X. The second semiconductor region 76 is included in the isolation section 16.

[0040] As Figure 2B shown, the third semiconductor region 74 is included in the fourth semiconductor region 72 at the second depth Y. The fourth semiconductor region 72 is included in the isolation section 16. From Figures 1 to 2B it can be seen that at least a part of the first semiconductor region 71 overlaps with the third semiconductor region 74, and the third semiconductor region 74 and the fourth semiconductor region 72 overlap with the fifth semiconductor region 75 in the plan view. In addition, at least a part of the second semiconductor region 76 overlaps with the fourth semiconductor region 72.

[0041] Figure 3 Shows the potential diagram of the avalanche diode. Figure 3 Shows Figure 1 An example of the potential distribution of the line segment JK and the line segment GH of the cross-sectional view shown. The dashed line 20 shows the potential distribution of the line segment GH, and the solid line 21 shows the potential distribution of the line segment JK. Here, the potential seen from electrons as signal charges is shown. If the signal charges consist of holes, the relationship of the potential levels is reversed.

[0042] In addition, in Figure 3 , the depths X, Y, Z, and W correspond to Figure 1 each depth shown, and the depth W is any depth between the depth Y and the depth Z.

[0043] The potential level of the XH level shows the potential level of the fourth semiconductor region 72. The potential level of the H level shows the potential level of the third semiconductor region 74. The potential level of the M level shows the potential level of the second semiconductor region 76. The potential level of the L level shows the potential level of the first semiconductor region 71. Here, it is assumed that the potential level of the second semiconductor region 76 is lower than the potential level of the third semiconductor region 74, but this relationship can be reversed.

[0044] The dashed line 20 shows the potential level between the XH level and the H level at the depth Z. As the depth approaches the depth W from the depth Z, the potential gradually decreases. Then, as the depth approaches the depth Y from the depth W, the potential gradually rises to reach the XH level at the depth Y. As the depth approaches the depth X from the depth Y, the potential gradually decreases. The potential reaches the M level at the depth X.

[0045] The solid line 21 shows the potential level between the XH level and the H level at the depth Z. Before the depth approaches the depth Y from the depth Z, the potential gradually decreases. When the depth approaches the depth Y, the level of the potential starts to decrease sharply to reach the potential level of the H level at the depth Y. Before the depth approaches the depth X from the depth Y, the potential level decreases sharply. Then, the potential level reaches the L level at the depth X.

[0046] The potentials of the dashed line 20 and the solid line 21 have almost the same level at the depth Z and have a potential gradient that gradually decreases toward the first surface side of the semiconductor substrate 15 in the regions indicated by the line segment GH and the line segment JK. Therefore, the charges generated in the photodetection device move to the first surface side due to the gradual potential gradient.

[0047] As the depth approaches the depth Y from the depth W, the solid line 21 has a gradually decreasing potential gradient, and the charges move to the first surface side. On the other hand, the dashed line 20 forms a potential gradient that acts as a barrier for the charges moving to the first surface. The barrier (the fourth semiconductor region 72) inhibits the movement of charges from the fifth semiconductor region 75 to the second semiconductor region 76. Since the potential in the direction of movement from the line segment GH to the line segment JK is lower than the barrier, the charges existing on the line segment GH can easily move to the vicinity of the line segment JK during the movement toward the first surface from the depth W to the depth Y.

[0048] The charges that have moved to the vicinity of the region indicated by the line segment JK are accelerated by a steep potential gradient (i.e., a strong electric field from the depth Y to the depth X), and the accelerated charges reach the first semiconductor region 71. Avalanche amplification occurs in the region from the depth Y to the depth X. In the region indicated by the line segment GH, on the contrary, the potential distribution is such that avalanche breakdown does not occur or is less likely to occur compared to the region indicated by the line segment JK (or particularly the region of the line segment JK from the depth Y to the depth X). As an example of implementing such a structure, a structure is adopted in which the difference between the potential level of the first semiconductor region 71 and the potential level of the third semiconductor region 74 is greater than the difference between the potential levels of the second semiconductor region 76 and the fourth semiconductor region 72.

[0049] By adopting such a potential structure, when compared with the conventional structure in which an avalanche breakdown occurs in a through avalanche diode, the noise charges generated by the above-mentioned tunneling effect can be reduced. In addition, according to the avalanche diode in the present exemplary embodiment, the sensitivity is not deteriorated. This is because the potential structure enables the signal charges existing in the region of the fifth semiconductor region 75 overlapping with the fourth semiconductor region 72 to easily move to the first semiconductor region via the third semiconductor region 74.

[0050] More specifically, this is because the potential level of the third semiconductor region 74 is lower than the potential level of the fourth semiconductor region 72. That is, the fourth semiconductor region 72 acts as a potential barrier for signal charges present in the fifth semiconductor region 75, and as a result, the charges can easily move to the first semiconductor region 71 via the third semiconductor region 74.

[0051] exist Figure 3 , the potential structure when the third semiconductor region 74 is a P-type semiconductor region is shown, but if the third semiconductor region 74 is an N-type semiconductor region, then as a potential level, the dotted line 20 is still higher than the solid line 21 at the position Y. In addition, the potential structure when the second semiconductor region 76 is an N-type semiconductor region is shown, but if the second semiconductor region 76 is a P-type semiconductor region, then as a potential level, the dotted line 20 is still higher than the solid line 21 at the position Y.

[0052] Incidentally, the entire area of ​​the first semiconductor region 71 in the plan view overlaps with the third semiconductor region 74. According to this structure, the first semiconductor region 71 and the fourth semiconductor region 72 do not form a PN junction. Therefore, avalanche amplification occurs in the PN junction between the first semiconductor region 71 and the fourth semiconductor region 72, thereby suppressing the generation of noise caused by the tunnel effect.

[0053] Hereinafter, the exemplary embodiments of the present disclosure will be described using specific exemplary embodiments. In each exemplary embodiment, a structure in which the signal charge is composed of electrons is described, but each exemplary embodiment is applicable even if the signal charge is composed of holes. However, in this case, the relationship between each semiconductor region and the potential is opposite.

[0054] Will refer to Figures 4 to 9B A first exemplary embodiment of a light detection device to which the present disclosure can be applied is described. Figures 1 to 3 Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted.

[0055] Figure 4 is a block diagram of a light detection device 1010 of the first exemplary embodiment. The light detection device 1010 includes a pixel unit 106 , a control pulse generation unit 109 , a horizontal scanning circuit unit 104 , a column circuit 105 , a signal line 107 , and a vertical scanning circuit unit 103 .

[0056] A plurality of pixels 100 are arranged in a matrix shape in a pixel unit 106. One pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 converts light into an electric signal. The pixel signal processing unit 102 outputs the converted electric signal to a column circuit 105.

[0057] The vertical scanning circuit unit 103 receives control pulses supplied from the control pulse generation unit 109 and supplies the control pulses to each pixel 100. A logic circuit such as a shift register or an address decoder is used as the vertical scanning circuit unit 103.

[0058] The signal line 107 supplies, as a potential signal, the signal output from the pixel 100 selected by the vertical scanning circuit unit 103 to the subsequent circuit of the pixel 100.

[0059] The signal of each pixel 100 is input to the column circuit 105 via the signal line 107 to perform a predetermined process. The predetermined process includes noise removal and amplification of the input signal, and conversion into a form for output outside the sensor. For example, the column circuit includes a parallel - serial conversion circuit.

[0060] The horizontal scanning circuit unit 104 supplies control pulses to the column circuit 105 to sequentially output the signal processed by the column circuit 105 to the output circuit 108.

[0061] The output circuit 108 includes a buffer amplifier, a differential amplifier, etc., and outputs the signal output from the column circuit 105 to a recording unit or a signal processing unit outside the light detection device 1010.

[0062] In Figure 4 , the pixels 100 can be arranged one - dimensionally in the pixel unit 106, or the pixel unit 106 can include only a single pixel. In addition, multiple pixel columns can be divided into blocks to arrange the vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the column circuit 105, and the pixel unit 106 in each block. Further, the vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the column circuit 105, and the pixel unit 106 can be arranged in each pixel column.

[0063] The function of the pixel signal processing unit 102 does not necessarily need to be provided to each of all the pixels 100. For example, one pixel signal processing unit 102 can be shared by multiple pixels 100 to sequentially perform signal processing. To increase the aperture ratio of the photoelectric conversion element 101, the pixel signal processing unit 102 can be provided on a semiconductor substrate different from that of the photoelectric conversion element 101. In this case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are electrically connected by connection lines provided for each pixel. The vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the signal line 107, and the column circuit 105 can also be provided on different semiconductor substrates as described above.

[0064] Figure 5 An example of a block diagram showing a pixel 100 including an equivalent circuit according to this exemplary embodiment. In Figure 5In this case, a pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102.

[0065] The photoelectric conversion element 101 includes a photoelectric conversion unit 201 and a control unit 202.

[0066] The photoelectric conversion unit 201 generates a pair of charges according to incident light through photoelectric conversion. For the photoelectric conversion unit 201, an avalanche diode is used.

[0067] A potential higher than the potential VL supplied to the anode, i.e., the potential VH, is supplied to the cathode of the photoelectric conversion unit 201. Then, potentials are supplied to the anode and cathode of the photoelectric conversion unit 201 such that a reverse bias is applied to allow the photoelectric conversion unit 201 to act as an avalanche diode. By performing photoelectric conversion while supplying such a potential for the reverse bias, the charges generated by the incident light cause avalanche amplification, generating an avalanche current.

[0068] If, when the potential for the reverse bias is supplied, the potential difference between the anode and the cathode is greater than the breakdown voltage, the avalanche diode performs Geiger mode operation. A photodiode that uses Geiger mode operation to detect weak signals at the single-photon level at high speed is a single-photon avalanche diode (SPAD).

[0069] If the potential difference between the anode and the cathode of the photoelectric conversion unit 201 is above the potential difference at which the charges generated in the photoelectric conversion unit 201 cause avalanche amplification and is equal to or less than the breakdown voltage, the avalanche diode enters the linear mode. An avalanche diode that performs light detection in the linear mode is called an avalanche photodiode (APD). In the present exemplary embodiment, the photoelectric conversion unit 201 can operate as an avalanche diode in either mode. The potential difference that causes avalanche amplification will be described below.

[0070] The control unit 202 is connected to the photoelectric conversion unit 201 and the power supply voltage that supplies the high potential VH. The control unit 202 has a function of replacing any change in the avalanche current generated by the photoelectric conversion unit 201 with a voltage signal. In addition, the control unit 202 serves as a load circuit (quenching circuit) during the signal amplification by avalanche amplification to suppress avalanche amplification by suppressing the voltage supplied to the photoelectric conversion unit 201 (quenching operation). As the control unit 202, for example, a resistance element or an active quenching circuit that actively suppresses avalanche amplification by detecting an increase in the avalanche current and performing feedback control is used.

[0071] The pixel signal processing unit 102 includes a waveform shaping unit 203, a counter circuit 209, and a selection circuit 206. The waveform shaping unit 203 shapes the voltage change obtained when a photon level signal is detected to output a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 203. An example of using one inverter is shown as the waveform shaping unit 203. However, a circuit in which multiple inverters are connected in series or other circuits having a waveform shaping effect may also be used.

[0072] The pulse signal output from the waveform shaping unit 203 is counted by the counter circuit 209. In the case of an N-bit counter (N: a positive integer), the counter circuit 209 can count up to approximately the 2 to the Nth power of the pulse signal of a single photon at most. The count signal is held as a detection signal. When the control pulse pRES is supplied through the drive line 207, the detection signal held in the counter circuit 209 is reset.

[0073] The control pulse pSEL is supplied from the Figure 4 vertical scanning circuit unit 103 in to the selection circuit 206 through the drive line 208 to switch the electrical connection and non-connection between the counter circuit 209 and the signal line 107. For example, as the selection circuit 206, a transistor or a buffer circuit that outputs a signal from the pixel is used.

[0074] Incidentally, the electrical connection can be switched by arranging a switch such as a transistor between the control unit 202 and the photoelectric conversion unit 201 or between the photoelectric conversion element 101 and the pixel signal processing unit 102. Similarly, the supply of the high potential VH supplied to the control unit 202 or the low potential VL supplied to the photoelectric conversion element 101 can be electrically switched by using a switch such as a transistor.

[0075] In the pixel unit 106 in which a plurality of pixels 100 are arranged in a matrix shape, a captured image can be obtained by a rolling shutter operation, in which the count of the counter circuit 209 is sequentially reset for each row, and the detected signal held in the counter circuit 209 is sequentially output for each row.

[0076] Alternatively, a captured image can be obtained by a global electronic shutter operation, in which the counts of the counter circuits 209 of all pixel rows are reset simultaneously, and the detection signals held in the counter circuits 209 are sequentially output for each row. When performing the global electronic shutter operation, it is preferably to provide a unit to switch between the case where the counter circuit 209 performs counting and the case where it does not perform counting. For example, the unit to be switched is the above-mentioned switch.

[0077] In the present exemplary embodiment, a configuration for obtaining a captured image by using a counter circuit 209 is shown. However, instead of the counter circuit 209, an optical detection device 1010 for obtaining a pulse detection timing may be configured by using a time-to-digital converter (TDC) and a memory.

[0078] In this case, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC. A control pulse pREF (reference signal) is supplied from the Figure 4 vertical scanning circuit unit 103 in to the TDC via a driving line to measure the timing of the pulse signal. When the signal output from each pixel via the waveform shaping unit 203 is set as a relative time with respect to the input timing of the control pulse pREF, the TDC acquires the signal as a digital signal.

[0079] For example, a delay line system in which buffer circuits are connected in series to generate a delay or a ring-shaped TDC system in which delay lines are connected like a ring is used as the circuit of the TDC. Although other systems may be used, a circuit system capable of achieving a time resolution equal to or higher than the time resolution of the photoelectric conversion unit 201 is used.

[0080] The digital signal indicating the pulse detection timing obtained by the TDC is stored in one or more memories. When a plurality of memories are arranged, output to the signal line 107 can be controlled for each memory by supplying a plurality of signals to the selection circuit 206 when the digital signal stored in the memory is output to the signal line 107.

[0081] Reference will be made to Figures 6 to 7C a schematic cross-sectional view and a schematic plan view of an avalanche diode according to the present exemplary embodiment. In Figure 6 the region where the first semiconductor region 71 in is arranged, an N-type semiconductor region 1 is arranged, and in the region where the second semiconductor region 76 in is arranged, an N-type semiconductor region 6 is arranged. In Figure 1 the region where the third semiconductor region 74 in is arranged, an N-type semiconductor region 4 is arranged, and in the region where the fourth semiconductor region 72 in is arranged, a P-type semiconductor region 2 is arranged. In Figure 1 the region where the fifth semiconductor region 75 in is arranged, an N-type semiconductor region 5 is arranged. Figure 6 First, reference will be made to Figure 1 the cross-sectional structure of the isolation portion 16 and the photoelectric conversion region surrounded by the isolation portion 16. Figure 1 Figure 6 Figure 1

[0082] Figure 6

[0083] ​​​​​The isolation portions 16 that isolate each of the plurality of pixels 100 are disposed on the semiconductor substrate 15 on which the plurality of pixels 100 are disposed.

[0084] The isolation portion 16 is formed of a P-type semiconductor region disposed from the first surface in the depth direction. More specifically, the P-type semiconductor region 3 and the P-type semiconductor region 7 are sequentially disposed from the first surface along the depth direction and are in contact with the isolation portion 16. The P-type semiconductor region 3 is electrically connected to the P-type semiconductor region 7, the P-type semiconductor region 8 described below, and the P-type semiconductor region 2 described below.

[0085] The impurity concentration of the P-type semiconductor region 3 is higher than the impurity concentrations of the P-type semiconductor region 7, the P-type semiconductor region 8, and the P-type semiconductor region 2. Therefore, for example, connecting the P-type semiconductor region 3 and the contact plug 17 can make the contact resistance lower than the contact resistance of connecting the P-type semiconductor region 7 and the contact plug 17.

[0086] The N-type semiconductor region 1 is a region having an impurity concentration higher than each of the impurity concentrations of the N-type semiconductor region 6, the N-type semiconductor region 4, and the N-type semiconductor region 5 described below. By adopting such an impurity concentration, the electric field of the depletion layer generated in the N-type semiconductor region 1 can be made stronger. Incidentally, a potential as a reverse bias with respect to the isolation portion 16 is supplied to the N-type semiconductor region 1.

[0087] The impurity concentration of the N-type semiconductor region 4 is set to be lower than the impurity concentration of the N-type semiconductor region 1. Therefore, it is easier for the charges near the N-type semiconductor region 4 to move to the N-type semiconductor region 1.

[0088] The impurity concentration of the N-type semiconductor region 6 is set to be lower than the impurity concentration of the N-type semiconductor region 1. For example, when the impurity concentration of the N-type semiconductor region 1 is 6.0×10 18 [atms / cm 3 or more, the impurity concentration of the N-type semiconductor region 6 is set to be 1.0×10 16 [atms / cm 3 or more and 1.0×10 18 [atms / cm 3 or less.

[0089] In Figure 6 is shown a structure in which the N-type semiconductor region 6 having no impurity concentration gradient is disposed in the second semiconductor region 76 in Figure 1 , however, Figure 1The semiconductor region disposed in the region with the second semiconductor region 76 has an impurity concentration gradient. By adopting a structure in which the region between the N-type semiconductor region 1 and the P-type semiconductor region 3 has an impurity concentration gradient, the strong electric field that may be generated between the N-type semiconductor region 1 and the P-type semiconductor region 3 can be weakened as compared with the case where there is no impurity concentration gradient in the N-type semiconductor region 6.

[0090] Two examples of the region with an impurity concentration gradient will be described. The first example is the case where an N-type semiconductor region having an impurity concentration lower than that of the N-type semiconductor region 1 is disposed in the region near the N-type semiconductor region 1, and an N-type semiconductor region having an impurity concentration lower than that of the above N-type semiconductor region is disposed in the region near the isolation part 16. The second example is the case where an N-type semiconductor region having an impurity concentration lower than that of the N-type semiconductor region 1 is disposed in the region near the N-type semiconductor region 1, and a P-type semiconductor region having an impurity concentration lower than that of the P-type semiconductor region 3 is disposed in the region near the isolation part 16. More specifically, as Figure 20 shown, a P-type semiconductor region 2000 having an impurity concentration lower than that of the P-type semiconductor region 3 is provided between the P-type semiconductor region 3 and the N-type semiconductor region 6.

[0091] Next, the impurity concentration of the P-type semiconductor region 2 is set to be lower than that of the P-type semiconductor region 7. The P-type semiconductor region 2 and the N-type semiconductor region 4 form a PN junction. Due to the PN junction, the entire region of the N-type semiconductor region 4 becomes a depletion layer region. In addition, the depletion layer region extends to reach a part of the N-type semiconductor region 1. A strong electric field is induced in the extended depletion layer region. Due to the strong electric field, avalanche amplification occurs in the depletion layer region that extends to the said part of the N-type semiconductor region 1, and a current based on the amplified charge is output from the wire 9. That is to say, in the present exemplary embodiment, the light detection region becomes the depletion layer region in the said part of the N-type semiconductor region 1.

[0092] In the present exemplary embodiment, the N-type semiconductor region 4 is formed by replacing the P-type region with an N-type region because in this way, charges can be obtained from a deeper part by widening the depletion layer deeper into the deep part of the N-type semiconductor region 5.

[0093] Furthermore, if the N-type semiconductor region 6 is to be a P-type semiconductor region, a depletion layer region can be formed between the P-type semiconductor region and the N-type semiconductor region 1, so that avalanche amplification may occur between the P-type semiconductor region and the N-type semiconductor region 1. In the present exemplary embodiment, the N-type semiconductor region 1 is formed of N-type because if the depletion layer region is widened to contact the first surface of the semiconductor substrate 15, the noise increases.

[0094] In addition, the impurity concentrations of the N-type semiconductor region 1, the N-type semiconductor region 4, and the P-type semiconductor region 2 are set such that the N-type semiconductor region 1 is not completely depleted when a potential difference that causes avalanche amplification in the depletion layer region generated in a part of the N-type semiconductor region 1 is supplied. This is because if the depletion layer region is widened to contact the first surface of the semiconductor substrate 15, noise may be generated on the first surface of the semiconductor substrate 15. On the other hand, the impurity concentration is set such that the N-type semiconductor region 4 is completely depleted.

[0095] The condition for complete depletion of the N-type semiconductor region 4 is shown in Equation 1. In this case, the impurity concentration of the N-type semiconductor region 4 is the impurity concentration Nd, the impurity concentration of the P-type semiconductor region 2 is the impurity concentration Na, the elementary charge is the elementary charge q. In addition, the dielectric constant of the semiconductor is the dielectric constant ε, the potential difference of the PN junction between the N-type semiconductor region 4 and the P-type semiconductor region 2 is the potential difference V, and the length of the N-type semiconductor region 4 surrounded by the P-type semiconductor region 2 is the length D.

[0096] [Mathematical formula 1]

[0097]

[0098] Assume that the impurity concentration that does not completely deplete the N-type semiconductor region 1 is, for example, 6.0×10 18 [atms / cm 3 or more. In this case, for the impurity concentration of the P-type semiconductor region 2, the impurity concentration that satisfies this depletion condition is 1.0×10 16 [atms / cm 3 or more, and for the impurity concentration of the N-type semiconductor region 4, the impurity concentration that satisfies this depletion condition is 1.0×10 17 [atms / cm 3 or less. However, the impurity concentration is not limited to the above impurity concentration.

[0099] Then, the potential difference between the N-type semiconductor region 1 and the isolation portion 16 is set such that the electric field in the depth direction induced in the extended depletion layer is large enough. Here, the potential difference that makes the electric field sufficiently large is the potential difference at which the charge affected by the electric field causes avalanche amplification. That is, the potential difference is the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3, at which the photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD).

[0100] More specifically, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is 6V or more. In this case, as described above, the N-type semiconductor region 4 electrically connected to the N-type semiconductor region 1 completely becomes a depletion layer region, and a strong electric field that can cause avalanche amplification is generated in the depletion layer region that extends to a part of the N-type semiconductor region 1.

[0101] In one embodiment, if the impurity concentration that satisfies the above depletion condition is considered, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 is 10V or more and 30V or less. At this time, for example, a potential of 10V or more is supplied to the N-type semiconductor region 1, and a potential of 0V or less is supplied to the P-type semiconductor region 3. However, when the potential difference is 6V or more, the potential values are not limited to the above values.

[0102] In addition, the depletion layer formed between the P-type semiconductor region 2 and the N-type semiconductor region 6 can extend to the N-type semiconductor region 1 to cause avalanche amplification. In this case, if the N-type semiconductor region 1 is completely depleted, noise may be generated. Therefore, the impurity concentration of the N-type semiconductor region 1 is set such that the N-type semiconductor region 1 is not completely depleted.

[0103] Incidentally, according to this exemplary embodiment, charges are generated in the N-type semiconductor region 5 and collected and read in the N-type semiconductor region 1. That is, the charges generated in the semiconductor region of the first conductivity type are read from the semiconductor region of the first conductivity type.

[0104] On the contrary, in the device discussed in the specification of U.S. Patent No. 9,209,336, the charges generated in the N-type epitaxial layer 2 are read from the p-type anode region 14 after avalanche amplification at the interface between the N-type epitaxial layer 2 and the p-type anode region 14. That is, the charges generated in the semiconductor region of the first conductivity type are read from the semiconductor region of the second conductivity type. In addition, in this regard, this exemplary embodiment is different from the device discussed in the specification of U.S. Patent No. 9,209,336.

[0105] In Figure 6In this case, an N-type semiconductor region 5 having an impurity concentration lower than that of the N-type semiconductor region 1 is disposed directly below the N-type semiconductor region 1 having a high impurity concentration, without providing the P-type semiconductor region 2 and the N-type semiconductor region 4. In this case, charges can be generated in the N-type semiconductor region 5 and read from the N-type semiconductor region 1, but it is difficult to achieve avalanche amplification under voltage conditions equivalent to those of the present exemplary embodiment. This is because most of the potential difference applied between the N-type semiconductor region 1 and the P-type semiconductor region 3 is applied to the depletion layer region of the N-type semiconductor region 5, so that the potential difference applied to the avalanche amplification region near the N-type semiconductor region 1 becomes smaller. On the other hand, in the present exemplary embodiment, the N-type semiconductor region 5 is surrounded by the P-type semiconductor region in all directions except at the position where it contacts the N-type semiconductor region 4, so that the potential of the N-type semiconductor region 5 is closer to the level of the surrounding P-type semiconductor region than the potential of the N-type semiconductor region 1. That is, by suppressing the depletion layer from expanding excessively into the deeper part of the substrate in the P-type semiconductor region 2, most of the above-applied potential difference can be concentrated on the avalanche amplification region near the N-type semiconductor region 1. As a result, avalanche amplification of photo carriers can be achieved at a lower voltage.

[0106] Next, the impurity concentration of the N-type semiconductor region 5 is equal to or less than the impurity concentration of the N-type semiconductor region 4. For example, the impurity concentration of the N-type semiconductor region 5 is 1.0×10 17 [atms / cm 3 or less. Due to "equal to or less than", the impurity concentrations of the N-type semiconductor region 5 and the N-type semiconductor region 4 may be equal. In addition, at least, the impurity concentration of the N-type semiconductor region 5 should be less than the impurity concentration of the N-type semiconductor region 1.

[0107] In Figure 6 an example of the N-type semiconductor region 5 is shown as a region having the same impurity concentration. However, it is better for the N-type semiconductor region 5 to have an impurity concentration gradient so as to realize a potential structure that allows charges to move to the first surface side of the semiconductor substrate 15. By adopting such an impurity concentration gradient, charges can be easily moved to the N-type semiconductor region 1.

[0108] If the impurity concentration gradient realizes a potential structure that allows charges to move to the first surface side of the semiconductor substrate 15, in the region where the N-type semiconductor region 5 is disposed, the first surface side may be an N-type semiconductor region, and the second surface side may be a P-type semiconductor region.

[0109] Alternatively, a P-type semiconductor region having an impurity concentration lower than that of the P-type semiconductor region 2 may be arranged instead of the N-type semiconductor region 5. Further, in this case, it is better to have an impurity concentration gradient so as to realize a potential structure that allows charges to move to the first surface side of the semiconductor substrate 15.

[0110] For example, the P-type semiconductor region has a first region, a second region arranged at a position deeper than the first region with respect to the first surface, and a third region arranged at a position deeper than the second region with respect to the first surface. Then, if the first region has a first impurity concentration, the second region has a second impurity concentration, and the third region has a third impurity concentration, the first impurity concentration < the second impurity concentration < the third impurity concentration can be set. Incidentally, the first impurity concentration is lower than the impurity concentration of the P-type semiconductor region 2. Here, the P-type semiconductor region arranged instead of the N-type semiconductor region 5 is divided into three regions, but the present exemplary embodiment is not limited to such an example.

[0111] The P-type semiconductor region 8 is arranged at a position deeper than the N-type semiconductor region 5 and defines the depth of the photoelectric conversion region. The N-type semiconductor region 5 forms a PN junction with each of the P-type semiconductor region 2, the P-type semiconductor region 7, and the P-type semiconductor region 8. The impurity concentration of the P-type semiconductor region 8 is set to be higher than the impurity concentration of the P-type semiconductor region 2. Therefore, the charges generated near the P-type semiconductor region 8 can easily move in the direction of the first surface.

[0112] The contact plug 18 is connected to the N-type semiconductor region 1, and the wire 9 is connected to the contact plug 18. Further, the contact plug 17 is connected to the P-type semiconductor region 3, and the wire 10 is connected to the contact plug 17. Then, the wire 9 or the wire 10 is connected to a control unit 202 such as a resistance element to perform a quenching operation. Hereinafter, it is assumed that the control unit 202 is connected to the wire 9.

[0113] In Figure 6 it is assumed that the contact plug 17 and the wire 10 are arranged on the first surface side. However, the contact plug 17 and the wire 10 may also be arranged on the second surface side.

[0114] In one embodiment, when the contact plug 17 and the wire 10 are arranged on the second surface side, the impurity concentration of the region of the P-type semiconductor region 8 where the contact plug 17 is arranged is higher than the impurity concentration of the P-type semiconductor region 7. That is, this region becomes the P-type semiconductor region 3. In this case, the contact plug 17 is not connected to the P-type semiconductor region 3 arranged on the first surface side. Therefore, it is better to set the impurity concentration to a level comparable to that of the P-type semiconductor region 7. Thus, the electric field generated between the P-type semiconductor region 3 and the N-type semiconductor region 1 can be weakened.

[0115] When the isolation part 16 has a dielectric isolation part on the first surface side, the contact plug 17 and the wire 10 are also arranged on the second surface side. In this case, the isolation part 16 is arranged such that the dielectric isolation part, the P-type semiconductor region 7, and the P-type semiconductor region 3 are sequentially placed on top of each other along the depth direction starting from the first surface.

[0116] Next, with reference to Figures 7A to 7C description Figure 6 the planar structure of the isolation part 16 and the photoelectric conversion region surrounded by the isolation part 16 at any depth of the cross-sectional structure in Figures 7A to 7C In

[0117] Figure 7A shows Figure 6 a schematic plan view of the line segment AB at the depth X of

[0118] Figure 7B shows Figure 6 a schematic plan view of the line segment CD at the depth Y of

[0119] Figure 7C shows Figure 6 a schematic plan view of the line segment EF at the depth Z of

[0120] Incidentally, when Figure 7B placed on Figure 7C the top of

[0121] In addition, when Figure 7A placed on Figure 7B the top of

[0122] Next, with reference to Figures 8A to 8D description of the method for manufacturing an avalanche diode in the schematic cross-sectional view shown in Figure 6 Processes for which no specific order is mentioned can be appropriately interchanged. In addition, regarding the processes whose description is omitted in Figures 8A to 8D known manufacturing methods can be applied.

[0123] As Figure 8A shown, P-type impurity ion implantation (hereinafter simply referred to as ion implantation) is performed in a region to be the N-type semiconductor region 5 from a direction perpendicular to the first surface of the semiconductor substrate 15. Accordingly, the P-type semiconductor region 8 is formed at a deep position from the first surface of the semiconductor substrate 15.

[0124] Next, as Figure 8B shown, a mask 77 is formed on the first surface of the semiconductor substrate 15. The mask 77 has an opening 30. Then, by performing P-type ion implantation from a direction perpendicular to the first surface of the semiconductor substrate 15, the P-type semiconductor region 3 and the P-type semiconductor region 7 are formed to be arranged in sequence from the first surface. At this time, a part of the P-type semiconductor region 7 and the P-type semiconductor region 8 are connected. In addition, the impurity concentration of the P-type semiconductor region 3 is set to be higher than that of the P-type semiconductor region 7. More specifically, for example, a method of performing multiple ion implantations with different amounts of ion implantation energy can be used.

[0125] Next, the mask 77 is removed and a mask 78 is arranged. The mask 78 has an opening 32. Then, as Figure 8C shown, by performing P-type ion implantation from a direction parallel to the direction perpendicular to the first surface of the semiconductor substrate 15, a region to be the P-type semiconductor region 2 is formed. Then, by performing N-type ion implantation at a position shallower than the position where P-type ion implantation has been performed to form the region to be the P-type semiconductor region 2 from the first surface, a region to be the N-type semiconductor region 6 is formed. Here, the region to be the N-type semiconductor region 6 is formed after the region to be the P-type semiconductor region 2 is formed, but the order can be reversed.

[0126] Next, the mask 78 is removed and a mask 73 is arranged. The mask 73 has an opening 33. As Figure 8D shown, by performing N-type ion implantation in the depth of the region to be the P-type semiconductor region 2 from a direction parallel to the direction perpendicular to the first surface of the semiconductor substrate 15, the N-type semiconductor region 4 is formed in a part of the region to be the P-type semiconductor region 2.

[0127] Then, by performing N-type ion implantation from a direction parallel to the direction perpendicular to the first surface of the semiconductor substrate 15 on the first surface side of the semiconductor substrate 15, the N-type semiconductor region 1 is formed. Here, the N-type semiconductor region 4 is formed first, but the N-type semiconductor region 1 can also be formed first.

[0128] Therefore, when ion implantation is performed using impurity ions of the same conductivity type, the diffusion of the impurity ions in the direction parallel to the first surface that is the incident plane is greater when ion implantation is performed at a deep position relative to the first surface than when ion implantation is performed at a shallow position relative to the first surface. That is, when ion implantation is performed using the same mask, the N-type semiconductor region 1 is included in the N-type semiconductor region 4 in the plan view.

[0129] Impurity ions having different thermal diffusion coefficients can be used as the impurity ions implanted to form the N-type semiconductor region 1 and the N-type semiconductor region 4. According to such a structure, the degree of freedom in the potential design of the regions where the N-type semiconductor region 1 and the N-type semiconductor region 4 are arranged is improved.

[0130] In Figure 8D if different masks are used for ion implantation when forming the N-type semiconductor region 1 and the N-type semiconductor region 4, a position shift may occur, and thus a tunneling effect may occur due to the generation of an asymmetric electric field distribution. On the other hand, according to the manufacturing method of the present exemplary embodiment, the N-type semiconductor region 1 and the N-type semiconductor region 4 are formed using the same mask, whereby the position shift in the two semiconductor regions can be suppressed, and thus the tunneling effect that may be caused by the position shift can be suppressed.

[0131] Next, the control unit 202 according to the present exemplary embodiment will be described with reference to Figure 9A and 9B In the present exemplary embodiment, the control unit 202 has two structures. As Figure 9A shown, the first structure is a structure in which the control unit 202 is arranged on the cathode side where the high potential VH of the photoelectric conversion unit 201 is supplied. As Figure 9B shown, the second structure is a structure in which the control unit 202 is arranged on the anode side where the low potential VL of the photoelectric conversion unit 201 is supplied.

[0132] In Figure 9A and Figure 9B structures, after the input potential of the waveform shaping unit 203 changes due to the avalanche current, a fixed time is required to return to the bias voltage of the initial state of the photoelectric conversion unit 201 through the voltage drop of the control unit 202. The period required to return to the bias state capable of detecting charges after detecting charges once is called the dead time. The number of charges that can be counted per unit time increases, and the dynamic range of the optical detection device increases as the dead time decreases.

[0133] As an example, when the control unit 202 is a resistive element, the dead time (τd [s]) of the avalanche diode according to the present exemplary embodiment is determined by the product of the resistance (R [Ω]) and the capacitance (C [F]) at the input terminal. In the following formula, the PN junction capacitance of the photoelectric conversion unit 201 is denoted as Cpd, the capacitance of the well of the photoelectric conversion unit 201 is denoted as Cw, and the parasitic capacitance of the wiring / diffusion layer is denoted as C.

[0134] In Figure 9A the case of, the dead time is determined by Equation 2:

[0135] [Equation 2]

[0136] τd = R (Cpd + C) … (Equation 2)

[0137] In Figure 9B the case of, the dead time is determined by Equation 3:

[0138] [Equation 3]

[0139] τd = R (Cpd + Cw + C) … (Equation 3)

[0140] The PN junction capacitance Cpd of the photoelectric conversion unit 201 is the PN junction capacitance of the light detection region that senses a strong electric field to cause avalanche amplification. Therefore, the PN junction capacitance Cpd changes proportionally to the area of the light detection region. That is, if the area of the light detection region is increased to improve the light detection efficiency, the PN junction capacitance Cpd increases, resulting in an increase in the dead time. As a result, the dynamic range decreases.

[0141] In other words, the light detection efficiency and the dynamic range are in a trade-off relationship. On the other hand, according to the pixel structure in the present exemplary embodiment, the area of the light detection region can be reduced while ensuring a large area of the photoelectric conversion region. Therefore, Cpd can be reduced and the dead time can be reduced. Therefore, high light detection efficiency and a wide dynamic range can be achieved simultaneously.

[0142] Since the improvement effect of the dynamic range caused by the pixel structure according to the present exemplary embodiment is Figure 9A more significantly shown in the structure of Figure 9B than in Figure 9A and Figure 9B For example, if the ratio of Cpd of the SPAD structure according to the present exemplary embodiment to Cpd of the conventional SPAD structure is A (0 < A < 1), then

[0143] [Equation 4]

[0144] Δ1 = (1 - A) Cpd / (ACpd + C) … (Equation 4)

[0145] [Mathematical formula 5]

[0146] Δ2 = (1 - A)Cpd / (ACpd + Cw + C)…(Equation 5)

[0147] In Equation 4 and Equation 5, the calculation is performed using the fact that the dynamic range is inversely proportional to the dead time. It is obvious from the above equation that Δ1 > Δ2 is satisfied.

[0148] As can be seen from the above, when Figure 9A and Figure 9B the structure of is applied to the structure according to the present exemplary embodiment, the improvement rate of the dynamic range is in Figure 9A and is in principle higher than Figure 9B .

[0149] So far, the description has been provided on the assumption that the control unit 202 is a resistive element, but the same is true when the control unit 202 is an active quenching circuit.

[0150] As can be seen from the above, when the control unit 202 for a pixel according to the present exemplary embodiment is arranged on the cathode side rather than the anode side of the photoelectric conversion unit 201, the improvement effect of the dynamic range can be made greater.

[0151] According to the structure of the present exemplary embodiment, the deterioration of the light detection efficiency can be suppressed by forming a path for charge movement. That is, the noise can be reduced while suppressing the deterioration of the light detection efficiency.

[0152] Figure 10 is a schematic cross-sectional view of an avalanche diode according to the second exemplary embodiment. Figure 4 , Figure 5 , Figures 8A to 8D and Figure 9A and 9B are the same as in the first exemplary embodiment. In addition, units having similar functions to Figures 1 to 9B are attached with similar reference numerals, and their detailed descriptions are omitted. Figure 10 The difference of is that a P-type semiconductor region 24 is arranged in the region where the N-type semiconductor region 4 is arranged in Figure 6 .

[0153] In Figure 10In this case, an N-type semiconductor region 1 and a P-type semiconductor region 24 form a PN junction. In addition, a P-type semiconductor region 3 is electrically connected to the P-type semiconductor region 24 via the P-type semiconductor region 2. Therefore, the potential of the P-type semiconductor region 24 is the reverse bias potential of the N-type semiconductor region 1. Then, a strong electric field is induced in the PN junction region between the N-type semiconductor region 1 and the P-type semiconductor region 24. Avalanche amplification is caused by the strong electric field in the PN junction region, and a current based on the amplified charge is output from the wire 9 or the wire 10. That is, in the present exemplary embodiment, the light detection region is the PN junction region between the N-type semiconductor region 1 and the P-type semiconductor region 24. If configured in this way, the potential difference required to cause avalanche amplification can be made smaller than that in the first exemplary embodiment. That is, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in the present exemplary embodiment can be made smaller than the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in the first exemplary embodiment.

[0154] In Figure 10 this case, the impurity concentration of the P-type semiconductor region 24 is lower than the impurity concentration of the P-type semiconductor region 2 and the impurity concentration of the P-type semiconductor region 7. Therefore, the above-described potential relationship as Figure 3 shown also applies to the present exemplary embodiment.

[0155] The impurity concentration of the N-type semiconductor region 1 is set such that when the potential for causing avalanche amplification in the PN junction is supplied, as described above, the N-type semiconductor region 1 is not completely depleted.

[0156] In the present exemplary embodiment, the impurity concentration that makes the N-type semiconductor region 1 not completely depleted is, for example, an impurity concentration of 6.0×10 18 [atms / cm 3 or more in the N-type semiconductor region 1. Then, the impurity concentration of the P-type semiconductor region 24 is 1.0×10 17 [atms / cm 3 or less. This is because if the depletion layer region widens to contact the first surface of the semiconductor substrate 15, noise may be generated on the first surface of the semiconductor substrate 15. However, the impurity concentration is not limited to the above example.

[0157] More specifically, when the photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD), the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is 6 V or more.

[0158] In one embodiment, if the above impurity concentration relationship is considered, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is 10 V or more. In this case, for example, a potential of 10 V or more is supplied to the N-type semiconductor region 1, and a potential of 0 V or less is supplied to the P-type semiconductor region 24 via the P-type semiconductor region 2. However, if the potential difference is 6 V or more, the potential is not limited to the above values.

[0159] When applying the Figures 8A to 8D manufacturing method shown in the present exemplary embodiment, the P-type semiconductor region 24 is formed by performing N-type ion implantation so that the impurity concentration in a part of the region to be the P-type semiconductor region 2 in Figure 8D is locally reduced.

[0160] In addition, in the present exemplary embodiment, an effect similar to that in the first exemplary embodiment is achieved.

[0161] Figure 11 is a schematic cross-sectional view of an avalanche diode according to the third exemplary embodiment. Similar reference numerals are assigned to units having similar functions, and their detailed descriptions are omitted. Figures 1 to 10 The potential in the region where the N-type semiconductor region 5 is arranged in

[0162] Figure 11 differs from that in the region where the N-type semiconductor region 5 is arranged in Figure 6 in that the height of the potential in the region farther from the isolation part 16 along the direction parallel to the first surface is lower than the height of the potential in the region closer to the isolation part 16.

[0163] In Figure 11 the N-type semiconductor region 28 is arranged in the region closer to the isolation part 16 along the direction parallel to the first surface, and the N-type semiconductor region 27 is arranged in the region farther from the isolation part 16.

[0164] In the present exemplary embodiment, by creating an impurity concentration relationship in which the potential height in the N-type semiconductor region 27 is lower than the potential height in the N-type semiconductor region 28, charges can move more readily from the N-type semiconductor region 28 to the N-type semiconductor region 27.

[0165] In other words, the potential height in the region farther from the isolation part 16 (N-type semiconductor region 27) along the direction parallel to the first surface is lower than the potential height in the region closer to the isolation part 16 (N-type semiconductor region 28).

[0166] Therefore, the impurity concentration of the N-type semiconductor region 28 is lower than the impurity concentration of the N-type semiconductor region 27. Then, the impurity concentration of the N-type semiconductor region 27 is made lower than the impurity concentration of the N-type semiconductor region 4 to form a potential gradient in the light detection region.

[0167] If a P-type semiconductor region is arranged instead of the N-type semiconductor region 27, a P-type semiconductor region having an impurity concentration higher than that of the P-type semiconductor region arranged in place thereof is arranged instead of the N-type semiconductor region 28.

[0168] According to such a structure, if the direction from the position where the isolation part 16 is arranged toward the position where the N-type semiconductor region 27 is arranged is defined as the in-plane direction, an electric field in the in-plane direction is induced by adopting an impurity distribution that allows charges to move in the in-plane direction. The charges generated inside the semiconductor substrate 15 at a depth move in the in-plane direction through this electric field.

[0169] According to such a structure, for example, the time required for the charges generated inside the semiconductor substrate 15 at a depth to move to the light detection region can be reduced.

[0170] In addition, as described above, a potential that allows charges to easily move from a deep position to a shallow position on the first surface of the semiconductor substrate 15 is adopted. By adopting such a potential relationship, the time required for the charges to move to the light detection region can be further reduced.

[0171] This exemplary embodiment can be applied to all exemplary embodiments.

[0172] Figure 12 is a schematic cross-sectional view of an avalanche diode according to the fourth exemplary embodiment. Similar reference numerals are attached to units having similar functions, and their detailed descriptions are omitted. Figures 1 to 11 Similar reference numerals are attached to units having similar functions, and their detailed descriptions are omitted.

[0173] Figure 12 With Figure 6 the P-type semiconductor region 2 in, the difference lies in that P-type semiconductor regions 2B and 2A having different depths are configured.

[0174] In Figure 12 the P-type semiconductor region 2 includes a P-type semiconductor region 2B and a P-type semiconductor region 2A. The P-type semiconductor region 2A is arranged between the N-type semiconductor region 6 at the first depth X and the P-type semiconductor region 3 constituting the isolation part 16. The P-type semiconductor region 2B is arranged between the N-type semiconductor region 5 and the N-type semiconductor region 4 at the second depth Y. A part of the P-type semiconductor region 2A is in contact with the N-type semiconductor region 5, and other regions of the P-type semiconductor region 2A are in contact with the P-type semiconductor region 2B.

[0175] Next, with reference to Figure 13A and 13B the planar structure of the isolation part 16 and the photoelectric conversion region surrounded by the isolation part 16 at any depth of the cross-sectional structure in Figure 12 will be described. InFigure 13A and 13B In [description of figure], the boundary of each semiconductor region is depicted as circular, but the boundary is not limited to such an example. Incidentally, the schematic plan view of the line segment EF in depth Z is similar to Figure 7C , and thus is omitted.

[0176] Figure 13A shows Figure 12 the schematic plan view of the line segment AB in the first depth X of [figure]. The N-type semiconductor region 1 is included in the N-type semiconductor region 6. The N-type semiconductor region 6 is included in the P-type semiconductor region 2A. The P-type semiconductor region 2A is included in the P-type semiconductor region 3.

[0177] Figure 13B shows Figure 12 the schematic plan view of the line segment CD in the second depth Y of [figure]. The N-type semiconductor region 4 is included in the P-type semiconductor region 2B. The P-type semiconductor region 2B is included in the N-type semiconductor region 5. The N-type semiconductor region 5 is included in the P-type semiconductor region 3.

[0178] When Figure 13A placed on the top of Figure 13B [figure], the P-type semiconductor region 2A overlaps with the P-type semiconductor region 2B and the N-type semiconductor region 5.

[0179] According to the structure of the present exemplary embodiment, a part of the region where the P-type semiconductor region 2 is arranged in the second depth Y of [figure] can be changed to the N-type semiconductor region 5. Therefore, especially when a front-illumination type is adopted, the light detection efficiency of short-wavelength light can be improved. Figure 6 [figure]

[0180] The present exemplary embodiment can be applied to all exemplary embodiments.

[0181] Figure 14 is a schematic cross-sectional view of an avalanche diode according to the fifth exemplary embodiment. Similar reference numerals are attached to units having similar functions to Figures 1 to 13B [figure], and their detailed descriptions are omitted. Figure 14 Differing from Figure 6 [figure], a plurality of N-type semiconductor regions 1 and a plurality of N-type semiconductor regions 4 are arranged.

[0182] Figure 14 shows the structure in which each pair of the N-type semiconductor regions 1 and the N-type semiconductor regions 4 are arranged, but as long as more than one region is provided, the number of regions is not limited to two.

[0183] The N-type semiconductor region 1A is surrounded by the N-type semiconductor region 6. Similarly, the N-type semiconductor region 1B is surrounded by the N-type semiconductor region 6.

[0184] The N-type semiconductor region 4A is surrounded by the P-type semiconductor region 2. Similarly, the N-type semiconductor region 4B is surrounded by the P-type semiconductor region 2.

[0185] Next, with reference to Figure 15A and 15B the isolation portion 16 at any depth of the cross-sectional structure in Figure 14 and the planar structure of the photoelectric conversion region surrounded by the isolation portion 16 will be described. In Figure 15A and 15B the boundaries of each semiconductor region are depicted as circular, but the boundaries are not limited to such examples. Incidentally, the schematic plan view of the line segment EF at the depth Z is similar to Figure 7C and is thus omitted.

[0186] Figure 15A shows the schematic plan view of the line segment AB at the depth X in Figure 14 The N-type semiconductor regions 1A and 1B are both included in the N-type semiconductor region 6. The N-type semiconductor region 6 is included in the P-type semiconductor region 3. The area of the N-type semiconductor region 6 is larger than the area of the N-type semiconductor region 1A or the N-type semiconductor region 1B.

[0187] Figure 15B shows Figure 14 the schematic plan view of the line segment CD at the depth Y in

[0188] When Figure 15B is placed on top of Figure 7C the N-type semiconductor regions 4A, 4B and the P-type semiconductor region 2 overlap with the N-type semiconductor region 5.

[0189] In addition, when Figure 15A is placed on top of Figure 15B in the plan view, the N-type semiconductor region 1A overlaps at least a part of the N-type semiconductor region 4A. The N-type semiconductor region 1B overlaps at least a part of the N-type semiconductor region 4B in the plan view. As described above, all regions in the N-type semiconductor region 1 overlap with the N-type semiconductor region 4 in the plan view as if they were included therein.

[0190] When Figure 15A is placed on top of Figure 15B the N-type semiconductor region 6 overlaps at least a part of the P-type semiconductor region 2.

[0191] According to the structure in this exemplary embodiment, by the N-type semiconductor regions 1 and 4 each arranged at multiple positions, the average moving distance of the charges generated in the photoelectric conversion region to the light detection region can be shortened. Therefore, the time required for charge detection of the charges generated at deep positions in the photoelectric conversion region can be reduced.

[0192] This exemplary embodiment can be applied to all exemplary embodiments.

[0193] Figure 16 is a schematic cross-sectional view of an avalanche diode and a control unit according to the sixth exemplary embodiment. Similar reference numerals are attached to units having similar functions, and their detailed descriptions are omitted. Figures 1 to 15B Similar reference numerals are attached to units having similar functions, and their detailed descriptions are omitted.

[0194] In Figure 16 the photoelectric conversion unit 201 and the control unit 202 are arranged on different semiconductor substrates. The structure of the avalanche diode constituting the photoelectric conversion unit 201 is similar to the structure in the first exemplary embodiment. A plurality of units of the photoelectric conversion unit 201 are arranged on the semiconductor substrate 15. Here, as an example, a structure in which two avalanche diodes are arranged is shown. The control unit 202 and the wire 1107 connected to the control unit 202 are arranged on the semiconductor substrate 1102. Here, a structure in which the control unit 202 and the wire 1107 are arranged on the semiconductor substrate 1102 is shown, but other circuits can also be arranged.

[0195] The avalanche diode according to this exemplary embodiment is configured as a back-illuminated type. Light enters from the direction of the N-type semiconductor region 5 toward the N-type semiconductor region 1. In this case, the light enters the N-type semiconductor region 5 through the microlens 1103 and the color filter 1104.

[0196] As described above, photoelectric conversion occurs in the N-type semiconductor region 5, and the generated charges move to the N-type semiconductor region 1 through the N-type semiconductor region 4. Avalanche amplification is caused by the electric field between the N-type semiconductor region 1 and the depletion layer generated between the P-type semiconductor region 2 and the N-type semiconductor region 4, such that current flows to the wire 9.

[0197] The wire 9 is connected to the control unit 202 provided on the semiconductor substrate 1102 separately generated via the connection portion 1105.

[0198] The signals detected for each avalanche diode are processed by a scanning circuit or the like provided in the periphery of the pixel region of the semiconductor substrate 1102. Incidentally, the scanning circuit can also be arranged on a semiconductor substrate different from the semiconductor substrate 15 and the semiconductor substrate 1102.

[0199] According to the structure in this exemplary embodiment, a semiconductor substrate 1102 different from the semiconductor substrate 15 on which an avalanche diode is disposed is stacked on the semiconductor substrate 15. Then, by disposing a processing circuit such as a control unit 202 on the stacked semiconductor substrate 1102, the light detection efficiency can be improved by increasing the aperture ratio of the avalanche diode.

[0200] When a microlens 1103 is disposed on each avalanche diode in this exemplary embodiment, a positional relationship is adopted such that the optical axis of the microlens 1103 is included in the N-type semiconductor region 4 in a plan view. If, for example, vertical light enters the central region of the photoelectric conversion element 101, the distribution of the generation probability of signal charges in the N-type semiconductor region 5 is maximum near the optical axis of the microlens 1103. Here, the optical axis of the microlens 1103 is an axis that passes through the center of the microlens 1103 and is perpendicular to the semiconductor substrate 15 in a plan view.

[0201] According to the structure of this exemplary embodiment, if the optical axis of the microlens 1103 is two-dimensionally included in the N-type semiconductor region 4, charges are more likely to be generated at positions in the N-type semiconductor region 5 closer to the N-type semiconductor region 4 in a plan view. Then, the generation probability of charges generated at positions farther two-dimensionally can be reduced, so that the deterioration of the time resolution before charges are detected in the light detection region can be suppressed by charges generated at a shallow position from the first surface of the semiconductor substrate 15 and charges generated at a deep position thereof.

[0202] In this exemplary embodiment, a back-illuminated photodiode is configured, but a front-illuminated type can also achieve the effects of this exemplary embodiment, that is, high light detection efficiency and low direct current resistance (DCR) are achieved simultaneously. However, in this exemplary embodiment, since the photoelectric conversion unit is configured to be formed on the back side, the back-illuminated type can detect charges generated near the uppermost surface (light incident side) of the substrate more effectively than the front-illuminated type. That is, from the viewpoint of being able to achieve high light detection efficiency in a wide wavelength range from short wavelengths to long wavelengths, the back-illuminated type is adopted for the photoelectric conversion unit 201 of this exemplary embodiment.

[0203] This exemplary embodiment can be applied to all exemplary embodiments.

[0204] In the seventh exemplary embodiment, an example of a light detection system using the light detection device 1010 according to each exemplary embodiment will be described. Reference will be made to Figure 17 Describe an invisible light detection system and a medical diagnostic system such as positron emission tomography (PET) as examples of the light detection system. For those having the same as Figures 1 to 16Units having similar functions are attached with similar reference numerals, and their detailed descriptions are omitted. Incidentally, the pixel 100 according to the present exemplary embodiment includes a TDC and a memory, rather than Figure 5 the counter circuit 209 in

[0205] Figure 17 is a block diagram showing the structure of an invisible light detection system. The invisible light detection system includes a wavelength conversion unit 1201, a data processing unit 1207, and a plurality of light detection devices 1010.

[0206] The irradiation source object 1200 emits light in a wavelength range as invisible light. The wavelength conversion unit 1201 receives the light in the wavelength range of the invisible light emitted from the irradiation source object 1200 and emits visible light.

[0207] The photoelectric conversion unit 201 into which the visible light emitted from the wavelength conversion unit 1201 has entered performs photoelectric conversion, and the light detection device 1010 holds a digital signal based on the signal according to the charge after photoelectric conversion in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. The plurality of light detection devices 1010 may be formed as one device or a plurality of devices arranged.

[0208] The plurality of digital signals of the plurality of light detection devices 1010 held in the memory 205 are signal-processed by the data processing unit 1207. Here, as the signal processing unit, combined processing of a plurality of images obtained from the plurality of digital signals is performed.

[0209] Next, as a specific example of the invisible light detection system, the structure of a medical diagnostic system such as PET will be described.

[0210] As an object of the irradiation source object 1200, a pair of radiations is emitted from inside the body. When the pair of radiations emitted from the object enters, the wavelength conversion unit 1201 constitutes a scintillator, and the scintillator emits visible light.

[0211] The photoelectric conversion unit 201 into which the visible light emitted from the scintillator has entered performs photoelectric conversion, and the light detection device 1010 holds a digital signal based on the signal according to the charge after photoelectric conversion in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. That is, the light detection device 1010 is arranged to detect the arrival time of the pair of radiations emitted from the object, and detect the visible light emitted from the scintillator and hold the digital signal in the memory 205.

[0212] The digital signals of the plurality of light detection devices 1010 held in the memory 205 are signal - processed by the data processing unit 1207. Here, as the signal - processing unit, a combined process such as image reconstruction is performed using a plurality of images obtained from the plurality of digital signals to form an image within the object body.

[0213] In the eighth exemplary embodiment, an example of an optical detection system using the light detection device 1010 according to each exemplary embodiment will be described. Units having similar functions are assigned similar reference numerals, and their detailed descriptions are omitted. Figures 1 to 16 Similar reference numerals are assigned to units having similar functions, and their detailed descriptions are omitted.

[0214] In Figure 18 a distance detection system, which is an example of an optical detection system, will be described. Incidentally, the pixel 100 according to the present exemplary embodiment includes a TDC and a memory, rather than the counter circuit 209 in Figure 5 Here, it is assumed that the TDC is the TDC 204 and the memory is the memory 205, and a description is provided.

[0215] An example of a block diagram of a distance detection system according to the present exemplary embodiment will be described with reference to Figure 18 The distance detection system includes a light source control unit 1301, a light - emitting unit 1302, an optical member 1303, a light detection device 1010, and a distance calculation unit 1309.

[0216] The light source control unit 1301 controls the driving of the light - emitting unit 1302. When receiving a signal from the light source control unit 1301, the light - emitting unit 1302 emits short - pulse (burst) light in the shooting direction.

[0217] The light emitted from the light - emitting unit 1302 is reflected by the subject 1304. The reflected light is received by the photoelectric conversion unit 201 of the light detection device 1010 through the optical member 1303, and the signal based on the charge after photoelectric conversion is input to the TDC 204 via the waveform shaping unit 203.

[0218] The TDC 204 compares the signal obtained from the light source control unit 1301 and the signal input from the waveform shaping unit 203. Then, the TDC 204 digitally converts with high precision the time from when the pulsed light is emitted from the light - emitting unit 1302 to when the reflected light reflected by the subject 1304 is received. The digital signal output from the TDC 204 is held in the memory 205.

[0219] The distance calculation unit 1309 calculates the distance from the light detection device 1010 to the subject 1304 based on the plurality of measured digital signals held in the memory 205. The distance detection system can be applied, for example, as an in - vehicle system.

[0220] Next,Figure 19A and 19B shows an example of an optical detection system with the counter circuit 209 in Figure 5 . In Figure 19A and 19B , an optical detection system related to an in-vehicle camera is shown as an example of an optical detection system.

[0221] The optical detection system 1000 is an optical detection system including focus pixels and imaging pixels according to the present disclosure. The optical detection system 1000 includes an image processing unit 1030 that performs image processing on a plurality of digital signals acquired by the optical detection device 1010. In addition, the optical detection system 1000 includes a parallax calculation unit 1040 that calculates a parallax (phase difference between parallax images) based on a plurality of image data acquired by the image processing unit 1030.

[0222] The optical detection system 1000 further includes: a distance measurement unit 1050 that calculates the distance to a target object based on the calculated parallax; and a collision determination unit 1060 that determines whether a collision is likely to occur based on the calculated distance. Here, the parallax calculation unit 1040 and the distance measurement unit 1050 are examples of distance information acquisition units that acquire distance information to the target object. That is, the distance information is information about parallax, defocus amount, distance to the target object, etc.

[0223] The collision determination unit 1060 can use any of the above information to determine the collision possibility. The distance information acquisition unit can be implemented by specially designed hardware, software modules, or a combination thereof. The distance information acquisition unit can also be implemented by a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) or a combination thereof.

[0224] The optical detection system 1000 is connected to a vehicle information acquisition device 1310 and can acquire vehicle information such as vehicle speed, yaw rate, and rudder angle. The optical detection system 1000 is also connected to a control electronic control unit (ECU) 1410 as a control device to output a control signal that generates braking force for the vehicle based on the determination result of the collision determination unit 1060.

[0225] The light detection system 1000 is also connected to an alarm device 1420, which issues an alarm to the driver based on the determination result of the collision determination unit 1060. For example, if the collision possibility is high as the determination result of the collision determination unit 1060, the control ECU 1410 performs vehicle control to avoid a collision by applying the brakes, releasing the accelerator, or controlling the engine output to reduce damage. The alarm device 1420 issues an alarm by generating an alarm such as a sound, displaying alarm information on the screen of an automotive navigation system, etc., or generating vibration in a seat belt or a steering wheel.

[0226] In the present exemplary embodiment, the surrounding environment of the vehicle (e.g., the front or the rear) is imaged by the light detection system 1000. In Figure 19B it, a light detection system when imaging the front of the vehicle is shown. The control for preventing a collision with another vehicle has been described above, but the present exemplary embodiment can also be applied to controlling autonomous driving by following another vehicle or controlling autonomous driving by preventing the vehicle from deviating from a lane. In addition, the light detection system 1000 can be applied not only to vehicles such as local vehicles but also to moving bodies (mobile devices) such as ships, airplanes, or industrial robots. In addition to moving bodies, the light detection system 1000 can also be applied to devices that widely use object recognition such as intelligent transportation systems (ITS).

[0227] Although the present disclosure has been described with reference to the exemplary embodiments, it should be understood that the present disclosure is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation so as to cover all such modifications as well as equivalent structures and functions.

Claims

1. An apparatus, comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; And A pixel unit having a plurality of pixels, each pixel of the plurality of pixels including an avalanche diode, the plurality of pixels being arranged on the semiconductor substrate, Wherein, the avalanche diode includes: An avalanche amplification region, including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the first semiconductor region being arranged at a first depth, and the second semiconductor region being arranged at a second depth greater than the first depth relative to the first surface; A third semiconductor region of the first conductivity type, arranged at a third depth greater than the second depth relative to the first surface, the third semiconductor region being arranged to overlap the center of the first semiconductor region in a plan view; and A fourth semiconductor region of the second conductivity type, arranged between each of the third semiconductor regions in the plurality of pixels, Wherein, in a plan view, the area of the region where the first semiconductor region and the second semiconductor region overlap each other is smaller than the area of the third semiconductor region, and The fourth semiconductor region is electrically connected to the second semiconductor region.

2. The apparatus according to claim 1, wherein, The charges generated in the third semiconductor region are collected into the avalanche amplification region.

3. The apparatus according to claim 1, wherein, In a plan view, the first semiconductor region completely overlaps the second semiconductor region.

4. The apparatus according to claim 1, wherein, The impurity concentration of the first semiconductor region is 6.0×10 18 [atms / cm 3 or more, and The impurity concentration of the second semiconductor region is 1.0×10 17 [atms / cm 3 or less.

5. The apparatus according to claim 1, wherein, The impurity concentration of the third semiconductor region is lower than that of the first semiconductor region.

6. The apparatus according to claim 1, wherein, For the charges of the first conductivity type, the potential height of the third semiconductor region is lower at a shallow position relative to the first surface than at a deep position relative to the first surface.

7. The apparatus according to claim 5, wherein, For the charges of the first conductivity type, in the third semiconductor region, in a direction parallel to the first surface, the potential height of the region farther from the fourth semiconductor region is lower than that of the region closer to the fourth semiconductor region.

8. The apparatus according to claim 1, wherein, In a plan view, the area of the region where the first semiconductor region and the second semiconductor region overlap each other is smaller than the area of the second semiconductor region.

9. The apparatus according to claim 1, wherein, The first conductivity type is N-type and the second conductivity type is P-type.

10. The apparatus according to claim 3, further comprising a fifth semiconductor region of a second conductivity type, the fifth semiconductor region being disposed at a fourth depth deeper than the third semiconductor region with respect to the first surface, wherein, The fourth semiconductor region is in contact with the fifth semiconductor region.

11. The apparatus according to claim 1, further comprising a different semiconductor substrate different from the semiconductor substrate, wherein, A control unit configured to control the potential supplied to the first semiconductor region is arranged on the different semiconductor substrate, Wherein, the semiconductor substrate and the different semiconductor substrate are stacked, and Wherein, the first semiconductor region is electrically connected to the control unit via a wire.

12. The apparatus according to claim 1, further comprising a microlens, Among them, A microlens is arranged such that the optical axis of the microlens overlaps with the second semiconductor region.

13. An optical detection system comprising the device according to claim 1, comprising: A wavelength conversion unit, configured to convert light in a first wavelength range into light in a second wavelength range different from the first wavelength range; The light in the second wavelength range is emitted from the wavelength conversion unit and enters the device; And A signal processing unit, configured to perform a combined processing of a plurality of images obtained from a plurality of digital signals, the plurality of digital signals corresponding to the second wavelength range and being held in the device.

14. An optical detection system comprising the device according to claim 1, comprising: A light emitting unit, configured to emit light to be detected by the device; And A distance calculation unit, configured to calculate a distance using the digital signals corresponding to the light detected by the device and held in the device.

15. A moving body, comprising: The device according to claim 1; A distance calculation unit configured to obtain distance information indicating a distance to a target object based on a signal from the device; and A control unit configured to control a moving body based on the distance information.

16. An optical detection system comprising the device according to claim 1, the optical detection system comprising: A signal processing unit configured to process a signal from the device.

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